ar71xx: wndr4300: indicate WNDR3700v4 in the kernel support files
[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-wlr8100.c
1 /*
2  * Sitecom X8 AC1750 WLR-8100 board support
3  *
4  * Based on the Qualcomm Atheros AP135/AP136 reference board support code
5  * Copyright (c) 2012 Qualcomm Atheros
6  * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
7  *
8  * Permission to use, copy, modify, and/or distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  *
20  */
21
22 #include <linux/platform_device.h>
23 #include <linux/ar8216_platform.h>
24
25 #include <asm/mach-ath79/ar71xx_regs.h>
26
27 #include "common.h"
28 #include "pci.h"
29 #include "dev-ap9x-pci.h"
30 #include "dev-gpio-buttons.h"
31 #include "dev-eth.h"
32 #include "dev-leds-gpio.h"
33 #include "dev-m25p80.h"
34 #include "dev-usb.h"
35 #include "dev-wmac.h"
36 #include "machtypes.h"
37
38 #define WLR8100_GPIO_LED_USB            4
39 #define WLR8100_GPIO_LED_WLAN_5G        12
40 #define WLR8100_GPIO_LED_WLAN_2G        13
41 #define WLR8100_GPIO_LED_STATUS_RED     14
42 #define WLR8100_GPIO_LED_WPS_RED        15
43 #define WLR8100_GPIO_LED_STATUS_AMBER   19
44 #define WLR8100_GPIO_LED_WPS_GREEN      20
45
46 #define WLR8100_GPIO_BTN_WPS            16
47 #define WLR8100_GPIO_BTN_RFKILL         21
48
49 #define WLR8100_KEYS_POLL_INTERVAL      20      /* msecs */
50 #define WLR8100_KEYS_DEBOUNCE_INTERVAL  (3 * WLR8100_KEYS_POLL_INTERVAL)
51
52 #define WLR8100_MAC0_OFFSET             0
53 #define WLR8100_MAC1_OFFSET             6
54 #define WLR8100_WMAC_CALDATA_OFFSET     0x1000
55 #define WLR8100_PCIE_CALDATA_OFFSET     0x5000
56
57 static struct gpio_led wlr8100_leds_gpio[] __initdata = {
58         {
59                 .name           = "wlr8100:amber:status",
60                 .gpio           = WLR8100_GPIO_LED_STATUS_AMBER,
61                 .active_low     = 1,
62         },
63         {
64                 .name           = "wlr8100:red:status",
65                 .gpio           = WLR8100_GPIO_LED_STATUS_RED,
66                 .active_low     = 1,
67         },
68         {
69                 .name           = "wlr8100:green:wps",
70                 .gpio           = WLR8100_GPIO_LED_WPS_GREEN,
71                 .active_low     = 1,
72         },
73         {
74                 .name           = "wlr8100:red:wps",
75                 .gpio           = WLR8100_GPIO_LED_WPS_RED,
76                 .active_low     = 1,
77         },
78         {
79                 .name           = "wlr8100:red:wlan-2g",
80                 .gpio           = WLR8100_GPIO_LED_WLAN_2G,
81                 .active_low     = 1,
82         },
83         {
84                 .name           = "wlr8100:red:usb",
85                 .gpio           = WLR8100_GPIO_LED_USB,
86                 .active_low     = 1,
87         }
88 };
89
90 static struct gpio_keys_button wlr8100_gpio_keys[] __initdata = {
91         {
92                 .desc           = "WPS button",
93                 .type           = EV_KEY,
94                 .code           = KEY_WPS_BUTTON,
95                 .debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL,
96                 .gpio           = WLR8100_GPIO_BTN_WPS,
97                 .active_low     = 1,
98         },
99         {
100                 .desc           = "RFKILL button",
101                 .type           = EV_KEY,
102                 .code           = KEY_RFKILL,
103                 .debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL,
104                 .gpio           = WLR8100_GPIO_BTN_RFKILL,
105                 .active_low     = 1,
106         },
107 };
108
109 static struct ar8327_pad_cfg wlr8100_ar8327_pad0_cfg;
110 static struct ar8327_pad_cfg wlr8100_ar8327_pad6_cfg;
111
112 static struct ar8327_platform_data wlr8100_ar8327_data = {
113         .pad0_cfg = &wlr8100_ar8327_pad0_cfg,
114         .pad6_cfg = &wlr8100_ar8327_pad6_cfg,
115         .port0_cfg = {
116                 .force_link = 1,
117                 .speed = AR8327_PORT_SPEED_1000,
118                 .duplex = 1,
119                 .txpause = 1,
120                 .rxpause = 1,
121         },
122         .port6_cfg = {
123                 .force_link = 1,
124                 .speed = AR8327_PORT_SPEED_1000,
125                 .duplex = 1,
126                 .txpause = 1,
127                 .rxpause = 1,
128         },
129 };
130
131 static struct mdio_board_info wlr8100_mdio0_info[] = {
132         {
133                 .bus_id = "ag71xx-mdio.0",
134                 .phy_addr = 0,
135                 .platform_data = &wlr8100_ar8327_data,
136         },
137 };
138
139 static void __init wlr8100_gmac_setup(void)
140 {
141         void __iomem *base;
142         u32 t;
143
144         base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
145
146         t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
147
148         t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
149         t |= QCA955X_ETH_CFG_RGMII_EN;
150
151         __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
152
153         iounmap(base);
154 }
155
156 static void __init wlr8100_common_setup(void)
157 {
158         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
159
160         ath79_register_m25p80(NULL);
161
162         ath79_register_leds_gpio(-1, ARRAY_SIZE(wlr8100_leds_gpio),
163                                  wlr8100_leds_gpio);
164         ath79_register_gpio_keys_polled(-1, WLR8100_KEYS_POLL_INTERVAL,
165                                         ARRAY_SIZE(wlr8100_gpio_keys),
166                                         wlr8100_gpio_keys);
167
168         ath79_register_usb();
169
170         ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
171
172         wlr8100_gmac_setup();
173
174         ath79_register_mdio(0, 0x0);
175
176         ath79_init_mac(ath79_eth0_data.mac_addr, art + WLR8100_MAC0_OFFSET, 0);
177
178         mdiobus_register_board_info(wlr8100_mdio0_info,
179                                     ARRAY_SIZE(wlr8100_mdio0_info));
180
181         /* GMAC0 is connected to the RMGII interface */
182         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
183         ath79_eth0_data.phy_mask = BIT(0);
184         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
185
186         ath79_register_eth(0);
187
188         /* GMAC1 is connected tot eh SGMII interface */
189         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
190         ath79_eth1_data.speed = SPEED_1000;
191         ath79_eth1_data.duplex = DUPLEX_FULL;
192
193         ath79_register_eth(1);
194 }
195
196 static void __init wlr8100_010_setup(void)
197 {
198         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
199
200         /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */
201         wlr8100_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
202         wlr8100_ar8327_pad0_cfg.txclk_delay_en = true;
203         wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true;
204         wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
205         wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
206
207         /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
208         wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
209         wlr8100_ar8327_pad6_cfg.rxclk_delay_en = true;
210         wlr8100_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
211
212         ath79_eth0_pll_data.pll_1000 = 0xa6000000;
213         ath79_eth1_pll_data.pll_1000 = 0x03000101;
214
215         wlr8100_common_setup();
216         ap91_pci_init(art + WLR8100_PCIE_CALDATA_OFFSET, NULL);
217 }
218
219 MIPS_MACHINE(ATH79_MACH_WLR8100, "WLR8100",
220              "Sitecom WLR-8100",
221              wlr8100_010_setup);
222