target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c

   1 /*
   2  *  Atheros AR71xx SoC platform devices
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22
  23 #include <asm/mach-ath79/ath79.h>
  24 #include <asm/mach-ath79/ar71xx_regs.h>
  25 #include <asm/mach-ath79/irq.h>
  26
  27 #include "common.h"
  28 #include "dev-eth.h"
  29
  30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
  31
  32 static struct resource ath79_mdio0_resources[] = {
  33         {
  34                 .name   = "mdio_base",
  35                 .flags  = IORESOURCE_MEM,
  36                 .start  = AR71XX_GE0_BASE,
  37                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
  38         }
  39 };
  40
  41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
  42
  43 struct platform_device ath79_mdio0_device = {
  44         .name           = "ag71xx-mdio",
  45         .id             = 0,
  46         .resource       = ath79_mdio0_resources,
  47         .num_resources  = ARRAY_SIZE(ath79_mdio0_resources),
  48         .dev = {
  49                 .platform_data = &ath79_mdio0_data,
  50         },
  51 };
  52
  53 static struct resource ath79_mdio1_resources[] = {
  54         {
  55                 .name   = "mdio_base",
  56                 .flags  = IORESOURCE_MEM,
  57                 .start  = AR71XX_GE1_BASE,
  58                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
  59         }
  60 };
  61
  62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
  63
  64 struct platform_device ath79_mdio1_device = {
  65         .name           = "ag71xx-mdio",
  66         .id             = 1,
  67         .resource       = ath79_mdio1_resources,
  68         .num_resources  = ARRAY_SIZE(ath79_mdio1_resources),
  69         .dev = {
  70                 .platform_data = &ath79_mdio1_data,
  71         },
  72 };
  73
  74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
  75 {
  76         void __iomem *base;
  77         u32 t;
  78
  79         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  80
  81         t = __raw_readl(base + cfg_reg);
  82         t &= ~(3 << shift);
  83         t |=  (2 << shift);
  84         __raw_writel(t, base + cfg_reg);
  85         udelay(100);
  86
  87         __raw_writel(pll_val, base + pll_reg);
  88
  89         t |= (3 << shift);
  90         __raw_writel(t, base + cfg_reg);
  91         udelay(100);
  92
  93         t &= ~(3 << shift);
  94         __raw_writel(t, base + cfg_reg);
  95         udelay(100);
  96
  97         printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
  98                 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
  99
 100         iounmap(base);
 101 }
 102
 103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
 104                                           unsigned int mii_if)
 105 {
 106         void __iomem *base;
 107         u32 t;
 108
 109         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 110
 111         t = __raw_readl(base + reg);
 112         t &= ~(AR71XX_MII_CTRL_IF_MASK);
 113         t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
 114         __raw_writel(t, base + reg);
 115
 116         iounmap(base);
 117 }
 118
 119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
 120 {
 121         void __iomem *base;
 122         unsigned int mii_speed;
 123         u32 t;
 124
 125         switch (speed) {
 126         case SPEED_10:
 127                 mii_speed =  AR71XX_MII_CTRL_SPEED_10;
 128                 break;
 129         case SPEED_100:
 130                 mii_speed =  AR71XX_MII_CTRL_SPEED_100;
 131                 break;
 132         case SPEED_1000:
 133                 mii_speed =  AR71XX_MII_CTRL_SPEED_1000;
 134                 break;
 135         default:
 136                 BUG();
 137         }
 138
 139         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 140
 141         t = __raw_readl(base + reg);
 142         t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
 143         t |= mii_speed  << AR71XX_MII_CTRL_SPEED_SHIFT;
 144         __raw_writel(t, base + reg);
 145
 146         iounmap(base);
 147 }
 148
 149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
 150 {
 151         struct platform_device *mdio_dev;
 152         struct ag71xx_mdio_platform_data *mdio_data;
 153         unsigned int max_id;
 154
 155         if (ath79_soc == ATH79_SOC_AR9341 ||
 156             ath79_soc == ATH79_SOC_AR9342 ||
 157             ath79_soc == ATH79_SOC_AR9344)
 158                 max_id = 1;
 159         else
 160                 max_id = 0;
 161
 162         if (id > max_id) {
 163                 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
 164                 return;
 165         }
 166
 167         switch (ath79_soc) {
 168         case ATH79_SOC_AR7241:
 169         case ATH79_SOC_AR9330:
 170         case ATH79_SOC_AR9331:
 171                 mdio_dev = &ath79_mdio1_device;
 172                 mdio_data = &ath79_mdio1_data;
 173                 break;
 174
 175         case ATH79_SOC_AR9341:
 176         case ATH79_SOC_AR9342:
 177         case ATH79_SOC_AR9344:
 178                 if (id == 0) {
 179                         mdio_dev = &ath79_mdio0_device;
 180                         mdio_data = &ath79_mdio0_data;
 181                 } else {
 182                         mdio_dev = &ath79_mdio1_device;
 183                         mdio_data = &ath79_mdio1_data;
 184                 }
 185                 break;
 186
 187         case ATH79_SOC_AR7242:
 188                 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
 189                                AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
 190                                AR71XX_ETH0_PLL_SHIFT);
 191                 /* fall through */
 192         default:
 193                 mdio_dev = &ath79_mdio0_device;
 194                 mdio_data = &ath79_mdio0_data;
 195                 break;
 196         }
 197
 198         mdio_data->phy_mask = phy_mask;
 199
 200         switch (ath79_soc) {
 201         case ATH79_SOC_AR7240:
 202         case ATH79_SOC_AR7241:
 203         case ATH79_SOC_AR9330:
 204         case ATH79_SOC_AR9331:
 205                 mdio_data->is_ar7240 = 1;
 206                 break;
 207
 208         case ATH79_SOC_AR9341:
 209         case ATH79_SOC_AR9342:
 210         case ATH79_SOC_AR9344:
 211                 if (id == 1)
 212                         mdio_data->is_ar7240 = 1;
 213                 break;
 214
 215         default:
 216                 break;
 217         }
 218
 219         platform_device_register(mdio_dev);
 220 }
 221
 222 struct ath79_eth_pll_data ath79_eth0_pll_data;
 223 struct ath79_eth_pll_data ath79_eth1_pll_data;
 224
 225 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
 226 {
 227         struct ath79_eth_pll_data *pll_data;
 228         u32 pll_val;
 229
 230         switch (mac) {
 231         case 0:
 232                 pll_data = &ath79_eth0_pll_data;
 233                 break;
 234         case 1:
 235                 pll_data = &ath79_eth1_pll_data;
 236                 break;
 237         default:
 238                 BUG();
 239         }
 240
 241         switch (speed) {
 242         case SPEED_10:
 243                 pll_val = pll_data->pll_10;
 244                 break;
 245         case SPEED_100:
 246                 pll_val = pll_data->pll_100;
 247                 break;
 248         case SPEED_1000:
 249                 pll_val = pll_data->pll_1000;
 250                 break;
 251         default:
 252                 BUG();
 253         }
 254
 255         return pll_val;
 256 }
 257
 258 static void ath79_set_speed_ge0(int speed)
 259 {
 260         u32 val = ath79_get_eth_pll(0, speed);
 261
 262         ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
 263                         val, AR71XX_ETH0_PLL_SHIFT);
 264         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
 265 }
 266
 267 static void ath79_set_speed_ge1(int speed)
 268 {
 269         u32 val = ath79_get_eth_pll(1, speed);
 270
 271         ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
 272                          val, AR71XX_ETH1_PLL_SHIFT);
 273         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
 274 }
 275
 276 static void ar724x_set_speed_ge0(int speed)
 277 {
 278         /* TODO */
 279 }
 280
 281 static void ar724x_set_speed_ge1(int speed)
 282 {
 283         /* TODO */
 284 }
 285
 286 static void ar7242_set_speed_ge0(int speed)
 287 {
 288         u32 val = ath79_get_eth_pll(0, speed);
 289         void __iomem *base;
 290
 291         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 292         __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
 293         iounmap(base);
 294 }
 295
 296 static void ar91xx_set_speed_ge0(int speed)
 297 {
 298         u32 val = ath79_get_eth_pll(0, speed);
 299
 300         ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
 301                          val, AR913X_ETH0_PLL_SHIFT);
 302         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
 303 }
 304
 305 static void ar91xx_set_speed_ge1(int speed)
 306 {
 307         u32 val = ath79_get_eth_pll(1, speed);
 308
 309         ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
 310                          val, AR913X_ETH1_PLL_SHIFT);
 311         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
 312 }
 313
 314 static void ar933x_set_speed_ge0(int speed)
 315 {
 316         /* TODO */
 317 }
 318
 319 static void ar933x_set_speed_ge1(int speed)
 320 {
 321         /* TODO */
 322 }
 323
 324 static void ar934x_set_speed_ge0(int speed)
 325 {
 326         /* TODO */
 327 }
 328
 329 static void ar934x_set_speed_ge1(int speed)
 330 {
 331         /* TODO */
 332 }
 333
 334 static void ath79_ddr_no_flush(void)
 335 {
 336 }
 337
 338 static void ath79_ddr_flush_ge0(void)
 339 {
 340         ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
 341 }
 342
 343 static void ath79_ddr_flush_ge1(void)
 344 {
 345         ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
 346 }
 347
 348 static void ar724x_ddr_flush_ge0(void)
 349 {
 350         ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
 351 }
 352
 353 static void ar724x_ddr_flush_ge1(void)
 354 {
 355         ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
 356 }
 357
 358 static void ar91xx_ddr_flush_ge0(void)
 359 {
 360         ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
 361 }
 362
 363 static void ar91xx_ddr_flush_ge1(void)
 364 {
 365         ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
 366 }
 367
 368 static void ar933x_ddr_flush_ge0(void)
 369 {
 370         ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
 371 }
 372
 373 static void ar933x_ddr_flush_ge1(void)
 374 {
 375         ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
 376 }
 377
 378 static struct resource ath79_eth0_resources[] = {
 379         {
 380                 .name   = "mac_base",
 381                 .flags  = IORESOURCE_MEM,
 382                 .start  = AR71XX_GE0_BASE,
 383                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 384         }, {
 385                 .name   = "mac_irq",
 386                 .flags  = IORESOURCE_IRQ,
 387                 .start  = ATH79_CPU_IRQ_GE0,
 388                 .end    = ATH79_CPU_IRQ_GE0,
 389         },
 390 };
 391
 392 struct ag71xx_platform_data ath79_eth0_data = {
 393         .reset_bit      = AR71XX_RESET_GE0_MAC,
 394 };
 395
 396 struct platform_device ath79_eth0_device = {
 397         .name           = "ag71xx",
 398         .id             = 0,
 399         .resource       = ath79_eth0_resources,
 400         .num_resources  = ARRAY_SIZE(ath79_eth0_resources),
 401         .dev = {
 402                 .platform_data = &ath79_eth0_data,
 403         },
 404 };
 405
 406 static struct resource ath79_eth1_resources[] = {
 407         {
 408                 .name   = "mac_base",
 409                 .flags  = IORESOURCE_MEM,
 410                 .start  = AR71XX_GE1_BASE,
 411                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 412         }, {
 413                 .name   = "mac_irq",
 414                 .flags  = IORESOURCE_IRQ,
 415                 .start  = ATH79_CPU_IRQ_GE1,
 416                 .end    = ATH79_CPU_IRQ_GE1,
 417         },
 418 };
 419
 420 struct ag71xx_platform_data ath79_eth1_data = {
 421         .reset_bit      = AR71XX_RESET_GE1_MAC,
 422 };
 423
 424 struct platform_device ath79_eth1_device = {
 425         .name           = "ag71xx",
 426         .id             = 1,
 427         .resource       = ath79_eth1_resources,
 428         .num_resources  = ARRAY_SIZE(ath79_eth1_resources),
 429         .dev = {
 430                 .platform_data = &ath79_eth1_data,
 431         },
 432 };
 433
 434 struct ag71xx_switch_platform_data ath79_switch_data;
 435
 436 #define AR71XX_PLL_VAL_1000     0x00110000
 437 #define AR71XX_PLL_VAL_100      0x00001099
 438 #define AR71XX_PLL_VAL_10       0x00991099
 439
 440 #define AR724X_PLL_VAL_1000     0x00110000
 441 #define AR724X_PLL_VAL_100      0x00001099
 442 #define AR724X_PLL_VAL_10       0x00991099
 443
 444 #define AR7242_PLL_VAL_1000     0x16000000
 445 #define AR7242_PLL_VAL_100      0x00000101
 446 #define AR7242_PLL_VAL_10       0x00001616
 447
 448 #define AR913X_PLL_VAL_1000     0x1a000000
 449 #define AR913X_PLL_VAL_100      0x13000a44
 450 #define AR913X_PLL_VAL_10       0x00441099
 451
 452 #define AR933X_PLL_VAL_1000     0x00110000
 453 #define AR933X_PLL_VAL_100      0x00001099
 454 #define AR933X_PLL_VAL_10       0x00991099
 455
 456 #define AR934X_PLL_VAL_1000     0x00110000
 457 #define AR934X_PLL_VAL_100      0x00001099
 458 #define AR934X_PLL_VAL_10       0x00991099
 459
 460 static void __init ath79_init_eth_pll_data(unsigned int id)
 461 {
 462         struct ath79_eth_pll_data *pll_data;
 463         u32 pll_10, pll_100, pll_1000;
 464
 465         switch (id) {
 466         case 0:
 467                 pll_data = &ath79_eth0_pll_data;
 468                 break;
 469         case 1:
 470                 pll_data = &ath79_eth1_pll_data;
 471                 break;
 472         default:
 473                 BUG();
 474         }
 475
 476         switch (ath79_soc) {
 477         case ATH79_SOC_AR7130:
 478         case ATH79_SOC_AR7141:
 479         case ATH79_SOC_AR7161:
 480                 pll_10 = AR71XX_PLL_VAL_10;
 481                 pll_100 = AR71XX_PLL_VAL_100;
 482                 pll_1000 = AR71XX_PLL_VAL_1000;
 483                 break;
 484
 485         case ATH79_SOC_AR7240:
 486         case ATH79_SOC_AR7241:
 487                 pll_10 = AR724X_PLL_VAL_10;
 488                 pll_100 = AR724X_PLL_VAL_100;
 489                 pll_1000 = AR724X_PLL_VAL_1000;
 490                 break;
 491
 492         case ATH79_SOC_AR7242:
 493                 pll_10 = AR7242_PLL_VAL_10;
 494                 pll_100 = AR7242_PLL_VAL_100;
 495                 pll_1000 = AR7242_PLL_VAL_1000;
 496                 break;
 497
 498         case ATH79_SOC_AR9130:
 499         case ATH79_SOC_AR9132:
 500                 pll_10 = AR913X_PLL_VAL_10;
 501                 pll_100 = AR913X_PLL_VAL_100;
 502                 pll_1000 = AR913X_PLL_VAL_1000;
 503                 break;
 504
 505         case ATH79_SOC_AR9330:
 506         case ATH79_SOC_AR9331:
 507                 pll_10 = AR933X_PLL_VAL_10;
 508                 pll_100 = AR933X_PLL_VAL_100;
 509                 pll_1000 = AR933X_PLL_VAL_1000;
 510                 break;
 511
 512         case ATH79_SOC_AR9341:
 513         case ATH79_SOC_AR9342:
 514         case ATH79_SOC_AR9344:
 515                 pll_10 = AR934X_PLL_VAL_10;
 516                 pll_100 = AR934X_PLL_VAL_100;
 517                 pll_1000 = AR934X_PLL_VAL_1000;
 518                 break;
 519
 520         default:
 521                 BUG();
 522         }
 523
 524         if (!pll_data->pll_10)
 525                 pll_data->pll_10 = pll_10;
 526
 527         if (!pll_data->pll_100)
 528                 pll_data->pll_100 = pll_100;
 529
 530         if (!pll_data->pll_1000)
 531                 pll_data->pll_1000 = pll_1000;
 532 }
 533
 534 static int __init ath79_setup_phy_if_mode(unsigned int id,
 535                                            struct ag71xx_platform_data *pdata)
 536 {
 537         unsigned int mii_if;
 538
 539         switch (id) {
 540         case 0:
 541                 switch (ath79_soc) {
 542                 case ATH79_SOC_AR7130:
 543                 case ATH79_SOC_AR7141:
 544                 case ATH79_SOC_AR7161:
 545                 case ATH79_SOC_AR9130:
 546                 case ATH79_SOC_AR9132:
 547                         switch (pdata->phy_if_mode) {
 548                         case PHY_INTERFACE_MODE_MII:
 549                                 mii_if = AR71XX_MII0_CTRL_IF_MII;
 550                                 break;
 551                         case PHY_INTERFACE_MODE_GMII:
 552                                 mii_if = AR71XX_MII0_CTRL_IF_GMII;
 553                                 break;
 554                         case PHY_INTERFACE_MODE_RGMII:
 555                                 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
 556                                 break;
 557                         case PHY_INTERFACE_MODE_RMII:
 558                                 mii_if = AR71XX_MII0_CTRL_IF_RMII;
 559                                 break;
 560                         default:
 561                                 return -EINVAL;
 562                         }
 563                         ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
 564                         break;
 565
 566                 case ATH79_SOC_AR7240:
 567                 case ATH79_SOC_AR7241:
 568                 case ATH79_SOC_AR9330:
 569                 case ATH79_SOC_AR9331:
 570                         pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
 571                         break;
 572
 573                 case ATH79_SOC_AR7242:
 574                         /* FIXME */
 575
 576                 case ATH79_SOC_AR9341:
 577                 case ATH79_SOC_AR9342:
 578                 case ATH79_SOC_AR9344:
 579                         switch (pdata->phy_if_mode) {
 580                         case PHY_INTERFACE_MODE_MII:
 581                         case PHY_INTERFACE_MODE_GMII:
 582                         case PHY_INTERFACE_MODE_RGMII:
 583                         case PHY_INTERFACE_MODE_RMII:
 584                                 break;
 585                         default:
 586                                 return -EINVAL;
 587                         }
 588                         break;
 589
 590                 default:
 591                         BUG();
 592                 }
 593                 break;
 594         case 1:
 595                 switch (ath79_soc) {
 596                 case ATH79_SOC_AR7130:
 597                 case ATH79_SOC_AR7141:
 598                 case ATH79_SOC_AR7161:
 599                 case ATH79_SOC_AR9130:
 600                 case ATH79_SOC_AR9132:
 601                         switch (pdata->phy_if_mode) {
 602                         case PHY_INTERFACE_MODE_RMII:
 603                                 mii_if = AR71XX_MII1_CTRL_IF_RMII;
 604                                 break;
 605                         case PHY_INTERFACE_MODE_RGMII:
 606                                 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
 607                                 break;
 608                         default:
 609                                 return -EINVAL;
 610                         }
 611                         ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
 612                         break;
 613
 614                 case ATH79_SOC_AR7240:
 615                 case ATH79_SOC_AR7241:
 616                 case ATH79_SOC_AR9330:
 617                 case ATH79_SOC_AR9331:
 618                         pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
 619                         break;
 620
 621                 case ATH79_SOC_AR7242:
 622                         /* FIXME */
 623
 624                 case ATH79_SOC_AR9341:
 625                 case ATH79_SOC_AR9342:
 626                 case ATH79_SOC_AR9344:
 627                         switch (pdata->phy_if_mode) {
 628                         case PHY_INTERFACE_MODE_MII:
 629                         case PHY_INTERFACE_MODE_GMII:
 630                                 break;
 631                         default:
 632                                 return -EINVAL;
 633                         }
 634                         break;
 635
 636                 default:
 637                         BUG();
 638                 }
 639                 break;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static int ath79_eth_instance __initdata;
 646 void __init ath79_register_eth(unsigned int id)
 647 {
 648         struct platform_device *pdev;
 649         struct ag71xx_platform_data *pdata;
 650         int err;
 651
 652         if (id > 1) {
 653                 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
 654                 return;
 655         }
 656
 657         ath79_init_eth_pll_data(id);
 658
 659         if (id == 0)
 660                 pdev = &ath79_eth0_device;
 661         else
 662                 pdev = &ath79_eth1_device;
 663
 664         pdata = pdev->dev.platform_data;
 665
 666         err = ath79_setup_phy_if_mode(id, pdata);
 667         if (err) {
 668                 printk(KERN_ERR
 669                        "ar71xx: invalid PHY interface mode for GE%u\n", id);
 670                 return;
 671         }
 672
 673         switch (ath79_soc) {
 674         case ATH79_SOC_AR7130:
 675                 if (id == 0) {
 676                         pdata->ddr_flush = ath79_ddr_flush_ge0;
 677                         pdata->set_speed = ath79_set_speed_ge0;
 678                 } else {
 679                         pdata->ddr_flush = ath79_ddr_flush_ge1;
 680                         pdata->set_speed = ath79_set_speed_ge1;
 681                 }
 682                 break;
 683
 684         case ATH79_SOC_AR7141:
 685         case ATH79_SOC_AR7161:
 686                 if (id == 0) {
 687                         pdata->ddr_flush = ath79_ddr_flush_ge0;
 688                         pdata->set_speed = ath79_set_speed_ge0;
 689                 } else {
 690                         pdata->ddr_flush = ath79_ddr_flush_ge1;
 691                         pdata->set_speed = ath79_set_speed_ge1;
 692                 }
 693                 pdata->has_gbit = 1;
 694                 break;
 695
 696         case ATH79_SOC_AR7242:
 697                 if (id == 0) {
 698                         pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
 699                                             AR71XX_RESET_GE0_PHY;
 700                         pdata->ddr_flush = ar724x_ddr_flush_ge0;
 701                         pdata->set_speed = ar7242_set_speed_ge0;
 702                 } else {
 703                         pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
 704                                             AR71XX_RESET_GE1_PHY;
 705                         pdata->ddr_flush = ar724x_ddr_flush_ge1;
 706                         pdata->set_speed = ar724x_set_speed_ge1;
 707                 }
 708                 pdata->has_gbit = 1;
 709                 pdata->is_ar724x = 1;
 710
 711                 if (!pdata->fifo_cfg1)
 712                         pdata->fifo_cfg1 = 0x0010ffff;
 713                 if (!pdata->fifo_cfg2)
 714                         pdata->fifo_cfg2 = 0x015500aa;
 715                 if (!pdata->fifo_cfg3)
 716                         pdata->fifo_cfg3 = 0x01f00140;
 717                 break;
 718
 719         case ATH79_SOC_AR7241:
 720                 if (id == 0)
 721                         pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
 722                 else
 723                         pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
 724                 /* fall through */
 725         case ATH79_SOC_AR7240:
 726                 if (id == 0) {
 727                         pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
 728                         pdata->ddr_flush = ar724x_ddr_flush_ge0;
 729                         pdata->set_speed = ar724x_set_speed_ge0;
 730
 731                         pdata->phy_mask = BIT(4);
 732                 } else {
 733                         pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
 734                         pdata->ddr_flush = ar724x_ddr_flush_ge1;
 735                         pdata->set_speed = ar724x_set_speed_ge1;
 736
 737                         pdata->speed = SPEED_1000;
 738                         pdata->duplex = DUPLEX_FULL;
 739                         pdata->switch_data = &ath79_switch_data;
 740                 }
 741                 pdata->has_gbit = 1;
 742                 pdata->is_ar724x = 1;
 743                 if (ath79_soc == ATH79_SOC_AR7240)
 744                         pdata->is_ar7240 = 1;
 745
 746                 if (!pdata->fifo_cfg1)
 747                         pdata->fifo_cfg1 = 0x0010ffff;
 748                 if (!pdata->fifo_cfg2)
 749                         pdata->fifo_cfg2 = 0x015500aa;
 750                 if (!pdata->fifo_cfg3)
 751                         pdata->fifo_cfg3 = 0x01f00140;
 752                 break;
 753
 754         case ATH79_SOC_AR9130:
 755                 if (id == 0) {
 756                         pdata->ddr_flush = ar91xx_ddr_flush_ge0;
 757                         pdata->set_speed = ar91xx_set_speed_ge0;
 758                 } else {
 759                         pdata->ddr_flush = ar91xx_ddr_flush_ge1;
 760                         pdata->set_speed = ar91xx_set_speed_ge1;
 761                 }
 762                 pdata->is_ar91xx = 1;
 763                 break;
 764
 765         case ATH79_SOC_AR9132:
 766                 if (id == 0) {
 767                         pdata->ddr_flush = ar91xx_ddr_flush_ge0;
 768                         pdata->set_speed = ar91xx_set_speed_ge0;
 769                 } else {
 770                         pdata->ddr_flush = ar91xx_ddr_flush_ge1;
 771                         pdata->set_speed = ar91xx_set_speed_ge1;
 772                 }
 773                 pdata->is_ar91xx = 1;
 774                 pdata->has_gbit = 1;
 775                 break;
 776
 777         case ATH79_SOC_AR9330:
 778         case ATH79_SOC_AR9331:
 779                 if (id == 0) {
 780                         pdata->reset_bit = AR933X_RESET_GE0_MAC |
 781                                            AR933X_RESET_GE0_MDIO;
 782                         pdata->ddr_flush = ar933x_ddr_flush_ge0;
 783                         pdata->set_speed = ar933x_set_speed_ge0;
 784
 785                         pdata->phy_mask = BIT(4);
 786                 } else {
 787                         pdata->reset_bit = AR933X_RESET_GE1_MAC |
 788                                            AR933X_RESET_GE1_MDIO;
 789                         pdata->ddr_flush = ar933x_ddr_flush_ge1;
 790                         pdata->set_speed = ar933x_set_speed_ge1;
 791
 792                         pdata->speed = SPEED_1000;
 793                         pdata->duplex = DUPLEX_FULL;
 794                         pdata->switch_data = &ath79_switch_data;
 795                 }
 796
 797                 pdata->has_gbit = 1;
 798                 pdata->is_ar724x = 1;
 799
 800                 if (!pdata->fifo_cfg1)
 801                         pdata->fifo_cfg1 = 0x0010ffff;
 802                 if (!pdata->fifo_cfg2)
 803                         pdata->fifo_cfg2 = 0x015500aa;
 804                 if (!pdata->fifo_cfg3)
 805                         pdata->fifo_cfg3 = 0x01f00140;
 806                 break;
 807
 808         case ATH79_SOC_AR9341:
 809         case ATH79_SOC_AR9342:
 810         case ATH79_SOC_AR9344:
 811                 if (id == 0) {
 812                         pdata->reset_bit = AR934X_RESET_GE0_MAC |
 813                                            AR934X_RESET_GE0_MDIO;
 814                         pdata->set_speed = ar934x_set_speed_ge0;
 815                 } else {
 816                         pdata->reset_bit = AR934X_RESET_GE1_MAC |
 817                                            AR934X_RESET_GE1_MDIO;
 818                         pdata->set_speed = ar934x_set_speed_ge1;
 819
 820                         pdata->switch_data = &ath79_switch_data;
 821                 }
 822
 823                 pdata->ddr_flush = ath79_ddr_no_flush;
 824                 pdata->has_gbit = 1;
 825                 pdata->is_ar724x = 1;
 826
 827                 if (!pdata->fifo_cfg1)
 828                         pdata->fifo_cfg1 = 0x0010ffff;
 829                 if (!pdata->fifo_cfg2)
 830                         pdata->fifo_cfg2 = 0x015500aa;
 831                 if (!pdata->fifo_cfg3)
 832                         pdata->fifo_cfg3 = 0x01f00140;
 833                 break;
 834
 835         default:
 836                 BUG();
 837         }
 838
 839         switch (pdata->phy_if_mode) {
 840         case PHY_INTERFACE_MODE_GMII:
 841         case PHY_INTERFACE_MODE_RGMII:
 842                 if (!pdata->has_gbit) {
 843                         printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
 844                                         id);
 845                         return;
 846                 }
 847                 /* fallthrough */
 848         default:
 849                 break;
 850         }
 851
 852         if (!is_valid_ether_addr(pdata->mac_addr)) {
 853                 random_ether_addr(pdata->mac_addr);
 854                 printk(KERN_DEBUG
 855                         "ar71xx: using random MAC address for eth%d\n",
 856                         ath79_eth_instance);
 857         }
 858
 859         if (pdata->mii_bus_dev == NULL) {
 860                 switch (ath79_soc) {
 861                 case ATH79_SOC_AR9341:
 862                 case ATH79_SOC_AR9342:
 863                 case ATH79_SOC_AR9344:
 864                         if (id == 0)
 865                                 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
 866                         else
 867                                 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
 868                         break;
 869
 870                 case ATH79_SOC_AR7241:
 871                 case ATH79_SOC_AR9330:
 872                 case ATH79_SOC_AR9331:
 873                         pdata->mii_bus_dev = &ath79_mdio1_device.dev;
 874                         break;
 875
 876                 default:
 877                         pdata->mii_bus_dev = &ath79_mdio0_device.dev;
 878                         break;
 879                 }
 880         }
 881
 882         /* Reset the device */
 883         ath79_device_reset_set(pdata->reset_bit);
 884         mdelay(100);
 885
 886         ath79_device_reset_clear(pdata->reset_bit);
 887         mdelay(100);
 888
 889         platform_device_register(pdev);
 890         ath79_eth_instance++;
 891 }
 892
 893 void __init ath79_set_mac_base(unsigned char *mac)
 894 {
 895         memcpy(ath79_mac_base, mac, ETH_ALEN);
 896 }
 897
 898 void __init ath79_parse_mac_addr(char *mac_str)
 899 {
 900         u8 tmp[ETH_ALEN];
 901         int t;
 902
 903         t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
 904                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
 905
 906         if (t != ETH_ALEN)
 907                 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
 908                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
 909
 910         if (t == ETH_ALEN)
 911                 ath79_set_mac_base(tmp);
 912         else
 913                 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
 914                                 "\"%s\"\n", mac_str);
 915 }
 916
 917 static int __init ath79_ethaddr_setup(char *str)
 918 {
 919         ath79_parse_mac_addr(str);
 920         return 1;
 921 }
 922 __setup("ethaddr=", ath79_ethaddr_setup);
 923
 924 static int __init ath79_kmac_setup(char *str)
 925 {
 926         ath79_parse_mac_addr(str);
 927         return 1;
 928 }
 929 __setup("kmac=", ath79_kmac_setup);
 930
 931 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
 932                             int offset)
 933 {
 934         int t;
 935
 936         if (!is_valid_ether_addr(src)) {
 937                 memset(dst, '\0', ETH_ALEN);
 938                 return;
 939         }
 940
 941         t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
 942         t += offset;
 943
 944         dst[0] = src[0];
 945         dst[1] = src[1];
 946         dst[2] = src[2];
 947         dst[3] = (t >> 16) & 0xff;
 948         dst[4] = (t >> 8) & 0xff;
 949         dst[5] = t & 0xff;
 950 }
 951
 952 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
 953 {
 954         int i;
 955
 956         if (!is_valid_ether_addr(src)) {
 957                 memset(dst, '\0', ETH_ALEN);
 958                 return;
 959         }
 960
 961         for (i = 0; i < ETH_ALEN; i++)
 962                 dst[i] = src[i];
 963         dst[0] |= 0x02;
 964 }