target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/bootmem.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/traps.h>
  24 #include <asm/time.h>           /* for mips_hpt_frequency */
  25 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  26 #include <asm/mips_machine.h>
  27
  28 #include <asm/mach-ar71xx/ar71xx.h>
  29 #include <asm/mach-ar71xx/pci.h>
  30 #include <asm/mach-ar71xx/platform.h>
  31
  32 #define AR71XX_SYS_TYPE_LEN     64
  33 #define AR71XX_BASE_FREQ        40000000
  34 #define AR91XX_BASE_FREQ        5000000
  35
  36 unsigned long ar71xx_mach_type;
  37
  38 u32 ar71xx_cpu_freq;
  39 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  40
  41 u32 ar71xx_ahb_freq;
  42 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  43
  44 u32 ar71xx_ddr_freq;
  45 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  46
  47 enum ar71xx_soc_type ar71xx_soc;
  48 EXPORT_SYMBOL_GPL(ar71xx_soc);
  49
  50 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
  51                              struct ar71xx_pci_irq *map) __initdata;
  52
  53 int (*ar71xx_pci_be_handler)(int is_fixup);
  54
  55 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  56
  57 static void ar71xx_restart(char *command)
  58 {
  59         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  60         for (;;)
  61                 if (cpu_wait)
  62                         cpu_wait();
  63 }
  64
  65 static void ar71xx_halt(void)
  66 {
  67         while (1)
  68                 cpu_wait();
  69 }
  70
  71 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
  72 {
  73         int err = 0;
  74
  75         if (ar71xx_pci_be_handler)
  76                 err = ar71xx_pci_be_handler(is_fixup);
  77
  78         return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  79 }
  80
  81 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
  82 {
  83         if (!ar71xx_pci_bios_init)
  84                 return 0;
  85
  86         return ar71xx_pci_bios_init(nr_irqs, map);
  87 }
  88
  89 static void __init ar71xx_detect_mem_size(void)
  90 {
  91         unsigned long size;
  92
  93         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  94              size <<= 1 ) {
  95                 if (!memcmp(ar71xx_detect_mem_size,
  96                             ar71xx_detect_mem_size + size, 1024))
  97                         break;
  98         }
  99
 100         add_memory_region(0, size, BOOT_MEM_RAM);
 101 }
 102
 103 static void __init ar71xx_detect_sys_type(void)
 104 {
 105         char *chip;
 106         u32 id;
 107         u32 rev;
 108
 109         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK;
 110         rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
 111
 112         switch (id & REV_ID_CHIP_MASK) {
 113         case REV_ID_CHIP_AR7130:
 114                 ar71xx_soc = AR71XX_SOC_AR7130;
 115                 chip = "7130";
 116                 break;
 117
 118         case REV_ID_CHIP_AR7141:
 119                 ar71xx_soc = AR71XX_SOC_AR7141;
 120                 chip = "7141";
 121                 break;
 122
 123         case REV_ID_CHIP_AR7161:
 124                 ar71xx_soc = AR71XX_SOC_AR7161;
 125                 chip = "7161";
 126                 break;
 127
 128         case REV_ID_CHIP_AR9130:
 129                 ar71xx_soc = AR71XX_SOC_AR9130;
 130                 chip = "9130";
 131                 break;
 132
 133         case REV_ID_CHIP_AR9132:
 134                 ar71xx_soc = AR71XX_SOC_AR9132;
 135                 chip = "9132";
 136                 break;
 137
 138         default:
 139                 panic("ar71xx: unknown chip id:0x%02x\n", id);
 140         }
 141
 142         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
 143                 chip, rev, id);
 144 }
 145
 146 static void __init ar91xx_detect_sys_frequency(void)
 147 {
 148         u32 pll;
 149         u32 freq;
 150         u32 div;
 151
 152         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 153
 154         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 155         freq = div * AR91XX_BASE_FREQ;
 156
 157         ar71xx_cpu_freq = freq;
 158
 159         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 160         ar71xx_ddr_freq = freq / div;
 161
 162         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 163         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 164 }
 165
 166 static void __init ar71xx_detect_sys_frequency(void)
 167 {
 168         u32 pll;
 169         u32 freq;
 170         u32 div;
 171
 172         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 173
 174         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 175         freq = div * AR71XX_BASE_FREQ;
 176
 177         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 178         ar71xx_cpu_freq = freq / div;
 179
 180         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 181         ar71xx_ddr_freq = freq / div;
 182
 183         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 184         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 185 }
 186
 187 static void __init detect_sys_frequency(void)
 188 {
 189         switch (ar71xx_soc) {
 190         case AR71XX_SOC_AR7130:
 191         case AR71XX_SOC_AR7141:
 192         case AR71XX_SOC_AR7161:
 193                 ar71xx_detect_sys_frequency();
 194                 break;
 195
 196         case AR71XX_SOC_AR9130:
 197         case AR71XX_SOC_AR9132:
 198                 ar91xx_detect_sys_frequency();
 199                 break;
 200
 201         default:
 202                 BUG();
 203         }
 204 }
 205
 206 #ifdef CONFIG_AR71XX_EARLY_SERIAL
 207 static void __init ar71xx_early_serial_setup(void)
 208 {
 209         struct uart_port p;
 210
 211         memset(&p, 0, sizeof(p));
 212
 213         p.flags         = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
 214         p.iotype        = UPIO_MEM32;
 215         p.uartclk       = ar71xx_ahb_freq;
 216         p.irq           = AR71XX_MISC_IRQ_UART;
 217         p.regshift      = 2;
 218         p.mapbase       = AR71XX_UART_BASE;
 219
 220         early_serial_setup(&p);
 221 }
 222 #else
 223 static inline void ar71xx_early_serial_setup(void) {};
 224 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
 225
 226 const char *get_system_type(void)
 227 {
 228         return ar71xx_sys_type;
 229 }
 230
 231 unsigned int __cpuinit get_c0_compare_irq(void)
 232 {
 233         return CP0_LEGACY_COMPARE_IRQ;
 234 }
 235
 236 void __init plat_mem_setup(void)
 237 {
 238         set_io_port_base(KSEG1);
 239
 240         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 241                                                 AR71XX_DDR_CTRL_SIZE);
 242
 243         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 244                                                 AR71XX_PLL_SIZE);
 245
 246         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 247                                                 AR71XX_RESET_SIZE);
 248
 249         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 250
 251         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 252                                                 AR71XX_USB_CTRL_SIZE);
 253
 254         ar71xx_detect_mem_size();
 255         ar71xx_detect_sys_type();
 256         detect_sys_frequency();
 257
 258         printk(KERN_INFO
 259                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 260                 ar71xx_sys_type,
 261                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 262                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 263                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 264
 265         _machine_restart = ar71xx_restart;
 266         _machine_halt = ar71xx_halt;
 267         pm_power_off = ar71xx_halt;
 268
 269         board_be_handler = ar71xx_be_handler;
 270
 271         ar71xx_early_serial_setup();
 272 }
 273
 274 void __init plat_time_init(void)
 275 {
 276         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 277 }
 278
 279 static int __init ar71xx_machine_setup(void)
 280 {
 281         ar71xx_gpio_init();
 282
 283         ar71xx_add_device_uart();
 284         ar71xx_add_device_wdt();
 285
 286         mips_machine_setup(ar71xx_mach_type);
 287         return 0;
 288 }
 289
 290 arch_initcall(ar71xx_machine_setup);