target/linux/adm5120/files/drivers/usb/host/adm5120-hcd.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * [ Initialisation is based on Linus'  ]
   8  * [ uhci code and gregs ahcd fragments ]
   9  * [ (C) Copyright 1999 Linus Torvalds  ]
  10  * [ (C) Copyright 1999 Gregory P. Smith]
  11  *
  12  *
  13  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  14  * interfaces (though some non-x86 Intel chips use it).  It supports
  15  * smarter hardware than UHCI.  A download link for the spec available
  16  * through the http://www.usb.org website.
  17  *
  18  * This file is licenced under the GPL.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/pci.h>
  24 #include <linux/kernel.h>
  25 #include <linux/delay.h>
  26 #include <linux/ioport.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <linux/errno.h>
  30 #include <linux/init.h>
  31 #include <linux/timer.h>
  32 #include <linux/list.h>
  33 #include <linux/usb.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/dmapool.h>
  37 #include <linux/reboot.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/irq.h>
  41 #include <asm/system.h>
  42 #include <asm/unaligned.h>
  43 #include <asm/byteorder.h>
  44
  45 #include "../core/hcd.h"
  46 #include "../core/hub.h"
  47
  48 #define DRIVER_VERSION  "v0.02"
  49 #define DRIVER_AUTHOR   "Gabor Juhos <juhosg at openwrt.org>"
  50 #define DRIVER_DESC     "ADMtek USB 1.1 Host Controller Driver"
  51
  52 /*-------------------------------------------------------------------------*/
  53
  54 #define ADMHC_VERBOSE_DEBUG     /* not always helpful */
  55 #undef LATE_ED_SCHEDULE
  56
  57 /* For initializing controller (mask in an HCFS mode too) */
  58 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  59
  60 #define ADMHC_INTR_INIT \
  61                 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
  62                 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
  63
  64 /*-------------------------------------------------------------------------*/
  65
  66 static const char hcd_name [] = "admhc-hcd";
  67
  68 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  69
  70 #include "adm5120.h"
  71
  72 static void admhc_dump(struct admhcd *ahcd, int verbose);
  73 static int admhc_init(struct admhcd *ahcd);
  74 static void admhc_stop(struct usb_hcd *hcd);
  75
  76 #include "adm5120-hub.c"
  77 #include "adm5120-dbg.c"
  78 #include "adm5120-mem.c"
  79 #include "adm5120-q.c"
  80
  81 /*-------------------------------------------------------------------------*/
  82
  83 /*
  84  * queue up an urb for anything except the root hub
  85  */
  86 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
  87         struct urb *urb, gfp_t mem_flags)
  88 {
  89         struct admhcd   *ahcd = hcd_to_admhcd(hcd);
  90         struct ed       *ed;
  91         struct urb_priv *urb_priv;
  92         unsigned int    pipe = urb->pipe;
  93         int             td_cnt = 0;
  94         unsigned long   flags;
  95         int             retval = 0;
  96
  97 #ifdef ADMHC_VERBOSE_DEBUG
  98         spin_lock_irqsave(&ahcd->lock, flags);
  99         urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe));
 100         spin_unlock_irqrestore(&ahcd->lock, flags);
 101 #endif
 102
 103         /* every endpoint has an ed, locate and maybe (re)initialize it */
 104         ed = ed_get(ahcd, ep, urb->dev, pipe, urb->interval);
 105         if (!ed)
 106                 return -ENOMEM;
 107
 108         /* for the private part of the URB we need the number of TDs */
 109         switch (ed->type) {
 110         case PIPE_CONTROL:
 111                 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
 112                         /* td_submit_urb() doesn't yet handle these */
 113                         return -EMSGSIZE;
 114
 115                 /* 1 TD for setup, 1 for ACK, plus ... */
 116                 td_cnt = 2;
 117                 if (urb->transfer_buffer_length)
 118                         td_cnt++;
 119                 break;
 120         case PIPE_BULK:
 121                 /* one TD for every 4096 Bytes (can be upto 8K) */
 122                 td_cnt = urb->transfer_buffer_length / TD_DATALEN_MAX;
 123                 /* ... and for any remaining bytes ... */
 124                 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
 125                         td_cnt++;
 126                 /* ... and maybe a zero length packet to wrap it up */
 127                 if (td_cnt == 0)
 128                         td_cnt++;
 129                 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 130                         && (urb->transfer_buffer_length
 131                                 % usb_maxpacket(urb->dev, pipe,
 132                                         usb_pipeout (pipe))) == 0)
 133                         td_cnt++;
 134                 break;
 135         case PIPE_INTERRUPT:
 136                 /*
 137                  * for Interrupt IN/OUT transactions, each ED contains
 138                  * only 1 TD.
 139                  * TODO: check transfer_buffer_length?
 140                  */
 141                 td_cnt = 1;
 142                 break;
 143         case PIPE_ISOCHRONOUS:
 144                 /* number of packets from URB */
 145                 td_cnt = urb->number_of_packets;
 146                 break;
 147         default:
 148                 /* paranoia */
 149                 admhc_err(ahcd, "bad EP type %d", ed->type);
 150                 return -EINVAL;
 151         }
 152
 153         urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
 154         if (!urb_priv)
 155                 return -ENOMEM;
 156
 157         urb_priv->ed = ed;
 158         urb_priv->urb = urb;
 159
 160         spin_lock_irqsave(&ahcd->lock, flags);
 161         /* don't submit to a dead HC */
 162         if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
 163                 retval = -ENODEV;
 164                 goto fail;
 165         }
 166         if (!HC_IS_RUNNING(hcd->state)) {
 167                 retval = -ENODEV;
 168                 goto fail;
 169         }
 170
 171         /* in case of unlink-during-submit */
 172         spin_lock(&urb->lock);
 173         if (urb->status != -EINPROGRESS) {
 174                 spin_unlock(&urb->lock);
 175                 urb->hcpriv = urb_priv;
 176                 finish_urb(ahcd, urb);
 177                 retval = 0;
 178                 goto fail;
 179         }
 180
 181         if (ed->type == PIPE_ISOCHRONOUS) {
 182                 if (ed->state == ED_NEW) {
 183                         u16     frame = admhc_frame_no(ahcd);
 184
 185                         /* delay a few frames before the first TD */
 186                         frame += max_t (u16, 8, ed->interval);
 187                         frame &= ~(ed->interval - 1);
 188                         frame |= ed->branch;
 189                         urb->start_frame = frame;
 190
 191                         /* yes, only URB_ISO_ASAP is supported, and
 192                          * urb->start_frame is never used as input.
 193                          */
 194                 } else
 195                         urb->start_frame = ed->last_iso + ed->interval;
 196         }
 197
 198         urb->hcpriv = urb_priv;
 199         td_submit_urb(ahcd, urb_priv->urb);
 200
 201         /* append it to the ED's queue */
 202         list_add_tail(&urb_priv->pending, &ed->urb_pending);
 203
 204         /* schedule the ED */
 205         retval = ed_schedule(ahcd, ed);
 206
 207 fail0:
 208         spin_unlock(&urb->lock);
 209 fail:
 210         if (retval) {
 211                 urb_priv = urb->hcpriv;
 212                 urb_priv_free(ahcd, urb_priv);
 213         }
 214
 215         spin_unlock_irqrestore(&ahcd->lock, flags);
 216         return retval;
 217 }
 218
 219 /*
 220  * decouple the URB from the HC queues (TDs, urb_priv); it's
 221  * already marked using urb->status.  reporting is always done
 222  * asynchronously, and we might be dealing with an urb that's
 223  * partially transferred, or an ED with other urbs being unlinked.
 224  */
 225 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
 226 {
 227         struct admhcd *ahcd = hcd_to_admhcd(hcd);
 228         struct urb_priv *up;
 229         unsigned long flags;
 230
 231         up = urb->hcpriv;
 232         if (!up)
 233                 return 0;
 234
 235         spin_lock_irqsave(&ahcd->lock, flags);
 236
 237 #ifdef ADMHC_VERBOSE_DEBUG
 238         urb_print(ahcd, urb, "DEQEUE", 1);
 239 #endif
 240
 241         if (HC_IS_RUNNING(hcd->state)) {
 242                 /* Unless an IRQ completed the unlink while it was being
 243                  * handed to us, flag it for unlink and giveback, and force
 244                  * some upcoming INTR_SF to call finish_unlinks()
 245                  */
 246                 if (up->ed->urb_active != up) {
 247                         list_del(&up->pending);
 248                         finish_urb(ahcd, urb);
 249                 } else {
 250                         ed_start_deschedule(ahcd, up->ed);
 251                 }
 252         } else {
 253                 /*
 254                  * with HC dead, we won't respect hc queue pointers
 255                  * any more ... just clean up every urb's memory.
 256                  */
 257                 if (up->ed->urb_active != up) {
 258                         list_del(&up->pending);
 259                         finish_urb(ahcd, urb);
 260                 } else {
 261                         finish_urb(ahcd, urb);
 262                         up->ed->urb_active = NULL;
 263                         up->ed->state = ED_IDLE;
 264                 }
 265         }
 266         spin_unlock_irqrestore(&ahcd->lock, flags);
 267
 268         return 0;
 269 }
 270
 271 /*-------------------------------------------------------------------------*/
 272
 273 /* frees config/altsetting state for endpoints,
 274  * including ED memory, dummy TD, and bulk/intr data toggle
 275  */
 276 static void admhc_endpoint_disable(struct usb_hcd *hcd,
 277                 struct usb_host_endpoint *ep)
 278 {
 279         struct admhcd           *ahcd = hcd_to_admhcd(hcd);
 280         unsigned long           flags;
 281         struct ed               *ed = ep->hcpriv;
 282         unsigned                limit = 1000;
 283
 284         /* ASSERT:  any requests/urbs are being unlinked */
 285         /* ASSERT:  nobody can be submitting urbs for this any more */
 286
 287         if (!ed)
 288                 return;
 289
 290 #ifdef ADMHC_VERBOSE_DEBUG
 291         spin_lock_irqsave(&ahcd->lock, flags);
 292         admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
 293         spin_unlock_irqrestore(&ahcd->lock, flags);
 294 #endif
 295
 296 rescan:
 297         spin_lock_irqsave(&ahcd->lock, flags);
 298
 299         if (!HC_IS_RUNNING(hcd->state)) {
 300 sanitize:
 301                 ed->state = ED_UNLINK;
 302                 admhc_finish_unlinks(ahcd, 0);
 303         }
 304
 305         switch (ed->state) {
 306         case ED_UNLINK:         /* wait for hw to finish? */
 307                 /* major IRQ delivery trouble loses INTR_SOFI too... */
 308                 if (limit-- == 0) {
 309                         admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
 310                         goto sanitize;
 311                 }
 312                 spin_unlock_irqrestore(&ahcd->lock, flags);
 313                 schedule_timeout_uninterruptible(1);
 314                 goto rescan;
 315         case ED_IDLE:
 316         case ED_NEW:            /* fully unlinked */
 317                 if (list_empty(&ed->urb_pending)) {
 318                         td_free(ahcd, ed->dummy);
 319                         ed_free(ahcd, ed);
 320                         break;
 321                 }
 322                 /* else FALL THROUGH */
 323         default:
 324                 /* caller was supposed to have unlinked any requests;
 325                  * that's not our job.  can't recover; must leak ed.
 326                  */
 327                 admhc_err(ahcd, "leak ed %p (#%02x) %s act %p%s\n",
 328                         ed, ep->desc.bEndpointAddress,
 329                         ed_statestring(ed->state),
 330                         ed->urb_active,
 331                         list_empty(&ed->urb_pending) ? "" : " (has urbs)");
 332                 break;
 333         }
 334
 335         ep->hcpriv = NULL;
 336
 337         spin_unlock_irqrestore(&ahcd->lock, flags);
 338         return;
 339 }
 340
 341 static int admhc_get_frame(struct usb_hcd *hcd)
 342 {
 343         struct admhcd *ahcd = hcd_to_admhcd(hcd);
 344
 345         return admhc_frame_no(ahcd);
 346 }
 347
 348 static void admhc_usb_reset(struct admhcd *ahcd)
 349 {
 350         ahcd->host_control = ADMHC_BUSS_RESET;
 351         admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
 352 }
 353
 354 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
 355  * other cases where the next software may expect clean state from the
 356  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 357  */
 358 static void
 359 admhc_shutdown(struct usb_hcd *hcd)
 360 {
 361         struct admhcd *ahcd;
 362
 363         ahcd = hcd_to_admhcd(hcd);
 364         admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
 365         admhc_dma_disable(ahcd);
 366         admhc_usb_reset(ahcd);
 367         /* flush the writes */
 368         admhc_writel_flush(ahcd);
 369 }
 370
 371 /*-------------------------------------------------------------------------*
 372  * HC functions
 373  *-------------------------------------------------------------------------*/
 374
 375 static void admhc_eds_cleanup(struct admhcd *ahcd)
 376 {
 377         if (ahcd->ed_tails[PIPE_INTERRUPT]) {
 378                 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
 379                 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
 380         }
 381
 382         if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
 383                 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
 384                 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
 385         }
 386
 387         if (ahcd->ed_tails[PIPE_CONTROL]) {
 388                 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
 389                 ahcd->ed_tails[PIPE_CONTROL] = NULL;
 390         }
 391
 392         if (ahcd->ed_tails[PIPE_BULK]) {
 393                 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
 394                 ahcd->ed_tails[PIPE_BULK] = NULL;
 395         }
 396
 397         ahcd->ed_head = NULL;
 398 }
 399
 400 #define ED_DUMMY_INFO   (ED_SPEED_FULL | ED_SKIP)
 401
 402 static int admhc_eds_init(struct admhcd *ahcd)
 403 {
 404         struct ed *ed;
 405
 406         ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
 407         if (!ed)
 408                 goto err;
 409
 410         ahcd->ed_tails[PIPE_INTERRUPT] = ed;
 411
 412         ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
 413         if (!ed)
 414                 goto err;
 415
 416         ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
 417         ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
 418         ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
 419         ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
 420
 421         ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
 422         if (!ed)
 423                 goto err;
 424
 425         ahcd->ed_tails[PIPE_CONTROL] = ed;
 426         ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
 427         ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
 428         ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
 429
 430         ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
 431         if (!ed)
 432                 goto err;
 433
 434         ahcd->ed_tails[PIPE_BULK] = ed;
 435         ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
 436         ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
 437         ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
 438
 439         ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
 440
 441 #ifdef ADMHC_VERBOSE_DEBUG
 442         admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
 443         admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
 444         admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
 445         admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
 446 #endif
 447
 448         return 0;
 449
 450 err:
 451         admhc_eds_cleanup(ahcd);
 452         return -ENOMEM;
 453 }
 454
 455 /* init memory, and kick BIOS/SMM off */
 456
 457 static int admhc_init(struct admhcd *ahcd)
 458 {
 459         struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
 460         int ret;
 461
 462         admhc_disable(ahcd);
 463         ahcd->regs = hcd->regs;
 464
 465         /* Disable HC interrupts */
 466         admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
 467
 468         /* Read the number of ports unless overridden */
 469         if (ahcd->num_ports == 0)
 470                 ahcd->num_ports = admhc_get_rhdesc(ahcd) & ADMHC_RH_NUMP;
 471
 472         ret = admhc_mem_init(ahcd);
 473         if (ret)
 474                 goto err;
 475
 476         /* init dummy endpoints */
 477         ret = admhc_eds_init(ahcd);
 478         if (ret)
 479                 goto err;
 480
 481         create_debug_files(ahcd);
 482
 483         return 0;
 484
 485 err:
 486         admhc_stop(hcd);
 487         return ret;
 488 }
 489
 490 /*-------------------------------------------------------------------------*/
 491
 492 /* Start an OHCI controller, set the BUS operational
 493  * resets USB and controller
 494  * enable interrupts
 495  */
 496 static int admhc_run(struct admhcd *ahcd)
 497 {
 498         u32                     temp;
 499         int                     first = ahcd->fminterval == 0;
 500         struct usb_hcd          *hcd = admhcd_to_hcd(ahcd);
 501
 502         admhc_disable(ahcd);
 503
 504         /* boot firmware should have set this up (5.1.1.3.1) */
 505         if (first) {
 506                 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
 507                 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
 508                 if (ahcd->fminterval != FI)
 509                         admhc_dbg(ahcd, "fminterval delta %d\n",
 510                                 ahcd->fminterval - FI);
 511                 ahcd->fminterval |=
 512                         (FSLDP (ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
 513                 /* also: power/overcurrent flags in rhdesc */
 514         }
 515
 516         switch (ahcd->host_control & ADMHC_HC_BUSS) {
 517         case ADMHC_BUSS_OPER:
 518                 temp = 0;
 519                 break;
 520         case ADMHC_BUSS_SUSPEND:
 521                 /* FALLTHROUGH ? */
 522         case ADMHC_BUSS_RESUME:
 523                 ahcd->host_control = ADMHC_BUSS_RESUME;
 524                 temp = 10 /* msec wait */;
 525                 break;
 526         /* case ADMHC_BUSS_RESET: */
 527         default:
 528                 ahcd->host_control = ADMHC_BUSS_RESET;
 529                 temp = 50 /* msec wait */;
 530                 break;
 531         }
 532         admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
 533
 534         /* flush the writes */
 535         admhc_writel_flush(ahcd);
 536
 537         msleep(temp);
 538         temp = admhc_get_rhdesc(ahcd);
 539         if (!(temp & ADMHC_RH_NPS)) {
 540                 /* power down each port */
 541                 for (temp = 0; temp < ahcd->num_ports; temp++)
 542                         admhc_writel(ahcd, ADMHC_PS_CPP,
 543                                 &ahcd->regs->portstatus[temp]);
 544         }
 545         /* flush those writes */
 546         admhc_writel_flush(ahcd);
 547
 548         /* 2msec timelimit here means no irqs/preempt */
 549         spin_lock_irq(&ahcd->lock);
 550
 551 retry:
 552         admhc_writel(ahcd, ADMHC_CTRL_SR,  &ahcd->regs->gencontrol);
 553         temp = 30;      /* ... allow extra time */
 554         while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
 555                 if (--temp == 0) {
 556                         spin_unlock_irq(&ahcd->lock);
 557                         admhc_err(ahcd, "USB HC reset timed out!\n");
 558                         return -1;
 559                 }
 560                 udelay (1);
 561         }
 562
 563         /* enable HOST mode, before access any host specific register */
 564         admhc_writel(ahcd, ADMHC_CTRL_UHFE,  &ahcd->regs->gencontrol);
 565
 566         /* Tell the controller where the descriptor list is */
 567         admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
 568
 569         periodic_reinit(ahcd);
 570
 571         /* use rhsc irqs after khubd is fully initialized */
 572         hcd->poll_rh = 1;
 573         hcd->uses_new_polling = 1;
 574
 575 #if 0
 576         /* wake on ConnectStatusChange, matching external hubs */
 577         admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
 578 #else
 579         /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
 580 #endif
 581
 582         /* Choose the interrupts we care about now, others later on demand */
 583         admhc_intr_ack(ahcd, ~0);
 584         admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
 585
 586         admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
 587
 588         /* flush those writes */
 589         admhc_writel_flush(ahcd);
 590
 591         /* start controller operations */
 592         ahcd->host_control = ADMHC_BUSS_OPER;
 593         admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
 594
 595         temp = 20;
 596         while ((admhc_readl(ahcd, &ahcd->regs->host_control)
 597                         & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
 598                 if (--temp == 0) {
 599                         spin_unlock_irq(&ahcd->lock);
 600                         admhc_err(ahcd, "unable to setup operational mode!\n");
 601                         return -1;
 602                 }
 603                 mdelay(1);
 604         }
 605
 606         hcd->state = HC_STATE_RUNNING;
 607
 608         ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
 609
 610 #if 0
 611         /* FIXME: enabling DMA is always failed here for an unknown reason */
 612         admhc_dma_enable(ahcd);
 613
 614         temp = 200;
 615         while ((admhc_readl(ahcd, &ahcd->regs->host_control)
 616                         & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
 617                 if (--temp == 0) {
 618                         spin_unlock_irq(&ahcd->lock);
 619                         admhc_err(ahcd, "unable to enable DMA!\n");
 620                         admhc_dump(ahcd, 1);
 621                         return -1;
 622                 }
 623                 mdelay(1);
 624         }
 625
 626 #endif
 627
 628         spin_unlock_irq(&ahcd->lock);
 629
 630         mdelay(ADMHC_POTPGT);
 631
 632         return 0;
 633 }
 634
 635 /*-------------------------------------------------------------------------*/
 636
 637 /* an interrupt happens */
 638
 639 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
 640 {
 641         struct admhcd *ahcd = hcd_to_admhcd(hcd);
 642         struct admhcd_regs __iomem *regs = ahcd->regs;
 643         u32 ints;
 644
 645         ints = admhc_readl(ahcd, &regs->int_status);
 646         if ((ints & ADMHC_INTR_INTA) == 0) {
 647                 /* no unmasked interrupt status is set */
 648                 return IRQ_NONE;
 649         }
 650
 651         ints &= admhc_readl(ahcd, &regs->int_enable);
 652
 653         spin_lock(&ahcd->lock);
 654         if (ints & ADMHC_INTR_FATI) {
 655                 /* e.g. due to PCI Master/Target Abort */
 656                 admhc_disable(ahcd);
 657                 admhc_err(ahcd, "Fatal Error, controller disabled\n");
 658                 admhc_dump(ahcd, 1);
 659                 admhc_usb_reset(ahcd);
 660         }
 661
 662         if (ints & ADMHC_INTR_BABI) {
 663                 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
 664                 admhc_err(ahcd, "Babble Detected\n");
 665                 admhc_disable(ahcd);
 666                 admhc_usb_reset(ahcd);
 667         }
 668
 669         if (ints & ADMHC_INTR_INSM) {
 670                 admhc_vdbg(ahcd, "Root Hub Status Change\n");
 671                 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
 672                 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
 673
 674                 /* NOTE: Vendors didn't always make the same implementation
 675                  * choices for RHSC.  Many followed the spec; RHSC triggers
 676                  * on an edge, like setting and maybe clearing a port status
 677                  * change bit.  With others it's level-triggered, active
 678                  * until khubd clears all the port status change bits.  We'll
 679                  * always disable it here and rely on polling until khubd
 680                  * re-enables it.
 681                  */
 682                 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
 683                 usb_hcd_poll_rh_status(hcd);
 684         } else if (ints & ADMHC_INTR_RESI) {
 685                 /* For connect and disconnect events, we expect the controller
 686                  * to turn on RHSC along with RD.  But for remote wakeup events
 687                  * this might not happen.
 688                  */
 689                 admhc_vdbg(ahcd, "Resume Detect\n");
 690                 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
 691                 hcd->poll_rh = 1;
 692                 if (ahcd->autostop) {
 693                         admhc_rh_resume(ahcd);
 694                 } else
 695                         usb_hcd_resume_root_hub(hcd);
 696         }
 697
 698         if (ints & ADMHC_INTR_TDC) {
 699                 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
 700                 if (HC_IS_RUNNING(hcd->state))
 701                         admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
 702                 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
 703                 admhc_td_complete(ahcd);
 704                 if (HC_IS_RUNNING(hcd->state))
 705                         admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
 706         }
 707
 708         if (ints & ADMHC_INTR_SO) {
 709                 /* could track INTR_SO to reduce available PCI/... bandwidth */
 710                 admhc_vdbg(ahcd, "Schedule Overrun\n");
 711         }
 712
 713         if (ints & ADMHC_INTR_SOFI) {
 714                 admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
 715                 /* handle any pending ED removes */
 716                 admhc_finish_unlinks(ahcd, admhc_frame_no(ahcd));
 717                 admhc_sof_refill(ahcd);
 718         }
 719
 720         if (HC_IS_RUNNING(hcd->state)) {
 721                 admhc_intr_ack(ahcd, ints);
 722                 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
 723                 admhc_writel_flush(ahcd);
 724         }
 725         spin_unlock(&ahcd->lock);
 726
 727         return IRQ_HANDLED;
 728 }
 729
 730 /*-------------------------------------------------------------------------*/
 731
 732 static void admhc_stop(struct usb_hcd *hcd)
 733 {
 734         struct admhcd *ahcd = hcd_to_admhcd(hcd);
 735
 736         admhc_dump(ahcd, 1);
 737
 738         flush_scheduled_work();
 739
 740         admhc_usb_reset(ahcd);
 741         admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
 742
 743         free_irq(hcd->irq, hcd);
 744         hcd->irq = -1;
 745
 746         remove_debug_files(ahcd);
 747         admhc_eds_cleanup(ahcd);
 748         admhc_mem_cleanup(ahcd);
 749 }
 750
 751 /*-------------------------------------------------------------------------*/
 752
 753 /* must not be called from interrupt context */
 754
 755 #ifdef  CONFIG_PM
 756
 757 static int admhc_restart(struct admhcd *ahcd)
 758 {
 759         int temp;
 760         int i;
 761         struct urb_priv *priv;
 762
 763         /* mark any devices gone, so they do nothing till khubd disconnects.
 764          * recycle any "live" eds/tds (and urbs) right away.
 765          * later, khubd disconnect processing will recycle the other state,
 766          * (either as disconnect/reconnect, or maybe someday as a reset).
 767          */
 768         spin_lock_irq(&ahcd->lock);
 769         admhc_disable(ahcd);
 770         usb_root_hub_lost_power(admhcd_to_hcd(ahcd)->self.root_hub);
 771         if (!list_empty(&ahcd->pending))
 772                 admhc_dbg(ahcd, "abort schedule...\n");
 773                 list_for_each_entry(priv, &ahcd->pending, pending) {
 774                 struct urb      *urb = priv->td[0]->urb;
 775                 struct ed       *ed = priv->ed;
 776
 777                 switch (ed->state) {
 778                 case ED_OPER:
 779                         ed->state = ED_UNLINK;
 780                         ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
 781                         ed_deschedule (ahcd, ed);
 782
 783                         ed->ed_next = ahcd->ed_rm_list;
 784                         ed->ed_prev = NULL;
 785                         ahcd->ed_rm_list = ed;
 786                         /* FALLTHROUGH */
 787                 case ED_UNLINK:
 788                         break;
 789                 default:
 790                         admhc_dbg(ahcd, "bogus ed %p state %d\n",
 791                                         ed, ed->state);
 792                 }
 793
 794                 spin_lock(&urb->lock);
 795                 urb->status = -ESHUTDOWN;
 796                 spin_unlock(&urb->lock);
 797         }
 798         finish_unlinks(ahcd, 0);
 799         spin_unlock_irq(&ahcd->lock);
 800
 801         /* paranoia, in case that didn't work: */
 802
 803         /* empty the interrupt branches */
 804         for (i = 0; i < NUM_INTS; i++) ahcd->load[i] = 0;
 805         for (i = 0; i < NUM_INTS; i++) ahcd->hcca->int_table[i] = 0;
 806
 807         /* no EDs to remove */
 808         ahcd->ed_rm_list = NULL;
 809
 810         /* empty control and bulk lists */
 811         ahcd->ed_controltail = NULL;
 812         ahcd->ed_bulktail    = NULL;
 813
 814         if ((temp = admhc_run(ahcd)) < 0) {
 815                 admhc_err(ahcd, "can't restart, %d\n", temp);
 816                 return temp;
 817         } else {
 818                 /* here we "know" root ports should always stay powered,
 819                  * and that if we try to turn them back on the root hub
 820                  * will respond to CSC processing.
 821                  */
 822                 i = ahcd->num_ports;
 823                 while (i--)
 824                         admhc_writel(ahcd, RH_PS_PSS,
 825                                 &ahcd->regs->portstatus[i]);
 826                 admhc_dbg(ahcd, "restart complete\n");
 827         }
 828         return 0;
 829 }
 830 #endif
 831
 832 /*-------------------------------------------------------------------------*/
 833
 834 #ifdef CONFIG_MIPS_ADM5120
 835 #include "adm5120-drv.c"
 836 #define PLATFORM_DRIVER         usb_hcd_adm5120_driver
 837 #endif
 838
 839 #if     !defined(PLATFORM_DRIVER)
 840 #error "missing bus glue for admhc-hcd"
 841 #endif
 842
 843 #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
 844
 845 static int __init admhc_hcd_mod_init(void)
 846 {
 847         int retval = 0;
 848
 849         if (usb_disabled())
 850                 return -ENODEV;
 851
 852         pr_info("%s: " DRIVER_INFO "\n", hcd_name);
 853         pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
 854                 sizeof (struct ed), sizeof (struct td));
 855
 856 #ifdef PLATFORM_DRIVER
 857         retval = platform_driver_register(&PLATFORM_DRIVER);
 858         if (retval < 0)
 859                 goto error_platform;
 860 #endif
 861
 862         return retval;
 863
 864 #ifdef PLATFORM_DRIVER
 865         platform_driver_unregister(&PLATFORM_DRIVER);
 866 error_platform:
 867 #endif
 868         return retval;
 869 }
 870 module_init(admhc_hcd_mod_init);
 871
 872 static void __exit admhc_hcd_mod_exit(void)
 873 {
 874         platform_driver_unregister(&PLATFORM_DRIVER);
 875 }
 876 module_exit(admhc_hcd_mod_exit);
 877
 878 MODULE_AUTHOR(DRIVER_AUTHOR);
 879 MODULE_DESCRIPTION(DRIVER_INFO);
 880 MODULE_LICENSE("GPL");