package/kernel/mac80211/patches/348-ath9k-Fix-RTC_DERIVED_CLK-usage.patch

   1 From: Miaoqing Pan <miaoqing@qca.qualcomm.com>
   2 Date: Thu, 6 Nov 2014 10:52:23 +0530
   3 Subject: [PATCH] ath9k: Fix RTC_DERIVED_CLK usage
   4
   5 Based on the reference clock, which could be 25MHz or 40MHz,
   6 AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
   7 But, when a chip reset is done, processing the initvals
   8 sets the register back to the default value.
   9
  10 Fix this by moving the code in ath9k_hw_init_pll() to
  11 ar9003_hw_override_ini(). Also, do this override for AR9531.
  12
  13 Cc: stable@vger.kernel.org
  14 Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
  15 Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
  16 ---
  17
  18 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
  19 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
  20 @@ -664,6 +664,19 @@ static void ar9003_hw_override_ini(struc
  21                 ah->enabled_cals |= TX_CL_CAL;
  22         else
  23                 ah->enabled_cals &= ~TX_CL_CAL;
  24 +
  25 +       if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) {
  26 +               if (ah->is_clk_25mhz) {
  27 +                       REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
  28 +                       REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
  29 +                       REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
  30 +               } else {
  31 +                       REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
  32 +                       REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
  33 +                       REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
  34 +               }
  35 +               udelay(100);
  36 +       }
  37  }
  38
  39  static void ar9003_hw_prog_ini(struct ath_hw *ah,
  40 --- a/drivers/net/wireless/ath/ath9k/hw.c
  41 +++ b/drivers/net/wireless/ath/ath9k/hw.c
  42 @@ -870,19 +870,6 @@ static void ath9k_hw_init_pll(struct ath
  43         udelay(RTC_PLL_SETTLE_DELAY);
  44
  45         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
  46 -
  47 -       if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
  48 -               if (ah->is_clk_25mhz) {
  49 -                       REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
  50 -                       REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
  51 -                       REG_WRITE(ah,  AR_SLP32_INC, 0x0001e7ae);
  52 -               } else {
  53 -                       REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
  54 -                       REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
  55 -                       REG_WRITE(ah,  AR_SLP32_INC, 0x0001e800);
  56 -               }
  57 -               udelay(100);
  58 -       }
  59  }
  60
  61  static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,