package/kernel/mac80211/patches/301-pending_work-rt2x00.patch

   1 Contains the following changes from wireless-testing/master-2013-08-26:
   2
   3   commit 8951b79a4e6d8228babf56ae79a345e4abc5ac82
   4   Author: Gabor Juhos <juhosg@openwrt.org>
   5   Date:   Mon Jul 8 11:25:52 2013 +0200
   6
   7       rt2x00: rt2800lib: introduce rt2800_eeprom_word enum
   8
   9   commit 3e38d3daf881a78ac13e93504a8ac5777040797e
  10   Author: Gabor Juhos <juhosg@openwrt.org>
  11   Date:   Mon Jul 8 11:25:53 2013 +0200
  12
  13       rt2x00: rt2800lib: introduce local EEPROM access functions
  14
  15   commit 022138ca93f016374d5d3f69c070c75596c5ecac
  16   Author: Gabor Juhos <juhosg@openwrt.org>
  17   Date:   Mon Jul 8 11:25:54 2013 +0200
  18
  19       rt2x00: rt2800lib: introduce rt2800_eeprom_read_from_array helper
  20
  21   commit 379448fe34e289fdcc473399d4f6cac19e757fb8
  22   Author: Gabor Juhos <juhosg@openwrt.org>
  23   Date:   Mon Jul 8 11:25:55 2013 +0200
  24
  25       rt2x00: rt2800lib: introduce rt2800_eeprom_word_index helper
  26
  27   commit fa31d157f83ef71b6530aacf0400bafe7816acbd
  28   Author: Gabor Juhos <juhosg@openwrt.org>
  29   Date:   Mon Jul 8 11:25:56 2013 +0200
  30
  31       rt2x00: rt2800lib: add EEPROM map for the RT3593 chipset
  32
  33   commit 1706d15d82f4a579119b419cd673987af60f1d9b
  34   Author: Gabor Juhos <juhosg@openwrt.org>
  35   Date:   Mon Jul 8 16:08:16 2013 +0200
  36
  37       rt2x00: rt2800lib: add MAC register initialization for RT3593
  38
  39   commit b189a1814135bc52f516ca61a1fa161914d57a54
  40   Author: Gabor Juhos <juhosg@openwrt.org>
  41   Date:   Mon Jul 8 16:08:17 2013 +0200
  42
  43       rt2x00: rt2800lib: add BBP register initialization for RT3593
  44
  45   commit ab7078ac3d920e0d49b17e92f327f3ada25600e8
  46   Author: Gabor Juhos <juhosg@openwrt.org>
  47   Date:   Mon Jul 8 16:08:18 2013 +0200
  48
  49       rt2x00: rt2800lib: add RFCSR register initialization for RT3593
  50
  51   commit d63f7e8ca560dc9a76a15c323cb9cba14b25f430
  52   Author: Gabor Juhos <juhosg@openwrt.org>
  53   Date:   Mon Jul 8 16:08:19 2013 +0200
  54
  55       rt2x00: rt2800lib: add BBP post initialization for RT3593
  56
  57   commit 34542ff5a665061d548c3f860807df341f718adf
  58   Author: Gabor Juhos <juhosg@openwrt.org>
  59   Date:   Mon Jul 8 16:08:20 2013 +0200
  60
  61       rt2x00: rt2800lib: add TX power configuration for RT3593
  62
  63   commit 4788ac1e4842d8ef46ee620cfccf96c426043177
  64   Author: Gabor Juhos <juhosg@openwrt.org>
  65   Date:   Mon Jul 8 16:08:21 2013 +0200
  66
  67       rt2x00: rt2800lib: fix BBP1_TX_ANTENNA field configuration for 3T devices
  68
  69   commit 5cddb3c2d5102d9a6b1b809e1518da54c8be8296
  70   Author: Gabor Juhos <juhosg@openwrt.org>
  71   Date:   Mon Jul 8 16:08:22 2013 +0200
  72
  73       rt2x00: rt2800lib: fix antenna configuration for RT3593
  74
  75   commit 97aa03f15e83174df74aa468eea127c5cee480f0
  76   Author: Gabor Juhos <juhosg@openwrt.org>
  77   Date:   Mon Jul 8 16:08:23 2013 +0200
  78
  79       rt2x00: rt2800lib: add rt2800_txpower_to_dev helper
  80
  81   commit fc739cfe0f305647677edbf99a76d9ece96e3795
  82   Author: Gabor Juhos <juhosg@openwrt.org>
  83   Date:   Mon Jul 8 16:08:24 2013 +0200
  84
  85       rt2x00: rt2800lib: fix default TX power values for RT3593
  86
  87   commit a3f1625dae58f06c5df1ec0094b275e9a46fd8b3
  88   Author: Gabor Juhos <juhosg@openwrt.org>
  89   Date:   Mon Jul 8 16:08:25 2013 +0200
  90
  91       rt2x00: rt2800lib: introduce rt2800_get_txmixer_gain_{24,5}g helpers
  92
  93   commit 6316c786cc8aff762530ea740233bf2da10fea33
  94   Author: Gabor Juhos <juhosg@openwrt.org>
  95   Date:   Mon Jul 8 16:08:26 2013 +0200
  96
  97       rt2x00: rt2800lib: hardcode TX mixer gain values for RT3593
  98
  99   commit f36bb0ca1be5bcb7148ad32263626f8609dfc0d7
 100   Author: Gabor Juhos <juhosg@openwrt.org>
 101   Date:   Mon Jul 8 16:08:27 2013 +0200
 102
 103       rt2x00: rt2800lib: fix LNA_A[12] gain values for RT3593
 104
 105   commit c0a14369ebd3e7940e70e397ecc3dd7eaf81e9ab
 106   Author: Gabor Juhos <juhosg@openwrt.org>
 107   Date:   Mon Jul 8 16:08:28 2013 +0200
 108
 109       rt2x00: rt2800lib: add default_power3 field for three-chain devices
 110
 111   commit c8b9d3dc83cab569de6054a10e355a143e2b52a0
 112   Author: Gabor Juhos <juhosg@openwrt.org>
 113   Date:   Mon Jul 8 16:08:29 2013 +0200
 114
 115       rt2x00: rt2800lib: add rf_vals for RF3053
 116
 117   commit f42b046578efb018064302fd9b66586f5da7d75b
 118   Author: Gabor Juhos <juhosg@openwrt.org>
 119   Date:   Mon Jul 8 16:08:30 2013 +0200
 120
 121       rt2x00: rt2800lib: add channel configuration for RF3053
 122
 123   commit 1095df07bfc5924e100f1748e6ebc9e5a5881565
 124   Author: Gabor Juhos <juhosg@openwrt.org>
 125   Date:   Mon Jul 8 16:08:31 2013 +0200
 126
 127       rt2x00: rt2800lib: enable VCO recalibration for RF3053
 128
 129   commit 0f5af26a49c8d6a50ecec2f1b66174069c9f9581
 130   Author: Gabor Juhos <juhosg@openwrt.org>
 131   Date:   Mon Jul 8 16:08:32 2013 +0200
 132
 133       rt2x00: rt2800lib: enable RF3053 support
 134
 135   commit 2dc2bd2f8aa8eb79184fb3c7e5f530006500897f
 136   Author: Gabor Juhos <juhosg@openwrt.org>
 137   Date:   Mon Jul 8 16:08:33 2013 +0200
 138
 139       rt2x00: rt2800lib: enable RT3593 support
 140
 141   commit 65d3c0d5cffb9f1227927544e418a9ac231eae42
 142   Author: Gabor Juhos <juhosg@openwrt.org>
 143   Date:   Mon Jul 8 16:08:34 2013 +0200
 144
 145       rt2x00: rt2800usb: use correct [RT]XWI size for RT3593
 146
 147   commit d02433d15566f542e42e3c469dfade0de332dc7b
 148   Author: Gabor Juhos <juhosg@openwrt.org>
 149   Date:   Mon Jul 8 16:08:35 2013 +0200
 150
 151       rt2x00: rt2800usb: add USB device ID for Linksys AE3000
 152
 153   commit 637065267eab4817c0b06cbf3c7fc80842acab99
 154   Author: Xose Vazquez Perez <xose.vazquez@gmail.com>
 155   Date:   Tue Jul 23 14:55:15 2013 +0200
 156
 157       wireless: rt2x00: rt2800usb: add RT3573 devices
 158
 159   commit ae1b1c5dcdef1ebd4b37a7d56ad767add757a660
 160   Author: Gabor Juhos <juhosg@openwrt.org>
 161   Date:   Fri Aug 16 10:23:29 2013 +0200
 162
 163       rt2x00: rt2800lib: introduce rt2800_get_txwi_rxwi_size helper
 164
 165   commit 41caa760d6acaf47cbd44c3d78307fb9be089111
 166   Author: Gabor Juhos <juhosg@openwrt.org>
 167   Date:   Fri Aug 16 10:23:30 2013 +0200
 168
 169       rt2x00: rt2800pci: fix AUX_CTRL register setup for RT3090/3390/3593/5592
 170
 171   commit 91a3fa39ddf2f85a15cb20ccc3a54c1f0497af1e
 172   Author: Gabor Juhos <juhosg@openwrt.org>
 173   Date:   Sat Aug 17 00:15:49 2013 +0200
 174
 175       rt2x00: rt2800: rename HW_BEACON_OFFSET macro
 176
 177   commit 77f7c0f3b8f2d464e841c5c35f3da8b4999a885c
 178   Author: Gabor Juhos <juhosg@openwrt.org>
 179   Date:   Sat Aug 17 00:15:50 2013 +0200
 180
 181       rt2x00: rt2800lib: pass beacon index to rt2800_clear_beacon_register
 182
 183   commit c1fada4e5e53d88a8edd3ff01cee9d316cbf6025
 184   Author: Gabor Juhos <juhosg@openwrt.org>
 185   Date:   Sat Aug 17 14:09:28 2013 +0200
 186
 187       rt2x00: rt2800lib: fix frequency offset boundary calculation
 188
 189   commit 6af1bdccabe956a08a37f2ae049d37307ec0c91c
 190   Author: Gabor Juhos <juhosg@openwrt.org>
 191   Date:   Sat Aug 17 14:09:29 2013 +0200
 192
 193       rt2x00: rt2800lib: optimize frequency offset adjustment
 194
 195   commit 76773f301f2210dcc20c466aebda7118062673eb
 196   Author: Gabor Juhos <juhosg@openwrt.org>
 197   Date:   Sat Aug 17 14:09:30 2013 +0200
 198
 199       rt2x00: rt2800lib: use a MCU command for frequency adjustment on USB devices
 200
 201   commit 8d38eca8e089179b6858ca5f3ea03f571a5892a5
 202   Author: Gabor Juhos <juhosg@openwrt.org>
 203   Date:   Sat Aug 17 14:09:31 2013 +0200
 204
 205       rt2x00: rt2800lib: use step-by-step frequency offset adjustment on MMIO devices
 206
 207   commit 3f1b8739a498c7570ca2fae6c49fd1561ef2358c
 208   Author: Gabor Juhos <juhosg@openwrt.org>
 209   Date:   Sat Aug 17 14:09:32 2013 +0200
 210
 211       rt2x00: rt2800lib: move rt2800_adjust_freq_offset function
 212
 213   commit e979a8ab204edbf7b0815162109ee9c85e4d7ea5
 214   Author: Gabor Juhos <juhosg@openwrt.org>
 215   Date:   Sat Aug 17 14:09:33 2013 +0200
 216
 217       rt2x00: rt2800lib: adjust frequency offset for RF3053
 218
 219   commit 21c6af6b69b609b7934caaccda1b4535dceb402c
 220   Author: Gabor Juhos <juhosg@openwrt.org>
 221   Date:   Thu Aug 22 20:53:21 2013 +0200
 222
 223       rt2x00: rt2800lib: add rt2800_hw_beacon_base helper
 224
 225   commit 634b80595fef79071d82bc231b7f82c4f808a1e8
 226   Author: Gabor Juhos <juhosg@openwrt.org>
 227   Date:   Thu Aug 22 20:53:22 2013 +0200
 228
 229       rt2x00: rt2800lib: don't hardcode beacon offsets
 230
 231   commit 6e956da2027c767859128b9bfef085cf2a8e233b
 232   Author: Stanislaw Gruszka <sgruszka@redhat.com>
 233   Date:   Mon Aug 26 15:18:53 2013 +0200
 234
 235       rt2800: fix wrong TX power compensation
 236
 237 ---
 238 --- a/drivers/net/wireless/rt2x00/Kconfig
 239 +++ b/drivers/net/wireless/rt2x00/Kconfig
 240 @@ -174,6 +174,12 @@ config RT2800USB_RT35XX
 241           rt2800usb driver.
 242           Supported chips: RT3572
 243
 244 +config RT2800USB_RT3573
 245 +       bool "rt2800usb - Include support for rt3573 devices (EXPERIMENTAL)"
 246 +       ---help---
 247 +         This enables support for RT3573 chipset based wireless USB devices
 248 +         in the rt2800usb driver.
 249 +
 250  config RT2800USB_RT53XX
 251         bool "rt2800usb - Include support for rt53xx devices (EXPERIMENTAL)"
 252         ---help---
 253 --- a/drivers/net/wireless/rt2x00/rt2800.h
 254 +++ b/drivers/net/wireless/rt2x00/rt2800.h
 255 @@ -88,6 +88,7 @@
 256  #define REV_RT3071E                    0x0211
 257  #define REV_RT3090E                    0x0211
 258  #define REV_RT3390E                    0x0211
 259 +#define REV_RT3593E                    0x0211
 260  #define REV_RT5390F                    0x0502
 261  #define REV_RT5390R                    0x1502
 262  #define REV_RT5592C                    0x0221
 263 @@ -1082,6 +1083,15 @@
 264  #define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
 265  #define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
 266  #define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
 267 +/* bits for 3T devices */
 268 +#define TX_PWR_CFG_0_CCK1_CH0          FIELD32(0x0000000f)
 269 +#define TX_PWR_CFG_0_CCK1_CH1          FIELD32(0x000000f0)
 270 +#define TX_PWR_CFG_0_CCK5_CH0          FIELD32(0x00000f00)
 271 +#define TX_PWR_CFG_0_CCK5_CH1          FIELD32(0x0000f000)
 272 +#define TX_PWR_CFG_0_OFDM6_CH0         FIELD32(0x000f0000)
 273 +#define TX_PWR_CFG_0_OFDM6_CH1         FIELD32(0x00f00000)
 274 +#define TX_PWR_CFG_0_OFDM12_CH0                FIELD32(0x0f000000)
 275 +#define TX_PWR_CFG_0_OFDM12_CH1                FIELD32(0xf0000000)
 276
 277  /*
 278   * TX_PWR_CFG_1:
 279 @@ -1095,6 +1105,15 @@
 280  #define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
 281  #define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
 282  #define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
 283 +/* bits for 3T devices */
 284 +#define TX_PWR_CFG_1_OFDM24_CH0                FIELD32(0x0000000f)
 285 +#define TX_PWR_CFG_1_OFDM24_CH1                FIELD32(0x000000f0)
 286 +#define TX_PWR_CFG_1_OFDM48_CH0                FIELD32(0x00000f00)
 287 +#define TX_PWR_CFG_1_OFDM48_CH1                FIELD32(0x0000f000)
 288 +#define TX_PWR_CFG_1_MCS0_CH0          FIELD32(0x000f0000)
 289 +#define TX_PWR_CFG_1_MCS0_CH1          FIELD32(0x00f00000)
 290 +#define TX_PWR_CFG_1_MCS2_CH0          FIELD32(0x0f000000)
 291 +#define TX_PWR_CFG_1_MCS2_CH1          FIELD32(0xf0000000)
 292
 293  /*
 294   * TX_PWR_CFG_2:
 295 @@ -1108,6 +1127,15 @@
 296  #define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
 297  #define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
 298  #define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
 299 +/* bits for 3T devices */
 300 +#define TX_PWR_CFG_2_MCS4_CH0          FIELD32(0x0000000f)
 301 +#define TX_PWR_CFG_2_MCS4_CH1          FIELD32(0x000000f0)
 302 +#define TX_PWR_CFG_2_MCS6_CH0          FIELD32(0x00000f00)
 303 +#define TX_PWR_CFG_2_MCS6_CH1          FIELD32(0x0000f000)
 304 +#define TX_PWR_CFG_2_MCS8_CH0          FIELD32(0x000f0000)
 305 +#define TX_PWR_CFG_2_MCS8_CH1          FIELD32(0x00f00000)
 306 +#define TX_PWR_CFG_2_MCS10_CH0         FIELD32(0x0f000000)
 307 +#define TX_PWR_CFG_2_MCS10_CH1         FIELD32(0xf0000000)
 308
 309  /*
 310   * TX_PWR_CFG_3:
 311 @@ -1121,6 +1149,15 @@
 312  #define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
 313  #define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
 314  #define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
 315 +/* bits for 3T devices */
 316 +#define TX_PWR_CFG_3_MCS12_CH0         FIELD32(0x0000000f)
 317 +#define TX_PWR_CFG_3_MCS12_CH1         FIELD32(0x000000f0)
 318 +#define TX_PWR_CFG_3_MCS14_CH0         FIELD32(0x00000f00)
 319 +#define TX_PWR_CFG_3_MCS14_CH1         FIELD32(0x0000f000)
 320 +#define TX_PWR_CFG_3_STBC0_CH0         FIELD32(0x000f0000)
 321 +#define TX_PWR_CFG_3_STBC0_CH1         FIELD32(0x00f00000)
 322 +#define TX_PWR_CFG_3_STBC2_CH0         FIELD32(0x0f000000)
 323 +#define TX_PWR_CFG_3_STBC2_CH1         FIELD32(0xf0000000)
 324
 325  /*
 326   * TX_PWR_CFG_4:
 327 @@ -1130,6 +1167,11 @@
 328  #define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
 329  #define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
 330  #define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
 331 +/* bits for 3T devices */
 332 +#define TX_PWR_CFG_3_STBC4_CH0         FIELD32(0x0000000f)
 333 +#define TX_PWR_CFG_3_STBC4_CH1         FIELD32(0x000000f0)
 334 +#define TX_PWR_CFG_3_STBC6_CH0         FIELD32(0x00000f00)
 335 +#define TX_PWR_CFG_3_STBC6_CH1         FIELD32(0x0000f000)
 336
 337  /*
 338   * TX_PIN_CFG:
 339 @@ -1451,6 +1493,81 @@
 340   */
 341  #define EXP_ACK_TIME                   0x1380
 342
 343 +/* TX_PWR_CFG_5 */
 344 +#define TX_PWR_CFG_5                   0x1384
 345 +#define TX_PWR_CFG_5_MCS16_CH0         FIELD32(0x0000000f)
 346 +#define TX_PWR_CFG_5_MCS16_CH1         FIELD32(0x000000f0)
 347 +#define TX_PWR_CFG_5_MCS16_CH2         FIELD32(0x00000f00)
 348 +#define TX_PWR_CFG_5_MCS18_CH0         FIELD32(0x000f0000)
 349 +#define TX_PWR_CFG_5_MCS18_CH1         FIELD32(0x00f00000)
 350 +#define TX_PWR_CFG_5_MCS18_CH2         FIELD32(0x0f000000)
 351 +
 352 +/* TX_PWR_CFG_6 */
 353 +#define TX_PWR_CFG_6                   0x1388
 354 +#define TX_PWR_CFG_6_MCS20_CH0         FIELD32(0x0000000f)
 355 +#define TX_PWR_CFG_6_MCS20_CH1         FIELD32(0x000000f0)
 356 +#define TX_PWR_CFG_6_MCS20_CH2         FIELD32(0x00000f00)
 357 +#define TX_PWR_CFG_6_MCS22_CH0         FIELD32(0x000f0000)
 358 +#define TX_PWR_CFG_6_MCS22_CH1         FIELD32(0x00f00000)
 359 +#define TX_PWR_CFG_6_MCS22_CH2         FIELD32(0x0f000000)
 360 +
 361 +/* TX_PWR_CFG_0_EXT */
 362 +#define TX_PWR_CFG_0_EXT               0x1390
 363 +#define TX_PWR_CFG_0_EXT_CCK1_CH2      FIELD32(0x0000000f)
 364 +#define TX_PWR_CFG_0_EXT_CCK5_CH2      FIELD32(0x00000f00)
 365 +#define TX_PWR_CFG_0_EXT_OFDM6_CH2     FIELD32(0x000f0000)
 366 +#define TX_PWR_CFG_0_EXT_OFDM12_CH2    FIELD32(0x0f000000)
 367 +
 368 +/* TX_PWR_CFG_1_EXT */
 369 +#define TX_PWR_CFG_1_EXT               0x1394
 370 +#define TX_PWR_CFG_1_EXT_OFDM24_CH2    FIELD32(0x0000000f)
 371 +#define TX_PWR_CFG_1_EXT_OFDM48_CH2    FIELD32(0x00000f00)
 372 +#define TX_PWR_CFG_1_EXT_MCS0_CH2      FIELD32(0x000f0000)
 373 +#define TX_PWR_CFG_1_EXT_MCS2_CH2      FIELD32(0x0f000000)
 374 +
 375 +/* TX_PWR_CFG_2_EXT */
 376 +#define TX_PWR_CFG_2_EXT               0x1398
 377 +#define TX_PWR_CFG_2_EXT_MCS4_CH2      FIELD32(0x0000000f)
 378 +#define TX_PWR_CFG_2_EXT_MCS6_CH2      FIELD32(0x00000f00)
 379 +#define TX_PWR_CFG_2_EXT_MCS8_CH2      FIELD32(0x000f0000)
 380 +#define TX_PWR_CFG_2_EXT_MCS10_CH2     FIELD32(0x0f000000)
 381 +
 382 +/* TX_PWR_CFG_3_EXT */
 383 +#define TX_PWR_CFG_3_EXT               0x139c
 384 +#define TX_PWR_CFG_3_EXT_MCS12_CH2     FIELD32(0x0000000f)
 385 +#define TX_PWR_CFG_3_EXT_MCS14_CH2     FIELD32(0x00000f00)
 386 +#define TX_PWR_CFG_3_EXT_STBC0_CH2     FIELD32(0x000f0000)
 387 +#define TX_PWR_CFG_3_EXT_STBC2_CH2     FIELD32(0x0f000000)
 388 +
 389 +/* TX_PWR_CFG_4_EXT */
 390 +#define TX_PWR_CFG_4_EXT               0x13a0
 391 +#define TX_PWR_CFG_4_EXT_STBC4_CH2     FIELD32(0x0000000f)
 392 +#define TX_PWR_CFG_4_EXT_STBC6_CH2     FIELD32(0x00000f00)
 393 +
 394 +/* TX_PWR_CFG_7 */
 395 +#define TX_PWR_CFG_7                   0x13d4
 396 +#define TX_PWR_CFG_7_OFDM54_CH0                FIELD32(0x0000000f)
 397 +#define TX_PWR_CFG_7_OFDM54_CH1                FIELD32(0x000000f0)
 398 +#define TX_PWR_CFG_7_OFDM54_CH2                FIELD32(0x00000f00)
 399 +#define TX_PWR_CFG_7_MCS7_CH0          FIELD32(0x000f0000)
 400 +#define TX_PWR_CFG_7_MCS7_CH1          FIELD32(0x00f00000)
 401 +#define TX_PWR_CFG_7_MCS7_CH2          FIELD32(0x0f000000)
 402 +
 403 +/* TX_PWR_CFG_8 */
 404 +#define TX_PWR_CFG_8                   0x13d8
 405 +#define TX_PWR_CFG_8_MCS15_CH0         FIELD32(0x0000000f)
 406 +#define TX_PWR_CFG_8_MCS15_CH1         FIELD32(0x000000f0)
 407 +#define TX_PWR_CFG_8_MCS15_CH2         FIELD32(0x00000f00)
 408 +#define TX_PWR_CFG_8_MCS23_CH0         FIELD32(0x000f0000)
 409 +#define TX_PWR_CFG_8_MCS23_CH1         FIELD32(0x00f00000)
 410 +#define TX_PWR_CFG_8_MCS23_CH2         FIELD32(0x0f000000)
 411 +
 412 +/* TX_PWR_CFG_9 */
 413 +#define TX_PWR_CFG_9                   0x13dc
 414 +#define TX_PWR_CFG_9_STBC7_CH0         FIELD32(0x0000000f)
 415 +#define TX_PWR_CFG_9_STBC7_CH1         FIELD32(0x000000f0)
 416 +#define TX_PWR_CFG_9_STBC7_CH2         FIELD32(0x00000f00)
 417 +
 418  /*
 419   * RX_FILTER_CFG: RX configuration register.
 420   */
 421 @@ -1902,11 +2019,13 @@ struct mac_iveiv_entry {
 422  #define HW_BEACON_BASE6                        0x5dc0
 423  #define HW_BEACON_BASE7                        0x5bc0
 424
 425 -#define HW_BEACON_OFFSET(__index) \
 426 +#define HW_BEACON_BASE(__index) \
 427         (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
 428           (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
 429           (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
 430
 431 +#define BEACON_BASE_TO_OFFSET(_base)   (((_base) - 0x4000) / 64)
 432 +
 433  /*
 434   * BBP registers.
 435   * The wordsize of the BBP is 8 bits.
 436 @@ -1975,6 +2094,10 @@ struct mac_iveiv_entry {
 437  #define BBP109_TX0_POWER               FIELD8(0x0f)
 438  #define BBP109_TX1_POWER               FIELD8(0xf0)
 439
 440 +/* BBP 110 */
 441 +#define BBP110_TX2_POWER               FIELD8(0x0f)
 442 +
 443 +
 444  /*
 445   * BBP 138: Unknown
 446   */
 447 @@ -2024,6 +2147,12 @@ struct mac_iveiv_entry {
 448  #define RFCSR3_PA2_CASCODE_BIAS_CCKK   FIELD8(0x80)
 449  /* Bits for RF3290/RF5360/RF5370/RF5372/RF5390/RF5392 */
 450  #define RFCSR3_VCOCAL_EN               FIELD8(0x80)
 451 +/* Bits for RF3050 */
 452 +#define RFCSR3_BIT1                    FIELD8(0x02)
 453 +#define RFCSR3_BIT2                    FIELD8(0x04)
 454 +#define RFCSR3_BIT3                    FIELD8(0x08)
 455 +#define RFCSR3_BIT4                    FIELD8(0x10)
 456 +#define RFCSR3_BIT5                    FIELD8(0x20)
 457
 458  /*
 459   * FRCSR 5:
 460 @@ -2036,6 +2165,8 @@ struct mac_iveiv_entry {
 461  #define RFCSR6_R1                      FIELD8(0x03)
 462  #define RFCSR6_R2                      FIELD8(0x40)
 463  #define RFCSR6_TXDIV           FIELD8(0x0c)
 464 +/* bits for RF3053 */
 465 +#define RFCSR6_VCO_IC                  FIELD8(0xc0)
 466
 467  /*
 468   * RFCSR 7:
 469 @@ -2060,7 +2191,12 @@ struct mac_iveiv_entry {
 470   * RFCSR 11:
 471   */
 472  #define RFCSR11_R                      FIELD8(0x03)
 473 +#define RFCSR11_PLL_MOD                        FIELD8(0x0c)
 474  #define RFCSR11_MOD                    FIELD8(0xc0)
 475 +/* bits for RF3053 */
 476 +/* TODO: verify RFCSR11_MOD usage on other chips */
 477 +#define RFCSR11_PLL_IDOH               FIELD8(0x40)
 478 +
 479
 480  /*
 481   * RFCSR 12:
 482 @@ -2092,6 +2228,10 @@ struct mac_iveiv_entry {
 483  #define RFCSR17_R                      FIELD8(0x20)
 484  #define RFCSR17_CODE                   FIELD8(0x7f)
 485
 486 +/* RFCSR 18 */
 487 +#define RFCSR18_XO_TUNE_BYPASS         FIELD8(0x40)
 488 +
 489 +
 490  /*
 491   * RFCSR 20:
 492   */
 493 @@ -2152,6 +2292,12 @@ struct mac_iveiv_entry {
 494  #define RFCSR31_RX_H20M                        FIELD8(0x20)
 495  #define RFCSR31_RX_CALIB               FIELD8(0x7f)
 496
 497 +/* RFCSR 32 bits for RF3053 */
 498 +#define RFCSR32_TX_AGC_FC              FIELD8(0xf8)
 499 +
 500 +/* RFCSR 36 bits for RF3053 */
 501 +#define RFCSR36_RF_BS                  FIELD8(0x80)
 502 +
 503  /*
 504   * RFCSR 38:
 505   */
 506 @@ -2160,6 +2306,7 @@ struct mac_iveiv_entry {
 507  /*
 508   * RFCSR 39:
 509   */
 510 +#define RFCSR39_RX_DIV                 FIELD8(0x40)
 511  #define RFCSR39_RX_LO2_EN              FIELD8(0x80)
 512
 513  /*
 514 @@ -2167,12 +2314,36 @@ struct mac_iveiv_entry {
 515   */
 516  #define RFCSR49_TX                     FIELD8(0x3f)
 517  #define RFCSR49_EP                     FIELD8(0xc0)
 518 +/* bits for RT3593 */
 519 +#define RFCSR49_TX_LO1_IC              FIELD8(0x1c)
 520 +#define RFCSR49_TX_DIV                 FIELD8(0x20)
 521
 522  /*
 523   * RFCSR 50:
 524   */
 525  #define RFCSR50_TX                     FIELD8(0x3f)
 526  #define RFCSR50_EP                     FIELD8(0xc0)
 527 +/* bits for RT3593 */
 528 +#define RFCSR50_TX_LO1_EN              FIELD8(0x20)
 529 +#define RFCSR50_TX_LO2_EN              FIELD8(0x10)
 530 +
 531 +/* RFCSR 51 */
 532 +/* bits for RT3593 */
 533 +#define RFCSR51_BITS01                 FIELD8(0x03)
 534 +#define RFCSR51_BITS24                 FIELD8(0x1c)
 535 +#define RFCSR51_BITS57                 FIELD8(0xe0)
 536 +
 537 +#define RFCSR53_TX_POWER               FIELD8(0x3f)
 538 +#define RFCSR53_UNKNOWN                        FIELD8(0xc0)
 539 +
 540 +#define RFCSR54_TX_POWER               FIELD8(0x3f)
 541 +#define RFCSR54_UNKNOWN                        FIELD8(0xc0)
 542 +
 543 +#define RFCSR55_TX_POWER               FIELD8(0x3f)
 544 +#define RFCSR55_UNKNOWN                        FIELD8(0xc0)
 545 +
 546 +#define RFCSR57_DRV_CC                 FIELD8(0xfc)
 547 +
 548
 549  /*
 550   * RF registers
 551 @@ -2206,28 +2377,67 @@ struct mac_iveiv_entry {
 552   * The wordsize of the EEPROM is 16 bits.
 553   */
 554
 555 -/*
 556 - * Chip ID
 557 - */
 558 -#define EEPROM_CHIP_ID                 0x0000
 559 +enum rt2800_eeprom_word {
 560 +       EEPROM_CHIP_ID = 0,
 561 +       EEPROM_VERSION,
 562 +       EEPROM_MAC_ADDR_0,
 563 +       EEPROM_MAC_ADDR_1,
 564 +       EEPROM_MAC_ADDR_2,
 565 +       EEPROM_NIC_CONF0,
 566 +       EEPROM_NIC_CONF1,
 567 +       EEPROM_FREQ,
 568 +       EEPROM_LED_AG_CONF,
 569 +       EEPROM_LED_ACT_CONF,
 570 +       EEPROM_LED_POLARITY,
 571 +       EEPROM_NIC_CONF2,
 572 +       EEPROM_LNA,
 573 +       EEPROM_RSSI_BG,
 574 +       EEPROM_RSSI_BG2,
 575 +       EEPROM_TXMIXER_GAIN_BG,
 576 +       EEPROM_RSSI_A,
 577 +       EEPROM_RSSI_A2,
 578 +       EEPROM_TXMIXER_GAIN_A,
 579 +       EEPROM_EIRP_MAX_TX_POWER,
 580 +       EEPROM_TXPOWER_DELTA,
 581 +       EEPROM_TXPOWER_BG1,
 582 +       EEPROM_TXPOWER_BG2,
 583 +       EEPROM_TSSI_BOUND_BG1,
 584 +       EEPROM_TSSI_BOUND_BG2,
 585 +       EEPROM_TSSI_BOUND_BG3,
 586 +       EEPROM_TSSI_BOUND_BG4,
 587 +       EEPROM_TSSI_BOUND_BG5,
 588 +       EEPROM_TXPOWER_A1,
 589 +       EEPROM_TXPOWER_A2,
 590 +       EEPROM_TSSI_BOUND_A1,
 591 +       EEPROM_TSSI_BOUND_A2,
 592 +       EEPROM_TSSI_BOUND_A3,
 593 +       EEPROM_TSSI_BOUND_A4,
 594 +       EEPROM_TSSI_BOUND_A5,
 595 +       EEPROM_TXPOWER_BYRATE,
 596 +       EEPROM_BBP_START,
 597 +
 598 +       /* IDs for extended EEPROM format used by three-chain devices */
 599 +       EEPROM_EXT_LNA2,
 600 +       EEPROM_EXT_TXPOWER_BG3,
 601 +       EEPROM_EXT_TXPOWER_A3,
 602 +
 603 +       /* New values must be added before this */
 604 +       EEPROM_WORD_COUNT
 605 +};
 606
 607  /*
 608   * EEPROM Version
 609   */
 610 -#define EEPROM_VERSION                 0x0001
 611  #define EEPROM_VERSION_FAE             FIELD16(0x00ff)
 612  #define EEPROM_VERSION_VERSION         FIELD16(0xff00)
 613
 614  /*
 615   * HW MAC address.
 616   */
 617 -#define EEPROM_MAC_ADDR_0              0x0002
 618  #define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
 619  #define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
 620 -#define EEPROM_MAC_ADDR_1              0x0003
 621  #define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
 622  #define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
 623 -#define EEPROM_MAC_ADDR_2              0x0004
 624  #define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
 625  #define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
 626
 627 @@ -2237,7 +2447,6 @@ struct mac_iveiv_entry {
 628   * TXPATH: 1: 1T, 2: 2T, 3: 3T
 629   * RF_TYPE: RFIC type
 630   */
 631 -#define        EEPROM_NIC_CONF0                0x001a
 632  #define EEPROM_NIC_CONF0_RXPATH                FIELD16(0x000f)
 633  #define EEPROM_NIC_CONF0_TXPATH                FIELD16(0x00f0)
 634  #define EEPROM_NIC_CONF0_RF_TYPE               FIELD16(0x0f00)
 635 @@ -2261,7 +2470,6 @@ struct mac_iveiv_entry {
 636   * BT_COEXIST: 0: disable, 1: enable
 637   * DAC_TEST: 0: disable, 1: enable
 638   */
 639 -#define        EEPROM_NIC_CONF1                0x001b
 640  #define EEPROM_NIC_CONF1_HW_RADIO              FIELD16(0x0001)
 641  #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC               FIELD16(0x0002)
 642  #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G               FIELD16(0x0004)
 643 @@ -2281,7 +2489,6 @@ struct mac_iveiv_entry {
 644  /*
 645   * EEPROM frequency
 646   */
 647 -#define        EEPROM_FREQ                     0x001d
 648  #define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
 649  #define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
 650  #define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
 651 @@ -2298,9 +2505,6 @@ struct mac_iveiv_entry {
 652   * POLARITY_GPIO_4: Polarity GPIO4 setting.
 653   * LED_MODE: Led mode.
 654   */
 655 -#define EEPROM_LED_AG_CONF             0x001e
 656 -#define EEPROM_LED_ACT_CONF            0x001f
 657 -#define EEPROM_LED_POLARITY            0x0020
 658  #define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
 659  #define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
 660  #define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
 661 @@ -2317,7 +2521,6 @@ struct mac_iveiv_entry {
 662   * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
 663   * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
 664   */
 665 -#define EEPROM_NIC_CONF2               0x0021
 666  #define EEPROM_NIC_CONF2_RX_STREAM             FIELD16(0x000f)
 667  #define EEPROM_NIC_CONF2_TX_STREAM             FIELD16(0x00f0)
 668  #define EEPROM_NIC_CONF2_CRYSTAL               FIELD16(0x0600)
 669 @@ -2325,54 +2528,46 @@ struct mac_iveiv_entry {
 670  /*
 671   * EEPROM LNA
 672   */
 673 -#define EEPROM_LNA                     0x0022
 674  #define EEPROM_LNA_BG                  FIELD16(0x00ff)
 675  #define EEPROM_LNA_A0                  FIELD16(0xff00)
 676
 677  /*
 678   * EEPROM RSSI BG offset
 679   */
 680 -#define EEPROM_RSSI_BG                 0x0023
 681  #define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
 682  #define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
 683
 684  /*
 685   * EEPROM RSSI BG2 offset
 686   */
 687 -#define EEPROM_RSSI_BG2                        0x0024
 688  #define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
 689  #define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
 690
 691  /*
 692   * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
 693   */
 694 -#define EEPROM_TXMIXER_GAIN_BG         0x0024
 695  #define EEPROM_TXMIXER_GAIN_BG_VAL     FIELD16(0x0007)
 696
 697  /*
 698   * EEPROM RSSI A offset
 699   */
 700 -#define EEPROM_RSSI_A                  0x0025
 701  #define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
 702  #define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
 703
 704  /*
 705   * EEPROM RSSI A2 offset
 706   */
 707 -#define EEPROM_RSSI_A2                 0x0026
 708  #define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
 709  #define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
 710
 711  /*
 712   * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
 713   */
 714 -#define EEPROM_TXMIXER_GAIN_A          0x0026
 715  #define EEPROM_TXMIXER_GAIN_A_VAL      FIELD16(0x0007)
 716
 717  /*
 718   * EEPROM EIRP Maximum TX power values(unit: dbm)
 719   */
 720 -#define EEPROM_EIRP_MAX_TX_POWER       0x0027
 721  #define EEPROM_EIRP_MAX_TX_POWER_2GHZ  FIELD16(0x00ff)
 722  #define EEPROM_EIRP_MAX_TX_POWER_5GHZ  FIELD16(0xff00)
 723
 724 @@ -2383,7 +2578,6 @@ struct mac_iveiv_entry {
 725   * TYPE: 1: Plus the delta value, 0: minus the delta value
 726   * ENABLE: enable tx power compensation for 40BW
 727   */
 728 -#define EEPROM_TXPOWER_DELTA           0x0028
 729  #define EEPROM_TXPOWER_DELTA_VALUE_2G  FIELD16(0x003f)
 730  #define EEPROM_TXPOWER_DELTA_TYPE_2G   FIELD16(0x0040)
 731  #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
 732 @@ -2394,8 +2588,6 @@ struct mac_iveiv_entry {
 733  /*
 734   * EEPROM TXPOWER 802.11BG
 735   */
 736 -#define        EEPROM_TXPOWER_BG1              0x0029
 737 -#define        EEPROM_TXPOWER_BG2              0x0030
 738  #define EEPROM_TXPOWER_BG_SIZE         7
 739  #define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
 740  #define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
 741 @@ -2407,7 +2599,6 @@ struct mac_iveiv_entry {
 742   * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
 743   *         reduced by (agc_step * -3)
 744   */
 745 -#define EEPROM_TSSI_BOUND_BG1          0x0037
 746  #define EEPROM_TSSI_BOUND_BG1_MINUS4   FIELD16(0x00ff)
 747  #define EEPROM_TSSI_BOUND_BG1_MINUS3   FIELD16(0xff00)
 748
 749 @@ -2418,7 +2609,6 @@ struct mac_iveiv_entry {
 750   * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
 751   *         reduced by (agc_step * -1)
 752   */
 753 -#define EEPROM_TSSI_BOUND_BG2          0x0038
 754  #define EEPROM_TSSI_BOUND_BG2_MINUS2   FIELD16(0x00ff)
 755  #define EEPROM_TSSI_BOUND_BG2_MINUS1   FIELD16(0xff00)
 756
 757 @@ -2428,7 +2618,6 @@ struct mac_iveiv_entry {
 758   * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
 759   *        increased by (agc_step * 1)
 760   */
 761 -#define EEPROM_TSSI_BOUND_BG3          0x0039
 762  #define EEPROM_TSSI_BOUND_BG3_REF      FIELD16(0x00ff)
 763  #define EEPROM_TSSI_BOUND_BG3_PLUS1    FIELD16(0xff00)
 764
 765 @@ -2439,7 +2628,6 @@ struct mac_iveiv_entry {
 766   * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
 767   *        increased by (agc_step * 3)
 768   */
 769 -#define EEPROM_TSSI_BOUND_BG4          0x003a
 770  #define EEPROM_TSSI_BOUND_BG4_PLUS2    FIELD16(0x00ff)
 771  #define EEPROM_TSSI_BOUND_BG4_PLUS3    FIELD16(0xff00)
 772
 773 @@ -2449,19 +2637,20 @@ struct mac_iveiv_entry {
 774   *        increased by (agc_step * 4)
 775   * AGC_STEP: Temperature compensation step.
 776   */
 777 -#define EEPROM_TSSI_BOUND_BG5          0x003b
 778  #define EEPROM_TSSI_BOUND_BG5_PLUS4    FIELD16(0x00ff)
 779  #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
 780
 781  /*
 782   * EEPROM TXPOWER 802.11A
 783   */
 784 -#define EEPROM_TXPOWER_A1              0x003c
 785 -#define EEPROM_TXPOWER_A2              0x0053
 786  #define EEPROM_TXPOWER_A_SIZE          6
 787  #define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
 788  #define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
 789
 790 +/* EEPROM_TXPOWER_{A,G} fields for RT3593 */
 791 +#define EEPROM_TXPOWER_ALC             FIELD8(0x1f)
 792 +#define EEPROM_TXPOWER_FINE_CTRL       FIELD8(0xe0)
 793 +
 794  /*
 795   * EEPROM temperature compensation boundaries 802.11A
 796   * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
 797 @@ -2469,7 +2658,6 @@ struct mac_iveiv_entry {
 798   * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
 799   *         reduced by (agc_step * -3)
 800   */
 801 -#define EEPROM_TSSI_BOUND_A1           0x006a
 802  #define EEPROM_TSSI_BOUND_A1_MINUS4    FIELD16(0x00ff)
 803  #define EEPROM_TSSI_BOUND_A1_MINUS3    FIELD16(0xff00)
 804
 805 @@ -2480,7 +2668,6 @@ struct mac_iveiv_entry {
 806   * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
 807   *         reduced by (agc_step * -1)
 808   */
 809 -#define EEPROM_TSSI_BOUND_A2           0x006b
 810  #define EEPROM_TSSI_BOUND_A2_MINUS2    FIELD16(0x00ff)
 811  #define EEPROM_TSSI_BOUND_A2_MINUS1    FIELD16(0xff00)
 812
 813 @@ -2490,7 +2677,6 @@ struct mac_iveiv_entry {
 814   * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
 815   *        increased by (agc_step * 1)
 816   */
 817 -#define EEPROM_TSSI_BOUND_A3           0x006c
 818  #define EEPROM_TSSI_BOUND_A3_REF       FIELD16(0x00ff)
 819  #define EEPROM_TSSI_BOUND_A3_PLUS1     FIELD16(0xff00)
 820
 821 @@ -2501,7 +2687,6 @@ struct mac_iveiv_entry {
 822   * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
 823   *        increased by (agc_step * 3)
 824   */
 825 -#define EEPROM_TSSI_BOUND_A4           0x006d
 826  #define EEPROM_TSSI_BOUND_A4_PLUS2     FIELD16(0x00ff)
 827  #define EEPROM_TSSI_BOUND_A4_PLUS3     FIELD16(0xff00)
 828
 829 @@ -2511,14 +2696,12 @@ struct mac_iveiv_entry {
 830   *        increased by (agc_step * 4)
 831   * AGC_STEP: Temperature compensation step.
 832   */
 833 -#define EEPROM_TSSI_BOUND_A5           0x006e
 834  #define EEPROM_TSSI_BOUND_A5_PLUS4     FIELD16(0x00ff)
 835  #define EEPROM_TSSI_BOUND_A5_AGC_STEP  FIELD16(0xff00)
 836
 837  /*
 838   * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
 839   */
 840 -#define EEPROM_TXPOWER_BYRATE          0x006f
 841  #define EEPROM_TXPOWER_BYRATE_SIZE     9
 842
 843  #define EEPROM_TXPOWER_BYRATE_RATE0    FIELD16(0x000f)
 844 @@ -2529,11 +2712,14 @@ struct mac_iveiv_entry {
 845  /*
 846   * EEPROM BBP.
 847   */
 848 -#define        EEPROM_BBP_START                0x0078
 849  #define EEPROM_BBP_SIZE                        16
 850  #define EEPROM_BBP_VALUE               FIELD16(0x00ff)
 851  #define EEPROM_BBP_REG_ID              FIELD16(0xff00)
 852
 853 +/* EEPROM_EXT_LNA2 */
 854 +#define EEPROM_EXT_LNA2_A1             FIELD16(0x00ff)
 855 +#define EEPROM_EXT_LNA2_A2             FIELD16(0xff00)
 856 +
 857  /*
 858   * EEPROM IQ Calibration, unlike other entries those are byte addresses.
 859   */
 860 @@ -2610,6 +2796,7 @@ struct mac_iveiv_entry {
 861  #define MCU_RADAR                      0x60
 862  #define MCU_BOOT_SIGNAL                        0x72
 863  #define MCU_ANT_SELECT                 0X73
 864 +#define MCU_FREQ_OFFSET                        0x74
 865  #define MCU_BBP_SIGNAL                 0x80
 866  #define MCU_POWER_SAVE                 0x83
 867  #define MCU_BAND_SELECT                0x91
 868 @@ -2630,6 +2817,7 @@ struct mac_iveiv_entry {
 869  #define TXWI_DESC_SIZE_5WORDS          (5 * sizeof(__le32))
 870
 871  #define RXWI_DESC_SIZE_4WORDS          (4 * sizeof(__le32))
 872 +#define RXWI_DESC_SIZE_5WORDS          (5 * sizeof(__le32))
 873  #define RXWI_DESC_SIZE_6WORDS          (6 * sizeof(__le32))
 874
 875  /*
 876 @@ -2750,18 +2938,15 @@ struct mac_iveiv_entry {
 877  #define MAX_A_TXPOWER  15
 878  #define DEFAULT_TXPOWER        5
 879
 880 +#define MIN_A_TXPOWER_3593     0
 881 +#define MAX_A_TXPOWER_3593     31
 882 +
 883  #define TXPOWER_G_FROM_DEV(__txpower) \
 884         ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
 885
 886 -#define TXPOWER_G_TO_DEV(__txpower) \
 887 -       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
 888 -
 889  #define TXPOWER_A_FROM_DEV(__txpower) \
 890         ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
 891
 892 -#define TXPOWER_A_TO_DEV(__txpower) \
 893 -       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
 894 -
 895  /*
 896   *  Board's maximun TX power limitation
 897   */
 898 --- a/drivers/net/wireless/rt2x00/rt2800lib.c
 899 +++ b/drivers/net/wireless/rt2x00/rt2800lib.c
 900 @@ -221,6 +221,157 @@ static void rt2800_rf_write(struct rt2x0
 901         mutex_unlock(&rt2x00dev->csr_mutex);
 902  }
 903
 904 +static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 905 +       [EEPROM_CHIP_ID]                = 0x0000,
 906 +       [EEPROM_VERSION]                = 0x0001,
 907 +       [EEPROM_MAC_ADDR_0]             = 0x0002,
 908 +       [EEPROM_MAC_ADDR_1]             = 0x0003,
 909 +       [EEPROM_MAC_ADDR_2]             = 0x0004,
 910 +       [EEPROM_NIC_CONF0]              = 0x001a,
 911 +       [EEPROM_NIC_CONF1]              = 0x001b,
 912 +       [EEPROM_FREQ]                   = 0x001d,
 913 +       [EEPROM_LED_AG_CONF]            = 0x001e,
 914 +       [EEPROM_LED_ACT_CONF]           = 0x001f,
 915 +       [EEPROM_LED_POLARITY]           = 0x0020,
 916 +       [EEPROM_NIC_CONF2]              = 0x0021,
 917 +       [EEPROM_LNA]                    = 0x0022,
 918 +       [EEPROM_RSSI_BG]                = 0x0023,
 919 +       [EEPROM_RSSI_BG2]               = 0x0024,
 920 +       [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 921 +       [EEPROM_RSSI_A]                 = 0x0025,
 922 +       [EEPROM_RSSI_A2]                = 0x0026,
 923 +       [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 924 +       [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 925 +       [EEPROM_TXPOWER_DELTA]          = 0x0028,
 926 +       [EEPROM_TXPOWER_BG1]            = 0x0029,
 927 +       [EEPROM_TXPOWER_BG2]            = 0x0030,
 928 +       [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 929 +       [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 930 +       [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 931 +       [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 932 +       [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 933 +       [EEPROM_TXPOWER_A1]             = 0x003c,
 934 +       [EEPROM_TXPOWER_A2]             = 0x0053,
 935 +       [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 936 +       [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 937 +       [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 938 +       [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 939 +       [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 940 +       [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 941 +       [EEPROM_BBP_START]              = 0x0078,
 942 +};
 943 +
 944 +static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 945 +       [EEPROM_CHIP_ID]                = 0x0000,
 946 +       [EEPROM_VERSION]                = 0x0001,
 947 +       [EEPROM_MAC_ADDR_0]             = 0x0002,
 948 +       [EEPROM_MAC_ADDR_1]             = 0x0003,
 949 +       [EEPROM_MAC_ADDR_2]             = 0x0004,
 950 +       [EEPROM_NIC_CONF0]              = 0x001a,
 951 +       [EEPROM_NIC_CONF1]              = 0x001b,
 952 +       [EEPROM_NIC_CONF2]              = 0x001c,
 953 +       [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 954 +       [EEPROM_FREQ]                   = 0x0022,
 955 +       [EEPROM_LED_AG_CONF]            = 0x0023,
 956 +       [EEPROM_LED_ACT_CONF]           = 0x0024,
 957 +       [EEPROM_LED_POLARITY]           = 0x0025,
 958 +       [EEPROM_LNA]                    = 0x0026,
 959 +       [EEPROM_EXT_LNA2]               = 0x0027,
 960 +       [EEPROM_RSSI_BG]                = 0x0028,
 961 +       [EEPROM_TXPOWER_DELTA]          = 0x0028, /* Overlaps with RSSI_BG */
 962 +       [EEPROM_RSSI_BG2]               = 0x0029,
 963 +       [EEPROM_TXMIXER_GAIN_BG]        = 0x0029, /* Overlaps with RSSI_BG2 */
 964 +       [EEPROM_RSSI_A]                 = 0x002a,
 965 +       [EEPROM_RSSI_A2]                = 0x002b,
 966 +       [EEPROM_TXMIXER_GAIN_A]         = 0x002b, /* Overlaps with RSSI_A2 */
 967 +       [EEPROM_TXPOWER_BG1]            = 0x0030,
 968 +       [EEPROM_TXPOWER_BG2]            = 0x0037,
 969 +       [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 970 +       [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 971 +       [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 972 +       [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 973 +       [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 974 +       [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 975 +       [EEPROM_TXPOWER_A1]             = 0x004b,
 976 +       [EEPROM_TXPOWER_A2]             = 0x0065,
 977 +       [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 978 +       [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 979 +       [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 980 +       [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 981 +       [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 982 +       [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 983 +       [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 984 +};
 985 +
 986 +static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 987 +                                            const enum rt2800_eeprom_word word)
 988 +{
 989 +       const unsigned int *map;
 990 +       unsigned int index;
 991 +
 992 +       if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 993 +                     "%s: invalid EEPROM word %d\n",
 994 +                     wiphy_name(rt2x00dev->hw->wiphy), word))
 995 +               return 0;
 996 +
 997 +       if (rt2x00_rt(rt2x00dev, RT3593))
 998 +               map = rt2800_eeprom_map_ext;
 999 +       else
1000 +               map = rt2800_eeprom_map;
1001 +
1002 +       index = map[word];
1003 +
1004 +       /* Index 0 is valid only for EEPROM_CHIP_ID.
1005 +        * Otherwise it means that the offset of the
1006 +        * given word is not initialized in the map,
1007 +        * or that the field is not usable on the
1008 +        * actual chipset.
1009 +        */
1010 +       WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
1011 +                 "%s: invalid access of EEPROM word %d\n",
1012 +                 wiphy_name(rt2x00dev->hw->wiphy), word);
1013 +
1014 +       return index;
1015 +}
1016 +
1017 +static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
1018 +                               const enum rt2800_eeprom_word word)
1019 +{
1020 +       unsigned int index;
1021 +
1022 +       index = rt2800_eeprom_word_index(rt2x00dev, word);
1023 +       return rt2x00_eeprom_addr(rt2x00dev, index);
1024 +}
1025 +
1026 +static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
1027 +                              const enum rt2800_eeprom_word word, u16 *data)
1028 +{
1029 +       unsigned int index;
1030 +
1031 +       index = rt2800_eeprom_word_index(rt2x00dev, word);
1032 +       rt2x00_eeprom_read(rt2x00dev, index, data);
1033 +}
1034 +
1035 +static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
1036 +                               const enum rt2800_eeprom_word word, u16 data)
1037 +{
1038 +       unsigned int index;
1039 +
1040 +       index = rt2800_eeprom_word_index(rt2x00dev, word);
1041 +       rt2x00_eeprom_write(rt2x00dev, index, data);
1042 +}
1043 +
1044 +static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
1045 +                                         const enum rt2800_eeprom_word array,
1046 +                                         unsigned int offset,
1047 +                                         u16 *data)
1048 +{
1049 +       unsigned int index;
1050 +
1051 +       index = rt2800_eeprom_word_index(rt2x00dev, array);
1052 +       rt2x00_eeprom_read(rt2x00dev, index + offset, data);
1053 +}
1054 +
1055  static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
1056  {
1057         u32 reg;
1058 @@ -370,6 +521,29 @@ void rt2800_disable_wpdma(struct rt2x00_
1059  }
1060  EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
1061
1062 +void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
1063 +                              unsigned short *txwi_size,
1064 +                              unsigned short *rxwi_size)
1065 +{
1066 +       switch (rt2x00dev->chip.rt) {
1067 +       case RT3593:
1068 +               *txwi_size = TXWI_DESC_SIZE_4WORDS;
1069 +               *rxwi_size = RXWI_DESC_SIZE_5WORDS;
1070 +               break;
1071 +
1072 +       case RT5592:
1073 +               *txwi_size = TXWI_DESC_SIZE_5WORDS;
1074 +               *rxwi_size = RXWI_DESC_SIZE_6WORDS;
1075 +               break;
1076 +
1077 +       default:
1078 +               *txwi_size = TXWI_DESC_SIZE_4WORDS;
1079 +               *rxwi_size = RXWI_DESC_SIZE_4WORDS;
1080 +               break;
1081 +       }
1082 +}
1083 +EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
1084 +
1085  static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
1086  {
1087         u16 fw_crc;
1088 @@ -609,16 +783,16 @@ static int rt2800_agc_to_rssi(struct rt2
1089         u8 offset2;
1090
1091         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1092 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
1093 +               rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
1094                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
1095                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
1096 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1097 +               rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1098                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
1099         } else {
1100 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
1101 +               rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
1102                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
1103                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
1104 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1105 +               rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1106                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
1107         }
1108
1109 @@ -766,6 +940,18 @@ void rt2800_txdone_entry(struct queue_en
1110  }
1111  EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1112
1113 +static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1114 +                                         unsigned int index)
1115 +{
1116 +       return HW_BEACON_BASE(index);
1117 +}
1118 +
1119 +static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1120 +                                         unsigned int index)
1121 +{
1122 +       return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1123 +}
1124 +
1125  void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1126  {
1127         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1128 @@ -818,7 +1004,8 @@ void rt2800_write_beacon(struct queue_en
1129                 return;
1130         }
1131
1132 -       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1133 +       beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1134 +
1135         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1136                                    entry->skb->len + padding_len);
1137
1138 @@ -837,10 +1024,13 @@ void rt2800_write_beacon(struct queue_en
1139  EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1140
1141  static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1142 -                                               unsigned int beacon_base)
1143 +                                               unsigned int index)
1144  {
1145         int i;
1146         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1147 +       unsigned int beacon_base;
1148 +
1149 +       beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1150
1151         /*
1152          * For the Beacon base registers we only need to clear
1153 @@ -867,8 +1057,7 @@ void rt2800_clear_beacon(struct queue_en
1154         /*
1155          * Clear beacon.
1156          */
1157 -       rt2800_clear_beacon_register(rt2x00dev,
1158 -                                    HW_BEACON_OFFSET(entry->entry_idx));
1159 +       rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1160
1161         /*
1162          * Enabled beaconing again.
1163 @@ -890,6 +1079,9 @@ const struct rt2x00debug rt2800_rt2x00de
1164                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1165         },
1166         .eeprom = {
1167 +               /* NOTE: The local EEPROM access functions can't
1168 +                * be used here, use the generic versions instead.
1169 +                */
1170                 .read           = rt2x00_eeprom_read,
1171                 .write          = rt2x00_eeprom_write,
1172                 .word_base      = EEPROM_BASE,
1173 @@ -1547,7 +1739,7 @@ static void rt2800_config_3572bt_ant(str
1174         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1175         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1176             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1177 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1178 +               rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1179                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1180                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1181                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1182 @@ -1609,7 +1801,7 @@ void rt2800_config_ant(struct rt2x00_dev
1183                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1184                 break;
1185         case 3:
1186 -               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1187 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1188                 break;
1189         }
1190
1191 @@ -1622,7 +1814,7 @@ void rt2800_config_ant(struct rt2x00_dev
1192                     rt2x00_rt(rt2x00dev, RT3090) ||
1193                     rt2x00_rt(rt2x00dev, RT3352) ||
1194                     rt2x00_rt(rt2x00dev, RT3390)) {
1195 -                       rt2x00_eeprom_read(rt2x00dev,
1196 +                       rt2800_eeprom_read(rt2x00dev,
1197                                            EEPROM_NIC_CONF1, &eeprom);
1198                         if (rt2x00_get_field16(eeprom,
1199                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1200 @@ -1649,6 +1841,13 @@ void rt2800_config_ant(struct rt2x00_dev
1201
1202         rt2800_bbp_write(rt2x00dev, 3, r3);
1203         rt2800_bbp_write(rt2x00dev, 1, r1);
1204 +
1205 +       if (rt2x00_rt(rt2x00dev, RT3593)) {
1206 +               if (ant->rx_chain_num == 1)
1207 +                       rt2800_bbp_write(rt2x00dev, 86, 0x00);
1208 +               else
1209 +                       rt2800_bbp_write(rt2x00dev, 86, 0x46);
1210 +       }
1211  }
1212  EXPORT_SYMBOL_GPL(rt2800_config_ant);
1213
1214 @@ -1659,22 +1858,73 @@ static void rt2800_config_lna_gain(struc
1215         short lna_gain;
1216
1217         if (libconf->rf.channel <= 14) {
1218 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1219 +               rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1220                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1221         } else if (libconf->rf.channel <= 64) {
1222 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1223 +               rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1224                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1225         } else if (libconf->rf.channel <= 128) {
1226 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1227 -               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1228 +               if (rt2x00_rt(rt2x00dev, RT3593)) {
1229 +                       rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1230 +                       lna_gain = rt2x00_get_field16(eeprom,
1231 +                                                     EEPROM_EXT_LNA2_A1);
1232 +               } else {
1233 +                       rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1234 +                       lna_gain = rt2x00_get_field16(eeprom,
1235 +                                                     EEPROM_RSSI_BG2_LNA_A1);
1236 +               }
1237         } else {
1238 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1239 -               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1240 +               if (rt2x00_rt(rt2x00dev, RT3593)) {
1241 +                       rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1242 +                       lna_gain = rt2x00_get_field16(eeprom,
1243 +                                                     EEPROM_EXT_LNA2_A2);
1244 +               } else {
1245 +                       rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1246 +                       lna_gain = rt2x00_get_field16(eeprom,
1247 +                                                     EEPROM_RSSI_A2_LNA_A2);
1248 +               }
1249         }
1250
1251         rt2x00dev->lna_gain = lna_gain;
1252  }
1253
1254 +#define FREQ_OFFSET_BOUND      0x5f
1255 +
1256 +static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1257 +{
1258 +       u8 freq_offset, prev_freq_offset;
1259 +       u8 rfcsr, prev_rfcsr;
1260 +
1261 +       freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1262 +       freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1263 +
1264 +       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1265 +       prev_rfcsr = rfcsr;
1266 +
1267 +       rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1268 +       if (rfcsr == prev_rfcsr)
1269 +               return;
1270 +
1271 +       if (rt2x00_is_usb(rt2x00dev)) {
1272 +               rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1273 +                                  freq_offset, prev_rfcsr);
1274 +               return;
1275 +       }
1276 +
1277 +       prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1278 +       while (prev_freq_offset != freq_offset) {
1279 +               if (prev_freq_offset < freq_offset)
1280 +                       prev_freq_offset++;
1281 +               else
1282 +                       prev_freq_offset--;
1283 +
1284 +               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1285 +               rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1286 +
1287 +               usleep_range(1000, 1500);
1288 +       }
1289 +}
1290 +
1291  static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1292                                          struct ieee80211_conf *conf,
1293                                          struct rf_channel *rf,
1294 @@ -1993,22 +2243,306 @@ static void rt2800_config_channel_rf3052
1295         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1296  }
1297
1298 -#define POWER_BOUND            0x27
1299 -#define POWER_BOUND_5G         0x2b
1300 -#define FREQ_OFFSET_BOUND      0x5f
1301 -
1302 -static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1303 +static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
1304 +                                        struct ieee80211_conf *conf,
1305 +                                        struct rf_channel *rf,
1306 +                                        struct channel_info *info)
1307  {
1308 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1309 +       u8 txrx_agc_fc;
1310 +       u8 txrx_h20m;
1311         u8 rfcsr;
1312 +       u8 bbp;
1313 +       const bool txbf_enabled = false; /* TODO */
1314
1315 -       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1316 -       if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
1317 -               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
1318 +       /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
1319 +       rt2800_bbp_read(rt2x00dev, 109, &bbp);
1320 +       rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
1321 +       rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
1322 +       rt2800_bbp_write(rt2x00dev, 109, bbp);
1323 +
1324 +       rt2800_bbp_read(rt2x00dev, 110, &bbp);
1325 +       rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
1326 +       rt2800_bbp_write(rt2x00dev, 110, bbp);
1327 +
1328 +       if (rf->channel <= 14) {
1329 +               /* Restore BBP 25 & 26 for 2.4 GHz */
1330 +               rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1331 +               rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1332 +       } else {
1333 +               /* Hard code BBP 25 & 26 for 5GHz */
1334 +
1335 +               /* Enable IQ Phase correction */
1336 +               rt2800_bbp_write(rt2x00dev, 25, 0x09);
1337 +               /* Setup IQ Phase correction value */
1338 +               rt2800_bbp_write(rt2x00dev, 26, 0xff);
1339 +       }
1340 +
1341 +       rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1342 +       rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
1343 +
1344 +       rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1345 +       rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
1346 +       rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1347 +
1348 +       rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1349 +       rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
1350 +       if (rf->channel <= 14)
1351 +               rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
1352         else
1353 -               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1354 -       rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1355 +               rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
1356 +       rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1357 +
1358 +       rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
1359 +       if (rf->channel <= 14) {
1360 +               rfcsr = 0;
1361 +               rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
1362 +                                 info->default_power1 & 0x1f);
1363 +       } else {
1364 +               if (rt2x00_is_usb(rt2x00dev))
1365 +                       rfcsr = 0x40;
1366 +
1367 +               rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
1368 +                                 ((info->default_power1 & 0x18) << 1) |
1369 +                                 (info->default_power1 & 7));
1370 +       }
1371 +       rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
1372 +
1373 +       rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
1374 +       if (rf->channel <= 14) {
1375 +               rfcsr = 0;
1376 +               rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
1377 +                                 info->default_power2 & 0x1f);
1378 +       } else {
1379 +               if (rt2x00_is_usb(rt2x00dev))
1380 +                       rfcsr = 0x40;
1381 +
1382 +               rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
1383 +                                 ((info->default_power2 & 0x18) << 1) |
1384 +                                 (info->default_power2 & 7));
1385 +       }
1386 +       rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
1387 +
1388 +       rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
1389 +       if (rf->channel <= 14) {
1390 +               rfcsr = 0;
1391 +               rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
1392 +                                 info->default_power3 & 0x1f);
1393 +       } else {
1394 +               if (rt2x00_is_usb(rt2x00dev))
1395 +                       rfcsr = 0x40;
1396 +
1397 +               rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
1398 +                                 ((info->default_power3 & 0x18) << 1) |
1399 +                                 (info->default_power3 & 7));
1400 +       }
1401 +       rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
1402 +
1403 +       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1404 +       rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1405 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1406 +       rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1407 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1408 +       rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1409 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1410 +       rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1411 +       rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1412 +
1413 +       switch (rt2x00dev->default_ant.tx_chain_num) {
1414 +       case 3:
1415 +               rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1416 +               /* fallthrough */
1417 +       case 2:
1418 +               rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1419 +               /* fallthrough */
1420 +       case 1:
1421 +               rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1422 +               break;
1423 +       }
1424 +
1425 +       switch (rt2x00dev->default_ant.rx_chain_num) {
1426 +       case 3:
1427 +               rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1428 +               /* fallthrough */
1429 +       case 2:
1430 +               rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1431 +               /* fallthrough */
1432 +       case 1:
1433 +               rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1434 +               break;
1435 +       }
1436 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1437 +
1438 +       rt2800_adjust_freq_offset(rt2x00dev);
1439 +
1440 +       if (conf_is_ht40(conf)) {
1441 +               txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
1442 +                                               RFCSR24_TX_AGC_FC);
1443 +               txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
1444 +                                             RFCSR24_TX_H20M);
1445 +       } else {
1446 +               txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
1447 +                                               RFCSR24_TX_AGC_FC);
1448 +               txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
1449 +                                             RFCSR24_TX_H20M);
1450 +       }
1451 +
1452 +       /* NOTE: the reference driver does not writes the new value
1453 +        * back to RFCSR 32
1454 +        */
1455 +       rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
1456 +       rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
1457 +
1458 +       if (rf->channel <= 14)
1459 +               rfcsr = 0xa0;
1460 +       else
1461 +               rfcsr = 0x80;
1462 +       rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1463 +
1464 +       rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1465 +       rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
1466 +       rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
1467 +       rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1468 +
1469 +       /* Band selection */
1470 +       rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
1471 +       if (rf->channel <= 14)
1472 +               rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
1473 +       else
1474 +               rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
1475 +       rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
1476 +
1477 +       rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
1478 +       if (rf->channel <= 14)
1479 +               rfcsr = 0x3c;
1480 +       else
1481 +               rfcsr = 0x20;
1482 +       rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
1483 +
1484 +       rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1485 +       if (rf->channel <= 14)
1486 +               rfcsr = 0x1a;
1487 +       else
1488 +               rfcsr = 0x12;
1489 +       rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1490 +
1491 +       rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1492 +       if (rf->channel >= 1 && rf->channel <= 14)
1493 +               rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
1494 +       else if (rf->channel >= 36 && rf->channel <= 64)
1495 +               rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
1496 +       else if (rf->channel >= 100 && rf->channel <= 128)
1497 +               rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
1498 +       else
1499 +               rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
1500 +       rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1501 +
1502 +       rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1503 +       rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
1504 +       rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1505 +
1506 +       rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
1507 +
1508 +       if (rf->channel <= 14) {
1509 +               rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
1510 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
1511 +       } else {
1512 +               rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
1513 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
1514 +       }
1515 +
1516 +       rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
1517 +       rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
1518 +       rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
1519 +
1520 +       rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
1521 +       if (rf->channel <= 14) {
1522 +               rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
1523 +               rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
1524 +       } else {
1525 +               rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
1526 +               rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
1527 +       }
1528 +       rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
1529 +
1530 +       rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1531 +       if (rf->channel <= 14)
1532 +               rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
1533 +       else
1534 +               rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
1535 +
1536 +       if (txbf_enabled)
1537 +               rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
1538 +
1539 +       rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1540 +
1541 +       rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
1542 +       rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
1543 +       rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
1544 +
1545 +       rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
1546 +       if (rf->channel <= 14)
1547 +               rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
1548 +       else
1549 +               rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
1550 +       rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
1551 +
1552 +       if (rf->channel <= 14) {
1553 +               rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
1554 +               rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
1555 +       } else {
1556 +               rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
1557 +               rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
1558 +       }
1559 +
1560 +       /* Initiate VCO calibration */
1561 +       rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1562 +       if (rf->channel <= 14) {
1563 +               rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
1564 +       } else {
1565 +               rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
1566 +               rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
1567 +               rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
1568 +               rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
1569 +               rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
1570 +               rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
1571 +       }
1572 +       rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1573 +
1574 +       if (rf->channel >= 1 && rf->channel <= 14) {
1575 +               rfcsr = 0x23;
1576 +               if (txbf_enabled)
1577 +                       rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
1578 +               rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
1579 +
1580 +               rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
1581 +       } else if (rf->channel >= 36 && rf->channel <= 64) {
1582 +               rfcsr = 0x36;
1583 +               if (txbf_enabled)
1584 +                       rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
1585 +               rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
1586 +
1587 +               rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
1588 +       } else if (rf->channel >= 100 && rf->channel <= 128) {
1589 +               rfcsr = 0x32;
1590 +               if (txbf_enabled)
1591 +                       rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
1592 +               rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
1593 +
1594 +               rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
1595 +       } else {
1596 +               rfcsr = 0x30;
1597 +               if (txbf_enabled)
1598 +                       rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
1599 +               rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
1600 +
1601 +               rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
1602 +       }
1603  }
1604
1605 +#define POWER_BOUND            0x27
1606 +#define POWER_BOUND_5G         0x2b
1607 +
1608  static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1609                                          struct ieee80211_conf *conf,
1610                                          struct rf_channel *rf,
1611 @@ -2563,6 +3097,23 @@ static void rt2800_iq_calibrate(struct r
1612         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
1613  }
1614
1615 +static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
1616 +                                 unsigned int channel,
1617 +                                 char txpower)
1618 +{
1619 +       if (rt2x00_rt(rt2x00dev, RT3593))
1620 +               txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
1621 +
1622 +       if (channel <= 14)
1623 +               return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
1624 +
1625 +       if (rt2x00_rt(rt2x00dev, RT3593))
1626 +               return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
1627 +                              MAX_A_TXPOWER_3593);
1628 +       else
1629 +               return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
1630 +}
1631 +
1632  static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1633                                   struct ieee80211_conf *conf,
1634                                   struct rf_channel *rf,
1635 @@ -2572,13 +3123,14 @@ static void rt2800_config_channel(struct
1636         unsigned int tx_pin;
1637         u8 bbp, rfcsr;
1638
1639 -       if (rf->channel <= 14) {
1640 -               info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1641 -               info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1642 -       } else {
1643 -               info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1644 -               info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1645 -       }
1646 +       info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
1647 +                                                    info->default_power1);
1648 +       info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
1649 +                                                    info->default_power2);
1650 +       if (rt2x00dev->default_ant.tx_chain_num > 2)
1651 +               info->default_power3 =
1652 +                       rt2800_txpower_to_dev(rt2x00dev, rf->channel,
1653 +                                             info->default_power3);
1654
1655         switch (rt2x00dev->chip.rf) {
1656         case RF2020:
1657 @@ -2591,6 +3143,9 @@ static void rt2800_config_channel(struct
1658         case RF3052:
1659                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
1660                 break;
1661 +       case RF3053:
1662 +               rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
1663 +               break;
1664         case RF3290:
1665                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
1666                 break;
1667 @@ -2636,6 +3191,23 @@ static void rt2800_config_channel(struct
1668                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
1669                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
1670                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
1671 +       } else if (rt2x00_rt(rt2x00dev, RT3593)) {
1672 +               if (rf->channel > 14) {
1673 +                       /* Disable CCK Packet detection on 5GHz */
1674 +                       rt2800_bbp_write(rt2x00dev, 70, 0x00);
1675 +               } else {
1676 +                       rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1677 +               }
1678 +
1679 +               if (conf_is_ht40(conf))
1680 +                       rt2800_bbp_write(rt2x00dev, 105, 0x04);
1681 +               else
1682 +                       rt2800_bbp_write(rt2x00dev, 105, 0x34);
1683 +
1684 +               rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1685 +               rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1686 +               rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1687 +               rt2800_bbp_write(rt2x00dev, 77, 0x98);
1688         } else {
1689                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1690                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1691 @@ -2651,16 +3223,27 @@ static void rt2800_config_channel(struct
1692                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1693                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1694                         } else {
1695 -                               rt2800_bbp_write(rt2x00dev, 82, 0x84);
1696 +                               if (rt2x00_rt(rt2x00dev, RT3593))
1697 +                                       rt2800_bbp_write(rt2x00dev, 82, 0x62);
1698 +                               else
1699 +                                       rt2800_bbp_write(rt2x00dev, 82, 0x84);
1700                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1701                         }
1702 +                       if (rt2x00_rt(rt2x00dev, RT3593))
1703 +                               rt2800_bbp_write(rt2x00dev, 83, 0x8a);
1704                 }
1705 +
1706         } else {
1707                 if (rt2x00_rt(rt2x00dev, RT3572))
1708                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
1709 +               else if (rt2x00_rt(rt2x00dev, RT3593))
1710 +                       rt2800_bbp_write(rt2x00dev, 82, 0x82);
1711                 else
1712                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1713
1714 +               if (rt2x00_rt(rt2x00dev, RT3593))
1715 +                       rt2800_bbp_write(rt2x00dev, 83, 0x9a);
1716 +
1717                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1718                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1719                 else
1720 @@ -2731,6 +3314,41 @@ static void rt2800_config_channel(struct
1721         if (rt2x00_rt(rt2x00dev, RT3572))
1722                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
1723
1724 +       if (rt2x00_rt(rt2x00dev, RT3593)) {
1725 +               if (rt2x00_is_usb(rt2x00dev)) {
1726 +                       rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1727 +
1728 +                       /* Band selection. GPIO #8 controls all paths */
1729 +                       rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
1730 +                       if (rf->channel <= 14)
1731 +                               rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
1732 +                       else
1733 +                               rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
1734 +
1735 +                       rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
1736 +                       rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1737 +
1738 +                       /* LNA PE control.
1739 +                       * GPIO #4 controls PE0 and PE1,
1740 +                       * GPIO #7 controls PE2
1741 +                       */
1742 +                       rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
1743 +                       rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1744 +
1745 +                       rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1746 +               }
1747 +
1748 +               /* AGC init */
1749 +               if (rf->channel <= 14)
1750 +                       reg = 0x1c + 2 * rt2x00dev->lna_gain;
1751 +               else
1752 +                       reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
1753 +
1754 +               rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
1755 +
1756 +               usleep_range(1000, 1500);
1757 +       }
1758 +
1759         if (rt2x00_rt(rt2x00dev, RT5592)) {
1760                 rt2800_bbp_write(rt2x00dev, 195, 141);
1761                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
1762 @@ -2790,6 +3408,13 @@ static int rt2800_get_gain_calibration_d
1763         int i;
1764
1765         /*
1766 +        * First check if temperature compensation is supported.
1767 +        */
1768 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1769 +       if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
1770 +               return 0;
1771 +
1772 +       /*
1773          * Read TSSI boundaries for temperature compensation from
1774          * the EEPROM.
1775          *
1776 @@ -2798,62 +3423,62 @@ static int rt2800_get_gain_calibration_d
1777          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1778          */
1779         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1780 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
1781 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
1782                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1783                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
1784                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1785                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
1786
1787 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
1788 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
1789                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1790                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
1791                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1792                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
1793
1794 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
1795 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
1796                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1797                                         EEPROM_TSSI_BOUND_BG3_REF);
1798                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1799                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
1800
1801 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
1802 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
1803                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1804                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
1805                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1806                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
1807
1808 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
1809 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
1810                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1811                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
1812
1813                 step = rt2x00_get_field16(eeprom,
1814                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
1815         } else {
1816 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
1817 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
1818                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1819                                         EEPROM_TSSI_BOUND_A1_MINUS4);
1820                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1821                                         EEPROM_TSSI_BOUND_A1_MINUS3);
1822
1823 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
1824 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
1825                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1826                                         EEPROM_TSSI_BOUND_A2_MINUS2);
1827                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1828                                         EEPROM_TSSI_BOUND_A2_MINUS1);
1829
1830 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
1831 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
1832                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1833                                         EEPROM_TSSI_BOUND_A3_REF);
1834                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1835                                         EEPROM_TSSI_BOUND_A3_PLUS1);
1836
1837 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
1838 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
1839                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1840                                         EEPROM_TSSI_BOUND_A4_PLUS2);
1841                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1842                                         EEPROM_TSSI_BOUND_A4_PLUS3);
1843
1844 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
1845 +               rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
1846                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1847                                         EEPROM_TSSI_BOUND_A5_PLUS4);
1848
1849 @@ -2899,7 +3524,7 @@ static int rt2800_get_txpower_bw_comp(st
1850         u8 comp_type;
1851         int comp_value = 0;
1852
1853 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1854 +       rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1855
1856         /*
1857          * HT40 compensation not required.
1858 @@ -2966,6 +3591,9 @@ static u8 rt2800_compensate_txpower(stru
1859         u8 eirp_txpower_criterion;
1860         u8 reg_limit;
1861
1862 +       if (rt2x00_rt(rt2x00dev, RT3593))
1863 +               return min_t(u8, txpower, 0xc);
1864 +
1865         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
1866                 /*
1867                  * Check if eirp txpower exceed txpower_limit.
1868 @@ -2974,12 +3602,12 @@ static u8 rt2800_compensate_txpower(stru
1869                  * .11b data rate need add additional 4dbm
1870                  * when calculating eirp txpower.
1871                  */
1872 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
1873 -                                  &eeprom);
1874 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
1875 +                                             1, &eeprom);
1876                 criterion = rt2x00_get_field16(eeprom,
1877                                                EEPROM_TXPOWER_BYRATE_RATE0);
1878
1879 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
1880 +               rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
1881                                    &eeprom);
1882
1883                 if (band == IEEE80211_BAND_2GHZ)
1884 @@ -3001,6 +3629,412 @@ static u8 rt2800_compensate_txpower(stru
1885         return min_t(u8, txpower, 0xc);
1886  }
1887
1888 +
1889 +enum {
1890 +       TX_PWR_CFG_0_IDX,
1891 +       TX_PWR_CFG_1_IDX,
1892 +       TX_PWR_CFG_2_IDX,
1893 +       TX_PWR_CFG_3_IDX,
1894 +       TX_PWR_CFG_4_IDX,
1895 +       TX_PWR_CFG_5_IDX,
1896 +       TX_PWR_CFG_6_IDX,
1897 +       TX_PWR_CFG_7_IDX,
1898 +       TX_PWR_CFG_8_IDX,
1899 +       TX_PWR_CFG_9_IDX,
1900 +       TX_PWR_CFG_0_EXT_IDX,
1901 +       TX_PWR_CFG_1_EXT_IDX,
1902 +       TX_PWR_CFG_2_EXT_IDX,
1903 +       TX_PWR_CFG_3_EXT_IDX,
1904 +       TX_PWR_CFG_4_EXT_IDX,
1905 +       TX_PWR_CFG_IDX_COUNT,
1906 +};
1907 +
1908 +static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
1909 +                                        struct ieee80211_channel *chan,
1910 +                                        int power_level)
1911 +{
1912 +       u8 txpower;
1913 +       u16 eeprom;
1914 +       u32 regs[TX_PWR_CFG_IDX_COUNT];
1915 +       unsigned int offset;
1916 +       enum ieee80211_band band = chan->band;
1917 +       int delta;
1918 +       int i;
1919 +
1920 +       memset(regs, '\0', sizeof(regs));
1921 +
1922 +       /* TODO: adapt TX power reduction from the rt28xx code */
1923 +
1924 +       /* calculate temperature compensation delta */
1925 +       delta = rt2800_get_gain_calibration_delta(rt2x00dev);
1926 +
1927 +       if (band == IEEE80211_BAND_5GHZ)
1928 +               offset = 16;
1929 +       else
1930 +               offset = 0;
1931 +
1932 +       if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1933 +               offset += 8;
1934 +
1935 +       /* read the next four txpower values */
1936 +       rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
1937 +                                     offset, &eeprom);
1938 +
1939 +       /* CCK 1MBS,2MBS */
1940 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
1941 +       txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
1942 +                                           txpower, delta);
1943 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
1944 +                          TX_PWR_CFG_0_CCK1_CH0, txpower);
1945 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
1946 +                          TX_PWR_CFG_0_CCK1_CH1, txpower);
1947 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
1948 +                          TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
1949 +
1950 +       /* CCK 5.5MBS,11MBS */
1951 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
1952 +       txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
1953 +                                           txpower, delta);
1954 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
1955 +                          TX_PWR_CFG_0_CCK5_CH0, txpower);
1956 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
1957 +                          TX_PWR_CFG_0_CCK5_CH1, txpower);
1958 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
1959 +                          TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
1960 +
1961 +       /* OFDM 6MBS,9MBS */
1962 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
1963 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
1964 +                                           txpower, delta);
1965 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
1966 +                          TX_PWR_CFG_0_OFDM6_CH0, txpower);
1967 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
1968 +                          TX_PWR_CFG_0_OFDM6_CH1, txpower);
1969 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
1970 +                          TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
1971 +
1972 +       /* OFDM 12MBS,18MBS */
1973 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
1974 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
1975 +                                           txpower, delta);
1976 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
1977 +                          TX_PWR_CFG_0_OFDM12_CH0, txpower);
1978 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
1979 +                          TX_PWR_CFG_0_OFDM12_CH1, txpower);
1980 +       rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
1981 +                          TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
1982 +
1983 +       /* read the next four txpower values */
1984 +       rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
1985 +                                     offset + 1, &eeprom);
1986 +
1987 +       /* OFDM 24MBS,36MBS */
1988 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
1989 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
1990 +                                           txpower, delta);
1991 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
1992 +                          TX_PWR_CFG_1_OFDM24_CH0, txpower);
1993 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
1994 +                          TX_PWR_CFG_1_OFDM24_CH1, txpower);
1995 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
1996 +                          TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
1997 +
1998 +       /* OFDM 48MBS */
1999 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
2000 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2001 +                                           txpower, delta);
2002 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
2003 +                          TX_PWR_CFG_1_OFDM48_CH0, txpower);
2004 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
2005 +                          TX_PWR_CFG_1_OFDM48_CH1, txpower);
2006 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
2007 +                          TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
2008 +
2009 +       /* OFDM 54MBS */
2010 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
2011 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2012 +                                           txpower, delta);
2013 +       rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
2014 +                          TX_PWR_CFG_7_OFDM54_CH0, txpower);
2015 +       rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
2016 +                          TX_PWR_CFG_7_OFDM54_CH1, txpower);
2017 +       rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
2018 +                          TX_PWR_CFG_7_OFDM54_CH2, txpower);
2019 +
2020 +       /* read the next four txpower values */
2021 +       rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
2022 +                                     offset + 2, &eeprom);
2023 +
2024 +       /* MCS 0,1 */
2025 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
2026 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2027 +                                           txpower, delta);
2028 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
2029 +                          TX_PWR_CFG_1_MCS0_CH0, txpower);
2030 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
2031 +                          TX_PWR_CFG_1_MCS0_CH1, txpower);
2032 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
2033 +                          TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
2034 +
2035 +       /* MCS 2,3 */
2036 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
2037 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2038 +                                           txpower, delta);
2039 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
2040 +                          TX_PWR_CFG_1_MCS2_CH0, txpower);
2041 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
2042 +                          TX_PWR_CFG_1_MCS2_CH1, txpower);
2043 +       rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
2044 +                          TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
2045 +
2046 +       /* MCS 4,5 */
2047 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
2048 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2049 +                                           txpower, delta);
2050 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
2051 +                          TX_PWR_CFG_2_MCS4_CH0, txpower);
2052 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
2053 +                          TX_PWR_CFG_2_MCS4_CH1, txpower);
2054 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
2055 +                          TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
2056 +
2057 +       /* MCS 6 */
2058 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
2059 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2060 +                                           txpower, delta);
2061 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
2062 +                          TX_PWR_CFG_2_MCS6_CH0, txpower);
2063 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
2064 +                          TX_PWR_CFG_2_MCS6_CH1, txpower);
2065 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
2066 +                          TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
2067 +
2068 +       /* read the next four txpower values */
2069 +       rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
2070 +                                     offset + 3, &eeprom);
2071 +
2072 +       /* MCS 7 */
2073 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
2074 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2075 +                                           txpower, delta);
2076 +       rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
2077 +                          TX_PWR_CFG_7_MCS7_CH0, txpower);
2078 +       rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
2079 +                          TX_PWR_CFG_7_MCS7_CH1, txpower);
2080 +       rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
2081 +                          TX_PWR_CFG_7_MCS7_CH2, txpower);
2082 +
2083 +       /* MCS 8,9 */
2084 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
2085 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2086 +                                           txpower, delta);
2087 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
2088 +                          TX_PWR_CFG_2_MCS8_CH0, txpower);
2089 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
2090 +                          TX_PWR_CFG_2_MCS8_CH1, txpower);
2091 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
2092 +                          TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
2093 +
2094 +       /* MCS 10,11 */
2095 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
2096 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2097 +                                           txpower, delta);
2098 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
2099 +                          TX_PWR_CFG_2_MCS10_CH0, txpower);
2100 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
2101 +                          TX_PWR_CFG_2_MCS10_CH1, txpower);
2102 +       rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
2103 +                          TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
2104 +
2105 +       /* MCS 12,13 */
2106 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
2107 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2108 +                                           txpower, delta);
2109 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
2110 +                          TX_PWR_CFG_3_MCS12_CH0, txpower);
2111 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
2112 +                          TX_PWR_CFG_3_MCS12_CH1, txpower);
2113 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
2114 +                          TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
2115 +
2116 +       /* read the next four txpower values */
2117 +       rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
2118 +                                     offset + 4, &eeprom);
2119 +
2120 +       /* MCS 14 */
2121 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
2122 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2123 +                                           txpower, delta);
2124 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
2125 +                          TX_PWR_CFG_3_MCS14_CH0, txpower);
2126 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
2127 +                          TX_PWR_CFG_3_MCS14_CH1, txpower);
2128 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
2129 +                          TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
2130 +
2131 +       /* MCS 15 */
2132 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
2133 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2134 +                                           txpower, delta);
2135 +       rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
2136 +                          TX_PWR_CFG_8_MCS15_CH0, txpower);
2137 +       rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
2138 +                          TX_PWR_CFG_8_MCS15_CH1, txpower);
2139 +       rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
2140 +                          TX_PWR_CFG_8_MCS15_CH2, txpower);
2141 +
2142 +       /* MCS 16,17 */
2143 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
2144 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2145 +                                           txpower, delta);
2146 +       rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
2147 +                          TX_PWR_CFG_5_MCS16_CH0, txpower);
2148 +       rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
2149 +                          TX_PWR_CFG_5_MCS16_CH1, txpower);
2150 +       rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
2151 +                          TX_PWR_CFG_5_MCS16_CH2, txpower);
2152 +
2153 +       /* MCS 18,19 */
2154 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
2155 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2156 +                                           txpower, delta);
2157 +       rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
2158 +                          TX_PWR_CFG_5_MCS18_CH0, txpower);
2159 +       rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
2160 +                          TX_PWR_CFG_5_MCS18_CH1, txpower);
2161 +       rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
2162 +                          TX_PWR_CFG_5_MCS18_CH2, txpower);
2163 +
2164 +       /* read the next four txpower values */
2165 +       rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
2166 +                                     offset + 5, &eeprom);
2167 +
2168 +       /* MCS 20,21 */
2169 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
2170 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2171 +                                           txpower, delta);
2172 +       rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
2173 +                          TX_PWR_CFG_6_MCS20_CH0, txpower);
2174 +       rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
2175 +                          TX_PWR_CFG_6_MCS20_CH1, txpower);
2176 +       rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
2177 +                          TX_PWR_CFG_6_MCS20_CH2, txpower);
2178 +
2179 +       /* MCS 22 */
2180 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
2181 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2182 +                                           txpower, delta);
2183 +       rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
2184 +                          TX_PWR_CFG_6_MCS22_CH0, txpower);
2185 +       rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
2186 +                          TX_PWR_CFG_6_MCS22_CH1, txpower);
2187 +       rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
2188 +                          TX_PWR_CFG_6_MCS22_CH2, txpower);
2189 +
2190 +       /* MCS 23 */
2191 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
2192 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2193 +                                           txpower, delta);
2194 +       rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
2195 +                          TX_PWR_CFG_8_MCS23_CH0, txpower);
2196 +       rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
2197 +                          TX_PWR_CFG_8_MCS23_CH1, txpower);
2198 +       rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
2199 +                          TX_PWR_CFG_8_MCS23_CH2, txpower);
2200 +
2201 +       /* read the next four txpower values */
2202 +       rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
2203 +                                     offset + 6, &eeprom);
2204 +
2205 +       /* STBC, MCS 0,1 */
2206 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
2207 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2208 +                                           txpower, delta);
2209 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
2210 +                          TX_PWR_CFG_3_STBC0_CH0, txpower);
2211 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
2212 +                          TX_PWR_CFG_3_STBC0_CH1, txpower);
2213 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
2214 +                          TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
2215 +
2216 +       /* STBC, MCS 2,3 */
2217 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
2218 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2219 +                                           txpower, delta);
2220 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
2221 +                          TX_PWR_CFG_3_STBC2_CH0, txpower);
2222 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
2223 +                          TX_PWR_CFG_3_STBC2_CH1, txpower);
2224 +       rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
2225 +                          TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
2226 +
2227 +       /* STBC, MCS 4,5 */
2228 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
2229 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2230 +                                           txpower, delta);
2231 +       rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
2232 +       rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
2233 +       rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
2234 +                          txpower);
2235 +
2236 +       /* STBC, MCS 6 */
2237 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
2238 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2239 +                                           txpower, delta);
2240 +       rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
2241 +       rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
2242 +       rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
2243 +                          txpower);
2244 +
2245 +       /* read the next four txpower values */
2246 +       rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
2247 +                                     offset + 7, &eeprom);
2248 +
2249 +       /* STBC, MCS 7 */
2250 +       txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
2251 +       txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
2252 +                                           txpower, delta);
2253 +       rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
2254 +                          TX_PWR_CFG_9_STBC7_CH0, txpower);
2255 +       rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
2256 +                          TX_PWR_CFG_9_STBC7_CH1, txpower);
2257 +       rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
2258 +                          TX_PWR_CFG_9_STBC7_CH2, txpower);
2259 +
2260 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
2261 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
2262 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
2263 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
2264 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
2265 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
2266 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
2267 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
2268 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
2269 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
2270 +
2271 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
2272 +                             regs[TX_PWR_CFG_0_EXT_IDX]);
2273 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
2274 +                             regs[TX_PWR_CFG_1_EXT_IDX]);
2275 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
2276 +                             regs[TX_PWR_CFG_2_EXT_IDX]);
2277 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
2278 +                             regs[TX_PWR_CFG_3_EXT_IDX]);
2279 +       rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
2280 +                             regs[TX_PWR_CFG_4_EXT_IDX]);
2281 +
2282 +       for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
2283 +               rt2x00_dbg(rt2x00dev,
2284 +                          "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
2285 +                          (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
2286 +                          (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
2287 +                                                               '4' : '2',
2288 +                          (i > TX_PWR_CFG_9_IDX) ?
2289 +                                       (i - TX_PWR_CFG_9_IDX - 1) : i,
2290 +                          (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
2291 +                          (unsigned long) regs[i]);
2292 +}
2293 +
2294  /*
2295   * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2296   * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2297 @@ -3010,9 +4044,9 @@ static u8 rt2800_compensate_txpower(stru
2298   * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2299   * current conditions (i.e. band, bandwidth, temperature, user settings).
2300   */
2301 -static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2302 -                                 struct ieee80211_channel *chan,
2303 -                                 int power_level)
2304 +static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
2305 +                                        struct ieee80211_channel *chan,
2306 +                                        int power_level)
2307  {
2308         u8 txpower, r1;
2309         u16 eeprom;
2310 @@ -3080,8 +4114,8 @@ static void rt2800_config_txpower(struct
2311                 rt2800_register_read(rt2x00dev, offset, &reg);
2312
2313                 /* read the next four txpower values */
2314 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2315 -                                  &eeprom);
2316 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
2317 +                                             i, &eeprom);
2318
2319                 is_rate_b = i ? 0 : 1;
2320                 /*
2321 @@ -3129,8 +4163,8 @@ static void rt2800_config_txpower(struct
2322                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2323
2324                 /* read the next four txpower values */
2325 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2326 -                                  &eeprom);
2327 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
2328 +                                             i + 1, &eeprom);
2329
2330                 is_rate_b = 0;
2331                 /*
2332 @@ -3184,6 +4218,16 @@ static void rt2800_config_txpower(struct
2333         }
2334  }
2335
2336 +static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2337 +                                 struct ieee80211_channel *chan,
2338 +                                 int power_level)
2339 +{
2340 +       if (rt2x00_rt(rt2x00dev, RT3593))
2341 +               rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
2342 +       else
2343 +               rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
2344 +}
2345 +
2346  void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2347  {
2348         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
2349 @@ -3219,6 +4263,7 @@ void rt2800_vco_calibration(struct rt2x0
2350                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2351                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2352                 break;
2353 +       case RF3053:
2354         case RF3290:
2355         case RF5360:
2356         case RF5370:
2357 @@ -3442,17 +4487,25 @@ static int rt2800_init_registers(struct
2358                 return ret;
2359
2360         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2361 -       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2362 -       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2363 -       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2364 -       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2365 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0,
2366 +                          rt2800_get_beacon_offset(rt2x00dev, 0));
2367 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1,
2368 +                          rt2800_get_beacon_offset(rt2x00dev, 1));
2369 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2,
2370 +                          rt2800_get_beacon_offset(rt2x00dev, 2));
2371 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3,
2372 +                          rt2800_get_beacon_offset(rt2x00dev, 3));
2373         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2374
2375         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2376 -       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2377 -       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2378 -       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2379 -       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2380 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4,
2381 +                          rt2800_get_beacon_offset(rt2x00dev, 4));
2382 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5,
2383 +                          rt2800_get_beacon_offset(rt2x00dev, 5));
2384 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6,
2385 +                          rt2800_get_beacon_offset(rt2x00dev, 6));
2386 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7,
2387 +                          rt2800_get_beacon_offset(rt2x00dev, 7));
2388         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2389
2390         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2391 @@ -3528,7 +4581,8 @@ static int rt2800_init_registers(struct
2392                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2393                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2394                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2395 -                       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2396 +                       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
2397 +                                          &eeprom);
2398                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2399                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2400                                                       0x0000002c);
2401 @@ -3559,6 +4613,23 @@ static int rt2800_init_registers(struct
2402         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2403                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2404                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2405 +       } else if (rt2x00_rt(rt2x00dev, RT3593)) {
2406 +               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
2407 +               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2408 +               if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
2409 +                       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
2410 +                                          &eeprom);
2411 +                       if (rt2x00_get_field16(eeprom,
2412 +                                              EEPROM_NIC_CONF1_DAC_TEST))
2413 +                               rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2414 +                                                     0x0000001f);
2415 +                       else
2416 +                               rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2417 +                                                     0x0000000f);
2418 +               } else {
2419 +                       rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2420 +                                             0x00000000);
2421 +               }
2422         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2423                    rt2x00_rt(rt2x00dev, RT5392) ||
2424                    rt2x00_rt(rt2x00dev, RT5592)) {
2425 @@ -3786,14 +4857,8 @@ static int rt2800_init_registers(struct
2426         /*
2427          * Clear all beacons
2428          */
2429 -       rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2430 -       rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2431 -       rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2432 -       rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2433 -       rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2434 -       rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2435 -       rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2436 -       rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2437 +       for (i = 0; i < 8; i++)
2438 +               rt2800_clear_beacon_register(rt2x00dev, i);
2439
2440         if (rt2x00_is_usb(rt2x00dev)) {
2441                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2442 @@ -3989,7 +5054,7 @@ static void rt2800_disable_unused_dac_ad
2443         u8 value;
2444
2445         rt2800_bbp_read(rt2x00dev, 138, &value);
2446 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2447 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2448         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2449                 value |= 0x20;
2450         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2451 @@ -4332,6 +5397,22 @@ static void rt2800_init_bbp_3572(struct
2452         rt2800_disable_unused_dac_adc(rt2x00dev);
2453  }
2454
2455 +static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
2456 +{
2457 +       rt2800_init_bbp_early(rt2x00dev);
2458 +
2459 +       rt2800_bbp_write(rt2x00dev, 79, 0x13);
2460 +       rt2800_bbp_write(rt2x00dev, 80, 0x05);
2461 +       rt2800_bbp_write(rt2x00dev, 81, 0x33);
2462 +       rt2800_bbp_write(rt2x00dev, 137, 0x0f);
2463 +
2464 +       rt2800_bbp_write(rt2x00dev, 84, 0x19);
2465 +
2466 +       /* Enable DC filter */
2467 +       if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
2468 +               rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2469 +}
2470 +
2471  static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
2472  {
2473         int ant, div_mode;
2474 @@ -4402,7 +5483,7 @@ static void rt2800_init_bbp_53xx(struct
2475
2476         rt2800_disable_unused_dac_adc(rt2x00dev);
2477
2478 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2479 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2480         div_mode = rt2x00_get_field16(eeprom,
2481                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
2482         ant = (div_mode == 3) ? 1 : 0;
2483 @@ -4488,7 +5569,7 @@ static void rt2800_init_bbp_5592(struct
2484
2485         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
2486
2487 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2488 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2489         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
2490         ant = (div_mode == 3) ? 1 : 0;
2491         rt2800_bbp_read(rt2x00dev, 152, &value);
2492 @@ -4547,6 +5628,9 @@ static void rt2800_init_bbp(struct rt2x0
2493         case RT3572:
2494                 rt2800_init_bbp_3572(rt2x00dev);
2495                 break;
2496 +       case RT3593:
2497 +               rt2800_init_bbp_3593(rt2x00dev);
2498 +               return;
2499         case RT5390:
2500         case RT5392:
2501                 rt2800_init_bbp_53xx(rt2x00dev);
2502 @@ -4557,7 +5641,8 @@ static void rt2800_init_bbp(struct rt2x0
2503         }
2504
2505         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2506 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2507 +               rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
2508 +                                             &eeprom);
2509
2510                 if (eeprom != 0xffff && eeprom != 0x0000) {
2511                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2512 @@ -4728,7 +5813,7 @@ static void rt2800_normal_mode_setup_3xx
2513         if (rt2x00_rt(rt2x00dev, RT3090)) {
2514                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
2515                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2516 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2517 +               rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2518                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2519                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2520                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2521 @@ -4771,6 +5856,42 @@ static void rt2800_normal_mode_setup_3xx
2522         }
2523  }
2524
2525 +static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
2526 +{
2527 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2528 +       u8 rfcsr;
2529 +       u8 tx_gain;
2530 +
2531 +       rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2532 +       rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
2533 +       rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2534 +
2535 +       rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2536 +       tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
2537 +                                   RFCSR17_TXMIXER_GAIN);
2538 +       rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
2539 +       rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2540 +
2541 +       rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
2542 +       rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
2543 +       rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
2544 +
2545 +       rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
2546 +       rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
2547 +       rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2548 +
2549 +       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2550 +       rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2551 +       rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2552 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2553 +
2554 +       rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2555 +       rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2556 +       rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2557 +
2558 +       /* TODO: enable stream mode */
2559 +}
2560 +
2561  static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
2562  {
2563         u8 reg;
2564 @@ -4778,7 +5899,7 @@ static void rt2800_normal_mode_setup_5xx
2565
2566         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
2567         rt2800_bbp_read(rt2x00dev, 138, &reg);
2568 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2569 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2570         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2571                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
2572         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2573 @@ -4884,7 +6005,8 @@ static void rt2800_init_rfcsr_30xx(struc
2574                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2575                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2576                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2577 -                       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2578 +                       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
2579 +                                          &eeprom);
2580                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2581                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2582                         else
2583 @@ -5152,6 +6274,136 @@ static void rt2800_init_rfcsr_3572(struc
2584         rt2800_normal_mode_setup_3xxx(rt2x00dev);
2585  }
2586
2587 +static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
2588 +{
2589 +       u8 bbp;
2590 +       bool txbf_enabled = false; /* FIXME */
2591 +
2592 +       rt2800_bbp_read(rt2x00dev, 105, &bbp);
2593 +       if (rt2x00dev->default_ant.rx_chain_num == 1)
2594 +               rt2x00_set_field8(&bbp, BBP105_MLD, 0);
2595 +       else
2596 +               rt2x00_set_field8(&bbp, BBP105_MLD, 1);
2597 +       rt2800_bbp_write(rt2x00dev, 105, bbp);
2598 +
2599 +       rt2800_bbp4_mac_if_ctrl(rt2x00dev);
2600 +
2601 +       rt2800_bbp_write(rt2x00dev, 92, 0x02);
2602 +       rt2800_bbp_write(rt2x00dev, 82, 0x82);
2603 +       rt2800_bbp_write(rt2x00dev, 106, 0x05);
2604 +       rt2800_bbp_write(rt2x00dev, 104, 0x92);
2605 +       rt2800_bbp_write(rt2x00dev, 88, 0x90);
2606 +       rt2800_bbp_write(rt2x00dev, 148, 0xc8);
2607 +       rt2800_bbp_write(rt2x00dev, 47, 0x48);
2608 +       rt2800_bbp_write(rt2x00dev, 120, 0x50);
2609 +
2610 +       if (txbf_enabled)
2611 +               rt2800_bbp_write(rt2x00dev, 163, 0xbd);
2612 +       else
2613 +               rt2800_bbp_write(rt2x00dev, 163, 0x9d);
2614 +
2615 +       /* SNR mapping */
2616 +       rt2800_bbp_write(rt2x00dev, 142, 6);
2617 +       rt2800_bbp_write(rt2x00dev, 143, 160);
2618 +       rt2800_bbp_write(rt2x00dev, 142, 7);
2619 +       rt2800_bbp_write(rt2x00dev, 143, 161);
2620 +       rt2800_bbp_write(rt2x00dev, 142, 8);
2621 +       rt2800_bbp_write(rt2x00dev, 143, 162);
2622 +
2623 +       /* ADC/DAC control */
2624 +       rt2800_bbp_write(rt2x00dev, 31, 0x08);
2625 +
2626 +       /* RX AGC energy lower bound in log2 */
2627 +       rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2628 +
2629 +       /* FIXME: BBP 105 owerwrite? */
2630 +       rt2800_bbp_write(rt2x00dev, 105, 0x04);
2631 +
2632 +}
2633 +
2634 +static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
2635 +{
2636 +       struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2637 +       u32 reg;
2638 +       u8 rfcsr;
2639 +
2640 +       /* Disable GPIO #4 and #7 function for LAN PE control */
2641 +       rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2642 +       rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
2643 +       rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
2644 +       rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2645 +
2646 +       /* Initialize default register values */
2647 +       rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
2648 +       rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
2649 +       rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
2650 +       rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2651 +       rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
2652 +       rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
2653 +       rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2654 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2655 +       rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
2656 +       rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2657 +       rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
2658 +       rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
2659 +       rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2660 +       rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2661 +       rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
2662 +       rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
2663 +       rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
2664 +       rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
2665 +       rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
2666 +       rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
2667 +       rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
2668 +       rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2669 +       rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2670 +       rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
2671 +       rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
2672 +       rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
2673 +       rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2674 +       rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
2675 +       rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
2676 +       rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
2677 +       rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
2678 +       rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
2679 +
2680 +       /* Initiate calibration */
2681 +       /* TODO: use rt2800_rf_init_calibration ? */
2682 +       rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2683 +       rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2684 +       rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2685 +
2686 +       rt2800_adjust_freq_offset(rt2x00dev);
2687 +
2688 +       rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
2689 +       rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
2690 +       rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
2691 +
2692 +       rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2693 +       rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2694 +       rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2695 +       rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2696 +       usleep_range(1000, 1500);
2697 +       rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2698 +       rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2699 +       rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2700 +
2701 +       /* Set initial values for RX filter calibration */
2702 +       drv_data->calibration_bw20 = 0x1f;
2703 +       drv_data->calibration_bw40 = 0x2f;
2704 +
2705 +       /* Save BBP 25 & 26 values for later use in channel switching */
2706 +       rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
2707 +       rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
2708 +
2709 +       rt2800_led_open_drain_enable(rt2x00dev);
2710 +       rt2800_normal_mode_setup_3593(rt2x00dev);
2711 +
2712 +       rt3593_post_bbp_init(rt2x00dev);
2713 +
2714 +       /* TODO: enable stream mode support */
2715 +}
2716 +
2717  static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
2718  {
2719         rt2800_rf_init_calibration(rt2x00dev, 2);
2720 @@ -5380,6 +6632,9 @@ static void rt2800_init_rfcsr(struct rt2
2721         case RT3572:
2722                 rt2800_init_rfcsr_3572(rt2x00dev);
2723                 break;
2724 +       case RT3593:
2725 +               rt2800_init_rfcsr_3593(rt2x00dev);
2726 +               break;
2727         case RT5390:
2728                 rt2800_init_rfcsr_5390(rt2x00dev);
2729                 break;
2730 @@ -5456,15 +6711,15 @@ int rt2800_enable_radio(struct rt2x00_de
2731         /*
2732          * Initialize LED control
2733          */
2734 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
2735 +       rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
2736         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
2737                            word & 0xff, (word >> 8) & 0xff);
2738
2739 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
2740 +       rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
2741         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
2742                            word & 0xff, (word >> 8) & 0xff);
2743
2744 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
2745 +       rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
2746         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
2747                            word & 0xff, (word >> 8) & 0xff);
2748
2749 @@ -5560,6 +6815,34 @@ int rt2800_read_eeprom_efuse(struct rt2x
2750  }
2751  EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2752
2753 +static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
2754 +{
2755 +       u16 word;
2756 +
2757 +       if (rt2x00_rt(rt2x00dev, RT3593))
2758 +               return 0;
2759 +
2760 +       rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
2761 +       if ((word & 0x00ff) != 0x00ff)
2762 +               return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
2763 +
2764 +       return 0;
2765 +}
2766 +
2767 +static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
2768 +{
2769 +       u16 word;
2770 +
2771 +       if (rt2x00_rt(rt2x00dev, RT3593))
2772 +               return 0;
2773 +
2774 +       rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
2775 +       if ((word & 0x00ff) != 0x00ff)
2776 +               return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
2777 +
2778 +       return 0;
2779 +}
2780 +
2781  static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2782  {
2783         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2784 @@ -5578,18 +6861,18 @@ static int rt2800_validate_eeprom(struct
2785         /*
2786          * Start validation of the data that has been read.
2787          */
2788 -       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2789 +       mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2790         if (!is_valid_ether_addr(mac)) {
2791                 eth_random_addr(mac);
2792                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
2793         }
2794
2795 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
2796 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
2797         if (word == 0xffff) {
2798                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2799                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
2800                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
2801 -               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2802 +               rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2803                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
2804         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2805                    rt2x00_rt(rt2x00dev, RT2872)) {
2806 @@ -5598,10 +6881,10 @@ static int rt2800_validate_eeprom(struct
2807                  */
2808                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
2809                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2810 -               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2811 +               rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2812         }
2813
2814 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
2815 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
2816         if (word == 0xffff) {
2817                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
2818                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
2819 @@ -5618,24 +6901,24 @@ static int rt2800_validate_eeprom(struct
2820                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
2821                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
2822                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
2823 -               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
2824 +               rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
2825                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
2826         }
2827
2828 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2829 +       rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2830         if ((word & 0x00ff) == 0x00ff) {
2831                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2832 -               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2833 +               rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2834                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
2835         }
2836         if ((word & 0xff00) == 0xff00) {
2837                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2838                                    LED_MODE_TXRX_ACTIVITY);
2839                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2840 -               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2841 -               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
2842 -               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
2843 -               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
2844 +               rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2845 +               rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
2846 +               rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
2847 +               rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
2848                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
2849         }
2850
2851 @@ -5644,56 +6927,61 @@ static int rt2800_validate_eeprom(struct
2852          * lna0 as correct value. Note that EEPROM_LNA
2853          * is never validated.
2854          */
2855 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2856 +       rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2857         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2858
2859 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2860 +       rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2861         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2862                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2863         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2864                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2865 -       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2866 +       rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2867
2868 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
2869 -       if ((word & 0x00ff) != 0x00ff) {
2870 -               drv_data->txmixer_gain_24g =
2871 -                       rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
2872 -       } else {
2873 -               drv_data->txmixer_gain_24g = 0;
2874 -       }
2875 +       drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
2876
2877 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2878 +       rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2879         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2880                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2881 -       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2882 -           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2883 -               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2884 -                                  default_lna_gain);
2885 -       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2886 -
2887 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
2888 -       if ((word & 0x00ff) != 0x00ff) {
2889 -               drv_data->txmixer_gain_5g =
2890 -                       rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
2891 -       } else {
2892 -               drv_data->txmixer_gain_5g = 0;
2893 +       if (!rt2x00_rt(rt2x00dev, RT3593)) {
2894 +               if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2895 +                   rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2896 +                       rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2897 +                                          default_lna_gain);
2898         }
2899 +       rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2900 +
2901 +       drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
2902
2903 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2904 +       rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2905         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2906                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2907         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2908                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2909 -       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2910 +       rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2911
2912 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2913 +       rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2914         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2915                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2916 -       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2917 -           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2918 -               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2919 -                                  default_lna_gain);
2920 -       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2921 +       if (!rt2x00_rt(rt2x00dev, RT3593)) {
2922 +               if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2923 +                   rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2924 +                       rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2925 +                                          default_lna_gain);
2926 +       }
2927 +       rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2928 +
2929 +       if (rt2x00_rt(rt2x00dev, RT3593)) {
2930 +               rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
2931 +               if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
2932 +                   rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
2933 +                       rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
2934 +                                          default_lna_gain);
2935 +               if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
2936 +                   rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
2937 +                       rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
2938 +                                          default_lna_gain);
2939 +               rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
2940 +       }
2941
2942         return 0;
2943  }
2944 @@ -5707,7 +6995,7 @@ static int rt2800_init_eeprom(struct rt2
2945         /*
2946          * Read EEPROM word for configuration.
2947          */
2948 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2949 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2950
2951         /*
2952          * Identify RF chipset by EEPROM value
2953 @@ -5717,7 +7005,7 @@ static int rt2800_init_eeprom(struct rt2
2954         if (rt2x00_rt(rt2x00dev, RT3290) ||
2955             rt2x00_rt(rt2x00dev, RT5390) ||
2956             rt2x00_rt(rt2x00dev, RT5392))
2957 -               rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
2958 +               rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
2959         else
2960                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
2961
2962 @@ -5731,6 +7019,7 @@ static int rt2800_init_eeprom(struct rt2
2963         case RF3021:
2964         case RF3022:
2965         case RF3052:
2966 +       case RF3053:
2967         case RF3290:
2968         case RF3320:
2969         case RF3322:
2970 @@ -5757,7 +7046,7 @@ static int rt2800_init_eeprom(struct rt2
2971         rt2x00dev->default_ant.rx_chain_num =
2972             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
2973
2974 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2975 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2976
2977         if (rt2x00_rt(rt2x00dev, RT3070) ||
2978             rt2x00_rt(rt2x00dev, RT3090) ||
2979 @@ -5810,7 +7099,7 @@ static int rt2800_init_eeprom(struct rt2
2980         /*
2981          * Read frequency offset and RF programming sequence.
2982          */
2983 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2984 +       rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2985         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2986
2987         /*
2988 @@ -5827,7 +7116,7 @@ static int rt2800_init_eeprom(struct rt2
2989         /*
2990          * Check if support EIRP tx power limit feature.
2991          */
2992 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2993 +       rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2994
2995         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
2996                                         EIRP_MAX_TX_POWER_LIMIT)
2997 @@ -6109,12 +7398,79 @@ static const struct rf_channel rf_vals_5
2998         {196, 83, 0, 12, 1},
2999  };
3000
3001 +static const struct rf_channel rf_vals_3053[] = {
3002 +       /* Channel, N, R, K */
3003 +       {1, 241, 2, 2},
3004 +       {2, 241, 2, 7},
3005 +       {3, 242, 2, 2},
3006 +       {4, 242, 2, 7},
3007 +       {5, 243, 2, 2},
3008 +       {6, 243, 2, 7},
3009 +       {7, 244, 2, 2},
3010 +       {8, 244, 2, 7},
3011 +       {9, 245, 2, 2},
3012 +       {10, 245, 2, 7},
3013 +       {11, 246, 2, 2},
3014 +       {12, 246, 2, 7},
3015 +       {13, 247, 2, 2},
3016 +       {14, 248, 2, 4},
3017 +
3018 +       {36, 0x56, 0, 4},
3019 +       {38, 0x56, 0, 6},
3020 +       {40, 0x56, 0, 8},
3021 +       {44, 0x57, 0, 0},
3022 +       {46, 0x57, 0, 2},
3023 +       {48, 0x57, 0, 4},
3024 +       {52, 0x57, 0, 8},
3025 +       {54, 0x57, 0, 10},
3026 +       {56, 0x58, 0, 0},
3027 +       {60, 0x58, 0, 4},
3028 +       {62, 0x58, 0, 6},
3029 +       {64, 0x58, 0, 8},
3030 +
3031 +       {100, 0x5B, 0, 8},
3032 +       {102, 0x5B, 0, 10},
3033 +       {104, 0x5C, 0, 0},
3034 +       {108, 0x5C, 0, 4},
3035 +       {110, 0x5C, 0, 6},
3036 +       {112, 0x5C, 0, 8},
3037 +
3038 +       /* NOTE: Channel 114 has been removed intentionally.
3039 +        * The EEPROM contains no TX power values for that,
3040 +        * and it is disabled in the vendor driver as well.
3041 +        */
3042 +
3043 +       {116, 0x5D, 0, 0},
3044 +       {118, 0x5D, 0, 2},
3045 +       {120, 0x5D, 0, 4},
3046 +       {124, 0x5D, 0, 8},
3047 +       {126, 0x5D, 0, 10},
3048 +       {128, 0x5E, 0, 0},
3049 +       {132, 0x5E, 0, 4},
3050 +       {134, 0x5E, 0, 6},
3051 +       {136, 0x5E, 0, 8},
3052 +       {140, 0x5F, 0, 0},
3053 +
3054 +       {149, 0x5F, 0, 9},
3055 +       {151, 0x5F, 0, 11},
3056 +       {153, 0x60, 0, 1},
3057 +       {157, 0x60, 0, 5},
3058 +       {159, 0x60, 0, 7},
3059 +       {161, 0x60, 0, 9},
3060 +       {165, 0x61, 0, 1},
3061 +       {167, 0x61, 0, 3},
3062 +       {169, 0x61, 0, 5},
3063 +       {171, 0x61, 0, 7},
3064 +       {173, 0x61, 0, 9},
3065 +};
3066 +
3067  static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3068  {
3069         struct hw_mode_spec *spec = &rt2x00dev->spec;
3070         struct channel_info *info;
3071         char *default_power1;
3072         char *default_power2;
3073 +       char *default_power3;
3074         unsigned int i;
3075         u16 eeprom;
3076         u32 reg;
3077 @@ -6149,7 +7505,7 @@ static int rt2800_probe_hw_mode(struct r
3078
3079         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3080         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3081 -                               rt2x00_eeprom_addr(rt2x00dev,
3082 +                               rt2800_eeprom_addr(rt2x00dev,
3083                                                    EEPROM_MAC_ADDR_0));
3084
3085         /*
3086 @@ -6165,7 +7521,7 @@ static int rt2800_probe_hw_mode(struct r
3087         rt2x00dev->hw->max_report_rates = 7;
3088         rt2x00dev->hw->max_rate_tries = 1;
3089
3090 -       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3091 +       rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3092
3093         /*
3094          * Initialize hw_mode information.
3095 @@ -6200,6 +7556,10 @@ static int rt2800_probe_hw_mode(struct r
3096                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3097                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3098                 spec->channels = rf_vals_3x;
3099 +       } else if (rt2x00_rf(rt2x00dev, RF3053)) {
3100 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
3101 +               spec->num_channels = ARRAY_SIZE(rf_vals_3053);
3102 +               spec->channels = rf_vals_3053;
3103         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
3104                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3105
3106 @@ -6265,21 +7625,40 @@ static int rt2800_probe_hw_mode(struct r
3107
3108         spec->channels_info = info;
3109
3110 -       default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3111 -       default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3112 +       default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3113 +       default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3114 +
3115 +       if (rt2x00dev->default_ant.tx_chain_num > 2)
3116 +               default_power3 = rt2800_eeprom_addr(rt2x00dev,
3117 +                                                   EEPROM_EXT_TXPOWER_BG3);
3118 +       else
3119 +               default_power3 = NULL;
3120
3121         for (i = 0; i < 14; i++) {
3122                 info[i].default_power1 = default_power1[i];
3123                 info[i].default_power2 = default_power2[i];
3124 +               if (default_power3)
3125 +                       info[i].default_power3 = default_power3[i];
3126         }
3127
3128         if (spec->num_channels > 14) {
3129 -               default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3130 -               default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3131 +               default_power1 = rt2800_eeprom_addr(rt2x00dev,
3132 +                                                   EEPROM_TXPOWER_A1);
3133 +               default_power2 = rt2800_eeprom_addr(rt2x00dev,
3134 +                                                   EEPROM_TXPOWER_A2);
3135 +
3136 +               if (rt2x00dev->default_ant.tx_chain_num > 2)
3137 +                       default_power3 =
3138 +                               rt2800_eeprom_addr(rt2x00dev,
3139 +                                                  EEPROM_EXT_TXPOWER_A3);
3140 +               else
3141 +                       default_power3 = NULL;
3142
3143                 for (i = 14; i < spec->num_channels; i++) {
3144                         info[i].default_power1 = default_power1[i - 14];
3145                         info[i].default_power2 = default_power2[i - 14];
3146 +                       if (default_power3)
3147 +                               info[i].default_power3 = default_power3[i - 14];
3148                 }
3149         }
3150
3151 @@ -6290,6 +7669,7 @@ static int rt2800_probe_hw_mode(struct r
3152         case RF3022:
3153         case RF3320:
3154         case RF3052:
3155 +       case RF3053:
3156         case RF3290:
3157         case RF5360:
3158         case RF5370:
3159 @@ -6328,6 +7708,7 @@ static int rt2800_probe_rt(struct rt2x00
3160         case RT3352:
3161         case RT3390:
3162         case RT3572:
3163 +       case RT3593:
3164         case RT5390:
3165         case RT5392:
3166         case RT5592:
3167 --- a/drivers/net/wireless/rt2x00/rt2800lib.h
3168 +++ b/drivers/net/wireless/rt2x00/rt2800lib.h
3169 @@ -226,4 +226,8 @@ int rt2800_get_survey(struct ieee80211_h
3170                       struct survey_info *survey);
3171  void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev);
3172
3173 +void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
3174 +                              unsigned short *txwi_size,
3175 +                              unsigned short *rxwi_size);
3176 +
3177  #endif /* RT2800LIB_H */
3178 --- a/drivers/net/wireless/rt2x00/rt2800pci.c
3179 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
3180 @@ -507,9 +507,13 @@ static int rt2800pci_init_registers(stru
3181         rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
3182
3183         if (rt2x00_is_pcie(rt2x00dev) &&
3184 -           (rt2x00_rt(rt2x00dev, RT3572) ||
3185 +           (rt2x00_rt(rt2x00dev, RT3090) ||
3186 +            rt2x00_rt(rt2x00dev, RT3390) ||
3187 +            rt2x00_rt(rt2x00dev, RT3572) ||
3188 +            rt2x00_rt(rt2x00dev, RT3593) ||
3189              rt2x00_rt(rt2x00dev, RT5390) ||
3190 -            rt2x00_rt(rt2x00dev, RT5392))) {
3191 +            rt2x00_rt(rt2x00dev, RT5392) ||
3192 +            rt2x00_rt(rt2x00dev, RT5592))) {
3193                 rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg);
3194                 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
3195                 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
3196 @@ -1189,12 +1193,17 @@ static const struct rt2x00lib_ops rt2800
3197
3198  static void rt2800pci_queue_init(struct data_queue *queue)
3199  {
3200 +       struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
3201 +       unsigned short txwi_size, rxwi_size;
3202 +
3203 +       rt2800_get_txwi_rxwi_size(rt2x00dev, &txwi_size, &rxwi_size);
3204 +
3205         switch (queue->qid) {
3206         case QID_RX:
3207                 queue->limit = 128;
3208                 queue->data_size = AGGREGATION_SIZE;
3209                 queue->desc_size = RXD_DESC_SIZE;
3210 -               queue->winfo_size = RXWI_DESC_SIZE_4WORDS;
3211 +               queue->winfo_size = rxwi_size;
3212                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3213                 break;
3214
3215 @@ -1205,7 +1214,7 @@ static void rt2800pci_queue_init(struct
3216                 queue->limit = 64;
3217                 queue->data_size = AGGREGATION_SIZE;
3218                 queue->desc_size = TXD_DESC_SIZE;
3219 -               queue->winfo_size = TXWI_DESC_SIZE_4WORDS;
3220 +               queue->winfo_size = txwi_size;
3221                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3222                 break;
3223
3224 @@ -1213,7 +1222,7 @@ static void rt2800pci_queue_init(struct
3225                 queue->limit = 8;
3226                 queue->data_size = 0; /* No DMA required for beacons */
3227                 queue->desc_size = TXD_DESC_SIZE;
3228 -               queue->winfo_size = TXWI_DESC_SIZE_4WORDS;
3229 +               queue->winfo_size = txwi_size;
3230                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3231                 break;
3232
3233 --- a/drivers/net/wireless/rt2x00/rt2800usb.c
3234 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
3235 @@ -854,13 +854,7 @@ static void rt2800usb_queue_init(struct
3236         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
3237         unsigned short txwi_size, rxwi_size;
3238
3239 -       if (rt2x00_rt(rt2x00dev, RT5592)) {
3240 -               txwi_size = TXWI_DESC_SIZE_5WORDS;
3241 -               rxwi_size = RXWI_DESC_SIZE_6WORDS;
3242 -       } else {
3243 -               txwi_size = TXWI_DESC_SIZE_4WORDS;
3244 -               rxwi_size = RXWI_DESC_SIZE_4WORDS;
3245 -       }
3246 +       rt2800_get_txwi_rxwi_size(rt2x00dev, &txwi_size, &rxwi_size);
3247
3248         switch (queue->qid) {
3249         case QID_RX:
3250 @@ -1194,6 +1188,40 @@ static struct usb_device_id rt2800usb_de
3251         /* Zinwell */
3252         { USB_DEVICE(0x5a57, 0x0284) },
3253  #endif
3254 +#ifdef CPTCFG_RT2800USB_RT3573
3255 +       /* AirLive */
3256 +       { USB_DEVICE(0x1b75, 0x7733) },
3257 +       /* ASUS */
3258 +       { USB_DEVICE(0x0b05, 0x17bc) },
3259 +       { USB_DEVICE(0x0b05, 0x17ad) },
3260 +       /* Belkin */
3261 +       { USB_DEVICE(0x050d, 0x1103) },
3262 +       /* Cameo */
3263 +       { USB_DEVICE(0x148f, 0xf301) },
3264 +       /* Edimax */
3265 +       { USB_DEVICE(0x7392, 0x7733) },
3266 +       /* Hawking */
3267 +       { USB_DEVICE(0x0e66, 0x0020) },
3268 +       { USB_DEVICE(0x0e66, 0x0021) },
3269 +       /* I-O DATA */
3270 +       { USB_DEVICE(0x04bb, 0x094e) },
3271 +       /* Linksys */
3272 +       { USB_DEVICE(0x13b1, 0x003b) },
3273 +       /* Logitec */
3274 +       { USB_DEVICE(0x0789, 0x016b) },
3275 +       /* NETGEAR */
3276 +       { USB_DEVICE(0x0846, 0x9012) },
3277 +       { USB_DEVICE(0x0846, 0x9019) },
3278 +       /* Planex */
3279 +       { USB_DEVICE(0x2019, 0xed19) },
3280 +       /* Ralink */
3281 +       { USB_DEVICE(0x148f, 0x3573) },
3282 +       /* Sitecom */
3283 +       { USB_DEVICE(0x0df6, 0x0067) },
3284 +       { USB_DEVICE(0x0df6, 0x006a) },
3285 +       /* ZyXEL */
3286 +       { USB_DEVICE(0x0586, 0x3421) },
3287 +#endif
3288  #ifdef CPTCFG_RT2800USB_RT53XX
3289         /* Arcadyan */
3290         { USB_DEVICE(0x043e, 0x7a12) },
3291 --- a/drivers/net/wireless/rt2x00/rt2x00.h
3292 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
3293 @@ -211,6 +211,7 @@ struct channel_info {
3294         short max_power;
3295         short default_power1;
3296         short default_power2;
3297 +       short default_power3;
3298  };
3299
3300  /*