1 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/cmd_boot.c u-boot-sunxi/arch/arm/cpu/armv7/cmd_boot.c
2 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/cmd_boot.c 1970-01-01 01:00:00.000000000 +0100
3 +++ u-boot-sunxi/arch/arm/cpu/armv7/cmd_boot.c 2014-03-05 23:14:47.108100778 +0100
6 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
8 + * See file CREDITS for list of people who contributed to this
11 + * This program is free software; you can redistribute it and/or
12 + * modify it under the terms of the GNU General Public License as
13 + * published by the Free Software Foundation; either version 2 of
14 + * the License, or (at your option) any later version.
16 + * This program is distributed in the hope that it will be useful,
17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 + * GNU General Public License for more details.
21 + * You should have received a copy of the GNU General Public License
22 + * along with this program; if not, write to the Free Software
23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 +unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
35 + char * const argv[])
37 + invalidate_icache_all();
38 + return entry(argc, argv);
41 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/Makefile u-boot-sunxi/arch/arm/cpu/armv7/Makefile
42 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/Makefile 2013-11-25 22:49:32.000000000 +0100
43 +++ u-boot-sunxi/arch/arm/cpu/armv7/Makefile 2014-03-05 23:14:47.108100778 +0100
50 -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
51 +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_SUNXI),)
52 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
53 obj-y += lowlevel_init.o
56 ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
57 obj-y += nonsec_virt.o
62 +ifneq ($(CONFIG_ARMV7_PSCI),)
66 obj-$(CONFIG_OMAP_COMMON) += omap-common/
67 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/nonsec_virt.S u-boot-sunxi/arch/arm/cpu/armv7/nonsec_virt.S
68 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/nonsec_virt.S 2013-11-25 22:49:32.000000000 +0100
69 +++ u-boot-sunxi/arch/arm/cpu/armv7/nonsec_virt.S 2014-03-05 23:14:47.116100672 +0100
71 #include <linux/linkage.h>
73 #include <asm/armv7.h>
74 +#include <asm/proc-armv/ptrace.h>
79 + .pushsection ._secure.text, "ax"
81 + .align 5 @ Minimal alignment for vectors
83 /* the vector table for secure state and HYP mode */
87 adr pc, _secure_monitor
95 +.macro is_cpu_virt_capable tmp
96 + mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
97 + and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
98 + cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
102 * secure monitor handler
103 * U-boot calls this "software interrupt" in start.S
104 * This is executed on a "smc" instruction, we use a "smc #0" to switch
105 * to non-secure state.
106 - * We use only r0 and r1 here, due to constraints in the caller.
107 + * r0, r1, r2: passed to the callee
112 - mrc p15, 0, r1, c1, c1, 0 @ read SCR
113 - bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
114 - orr r1, r1, #0x31 @ enable NS, AW, FW bits
116 -#ifdef CONFIG_ARMV7_VIRT
117 - mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
118 - and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
119 - cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
120 - orreq r1, r1, #0x100 @ allow HVC instruction
121 +#ifdef CONFIG_ARMV7_PSCI
122 + ldr r5, =_psci_vectors @ Switch to the next monitor
123 + mcr p15, 0, r5, c12, c0, 1
127 - mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
128 + mrc p15, 0, r5, c1, c1, 0 @ read SCR
129 + bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits
130 + orr r5, r5, #0x31 @ enable NS, AW, FW bits
132 + mov r6, #SVC_MODE @ default mode is SVC
133 + is_cpu_virt_capable r4
134 #ifdef CONFIG_ARMV7_VIRT
135 - mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
136 - mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR
137 + orreq r5, r5, #0x100 @ allow HVC instruction
138 + moveq r6, #HYP_MODE @ Enter the kernel as HYP
141 - movs pc, lr @ return to non-secure SVC
142 + mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
147 + @ Reset CNTVOFF to 0 before leaving monitor mode
148 + mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
149 + ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
151 + mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
154 + mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
155 + tst lr, #1 @ Check for Thumb PC
156 + orrne ip, ip, #T_BIT @ Set T if Thumb
157 + orr ip, ip, r6 @ Slot target mode in
158 + msr spsr_cxfs, ip @ Set full SPSR
159 + movs pc, lr @ ERET to non-secure
161 +ENTRY(_do_nonsec_entry)
167 +ENDPROC(_do_nonsec_entry)
169 +.macro get_cbar_addr addr
170 +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
171 + ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
173 + mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
174 + bfc \addr, #0, #15 @ clear reserved bits
179 - mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
180 - mov pc, lr @ do no switch modes, but
182 +.macro get_gicd_addr addr
183 + get_cbar_addr \addr
184 + add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
187 +.macro get_gicc_addr addr, tmp
188 + get_cbar_addr \addr
189 + is_cpu_virt_capable \tmp
190 + movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
191 + moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
192 + add \addr, \addr, \tmp
195 +#ifndef CONFIG_ARMV7_PSCI
197 * Secondary CPUs start here and call the code for the core specific parts
198 * of the non-secure and HYP mode transition. The GIC distributor specific
200 * Then they go back to wfi and wait to be woken up by the kernel again.
205 - msr cpsr, r0 @ disable interrupts
207 - mcr p15, 0, r1, c12, c0, 0 @ set VBAR
212 - mov r12, r0 @ save GICC address
213 -#ifdef CONFIG_ARMV7_VIRT
217 - ldr r1, [r12, #GICC_IAR] @ acknowledge IPI
218 - str r1, [r12, #GICC_EOIR] @ signal end of interrupt
220 adr r0, _smp_pen @ do not use this address again
221 b smp_waitloop @ wait for IPIs, board specific
226 * Switch a core to non-secure state.
228 * 1. initialize the GIC per-core interface
229 * 2. allow coprocessor access in non-secure modes
230 - * 3. switch the cpu mode (by calling "smc #0")
232 * Called from smp_pen by secondary cores and directly by the BSP.
233 * Do not assume that the stack is available and only use registers
234 @@ -100,38 +143,23 @@
235 * though, but we check this in C before calling this function.
238 -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
239 - ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS
241 - mrc p15, 4, r2, c15, c0, 0 @ read CBAR
242 - bfc r2, #0, #15 @ clear reserved bits
244 - add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset
247 mvn r1, #0 @ all bits to 1
248 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
250 - mrc p15, 0, r0, c0, c0, 0 @ read MIDR
251 - ldr r1, =MIDR_PRIMARY_PART_MASK
252 - and r0, r0, r1 @ mask out variant and revision
254 - ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
255 - cmp r0, r1 @ check for Cortex-A7
257 - ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
258 - cmpne r0, r1 @ check for Cortex-A15
260 - movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
261 - moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
262 - add r3, r2, r1 @ r3 = GIC CPU i/f addr
263 + get_gicc_addr r3, r1
265 mov r1, #1 @ set GICC_CTLR[enable]
266 str r1, [r3, #GICC_CTLR] @ and clear all other bits
268 str r1, [r3, #GICC_PMR] @ set priority mask register
270 + mrc p15, 0, r0, c1, c1, 2
273 - mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec
276 + mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
278 /* The CNTFRQ register of the generic timer needs to be
279 * programmed in secure state. Some primary bootloaders / firmware
280 @@ -149,44 +177,24 @@
282 adr r1, _monitor_vectors
283 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
285 - mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR
288 - smc #0 @ call into MONITOR mode
290 - mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR
293 - str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f
294 - add r2, r2, #GIC_DIST_OFFSET
295 - str r1, [r2, #GICD_CTLR] @ allow private interrupts
297 mov r0, r3 @ return GICC address
300 ENDPROC(_nonsec_init)
302 #ifdef CONFIG_SMP_PEN_ADDR
303 /* void __weak smp_waitloop(unsigned previous_address); */
307 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
309 cmp r0, r1 @ make sure we dont execute this code
310 beq smp_waitloop @ again (due to a spurious wakeup)
314 ENDPROC(smp_waitloop)
318 -ENTRY(_switch_to_hyp)
320 - mov r1, sp @ save SVC copy of LR and SP
322 - hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
324 - mov lr, r0 @ restore SVC copy of LR and SP
327 -ENDPROC(_switch_to_hyp)
329 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/psci.S u-boot-sunxi/arch/arm/cpu/armv7/psci.S
330 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/psci.S 1970-01-01 01:00:00.000000000 +0100
331 +++ u-boot-sunxi/arch/arm/cpu/armv7/psci.S 2014-03-05 23:14:47.124100564 +0100
334 + * Copyright (C) 2013 - ARM Ltd
335 + * Author: Marc Zyngier <marc.zyngier@arm.com>
337 + * This program is free software; you can redistribute it and/or modify
338 + * it under the terms of the GNU General Public License version 2 as
339 + * published by the Free Software Foundation.
341 + * This program is distributed in the hope that it will be useful,
342 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
343 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
344 + * GNU General Public License for more details.
346 + * You should have received a copy of the GNU General Public License
347 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
351 +#include <linux/linkage.h>
352 +#include <asm/psci.h>
354 + .pushsection ._secure.text, "ax"
356 + .arch_extension sec
359 + .globl _psci_vectors
363 + adr pc, _smc_psci @ smc
370 +ENTRY(psci_cpu_suspend)
374 + mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
376 +ENDPROC(psci_migrate)
377 +ENDPROC(psci_cpu_on)
378 +ENDPROC(psci_cpu_off)
379 +ENDPROC(psci_cpu_suspend)
380 +.weak psci_cpu_suspend
386 + .word ARM_PSCI_FN_CPU_SUSPEND
387 + .word psci_cpu_suspend
388 + .word ARM_PSCI_FN_CPU_OFF
390 + .word ARM_PSCI_FN_CPU_ON
392 + .word ARM_PSCI_FN_MIGRATE
397 +_secure_stacks: @ Enough to save 16 registers per CPU
398 + .skip 16*4*CONFIG_ARMV7_PSCI_NR_CPUS
402 + @ Switch to secure mode
403 + mrc p15, 0, sp, c1, c1, 0
405 + mcr p15, 0, sp, c1, c1, 0
407 + adr sp, _secure_stack_base
408 + mcr p15, 0, r0, c13, c0, 4 @ use TPIDRPRW as a tmp reg
409 + mcr p15, 0, r1, c13, c0, 3 @ use TPIDRURO as a tmp reg
410 + mrc p15, 0, r0, c0, c0, 5 @ MPIDR
411 + and r1, r0, #3 @ cpu number in cluster
413 + and r0, r0, #3 @ cluster number
414 + mul r1, r1, r0 @ absolute cpu nr
415 + sbc sp, sp, r1, lsl #6 @ sp = sp_base - 64*cpunr
417 + mrc p15, 0, r0, c13, c0, 4 @ restore r0
418 + mrc p15, 0, r1, c13, c0, 3 @ restore r1
422 + adr r4, _psci_table
423 +1: ldr r5, [r4] @ Load PSCI function ID
424 + ldr r6, [r4, #4] @ Load target PC
425 + cmp r5, #0 @ If reach the end, bail out
426 + mvneq r0, #0 @ Return -1 (Not Implemented)
428 + cmp r0, r5 @ If not matching, try next entry
431 + cmp r6, #0 @ Not implemented
432 + moveq r0, #ARM_PSCI_RET_NI
435 + blx r6 @ Execute PSCI function
439 + @ Back to non-secure
440 + mrc p15, 0, sp, c1, c1, 0
442 + mcr p15, 0, sp, c1, c1, 0
443 + movs pc, lr @ Return to the kernel
446 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/board.c
447 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/board.c 1970-01-01 01:00:00.000000000 +0100
448 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/board.c 2014-03-05 23:14:47.128100511 +0100
451 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
453 + * (C) Copyright 2007-2011
454 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
455 + * Tom Cubie <tangliang@allwinnertech.com>
457 + * Some init for sunxi platform.
459 + * See file CREDITS for list of people who contributed to this
462 + * This program is free software; you can redistribute it and/or
463 + * modify it under the terms of the GNU General Public License as
464 + * published by the Free Software Foundation; either version 2 of
465 + * the License, or (at your option) any later version.
467 + * This program is distributed in the hope that it will be useful,
468 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
469 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
470 + * GNU General Public License for more details.
472 + * You should have received a copy of the GNU General Public License
473 + * along with this program; if not, write to the Free Software
474 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
475 + * MA 02111-1307 USA
483 +#ifdef CONFIG_SPL_BUILD
486 +#include <asm/gpio.h>
488 +#include <asm/arch/clock.h>
489 +#include <asm/arch/gpio.h>
490 +#include <asm/arch/sys_proto.h>
491 +#include <asm/arch/timer.h>
492 +#include <asm/arch/watchdog.h>
494 +#ifdef CONFIG_SPL_BUILD
495 +/* Pointer to the global data structure for SPL */
496 +DECLARE_GLOBAL_DATA_PTR;
498 +/* The sunxi internal brom will try to loader external bootloader
499 + * from mmc0, nannd flash, mmc2.
500 + * Unfortunately we can't check how SPL was loaded so assume
501 + * it's always the first SD/MMC controller
503 +u32 spl_boot_device(void)
505 + return BOOT_DEVICE_MMC1;
508 +/* No confirmation data available in SPL yet. Hardcode bootmode */
509 +u32 spl_boot_mode(void)
511 + return MMCSD_MODE_RAW;
517 +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
518 +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
519 + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
520 + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
521 + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
523 + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
524 + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
525 + sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
526 +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
527 + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
528 + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
529 + sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
530 +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
531 + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2);
532 + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2);
533 + sunxi_gpio_set_pull(SUNXI_GPH(21), 1);
534 +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
535 + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
536 + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
537 + sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
538 +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
539 + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART0_TX);
540 + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART0_RX);
541 + sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
543 +#error Unsupported console port number. Please fix pin mux settings in board.c
549 +void reset_cpu(ulong addr)
555 +/* do some early init */
558 +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
559 + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
561 + "mrc p15, 0, r0, c1, c0, 1\n"
562 + "orr r0, r0, #0x40\n"
563 + "mcr p15, 0, r0, c1, c0, 1\n");
571 +#ifdef CONFIG_SPL_BUILD
573 + preloader_console_init();
575 +#ifdef CONFIG_SPL_I2C_SUPPORT
576 + /* Needed early by sunxi_board_init if PMU is enabled */
577 + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
580 + sunxi_board_init();
584 +#ifndef CONFIG_SYS_DCACHE_OFF
585 +void enable_caches(void)
587 + /* Enable D-cache. I-cache is already enabled in start.S */
592 +#if defined(CONFIG_SUNXI_EMAC) || defined(CONFIG_SUNXI_GMAC)
594 + * Initializes on-chip ethernet controllers.
595 + * to override, implement board_eth_init()
597 +int cpu_eth_init(bd_t *bis)
599 +#ifdef CONFIG_SUNXI_EMAC
600 + sunxi_emac_initialize(bis);
602 + sunxi_gmac_initialize(bis);
608 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock.c
609 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/clock.c 1970-01-01 01:00:00.000000000 +0100
610 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock.c 2014-03-05 23:14:47.128100511 +0100
613 + * (C) Copyright 2007-2012
614 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
615 + * Tom Cubie <tangliang@allwinnertech.com>
617 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
619 + * See file CREDITS for list of people who contributed to this
622 + * This program is free software; you can redistribute it and/or
623 + * modify it under the terms of the GNU General Public License as
624 + * published by the Free Software Foundation; either version 2 of
625 + * the License, or (at your option) any later version.
627 + * This program is distributed in the hope that it will be useful,
628 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
629 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
630 + * GNU General Public License for more details.
632 + * You should have received a copy of the GNU General Public License
633 + * along with this program; if not, write to the Free Software
634 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
635 + * MA 02111-1307 USA
640 +#include <asm/arch/clock.h>
641 +#include <asm/arch/gpio.h>
642 +#include <asm/arch/sys_proto.h>
644 +#ifdef CONFIG_SPL_BUILD
645 +static void clock_init_safe(void)
647 + struct sunxi_ccm_reg * const ccm =
648 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
650 + /* Set safe defaults until PMU is configured */
651 + writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
652 + CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg);
653 + writel(0xa1005000, &ccm->pll1_cfg);
655 + writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
656 + CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
658 + /* Power on reset default for PLL6 is 2400 MHz, which is faster then
659 + * it can reliable do :| Set it to a 600 MHz instead. */
660 + writel(0x21009911, &ccm->pll6_cfg);
663 + writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
664 + writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);
669 +int clock_init(void)
671 + struct sunxi_ccm_reg *const ccm =
672 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
674 +#ifdef CONFIG_SPL_BUILD
678 +#if defined(CONFIG_SUN6I)
679 + /* uart clock source is apb2 */
680 + sr32(&ccm->apb2_div, 24, 2, APB2_CLK_SRC_OSC24M);
681 + sr32(&ccm->apb2_div, 16, 2, APB2_FACTOR_N);
682 + sr32(&ccm->apb2_div, 0, 5, APB2_FACTOR_M);
684 + /* open the clock for uart */
685 + sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
687 + /* uart clock source is apb1 */
688 + sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
689 + sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
690 + sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);
692 + /* open the clock for uart */
693 + sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
696 +#ifdef CONFIG_NAND_SUNXI
697 + /* nand clock source is osc24m */
698 + sr32(&ccm->nand_sclk_cfg, 24, 2, NAND_CLK_SRC_OSC24);
699 + sr32(&ccm->nand_sclk_cfg, 16, 2, NAND_CLK_DIV_N);
700 + sr32(&ccm->nand_sclk_cfg, 0, 4, NAND_CLK_DIV_M);
701 + sr32(&ccm->nand_sclk_cfg, 31, 1, CLK_GATE_OPEN);
702 + /* open clock for nand */
703 + sr32(&ccm->ahb_gate0, AHB_GATE_OFFSET_NAND, 1, CLK_GATE_OPEN);
709 +/* Return PLL5 frequency in Hz
710 + * Note: Assumes PLL5 reference is 24MHz clock
712 +unsigned int clock_get_pll5(void)
714 + struct sunxi_ccm_reg *const ccm =
715 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
716 + uint32_t rval = readl(&ccm->pll5_cfg);
717 + int n = (rval >> 8) & 0x1f;
718 + int k = ((rval >> 4) & 3) + 1;
719 + int p = 1 << ((rval >> 16) & 3);
720 + return 24000000 * n * k / p;
723 +int clock_twi_onoff(int port, int state)
725 + struct sunxi_ccm_reg *const ccm =
726 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
731 + /* set the apb1 clock gate for twi */
732 + sr32(&ccm->apb1_gate, 0 + port, 1, state);
737 +#ifdef CONFIG_SPL_BUILD
738 +#define PLL1_CFG(N, K, M, P) (1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \
739 + 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \
740 + (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0)
741 +#define RDIV(a, b) ((a + (b) - 1) / (b))
747 + { PLL1_CFG(16, 0, 0, 0), 384000000 },
748 + { PLL1_CFG(16, 1, 0, 0), 768000000 },
749 + { PLL1_CFG(20, 1, 0, 0), 960000000 },
750 + { PLL1_CFG(21, 1, 0, 0), 1008000000},
751 + { PLL1_CFG(22, 1, 0, 0), 1056000000},
752 + { PLL1_CFG(23, 1, 0, 0), 1104000000},
753 + { PLL1_CFG(24, 1, 0, 0), 1152000000},
754 + { PLL1_CFG(25, 1, 0, 0), 1200000000},
755 + { PLL1_CFG(26, 1, 0, 0), 1248000000},
756 + { PLL1_CFG(27, 1, 0, 0), 1296000000},
757 + { PLL1_CFG(28, 1, 0, 0), 1344000000},
758 + { PLL1_CFG(29, 1, 0, 0), 1392000000},
759 + { PLL1_CFG(30, 1, 0, 0), 1440000000},
760 + { PLL1_CFG(31, 1, 0, 0), 1488000000},
761 + { PLL1_CFG(31, 1, 0, 0), ~0},
764 +void clock_set_pll1(int hz)
767 + int axi, ahb, apb0;
768 + struct sunxi_ccm_reg * const ccm =
769 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
771 + /* Find target frequency */
772 + while (pll1_para[i].freq < hz)
775 + hz = pll1_para[i].freq;
777 + /* Calculate system clock divisors */
778 + axi = RDIV(hz, 432000000); /* Max 450MHz */
779 + ahb = RDIV(hz/axi, 204000000); /* Max 250MHz */
780 + apb0 = 2; /* Max 150MHz */
782 + printf("CPU: %dHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
784 + /* Map divisors to register values */
797 + /* Switch to 24MHz clock while changing PLL1 */
798 + writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
799 + CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg);
802 + /* Configure sys clock divisors */
803 + writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_OSC24M << 16,
804 + &ccm->cpu_ahb_apb0_cfg);
806 + /* Configure PLL1 at the desired frequency */
807 + writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
810 + /* Switch CPU to PLL1 */
811 + writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_PLL1 << 16,
812 + &ccm->cpu_ahb_apb0_cfg);
816 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c
817 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c 1970-01-01 01:00:00.000000000 +0100
818 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c 2014-03-05 23:14:47.128100511 +0100
821 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
823 + * This program is free software; you can redistribute it and/or
824 + * modify it under the terms of the GNU General Public License as
825 + * published by the Free Software Foundation; either version 2 of
826 + * the License, or (at your option) any later version.
828 + * This program is distributed in the hope that it will be useful,
829 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
830 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
831 + * GNU General Public License for more details.
833 + * You should have received a copy of the GNU General Public License
834 + * along with this program; if not, write to the Free Software
835 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
836 + * MA 02111-1307 USA
841 +#include <asm/arch/watchdog.h>
843 +int do_sunxi_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, const char *argv[])
845 + unsigned long interval;
848 + printf("usage: watchdog seconds\n");
849 + printf("over %d to disable watchdog\n", WDT_MAX_TIMEOUT);
851 + interval = simple_strtoul(argv[1], NULL, 10);
852 + watchdog_set((unsigned int)interval);
858 + watchdog, 2, 1, do_sunxi_watchdog,
859 + "Set watchdog [0 - 16]. [17+} disables",
862 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/config.mk u-boot-sunxi/arch/arm/cpu/armv7/sunxi/config.mk
863 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/config.mk 1970-01-01 01:00:00.000000000 +0100
864 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/config.mk 2014-03-05 23:14:47.128100511 +0100
866 +# Build a combined spl + u-boot image
868 +ifndef CONFIG_SPL_BUILD
869 +ifndef CONFIG_SPL_FEL
870 +ALL-y = $(obj)u-boot-sunxi-with-spl.bin
874 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cpu_info.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cpu_info.c
875 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/cpu_info.c 1970-01-01 01:00:00.000000000 +0100
876 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cpu_info.c 2014-03-05 23:14:47.128100511 +0100
879 + * (C) Copyright 2007-2011
880 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
881 + * Tom Cubie <tangliang@allwinnertech.com>
883 + * See file CREDITS for list of people who contributed to this
886 + * This program is free software; you can redistribute it and/or
887 + * modify it under the terms of the GNU General Public License as
888 + * published by the Free Software Foundation; either version 2 of
889 + * the License, or (at your option) any later version.
891 + * This program is distributed in the hope that it will be useful,
892 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
893 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
894 + * GNU General Public License for more details.
896 + * You should have received a copy of the GNU General Public License
897 + * along with this program; if not, write to the Free Software
898 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
899 + * MA 02111-1307 USA
904 +#include <asm/arch/cpu.h>
906 +#ifdef CONFIG_DISPLAY_CPUINFO
907 +int print_cpuinfo(void)
910 + puts("CPU: Allwinner A10 (SUN4I)\n");
911 +#elif defined CONFIG_SUN5I
912 + /* TODO: Distinguish A13/A10s */
913 + puts("CPU: Allwinner A13/A10s (SUN5I)\n");
914 +#elif defined CONFIG_SUN6I
915 + puts("CPU: Allwinner A31 (SUN6I)\n");
916 +#elif defined CONFIG_SUN7I
917 + puts("CPU: Allwinner A20 (SUN7I)\n");
919 +#warning Please update cpu_info.c with correct CPU information
920 + puts("CPU: SUNXI Family\n");
925 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/dram.c
926 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/dram.c 1970-01-01 01:00:00.000000000 +0100
927 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/dram.c 2014-03-05 23:14:47.128100511 +0100
930 + * sunxi DRAM controller initialization
931 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
932 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
934 + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
935 + * and earlier U-Boot Allwiner A10 SPL work
937 + * (C) Copyright 2007-2012
938 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
939 + * Berg Xing <bergxing@allwinnertech.com>
940 + * Tom Cubie <tangliang@allwinnertech.com>
942 + * See file CREDITS for list of people who contributed to this
945 + * This program is free software; you can redistribute it and/or
946 + * modify it under the terms of the GNU General Public License as
947 + * published by the Free Software Foundation; either version 2 of
948 + * the License, or (at your option) any later version.
950 + * This program is distributed in the hope that it will be useful,
951 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
952 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
953 + * GNU General Public License for more details.
955 + * You should have received a copy of the GNU General Public License
956 + * along with this program; if not, write to the Free Software
957 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
958 + * MA 02111-1307 USA
963 +#include <asm/arch/clock.h>
964 +#include <asm/arch/dram.h>
965 +#include <asm/arch/timer.h>
966 +#include <asm/arch/sys_proto.h>
968 +#define CPU_CFG_CHIP_VER(n) ((n) << 6)
969 +#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
970 +#define CPU_CFG_CHIP_REV_A 0x0
971 +#define CPU_CFG_CHIP_REV_C1 0x1
972 +#define CPU_CFG_CHIP_REV_C2 0x2
973 +#define CPU_CFG_CHIP_REV_B 0x3
975 +static void mctl_ddr3_reset(void)
977 + struct sunxi_dram_reg *dram =
978 + (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
981 + struct sunxi_timer_reg *timer =
982 + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
985 + writel(0, &timer->cpu_cfg);
986 + reg_val = readl(&timer->cpu_cfg);
988 + if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
989 + CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
990 + setbits_le32(&dram->mcr, DRAM_MCR_RESET);
992 + clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
996 + clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
998 + setbits_le32(&dram->mcr, DRAM_MCR_RESET);
1002 +static void mctl_set_drive(void)
1004 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1006 +#ifdef CONFIG_SUN7I
1007 + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
1009 + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
1011 + DRAM_MCR_MODE_EN(0x3) |
1015 +static void mctl_itm_disable(void)
1017 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1019 + clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
1022 +static void mctl_itm_enable(void)
1024 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1026 + clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
1029 +static void mctl_enable_dll0(u32 phase)
1031 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1033 + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
1034 + ((phase >> 16) & 0x3f) << 6);
1035 + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
1038 + clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
1041 + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
1046 + * Note: This differs from pm/standby in that it checks the bus width
1048 +static void mctl_enable_dllx(u32 phase)
1050 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1051 + u32 i, n, bus_width;
1053 + bus_width = readl(&dram->dcr);
1055 + if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
1056 + DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
1057 + n = DRAM_DCR_NR_DLLCR_32BIT;
1059 + n = DRAM_DCR_NR_DLLCR_16BIT;
1061 + for (i = 1; i < n; i++) {
1062 +#ifdef CONFIG_SUN7I
1063 + clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
1065 + clrsetbits_le32(&dram->dllcr[i], 0x4 << 14,
1067 + (phase & 0xf) << 14);
1068 + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
1069 + DRAM_DLLCR_DISABLE);
1074 + for (i = 1; i < n; i++)
1075 + clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
1076 + DRAM_DLLCR_DISABLE);
1079 + for (i = 1; i < n; i++)
1080 + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
1081 + DRAM_DLLCR_NRESET);
1085 +static u32 hpcr_value[32] = {
1086 +#ifdef CONFIG_SUN5I
1091 + 0x1031, 0x1031, 0x0735, 0x1035,
1092 + 0x1035, 0x0731, 0x1031, 0,
1093 + 0x0301, 0x0301, 0x0301, 0x0301,
1094 + 0x0301, 0x0301, 0x0301, 0
1096 +#ifdef CONFIG_SUN4I
1097 + 0x0301, 0x0301, 0x0301, 0x0301,
1098 + 0x0301, 0x0301, 0, 0,
1101 + 0x1031, 0x1031, 0x0735, 0x1035,
1102 + 0x1035, 0x0731, 0x1031, 0x0735,
1103 + 0x1035, 0x1031, 0x0731, 0x1035,
1104 + 0x1031, 0x0301, 0x0301, 0x0731
1106 +#ifdef CONFIG_SUN7I
1107 + 0x0301, 0x0301, 0x0301, 0x0301,
1108 + 0x0301, 0x0301, 0x0301, 0x0301,
1111 + 0x1031, 0x1031, 0x0735, 0x1035,
1112 + 0x1035, 0x0731, 0x1031, 0x0735,
1113 + 0x1035, 0x1031, 0x0731, 0x1035,
1114 + 0x0001, 0x1031, 0, 0x1031
1115 + /* last row differs from boot0 source table
1116 + * 0x1031, 0x0301, 0x0301, 0x0731
1117 + * but boot0 code skips #28 and #30, and sets #29 and #31 to the
1118 + * value from #28 entry (0x1031)
1123 +static void mctl_configure_hostport(void)
1125 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1128 + for (i = 0; i < 32; i++)
1129 + writel(hpcr_value[i], &dram->hpcr[i]);
1132 +static void mctl_setup_dram_clock(u32 clk)
1135 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
1137 + /* setup DRAM PLL */
1138 + reg_val = readl(&ccm->pll5_cfg);
1139 + reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
1140 + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
1141 + reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
1142 + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
1143 + reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
1144 + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
1145 + reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
1146 + reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
1147 + reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
1148 + reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */
1149 + writel(reg_val, &ccm->pll5_cfg);
1152 + setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
1154 +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
1156 + clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
1157 + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
1159 + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
1162 + /* setup MBUS clock */
1163 + reg_val = CCM_MBUS_CTRL_GATE |
1164 +#if defined(CONFIG_SUN7I) && defined(CONFIG_FAST_MBUS)
1165 + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
1166 + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
1167 + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(3));
1168 +#elif defined(CONFIG_SUN7I) && !defined(CONFIG_FAST_MBUS)
1169 + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
1170 + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
1171 + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
1172 +#else /* defined(CONFIG_SUN5I) */
1173 + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
1174 + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
1175 + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
1177 + writel(reg_val, &ccm->mbus_clk_cfg);
1180 + * open DRAMC AHB & DLL register clock
1183 +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
1184 + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
1186 + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
1190 + /* then open it */
1191 +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
1192 + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
1194 + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
1199 +static int dramc_scan_readpipe(void)
1201 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1204 + /* data training trigger */
1205 +#ifdef CONFIG_SUN7I
1206 + clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
1208 + setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
1210 + /* check whether data training process has completed */
1211 + while (readl(&dram->ccr) & DRAM_CCR_DATA_TRAINING);
1213 + /* check data training result */
1214 + reg_val = readl(&dram->csr);
1215 + if (reg_val & DRAM_CSR_FAILED)
1221 +static int dramc_scan_dll_para(void)
1223 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1224 + const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
1225 + const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
1226 + 0x02, 0x01, 0x00, 0x08, 0x10,
1227 + 0x18, 0x20, 0x28, 0x30, 0x38};
1228 + u32 clk_dqs_count[15];
1229 + u32 dqs_i, clk_i, cr_i;
1230 + u32 max_val, min_val;
1231 + u32 dqs_index, clk_index;
1233 + /* Find DQS_DLY Pass Count for every CLK_DLY */
1234 + for (clk_i = 0; clk_i < 15; clk_i++) {
1235 + clk_dqs_count[clk_i] = 0;
1236 + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
1237 + (clk_dly[clk_i] & 0x3f) << 6);
1238 + for (dqs_i = 0; dqs_i < 7; dqs_i++) {
1239 + for (cr_i = 1; cr_i < 5; cr_i++) {
1240 + clrsetbits_le32(&dram->dllcr[cr_i],
1242 + (dqs_dly[dqs_i] & 0x4f) << 14);
1245 + if (dramc_scan_readpipe() == 0)
1246 + clk_dqs_count[clk_i]++;
1249 + /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
1250 + for (dqs_i = 15; dqs_i > 0; dqs_i--) {
1253 + for (clk_i = 0; clk_i < 15; clk_i++) {
1254 + if (clk_dqs_count[clk_i] == dqs_i) {
1256 + if (min_val == 15)
1264 + /* Check if Find a CLK_DLY failed */
1268 + /* Find the middle index of CLK_DLY */
1269 + clk_index = (max_val + min_val) >> 1;
1270 + if ((max_val == (15 - 1)) && (min_val > 0))
1271 + /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
1272 + * value can be more close to the max_val
1274 + clk_index = (15 + clk_index) >> 1;
1275 + else if ((max_val < (15 - 1)) && (min_val == 0))
1276 + /* if CLK_DLY[0] is very good, then the middle value can be more
1277 + * close to the min_val
1280 + if (clk_dqs_count[clk_index] < dqs_i)
1281 + clk_index = min_val;
1283 + /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
1286 + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
1287 + (clk_dly[clk_index] & 0x3f) << 6);
1290 + for (dqs_i = 0; dqs_i < 7; dqs_i++) {
1291 + clk_dqs_count[dqs_i] = 0;
1292 + for (cr_i = 1; cr_i < 5; cr_i++) {
1293 + clrsetbits_le32(&dram->dllcr[cr_i],
1295 + (dqs_dly[dqs_i] & 0x4f) << 14);
1298 + if (dramc_scan_readpipe() == 0) {
1299 + clk_dqs_count[dqs_i] = 1;
1306 + if (max_val < 7) {
1307 + dqs_index = (max_val + min_val) >> 1;
1308 + if ((max_val == (7-1)) && (min_val > 0))
1309 + dqs_index = (7 + dqs_index) >> 1;
1310 + else if ((max_val < (7-1)) && (min_val == 0))
1312 + if (!clk_dqs_count[dqs_index])
1313 + dqs_index = min_val;
1314 + for (cr_i = 1; cr_i < 5; cr_i++) {
1315 + clrsetbits_le32(&dram->dllcr[cr_i],
1317 + (dqs_dly[dqs_index] & 0x4f) << 14);
1320 + return dramc_scan_readpipe();
1324 + clrbits_le32(&dram->dllcr[0], 0x3f << 6);
1325 + for (cr_i = 1; cr_i < 5; cr_i++)
1326 + clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14);
1329 + return dramc_scan_readpipe();
1332 +static void dramc_clock_output_en(u32 on)
1334 +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
1335 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1338 + setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
1340 + clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
1342 +#ifdef CONFIG_SUN4I
1343 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
1345 + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
1347 + clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
1351 +#ifdef CONFIG_SUN4I
1352 +static void dramc_set_autorefresh_cycle(u32 clk)
1354 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1360 + reg_dcr = readl(&dram->dcr);
1361 + if ((reg_dcr & DRAM_DCR_CHIP_DENSITY_MASK) <=
1362 + DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M))
1363 + reg_val = (131 * clk) >> 10;
1365 + reg_val = (336 * clk) >> 10;
1367 + tmp_val = (7987 * clk) >> 10;
1368 + tmp_val = tmp_val * 9 - 200;
1369 + reg_val |= tmp_val << 8;
1370 + reg_val |= 0x8 << 24;
1371 + writel(reg_val, &dram->drr);
1373 + writel(0x0, &dram->drr);
1378 +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
1379 +static void dramc_set_autorefresh_cycle(u32 clk)
1381 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1386 + tmp_val = (7987 * clk) >> 10;
1387 + tmp_val = tmp_val * 9 - 200;
1388 + reg_val |= tmp_val << 8;
1389 + reg_val |= 0x8 << 24;
1390 + writel(reg_val, &dram->drr);
1394 +unsigned long dramc_init(struct dram_para *para)
1396 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1400 + /* check input dram parameter structure */
1404 + /* setup DRAM relative clock */
1405 + mctl_setup_dram_clock(para->clock);
1407 +#ifdef CONFIG_SUN5I
1408 + /* Disable any pad power save control */
1409 + writel(0, &dram->ppwrsctl);
1412 + /* reset external DRAM */
1413 +#ifndef CONFIG_SUN7I
1414 + mctl_ddr3_reset();
1418 + /* dram clock off */
1419 + dramc_clock_output_en(0);
1421 +#ifdef CONFIG_SUN4I
1422 + /* select dram controller 1 */
1423 + writel(DRAM_CSEL_MAGIC, &dram->csel);
1426 + mctl_itm_disable();
1427 + mctl_enable_dll0(para->tpr3);
1429 + /* configure external DRAM */
1431 + if (para->type == DRAM_MEMORY_TYPE_DDR3)
1432 + reg_val |= DRAM_DCR_TYPE_DDR3;
1433 + reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
1435 + if (para->density == 256)
1436 + reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M);
1437 + else if (para->density == 512)
1438 + reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_512M);
1439 + else if (para->density == 1024)
1440 + reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M);
1441 + else if (para->density == 2048)
1442 + reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_2048M);
1443 + else if (para->density == 4096)
1444 + reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_4096M);
1445 + else if (para->density == 8192)
1446 + reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_8192M);
1448 + reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M);
1450 + reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
1451 + reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
1452 + reg_val |= DRAM_DCR_CMD_RANK_ALL;
1453 + reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
1454 + writel(reg_val, &dram->dcr);
1456 +#ifdef CONFIG_SUN7I
1457 + setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
1458 + if (para->tpr4 & 0x2)
1459 + clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
1460 + dramc_clock_output_en(1);
1463 +#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
1464 + /* set odt impendance divide ratio */
1465 + reg_val = ((para->zq) >> 8) & 0xfffff;
1466 + reg_val |= ((para->zq) & 0xff) << 20;
1467 + reg_val |= (para->zq) & 0xf0000000;
1468 + writel(reg_val, &dram->zqcr0);
1471 +#ifdef CONFIG_SUN7I
1472 + /* Set CKE Delay to about 1ms */
1473 + setbits_le32(&dram->idcr, 0x1ffff);
1476 +#ifdef CONFIG_SUN7I
1477 + if ((readl(&dram->ppwrsctl) & 0x1) != 0x1)
1478 + mctl_ddr3_reset();
1480 + setbits_le32(&dram->mcr, DRAM_MCR_RESET);
1482 + /* dram clock on */
1483 + dramc_clock_output_en(1);
1488 + while (readl(&dram->ccr) & DRAM_CCR_INIT);
1490 + mctl_enable_dllx(para->tpr3);
1492 +#ifdef CONFIG_SUN4I
1493 + /* set odt impendance divide ratio */
1494 + reg_val = ((para->zq) >> 8) & 0xfffff;
1495 + reg_val |= ((para->zq) & 0xff) << 20;
1496 + reg_val |= (para->zq) & 0xf0000000;
1497 + writel(reg_val, &dram->zqcr0);
1500 +#ifdef CONFIG_SUN4I
1501 + /* set I/O configure register */
1502 + reg_val = 0x00cc0000;
1503 + reg_val |= (para->odt_en) & 0x3;
1504 + reg_val |= ((para->odt_en) & 0x3) << 30;
1505 + writel(reg_val, &dram->iocr);
1508 + /* set refresh period */
1509 + dramc_set_autorefresh_cycle(para->clock);
1511 + /* set timing parameters */
1512 + writel(para->tpr0, &dram->tpr0);
1513 + writel(para->tpr1, &dram->tpr1);
1514 + writel(para->tpr2, &dram->tpr2);
1516 + if (para->type == DRAM_MEMORY_TYPE_DDR3) {
1517 + reg_val = DRAM_MR_BURST_LENGTH(0x0);
1518 +#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
1519 + reg_val |= DRAM_MR_POWER_DOWN;
1521 + reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
1522 + reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
1523 + } else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
1524 + reg_val = DRAM_MR_BURST_LENGTH(0x2);
1525 + reg_val |= DRAM_MR_CAS_LAT(para->cas);
1526 + reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
1528 + writel(reg_val, &dram->mr);
1530 + writel(para->emr1, &dram->emr);
1531 + writel(para->emr2, &dram->emr2);
1532 + writel(para->emr3, &dram->emr3);
1534 + /* set DQS window mode */
1535 + clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
1537 +#ifdef CONFIG_SUN7I
1538 + /* Command rate timing mode 2T & 1T */
1539 + if (para->tpr4 & 0x1)
1540 + setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
1542 + /* reset external DRAM */
1543 + setbits_le32(&dram->ccr, DRAM_CCR_INIT);
1544 + while (readl(&dram->ccr) & DRAM_CCR_INIT);
1546 +#ifdef CONFIG_SUN7I
1547 + /* setup zq calibration manual */
1548 + reg_val = readl(&dram->ppwrsctl);
1549 + if ((reg_val & 0x1) == 1) {
1550 + /* super_standby_flag = 1 */
1552 + reg_val = readl(0x01c20c00 + 0x120); /* rtc */
1553 + reg_val &= 0x000fffff;
1554 + reg_val |= 0x17b00000;
1555 + writel(reg_val, &dram->zqcr0);
1557 + /* exit self-refresh state */
1558 + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
1559 + /* check whether command has been executed */
1560 + while (readl(&dram->dcr) & (0x1 << 31));
1564 + /* dram pad hold off */
1565 + setbits_le32(&dram->ppwrsctl, 0x16510000);
1567 + while (readl(&dram->ppwrsctl) & 0x1);
1569 + /* exit self-refresh state */
1570 + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
1572 + /* check whether command has been executed */
1573 + while (readl(&dram->dcr) & (0x1 << 31));
1576 + /* issue a refresh command */
1577 + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
1578 + while (readl(&dram->dcr) & (0x1 << 31));
1584 + /* scan read pipe value */
1585 + mctl_itm_enable();
1586 + if (para->tpr3 & (0x1 << 31)) {
1587 + ret_val = dramc_scan_dll_para();
1590 + (((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) |
1591 + (((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) |
1592 + (((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) |
1593 + (((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) |
1594 + (((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12
1597 + ret_val = dramc_scan_readpipe();
1603 + /* configure all host port */
1604 + mctl_configure_hostport();
1606 + return get_ram_size((unsigned long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
1608 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/early_print.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/early_print.c
1609 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/early_print.c 1970-01-01 01:00:00.000000000 +0100
1610 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/early_print.c 2014-03-05 23:14:47.128100511 +0100
1613 + * (C) Copyright 2007-2012
1614 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
1615 + * Tom Cubie <tangliang@allwinnertech.com>
1617 + * Early uart print for debugging.
1619 + * See file CREDITS for list of people who contributed to this
1622 + * This program is free software; you can redistribute it and/or
1623 + * modify it under the terms of the GNU General Public License as
1624 + * published by the Free Software Foundation; either version 2 of
1625 + * the License, or (at your option) any later version.
1627 + * This program is distributed in the hope that it will be useful,
1628 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1629 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1630 + * GNU General Public License for more details.
1632 + * You should have received a copy of the GNU General Public License
1633 + * along with this program; if not, write to the Free Software
1634 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1635 + * MA 02111-1307 USA
1638 +#include <common.h>
1639 +#include <asm/io.h>
1640 +#include <asm/arch/cpu.h>
1641 +#include <asm/arch/early_print.h>
1642 +#include <asm/arch/gpio.h>
1643 +#include <asm/arch/sys_proto.h>
1645 +static int uart_initialized = 0;
1647 +#define UART CONFIG_CONS_INDEX-1
1648 +void uart_init(void) {
1650 + /* select dll dlh */
1651 + writel(UART_LCR_DLAB, UART_LCR(UART));
1652 + /* set baudrate */
1653 + writel(0, UART_DLH(UART));
1654 + writel(BAUD_115200, UART_DLL(UART));
1655 + /* set line control */
1656 + writel(LC_8_N_1, UART_LCR(UART));
1658 + uart_initialized = 1;
1661 +#define TX_READY (readl(UART_LSR(UART)) & UART_LSR_TEMT)
1663 +void uart_putc(char c) {
1667 + writel(c, UART_THR(UART));
1670 +void uart_puts(const char *s) {
1677 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/key.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/key.c
1678 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/key.c 1970-01-01 01:00:00.000000000 +0100
1679 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/key.c 2014-03-05 23:14:47.128100511 +0100
1682 + * (C) Copyright 2007-2011
1683 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
1684 + * Tom Cubie <tangliang@allwinnertech.com>
1686 + * See file CREDITS for list of people who contributed to this
1689 + * This program is free software; you can redistribute it and/or
1690 + * modify it under the terms of the GNU General Public License as
1691 + * published by the Free Software Foundation; either version 2 of
1692 + * the License, or (at your option) any later version.
1694 + * This program is distributed in the hope that it will be useful,
1695 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1696 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1697 + * GNU General Public License for more details.
1699 + * You should have received a copy of the GNU General Public License
1700 + * along with this program; if not, write to the Free Software
1701 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1702 + * MA 02111-1307 USA
1705 +#include <common.h>
1706 +#include <asm/io.h>
1707 +#include <asm/arch/cpu.h>
1708 +#include <asm/arch/key.h>
1709 +#include <asm/arch/sys_proto.h>
1711 +int sunxi_key_init(void)
1713 + struct sunxi_lradc *sunxi_key_base =
1714 + (struct sunxi_lradc *)SUNXI_LRADC_BASE;
1716 + sr32(&sunxi_key_base->ctrl, 0, 1, LRADC_EN);
1717 + sr32(&sunxi_key_base->ctrl, 2, 2, LRADC_SAMPLE_RATE);
1718 + sr32(&sunxi_key_base->ctrl, 4, 2, LEVELB_VOL);
1719 + sr32(&sunxi_key_base->ctrl, 6, 1, LRADC_HOLD_EN);
1720 + sr32(&sunxi_key_base->ctrl, 12, 2, KEY_MODE_SELECT);
1722 + /* disable all key irq */
1723 + writel(0x0, &sunxi_key_base->intc);
1724 + /* clear all key pending */
1725 + writel(0xffffffff, &sunxi_key_base->ints);
1730 +u32 sunxi_read_key(void)
1734 + struct sunxi_lradc *sunxi_key_base =
1735 + (struct sunxi_lradc *)SUNXI_LRADC_BASE;
1737 + ints = readl(&sunxi_key_base->ints);
1739 + /* if there is already data pending,
1741 + if (ints & ADC0_DATA_PENDING) {
1742 + key = readl(&sunxi_key_base->data0);
1744 + printf("key pressed, value=0x%x\n", key);
1747 + /* clear the pending data */
1748 + writel(ints, &sunxi_key_base->ints);
1751 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/Makefile u-boot-sunxi/arch/arm/cpu/armv7/sunxi/Makefile
1752 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/Makefile 1970-01-01 01:00:00.000000000 +0100
1753 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/Makefile 2014-03-05 23:14:47.128100511 +0100
1756 +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
1758 +# Based on some other Makefile
1759 +# (C) Copyright 2000-2003
1760 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1762 +# See file CREDITS for list of people who contributed to this
1765 +# This program is free software; you can redistribute it and/or
1766 +# modify it under the terms of the GNU General Public License as
1767 +# published by the Free Software Foundation; either version 2 of
1768 +# the License, or (at your option) any later version.
1770 +# This program is distributed in the hope that it will be useful,
1771 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1772 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1773 +# GNU General Public License for more details.
1775 +# You should have received a copy of the GNU General Public License
1776 +# along with this program; if not, write to the Free Software
1777 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1778 +# MA 02111-1307 USA
1785 +obj-y += watchdog.o
1787 +obj-y += early_print.o
1789 +obj-$(CONFIG_BOARD_POSTCLK_INIT) += postclk_init.o
1790 +obj-$(CONFIG_SYS_SECONDARY_ON) += secondary_init.o
1791 +obj-$(CONFIG_SYS_SECONDARY_ON) += smp.o
1793 +ifndef CONFIG_SPL_BUILD
1795 +obj-y += cpu_info.o
1796 +ifdef CONFIG_CMD_WATCHDOG
1797 +obj-$(CONFIG_CMD_WATCHDOG) += cmd_watchdog.o
1799 +ifdef CONFIG_ARMV7_PSCI
1804 +ifdef CONFIG_SPL_BUILD
1806 +ifdef CONFIG_SPL_FEL
1811 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/pinmux.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/pinmux.c
1812 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/pinmux.c 1970-01-01 01:00:00.000000000 +0100
1813 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/pinmux.c 2014-03-05 23:14:47.128100511 +0100
1816 + * (C) Copyright 2007-2011
1817 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
1818 + * Tom Cubie <tangliang@allwinnertech.com>
1820 + * See file CREDITS for list of people who contributed to this
1823 + * This program is free software; you can redistribute it and/or
1824 + * modify it under the terms of the GNU General Public License as
1825 + * published by the Free Software Foundation; either version 2 of
1826 + * the License, or (at your option) any later version.
1828 + * This program is distributed in the hope that it will be useful,
1829 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1830 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1831 + * GNU General Public License for more details.
1833 + * You should have received a copy of the GNU General Public License
1834 + * along with this program; if not, write to the Free Software
1835 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1836 + * MA 02111-1307 USA
1839 +#include <common.h>
1840 +#include <asm/io.h>
1841 +#include <asm/arch/gpio.h>
1843 +int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
1846 + u32 bank = GPIO_BANK(pin);
1847 + u32 index = GPIO_CFG_INDEX(pin);
1848 + u32 offset = GPIO_CFG_OFFSET(pin);
1849 + struct sunxi_gpio *pio =
1850 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
1852 + cfg = readl(&pio->cfg[0] + index);
1853 + cfg &= ~(0xf << offset);
1854 + cfg |= val << offset;
1856 + writel(cfg, &pio->cfg[0] + index);
1861 +int sunxi_gpio_get_cfgpin(u32 pin)
1864 + u32 bank = GPIO_BANK(pin);
1865 + u32 index = GPIO_CFG_INDEX(pin);
1866 + u32 offset = GPIO_CFG_OFFSET(pin);
1867 + struct sunxi_gpio *pio =
1868 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
1870 + cfg = readl(&pio->cfg[0] + index);
1876 +int sunxi_gpio_set_drv(u32 pin, u32 val)
1879 + u32 bank = GPIO_BANK(pin);
1880 + u32 index = GPIO_DRV_INDEX(pin);
1881 + u32 offset = GPIO_DRV_OFFSET(pin);
1882 + struct sunxi_gpio *pio =
1883 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
1885 + drv = readl(&pio->drv[0] + index);
1886 + drv &= ~(0x3 << offset);
1887 + drv |= val << offset;
1889 + writel(drv, &pio->drv[0] + index);
1894 +int sunxi_gpio_set_pull(u32 pin, u32 val)
1897 + u32 bank = GPIO_BANK(pin);
1898 + u32 index = GPIO_PULL_INDEX(pin);
1899 + u32 offset = GPIO_PULL_OFFSET(pin);
1900 + struct sunxi_gpio *pio =
1901 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
1903 + pull = readl(&pio->pull[0] + index);
1904 + pull &= ~(0x3 << offset);
1905 + pull |= val << offset;
1907 + writel(pull, &pio->pull[0] + index);
1911 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/postclk_init.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/postclk_init.c
1912 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/postclk_init.c 1970-01-01 01:00:00.000000000 +0100
1913 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/postclk_init.c 2014-03-05 23:14:47.128100511 +0100
1916 + * (C) Copyright 2013
1917 + * Carl van Schaik <carl@ok-labs.com>
1919 + * See file CREDITS for list of people who contributed to this
1922 + * This program is free software; you can redistribute it and/or
1923 + * modify it under the terms of the GNU General Public License as
1924 + * published by the Free Software Foundation; either version 2 of
1925 + * the License, or (at your option) any later version.
1927 + * This program is distributed in the hope that it will be useful,
1928 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1929 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1930 + * GNU General Public License for more details.
1932 + * You should have received a copy of the GNU General Public License
1933 + * along with this program; if not, write to the Free Software
1934 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1935 + * MA 02111-1307 USA
1938 +#include <common.h>
1939 +#if defined(CONFIG_SYS_SECONDARY_ON)
1940 +#include <asm/arch/smp.h>
1944 +int board_postclk_init(void)
1946 +#if defined(CONFIG_SYS_SECONDARY_ON)
1947 + startup_secondaries();
1951 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/psci.S u-boot-sunxi/arch/arm/cpu/armv7/sunxi/psci.S
1952 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/psci.S 1970-01-01 01:00:00.000000000 +0100
1953 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/psci.S 2014-03-05 23:14:47.128100511 +0100
1956 + * Copyright (C) 2013 - ARM Ltd
1957 + * Author: Marc Zyngier <marc.zyngier@arm.com>
1959 + * Based on code by Carl van Schaik <carl@ok-labs.com>.
1961 + * This program is free software; you can redistribute it and/or modify
1962 + * it under the terms of the GNU General Public License version 2 as
1963 + * published by the Free Software Foundation.
1965 + * This program is distributed in the hope that it will be useful,
1966 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1967 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1968 + * GNU General Public License for more details.
1970 + * You should have received a copy of the GNU General Public License
1971 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1974 +#include <config.h>
1975 +#include <asm/psci.h>
1976 +#include <asm/arch/cpu.h>
1978 + .pushsection ._secure.text, "ax"
1980 + .arch_extension sec
1982 +#define TEN_MS (10 * CONFIG_SYS_CLK_FREQ / 1000)
1988 + adr r0, _target_pc
1992 + movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
1993 + movt r0, #(SUNXI_CPUCFG_BASE >> 16)
1996 + and r1, r1, #3 @ only care about first cluster
2000 + adr r6, _sunxi_cpu_entry
2001 + str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
2003 + @ Assert reset on target CPU
2005 + lsl r5, r1, #6 @ 64 bytes per CPU
2006 + add r5, r5, #0x40 @ Offset from base
2007 + add r5, r5, r0 @ CPU control block
2008 + str r6, [r5] @ Reset CPU
2011 + ldr r6, [r0, #0x184]
2013 + str r6, [r0, #0x184]
2016 + ldr r6, [r0, #0x1e4]
2018 + str r6, [r0, #0x1e4]
2020 + @ Release power clamp
2024 + str r6, [r0, #0x1b0]
2027 + @ Write CNTP_TVAL : 10ms @ 24MHz (240000 cycles)
2028 + movw r1, #(TEN_MS & 0xffff)
2029 + movt r1, #(TEN_MS >> 16)
2030 + mcr p15, 0, r1, c14, c2, 0
2032 + @ Enable physical timer, mask interrupt
2034 + mcr p15, 0, r1, c14, c2, 1
2035 + @ Poll physical timer until ISTATUS is on
2037 + mrc p15, 0, r1, c14, c2, 1
2042 + mcr p15, 0, r1, c14, c2, 1
2045 + @ Clear power gating
2046 + ldr r6, [r0, #0x1b4]
2048 + str r6, [r0, #0x1b4]
2050 + @ Deassert reset on target CPU
2055 + ldr r6, [r0, #0x1e4]
2057 + str r6, [r0, #0x1e4]
2059 + mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
2067 + mrc p15, 0, r0, c1, c0, 1
2069 + mcr p15, 0, r0, c1, c0, 1
2074 + adr r0, _target_pc
2076 + b _do_nonsec_entry
2079 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/secondary_init.S u-boot-sunxi/arch/arm/cpu/armv7/sunxi/secondary_init.S
2080 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/secondary_init.S 1970-01-01 01:00:00.000000000 +0100
2081 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/secondary_init.S 2014-03-05 23:14:47.128100511 +0100
2084 + * A lowlevel_init function that sets up the stack to call a C function to
2085 + * perform further init.
2087 + * (C) Copyright 2013
2088 + * Carl van Schaik <carl@ok-labs.com>
2090 + * See file CREDITS for list of people who contributed to this
2093 + * This program is free software; you can redistribute it and/or
2094 + * modify it under the terms of the GNU General Public License as
2095 + * published by the Free Software Foundation; either version 2 of
2096 + * the License, or (at your option) any later version.
2098 + * This program is distributed in the hope that it will be useful,
2099 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2100 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2101 + * GNU General Public License for more details.
2103 + * You should have received a copy of the GNU General Public License
2104 + * along with this program; if not, write to the Free Software
2105 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2106 + * MA 02111-1307 USA
2109 +#include <asm-offsets.h>
2110 +#include <config.h>
2111 +#include <linux/linkage.h>
2113 +ENTRY(secondary_init)
2114 + /* Get cpu number : r5 */
2115 + mrc p15, 0, r5, c0, c0, 5
2119 + * Setup a secondary stack, each core gets 128 bytes.
2121 + ldr sp, =secondary_stack
2123 + add sp, sp, r0, lsl r5
2128 + bl secondary_start
2129 +ENDPROC(secondary_init)
2131 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/smp.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/smp.c
2132 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/smp.c 1970-01-01 01:00:00.000000000 +0100
2133 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/smp.c 2014-03-05 23:14:47.128100511 +0100
2136 + * (C) Copyright 2013
2137 + * Carl van Schaik <carl@ok-labs.com>
2139 + * See file CREDITS for list of people who contributed to this
2142 + * This program is free software; you can redistribute it and/or
2143 + * modify it under the terms of the GNU General Public License as
2144 + * published by the Free Software Foundation; either version 2 of
2145 + * the License, or (at your option) any later version.
2147 + * This program is distributed in the hope that it will be useful,
2148 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2149 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2150 + * GNU General Public License for more details.
2152 + * You should have received a copy of the GNU General Public License
2153 + * along with this program; if not, write to the Free Software
2154 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2155 + * MA 02111-1307 USA
2158 +#include <common.h>
2159 +#include <asm/io.h>
2160 +#include <asm/arch/smp.h>
2161 +#include <asm/arch/cpucfg.h>
2163 +/* Right now we assume only a single secondary as in sun7i */
2164 +#if defined(CONFIG_SUN7I)
2165 +#define NUM_CORES 2
2167 +#error unsupported SoC
2170 +static void secondary_pen(void)
2172 + struct sunxi_cpucfg *cpucfg = (struct sunxi_cpucfg *)SUNXI_CPUCFG_BASE;
2175 + __asm__ __volatile__("wfe" ::: "memory");
2177 + unsigned long boot_addr = readl(&cpucfg->boot_addr);
2179 + __asm__ __volatile__(
2182 + : : "r" (boot_addr)
2187 +u32 secondary_stack[32*(NUM_CORES-1)];
2189 +void secondary_start(void)
2194 +/* Power on secondaries */
2195 +void startup_secondaries(void)
2198 + struct sunxi_cpucfg *cpucfg = (struct sunxi_cpucfg *)SUNXI_CPUCFG_BASE;
2200 + writel((u32)secondary_init, &cpucfg->boot_addr);
2202 + for (i = 1; i < NUM_CORES; i++) {
2203 + /* Assert CPU reset just in case */
2204 + writel(CPU_RESET_SET, &cpucfg->cpu[i].reset_ctrl);
2205 + /* Ensure CPU reset also invalidates L1 caches */
2206 + clrbits_le32(&cpucfg->general_ctrl,
2207 + GENERAL_CTRL_NO_L1_RESET_CPU(i));
2209 + clrbits_le32(&cpucfg->debug1_ctrl, 1 << i);
2211 + /* Ramp up power to CPU1 */
2213 + u32 j = 0xff << 1;
2216 + writel(j, &cpucfg->cpu1_power_clamp);
2219 + udelay(10*1000); /* 10ms */
2221 + clrbits_le32(&cpucfg->cpu1_power_off, 1);
2222 + /* Release CPU reset */
2223 + writel(CPU_RESET_CLEAR, &cpucfg->cpu[i].reset_ctrl);
2226 + setbits_le32(&cpucfg->debug1_ctrl, 1 << i);
2228 + printf("Secondary CPU%d power-on\n", i);
2231 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/start.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/start.c
2232 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/start.c 1970-01-01 01:00:00.000000000 +0100
2233 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/start.c 2014-03-05 23:14:47.128100511 +0100
2235 +/* Intentionally empty. Only needed to get FEL SPL link line right */
2236 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/timer.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/timer.c
2237 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/timer.c 1970-01-01 01:00:00.000000000 +0100
2238 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/timer.c 2014-03-05 23:14:47.132100458 +0100
2241 + * (C) Copyright 2007-2011
2242 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2243 + * Tom Cubie <tangliang@allwinnertech.com>
2245 + * See file CREDITS for list of people who contributed to this
2248 + * This program is free software; you can redistribute it and/or
2249 + * modify it under the terms of the GNU General Public License as
2250 + * published by the Free Software Foundation; either version 2 of
2251 + * the License, or (at your option) any later version.
2253 + * This program is distributed in the hope that it will be useful,
2254 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2255 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2256 + * GNU General Public License for more details.
2258 + * You should have received a copy of the GNU General Public License
2259 + * along with this program; if not, write to the Free Software
2260 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2261 + * MA 02111-1307 USA
2264 +#include <common.h>
2265 +#include <asm/io.h>
2266 +#include <asm/arch/timer.h>
2268 +DECLARE_GLOBAL_DATA_PTR;
2270 +#define TIMER_MODE (0x0 << 7) /* continuous mode */
2271 +#define TIMER_DIV (0x0 << 4) /* pre scale 1 */
2272 +#define TIMER_SRC (0x1 << 2) /* osc24m */
2273 +#define TIMER_RELOAD (0x1 << 1) /* reload internal value */
2274 +#define TIMER_EN (0x1 << 0) /* enable timer */
2276 +#define TIMER_CLOCK (24 * 1000 * 1000)
2277 +#define COUNT_TO_USEC(x) ((x) / 24)
2278 +#define USEC_TO_COUNT(x) ((x) * 24)
2279 +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
2280 +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
2282 +#define TIMER_LOAD_VAL 0xffffffff
2284 +#define TIMER_NUM 0 /* we use timer 0 */
2286 +static struct sunxi_timer *timer_base =
2287 + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->timer[TIMER_NUM];
2289 +/* macro to read the 32 bit timer: since it decrements, we invert read value */
2290 +#define READ_TIMER() (~readl(&timer_base->val))
2292 +/* init timer register */
2293 +int timer_init(void)
2295 + writel(TIMER_LOAD_VAL, &timer_base->inter);
2296 + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
2297 + &timer_base->ctl);
2302 +/* timer without interrupts */
2303 +ulong get_timer(ulong base)
2305 + return get_timer_masked() - base;
2308 +ulong get_timer_masked(void)
2310 + /* current tick value */
2311 + ulong now = TICKS_TO_HZ(READ_TIMER());
2313 + if (now >= gd->arch.lastinc) /* normal (non rollover) */
2314 + gd->arch.tbl += (now - gd->arch.lastinc);
2317 + gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
2318 + - gd->arch.lastinc) + now;
2320 + gd->arch.lastinc = now;
2322 + return gd->arch.tbl;
2325 +/* delay x useconds */
2326 +void __udelay(unsigned long usec)
2328 + long tmo = USEC_TO_COUNT(usec);
2329 + ulong now, last = READ_TIMER();
2332 + now = READ_TIMER();
2333 + if (now > last) /* normal (non rollover) */
2334 + tmo -= now - last;
2335 + else /* rollover */
2336 + tmo -= TIMER_LOAD_VAL - last + now;
2342 + * This function is derived from PowerPC code (read timebase as long long).
2343 + * On ARM it just returns the timer value.
2345 +unsigned long long get_ticks(void)
2347 + return get_timer(0);
2351 + * This function is derived from PowerPC code (timebase clock frequency).
2352 + * On ARM it returns the number of timer ticks per second.
2354 +ulong get_tbclk(void)
2357 + tbclk = CONFIG_SYS_HZ;
2360 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-psci.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-psci.lds
2361 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-psci.lds 1970-01-01 01:00:00.000000000 +0100
2362 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-psci.lds 2014-03-05 23:14:47.132100458 +0100
2365 + * (C) Copyright 2013 ARM Ltd
2366 + * Marc Zyngier <marc.zyngier@arm.com>
2368 + * Based on sunxi/u-boot-spl.lds:
2370 + * (C) Copyright 2012
2371 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2372 + * Tom Cubie <tangliang@allwinnertech.com>
2374 + * Based on omap-common/u-boot-spl.lds:
2376 + * (C) Copyright 2002
2377 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
2379 + * (C) Copyright 2010
2380 + * Texas Instruments, <www.ti.com>
2381 + * Aneesh V <aneesh@ti.com>
2383 + * See file CREDITS for list of people who contributed to this
2386 + * This program is free software; you can redistribute it and/or
2387 + * modify it under the terms of the GNU General Public License as
2388 + * published by the Free Software Foundation; either version 2 of
2389 + * the License, or (at your option) any later version.
2391 + * This program is distributed in the hope that it will be useful,
2392 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2393 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2394 + * GNU General Public License for more details.
2396 + * You should have received a copy of the GNU General Public License
2397 + * along with this program; if not, write to the Free Software
2398 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2399 + * MA 02111-1307 USA
2402 +MEMORY { sram : ORIGIN = CONFIG_ARMV7_PSCI_BASE, LENGTH = 0x1000 }
2403 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
2415 + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > sram
2418 + .data : { *(SORT_BY_ALIGNMENT(.data*)) } > sram
2427 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
2428 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds 1970-01-01 01:00:00.000000000 +0100
2429 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds 2014-03-05 23:14:47.132100458 +0100
2431 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
2444 + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
2453 + __rel_dyn_start = .;
2455 + __rel_dyn_end = .;
2458 + __dynsym_start = .;
2462 + .note.gnu.build-id :
2464 + *(.note.gnu.build-id)
2471 + .bss_start __rel_dyn_start (OVERLAY) : {
2472 + KEEP(*(.__bss_start));
2475 + .bss __bss_base (OVERLAY) : {
2480 + .bss_end __bss_limit (OVERLAY) : {
2481 + KEEP(*(.__bss_end));
2483 + /DISCARD/ : { *(.dynstr*) }
2484 + /DISCARD/ : { *(.dynamic*) }
2485 + /DISCARD/ : { *(.plt*) }
2486 + /DISCARD/ : { *(.interp*) }
2487 + /DISCARD/ : { *(.gnu*) }
2488 + /DISCARD/ : { *(.note*) }
2490 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
2491 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds 1970-01-01 01:00:00.000000000 +0100
2492 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds 2014-03-05 23:14:47.132100458 +0100
2495 + * (C) Copyright 2012
2496 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2497 + * Tom Cubie <tangliang@allwinnertech.com>
2499 + * Based on omap-common/u-boot-spl.lds:
2501 + * (C) Copyright 2002
2502 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
2504 + * (C) Copyright 2010
2505 + * Texas Instruments, <www.ti.com>
2506 + * Aneesh V <aneesh@ti.com>
2508 + * See file CREDITS for list of people who contributed to this
2511 + * This program is free software; you can redistribute it and/or
2512 + * modify it under the terms of the GNU General Public License as
2513 + * published by the Free Software Foundation; either version 2 of
2514 + * the License, or (at your option) any later version.
2516 + * This program is distributed in the hope that it will be useful,
2517 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2518 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2519 + * GNU General Public License for more details.
2521 + * You should have received a copy of the GNU General Public License
2522 + * along with this program; if not, write to the Free Software
2523 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2524 + * MA 02111-1307 USA
2527 +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
2528 + LENGTH = CONFIG_SPL_MAX_SIZE }
2529 +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
2530 + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
2532 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
2540 + arch/arm/cpu/armv7/start.o (.text)
2545 + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
2548 + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
2551 + __image_copy_end = .;
2563 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/watchdog.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/watchdog.c
2564 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/sunxi/watchdog.c 1970-01-01 01:00:00.000000000 +0100
2565 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/watchdog.c 2014-03-05 23:14:47.132100458 +0100
2568 + * Watchdog driver for the Allwinner sunxi platform.
2569 + * Copyright (C) 2013 Oliver Schinagl <oliver@schinagl.nl>
2570 + * http://www.linux-sunxi.org/
2572 + * This program is free software; you can redistribute it and/or
2573 + * modify it under the terms of the GNU General Public License
2574 + * as published by the Free Software Foundation; either version 2
2575 + * of the License, or (at your option) any later version.
2577 + * This program is distributed in the hope that it will be useful,
2578 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2579 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2580 + * GNU General Public License for more details.
2582 + * You should have received a copy of the GNU General Public License
2583 + * along with this program; if not, write to the Free Software
2584 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
2585 + * MA 02110-1301, USA.
2588 +#include <asm/io.h>
2589 +#include <asm/arch/timer.h>
2590 +#include <asm/arch/watchdog.h>
2591 +#include <common.h>
2592 +#include <watchdog.h>
2595 +#define WDT_CTRL_RESTART (0x1 << 0)
2596 +#define WDT_CTRL_KEY (0x0a57 << 1)
2598 +#define WDT_MODE_EN (0x1 << 0)
2599 +#define WDT_MODE_RESET_EN (0x1 << 1)
2600 +#define WDT_MAX_TIMEOUT 16
2601 +#define WDT_MODE_TIMEOUT(n) \
2602 + (wdt_timeout_map[(n) < WDT_MAX_TIMEOUT ? (n) : WDT_MAX_TIMEOUT] << 3)
2606 + * Watchdog timeout table. The sunxi cores only use 4 bits for the watchdog as
2607 + * set by the table below. The gaps are filled by rounding up to the next
2610 +const unsigned int wdt_timeout_map[] = {
2611 + [0] = 0b0000, /* 0.5s*/
2612 + [1] = 0b0001, /* 1s */
2613 + [2] = 0b0010, /* 2s */
2614 + [3] = 0b0011, /* 3s */
2615 + [4] = 0b0100, /* 4s */
2616 + [5] = 0b0101, /* 5s */
2617 + [6] = 0b0110, /* 6s */
2618 + [7] = 0b0111, /* 8s */
2619 + [8] = 0b0111, /* 8s */
2620 + [9] = 0b1000, /* 10s */
2621 + [10] = 0b1000, /* 10s */
2622 + [11] = 0b1001, /* 12s */
2623 + [12] = 0b1001, /* 12s */
2624 + [13] = 0b1010, /* 14s */
2625 + [14] = 0b1010, /* 14s */
2626 + [15] = 0b1011, /* 16s */
2627 + [16] = 0b1011, /* 16s */
2631 +void watchdog_reset(void)
2633 + static const struct sunxi_wdog *wdog =
2634 + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
2636 + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
2639 +void watchdog_set(int timeout)
2641 + static struct sunxi_wdog *const wdog =
2642 + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
2644 + /* Set timeout, reset & enable */
2645 + if (timeout >= 0) {
2646 + writel(WDT_MODE_TIMEOUT(timeout) |
2647 + WDT_MODE_RESET_EN | WDT_MODE_EN,
2650 + writel(0, &wdog->mode);
2655 +void watchdog_init(void)
2657 +#ifdef CONFIG_WATCHDOG
2658 + watchdog_set(WDT_MAX_TIMEOUT);
2660 + watchdog_set(WDT_OFF); /* no timeout */
2663 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/virt-dt.c u-boot-sunxi/arch/arm/cpu/armv7/virt-dt.c
2664 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/virt-dt.c 1970-01-01 01:00:00.000000000 +0100
2665 +++ u-boot-sunxi/arch/arm/cpu/armv7/virt-dt.c 2014-03-05 23:14:47.132100458 +0100
2668 + * Copyright (C) 2013 - ARM Ltd
2669 + * Author: Marc Zyngier <marc.zyngier@arm.com>
2671 + * This program is free software; you can redistribute it and/or modify
2672 + * it under the terms of the GNU General Public License version 2 as
2673 + * published by the Free Software Foundation.
2675 + * This program is distributed in the hope that it will be useful,
2676 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2677 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2678 + * GNU General Public License for more details.
2680 + * You should have received a copy of the GNU General Public License
2681 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
2684 +#include <common.h>
2685 +#include <stdio_dev.h>
2686 +#include <linux/ctype.h>
2687 +#include <linux/types.h>
2688 +#include <asm/global_data.h>
2689 +#include <libfdt.h>
2690 +#include <fdt_support.h>
2691 +#include <asm/armv7.h>
2692 +#include <asm/psci.h>
2694 +static int fdt_psci(void *fdt)
2696 +#ifdef CONFIG_ARMV7_PSCI
2700 + nodeoff = fdt_path_offset(fdt, "/cpus");
2701 + if (nodeoff < 0) {
2702 + printf("couldn't find /cpus\n");
2706 + /* add 'enable-method = "psci"' to each cpu node */
2707 + for (tmp = fdt_first_subnode(fdt, nodeoff);
2709 + tmp = fdt_next_subnode(fdt, tmp)) {
2710 + const struct fdt_property *prop;
2713 + prop = fdt_get_property(fdt, tmp, "device_type", &len);
2718 + if (strcmp(prop->data, "cpu"))
2721 + fdt_setprop_string(fdt, tmp, "enable-method", "psci");
2724 + nodeoff = fdt_path_offset(fdt, "/psci");
2725 + if (nodeoff < 0) {
2726 + nodeoff = fdt_path_offset(fdt, "/");
2730 + nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
2735 + tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
2738 + tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
2741 + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND);
2744 + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
2747 + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
2750 + tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
2757 +int armv7_update_dt(void *fdt)
2759 +#ifndef CONFIG_ARMV7_SECURE_BASE
2760 + /* secure code lives in RAM, keep it alive */
2761 + fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
2762 + __secure_end - __secure_start);
2765 + return fdt_psci(fdt);
2767 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/armv7/virt-v7.c u-boot-sunxi/arch/arm/cpu/armv7/virt-v7.c
2768 --- u-boot-2014.01-rc1/arch/arm/cpu/armv7/virt-v7.c 2013-11-25 22:49:32.000000000 +0100
2769 +++ u-boot-sunxi/arch/arm/cpu/armv7/virt-v7.c 2014-03-05 23:14:47.132100458 +0100
2771 #include <asm/armv7.h>
2772 #include <asm/gic.h>
2774 +#include <asm/secure.h>
2776 unsigned long gic_dist_addr;
2778 -static unsigned int read_cpsr(void)
2782 - asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
2786 static unsigned int read_id_pfr1(void)
2793 +static void relocate_secure_section(void)
2795 +#ifdef CONFIG_ARMV7_SECURE_BASE
2796 + size_t sz = __secure_end - __secure_start;
2798 + memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
2799 + flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
2800 + CONFIG_ARMV7_SECURE_BASE + sz + 1);
2801 + invalidate_icache_all();
2805 static void kick_secondary_cpus_gic(unsigned long gicdaddr)
2807 /* kick all CPUs (except this one) by writing to GICD_SGIR */
2809 kick_secondary_cpus_gic(gic_dist_addr);
2812 -int armv7_switch_hyp(void)
2816 - /* check whether we are in HYP mode already */
2817 - if ((read_cpsr() & 0x1f) == 0x1a) {
2818 - debug("CPU already in HYP mode\n");
2822 - /* check whether the CPU supports the virtualization extensions */
2823 - reg = read_id_pfr1();
2824 - if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
2825 - printf("HYP mode: Virtualization extensions not implemented.\n");
2829 - /* call the HYP switching code on this CPU also */
2832 - if ((read_cpsr() & 0x1F) != 0x1a) {
2833 - printf("HYP mode: switch not successful.\n");
2840 -int armv7_switch_nonsec(void)
2841 +int armv7_init_nonsec(void)
2844 unsigned itlinesnr, i;
2845 @@ -147,11 +124,13 @@
2846 for (i = 1; i <= itlinesnr; i++)
2847 writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
2849 - smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
2850 +#ifndef CONFIG_ARMV7_PSCI
2851 + smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
2852 smp_kick_all_cpus();
2855 /* call the non-sec switching code on this CPU also */
2858 + relocate_secure_section();
2859 + secure_ram_addr(_nonsec_init)();
2862 diff -ruN u-boot-2014.01-rc1/arch/arm/cpu/u-boot.lds u-boot-sunxi/arch/arm/cpu/u-boot.lds
2863 --- u-boot-2014.01-rc1/arch/arm/cpu/u-boot.lds 2013-11-25 22:49:32.000000000 +0100
2864 +++ u-boot-sunxi/arch/arm/cpu/u-boot.lds 2014-03-05 23:14:47.136100405 +0100
2866 * SPDX-License-Identifier: GPL-2.0+
2869 +#include <config.h>
2871 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
2878 +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
2880 +#ifndef CONFIG_ARMV7_SECURE_BASE
2881 +#define CONFIG_ARMV7_SECURE_BASE
2884 + .__secure_start : {
2885 + . = ALIGN(0x1000);
2886 + *(.__secure_start)
2889 + .secure_text CONFIG_ARMV7_SECURE_BASE :
2890 + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
2895 + . = LOADADDR(.__secure_start) +
2896 + SIZEOF(.__secure_start) +
2897 + SIZEOF(.secure_text);
2899 + __secure_end_lma = .;
2900 + .__secure_end : AT(__secure_end_lma) {
2902 + LONG(0x1d1071c); /* Must output something to reset LMA */
2907 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
2909 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock.h
2910 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/clock.h 1970-01-01 01:00:00.000000000 +0100
2911 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock.h 2014-03-05 23:14:47.176099871 +0100
2914 + * (C) Copyright 2007-2011
2915 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2916 + * Tom Cubie <tangliang@allwinnertech.com>
2918 + * See file CREDITS for list of people who contributed to this
2921 + * This program is free software; you can redistribute it and/or
2922 + * modify it under the terms of the GNU General Public License as
2923 + * published by the Free Software Foundation; either version 2 of
2924 + * the License, or (at your option) any later version.
2926 + * This program is distributed in the hope that it will be useful,
2927 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2928 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2929 + * GNU General Public License for more details.
2931 + * You should have received a copy of the GNU General Public License
2932 + * along with this program; if not, write to the Free Software
2933 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2934 + * MA 02111-1307 USA
2937 +#ifndef _SUNXI_CLOCK_H
2938 +#define _SUNXI_CLOCK_H
2940 +#include <linux/types.h>
2942 +#define CLK_GATE_OPEN 0x1
2943 +#define CLK_GATE_CLOSE 0x0
2945 +/* clock control module regs definition */
2946 +#if defined(CONFIG_SUN6I)
2947 +struct sunxi_ccm_reg {
2948 + u32 pll1_cfg; /* 0x00 pll1 control */
2950 + u32 pll2_cfg; /* 0x08 pll2 control */
2952 + u32 pll3_cfg; /* 0x10 pll3 control */
2954 + u32 pll4_cfg; /* 0x18 pll4 control */
2956 + u32 pll5_cfg; /* 0x20 pll5 control */
2958 + u32 pll6_cfg; /* 0x28 pll6 control */
2960 + u32 pll7_cfg; /* 0x30 pll7 control */
2962 + u32 pll8_cfg; /* 0x38 pll8 control */
2964 + u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
2965 + u32 pll9_cfg; /* 0x44 pll9 control */
2966 + u32 pll10_cfg; /* 0x48 pll10 control */
2968 + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
2969 + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
2970 + u32 apb2_div; /* 0x58 APB2 divide ratio */
2971 + u32 axi_gate; /* 0x5c axi module clock gating */
2972 + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
2973 + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
2974 + u32 apb1_gate; /* 0x68 apb1 module clock gating */
2975 + u32 apb2_gate; /* 0x6c apb2 module clock gating */
2977 + u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
2978 + u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
2979 + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
2980 + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
2981 + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
2982 + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
2983 + u32 ts_clk_cfg; /* 0x98 transport stream clock control */
2984 + u32 ss_clk_cfg; /* 0x9c security system clock control */
2985 + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
2986 + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
2987 + u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */
2988 + u32 spi3_clk_cfg; /* 0xac spi3 clock control */
2989 + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/
2990 + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
2991 + u32 reserved10[2];
2992 + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
2993 + u32 reserved11[2];
2994 + u32 usb_clk_cfg; /* 0xcc USB clock control */
2995 + u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
2996 + u32 reserved12[7];
2997 + u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
2998 + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
2999 + u32 reserved13[2];
3000 + u32 dram_clk_gate; /* 0x100 DRAM module gating */
3001 + u32 be0_clk_cfg; /* 0x104 BE0 module clock */
3002 + u32 be1_clk_cfg; /* 0x108 BE1 module clock */
3003 + u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
3004 + u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
3005 + u32 mp_clk_cfg; /* 0x114 MP module clock */
3006 + u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
3007 + u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
3008 + u32 reserved14[3];
3009 + u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
3010 + u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
3011 + u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */
3012 + u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */
3013 + u32 ve_clk_cfg; /* 0x13c VE module clock */
3014 + u32 adda_clk_cfg; /* 0x140 ADDA module clock */
3015 + u32 avs_clk_cfg; /* 0x144 AVS module clock */
3016 + u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
3018 + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
3019 + u32 ps_clk_cfg; /* 0x154 PS module clock */
3020 + u32 mtc_clk_cfg; /* 0x158 MTC module clock */
3021 + u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
3022 + u32 mbus1_clk_cfg; /* 0x160 MBUS0 module clock */
3024 + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
3025 + u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
3026 + u32 reserved17[4];
3027 + u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */
3028 + u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */
3029 + u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */
3030 + u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */
3031 + u32 reserved18[4];
3032 + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
3033 + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
3034 + u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */
3035 + u32 reserved19[21];
3036 + u32 pll_lock; /* 0x200 PLL Lock Time */
3037 + u32 pll1_lock; /* 0x204 PLL1 Lock Time */
3038 + u32 reserved20[6];
3039 + u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
3040 + u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
3041 + u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
3042 + u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
3043 + u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
3044 + u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
3045 + u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
3046 + u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */
3047 + u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
3048 + u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
3049 + u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
3050 + u32 reserved21[13];
3051 + u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
3052 + u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
3053 + u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
3054 + u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
3055 + u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
3056 + u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
3057 + u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
3058 + u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */
3059 + u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
3060 + u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
3061 + u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
3062 + u32 reserved22[5];
3063 + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
3064 + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
3065 + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
3067 + u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
3069 + u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
3072 +/* apb2 bit field */
3073 +#define APB2_CLK_SRC_OSC24M 1
3074 +#define APB2_FACTOR_M 0
3075 +#define APB2_FACTOR_N 0
3079 +struct sunxi_ccm_reg {
3080 + u32 pll1_cfg; /* 0x00 pll1 control */
3081 + u32 pll1_tun; /* 0x04 pll1 tuning */
3082 + u32 pll2_cfg; /* 0x08 pll2 control */
3083 + u32 pll2_tun; /* 0x0c pll2 tuning */
3084 + u32 pll3_cfg; /* 0x10 pll3 control */
3086 + u32 pll4_cfg; /* 0x18 pll4 control */
3088 + u32 pll5_cfg; /* 0x20 pll5 control */
3089 + u32 pll5_tun; /* 0x24 pll5 tuning */
3090 + u32 pll6_cfg; /* 0x28 pll6 control */
3091 + u32 pll6_tun; /* 0x2c pll6 tuning */
3092 + u32 pll7_cfg; /* 0x30 pll7 control */
3093 + u32 pll1_tun2; /* 0x34 pll5 tuning2 */
3095 + u32 pll5_tun2; /* 0x3c pll5 tuning2 */
3097 + u32 pll_lock_dbg; /* 0x4c pll lock time debug */
3098 + u32 osc24m_cfg; /* 0x50 osc24m control */
3099 + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
3100 + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
3101 + u32 axi_gate; /* 0x5c axi module clock gating */
3102 + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
3103 + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
3104 + u32 apb0_gate; /* 0x68 apb0 module clock gating */
3105 + u32 apb1_gate; /* 0x6c apb1 module clock gating */
3107 + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
3108 + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
3109 + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
3110 + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
3111 + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
3112 + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
3113 + u32 ts_clk_cfg; /* 0x98 transport stream clock control */
3114 + u32 ss_clk_cfg; /* 0x9c */
3115 + u32 spi0_clk_cfg; /* 0xa0 */
3116 + u32 spi1_clk_cfg; /* 0xa4 */
3117 + u32 spi2_clk_cfg; /* 0xa8 */
3118 + u32 pata_clk_cfg; /* 0xac */
3119 + u32 ir0_clk_cfg; /* 0xb0 */
3120 + u32 ir1_clk_cfg; /* 0xb4 */
3121 + u32 iis_clk_cfg; /* 0xb8 */
3122 + u32 ac97_clk_cfg; /* 0xbc */
3123 + u32 spdif_clk_cfg; /* 0xc0 */
3124 + u32 keypad_clk_cfg; /* 0xc4 */
3125 + u32 sata_clk_cfg; /* 0xc8 */
3126 + u32 usb_clk_cfg; /* 0xcc */
3127 + u32 gps_clk_cfg; /* 0xd0 */
3128 + u32 spi3_clk_cfg; /* 0xd4 */
3130 + u32 dram_clk_cfg; /* 0x100 */
3131 + u32 be0_clk_cfg; /* 0x104 */
3132 + u32 be1_clk_cfg; /* 0x108 */
3133 + u32 fe0_clk_cfg; /* 0x10c */
3134 + u32 fe1_clk_cfg; /* 0x110 */
3135 + u32 mp_clk_cfg; /* 0x114 */
3136 + u32 lcd0_ch0_clk_cfg; /* 0x118 */
3137 + u32 lcd1_ch0_clk_cfg; /* 0x11c */
3138 + u32 csi_isp_clk_cfg; /* 0x120 */
3140 + u32 tvd_clk_reg; /* 0x128 */
3141 + u32 lcd0_ch1_clk_cfg; /* 0x12c */
3142 + u32 lcd1_ch1_clk_cfg; /* 0x130 */
3143 + u32 csi0_clk_cfg; /* 0x134 */
3144 + u32 csi1_clk_cfg; /* 0x138 */
3145 + u32 ve_clk_cfg; /* 0x13c */
3146 + u32 audio_codec_clk_cfg; /* 0x140 */
3147 + u32 avs_clk_cfg; /* 0x144 */
3148 + u32 ace_clk_cfg; /* 0x148 */
3149 + u32 lvds_clk_cfg; /* 0x14c */
3150 + u32 hdmi_clk_cfg; /* 0x150 */
3151 + u32 mali_clk_cfg; /* 0x154 */
3153 + u32 mbus_clk_cfg; /* 0x15c */
3155 + u32 gmac_clk_cfg; /* 0x164 */
3158 +/* apb1 bit field */
3159 +#define APB1_CLK_SRC_OSC24M 0
3160 +#define APB1_FACTOR_M 0
3161 +#define APB1_FACTOR_N 0
3164 +#define CPU_CLK_SRC_OSC24M 1
3165 +#define CPU_CLK_SRC_PLL1 2
3166 +#define AXI_DIV_1 0
3167 +#define AXI_DIV_2 1
3168 +#define AXI_DIV_3 2
3169 +#define AXI_DIV_4 3
3170 +#define AHB_DIV_1 0
3171 +#define AHB_DIV_2 1
3172 +#define AHB_DIV_4 2
3173 +#define AHB_DIV_8 3
3174 +#define APB0_DIV_1 0
3175 +#define APB0_DIV_2 1
3176 +#define APB0_DIV_4 2
3177 +#define APB0_DIV_8 3
3179 +#ifdef CONFIG_SUN5I
3180 +#define AHB_CLK_SRC_AXI 0
3184 +#define NAND_CLK_SRC_OSC24 0
3185 +#define NAND_CLK_DIV_N 0
3186 +#define NAND_CLK_DIV_M 0
3189 +#define GPS_SCLK_GATING_OFF 0
3190 +#define GPS_RESET 0
3192 +/* ahb clock gate bit offset */
3193 +#define AHB_GATE_OFFSET_GPS 26
3194 +#define AHB_GATE_OFFSET_SATA 25
3195 +#define AHB_GATE_OFFSET_PATA 24
3196 +#define AHB_GATE_OFFSET_SPI3 23
3197 +#define AHB_GATE_OFFSET_SPI2 22
3198 +#define AHB_GATE_OFFSET_SPI1 21
3199 +#define AHB_GATE_OFFSET_SPI0 20
3200 +#define AHB_GATE_OFFSET_TS0 18
3201 +#define AHB_GATE_OFFSET_EMAC 17
3202 +#define AHB_GATE_OFFSET_ACE 16
3203 +#define AHB_GATE_OFFSET_DLL 15
3204 +#define AHB_GATE_OFFSET_SDRAM 14
3205 +#define AHB_GATE_OFFSET_NAND 13
3206 +#define AHB_GATE_OFFSET_MS 12
3207 +#define AHB_GATE_OFFSET_MMC3 11
3208 +#define AHB_GATE_OFFSET_MMC2 10
3209 +#define AHB_GATE_OFFSET_MMC1 9
3210 +#define AHB_GATE_OFFSET_MMC0 8
3211 +#define AHB_GATE_OFFSET_BIST 7
3212 +#define AHB_GATE_OFFSET_DMA 6
3213 +#define AHB_GATE_OFFSET_SS 5
3214 +#define AHB_GATE_OFFSET_USB_OHCI1 4
3215 +#define AHB_GATE_OFFSET_USB_EHCI1 3
3216 +#define AHB_GATE_OFFSET_USB_OHCI0 2
3217 +#define AHB_GATE_OFFSET_USB_EHCI0 1
3218 +#define AHB_GATE_OFFSET_USB 0
3220 +/* ahb clock gate bit offset (second register) */
3221 +#define AHB_GATE_OFFSET_GMAC 17
3223 +#define CCM_AHB_GATE_GPS (0x1 << 26)
3224 +#define CCM_AHB_GATE_SDRAM (0x1 << 14)
3225 +#define CCM_AHB_GATE_DLL (0x1 << 15)
3226 +#define CCM_AHB_GATE_ACE (0x1 << 16)
3228 +#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
3229 +#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
3230 +#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
3231 +#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2)
3232 +#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
3233 +#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
3234 +#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
3235 +#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
3236 +#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
3237 +#define CCM_PLL5_CTRL_LDO (0x1 << 7)
3238 +#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
3239 +#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
3240 +#define CCM_PLL5_CTRL_N_X(n) (n)
3241 +#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
3242 +#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
3243 +#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
3244 +#define CCM_PLL5_CTRL_BW (0x1 << 18)
3245 +#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19)
3246 +#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20)
3247 +#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f)
3248 +#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1)
3249 +#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25)
3250 +#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29)
3251 +#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
3252 +#define CCM_PLL5_CTRL_EN (0x1 << 31)
3254 +#define CCM_GPS_CTRL_RESET (0x1 << 0)
3255 +#define CCM_GPS_CTRL_GATE (0x1 << 1)
3257 +#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15)
3259 +#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0)
3260 +#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf)
3261 +#define CCM_MBUS_CTRL_M_X(n) ((n) - 1)
3262 +#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16)
3263 +#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf)
3264 +#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0)))
3265 +#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24)
3266 +#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3)
3267 +#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0
3268 +#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1
3269 +#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
3270 +#define CCM_MBUS_CTRL_GATE (0x1 << 31)
3272 +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
3273 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
3274 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
3275 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
3276 +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
3278 +#endif /* CONFIG_SUN6I */
3280 +#ifndef __ASSEMBLY__
3281 +int clock_init(void);
3282 +int clock_twi_onoff(int port, int state);
3283 +void clock_set_pll1(int mhz);
3284 +unsigned int clock_get_pll5(void);
3287 +#endif /* _SUNXI_CLOCK_H */
3288 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpucfg.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpucfg.h
3289 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpucfg.h 1970-01-01 01:00:00.000000000 +0100
3290 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpucfg.h 2014-03-05 23:14:47.176099871 +0100
3293 + * (C) Copyright 2013
3294 + * Carl van Schaik <carl@ok-labs.com>
3296 + * CPU configuration registers for the sun7i (A20).
3298 + * See file CREDITS for list of people who contributed to this
3301 + * This program is free software; you can redistribute it and/or
3302 + * modify it under the terms of the GNU General Public License as
3303 + * published by the Free Software Foundation; either version 2 of
3304 + * the License, or (at your option) any later version.
3306 + * This program is distributed in the hope that it will be useful,
3307 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3308 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3309 + * GNU General Public License for more details.
3311 + * You should have received a copy of the GNU General Public License
3312 + * along with this program; if not, write to the Free Software
3313 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3314 + * MA 02111-1307 USA
3317 +#ifndef _SUNXI_CPUCFG_H_
3318 +#define _SUNXI_CPUCFG_H_
3320 +#ifndef __ASSEMBLY__
3322 +struct sunxi_cpu_ctrl {
3329 +#define CPU_RESET_SET 0
3330 +#define CPU_RESET_CLEAR 3
3332 +#define CPU_STATUS_SMP (1 << 0)
3333 +#define CPU_STATUS_WFE (1 << 1)
3334 +#define CPU_STATUS_WFI (1 << 2)
3336 +struct sunxi_cpucfg {
3337 + u32 _res1[16]; /* 0x000 */
3338 + struct sunxi_cpu_ctrl cpu[2]; /* 0x040 */
3339 + u32 _res2[48]; /* 0x0c0 */
3340 + u32 _res3; /* 0x180 */
3341 + u32 general_ctrl; /* 0x184 */
3342 + u32 _res4[2]; /* 0x188 */
3343 + u32 event_input; /* 0x190 */
3344 + u32 _res5[4]; /* 0x194 */
3345 + u32 boot_addr; /* 0x1a4 - also known as PRIVATE_REG */
3346 + u32 _res6[2]; /* 0x1a8 */
3347 + u32 cpu1_power_clamp; /* 0x1b0 */
3348 + u32 cpu1_power_off; /* 0x1b4 */
3349 + u32 _res7[10]; /* 0x1b8 */
3350 + u32 debug0_ctrl; /* 0x1e0 */
3351 + u32 debug1_ctrl; /* 0x1e4 */
3354 +#define GENERAL_CTRL_NO_L1_RESET_CPU(x) (1UL << (x))
3355 +#define GENERAL_CTRL_NO_L2_AUTO_RESET (1UL << 4)
3356 +#define GENERAL_CTRL_L2_RESET_SET (0UL << 5)
3357 +#define GENERAL_CTRL_L2_RESET_CLEAR (1UL << 5)
3358 +#define GENERAL_CTRL_CFGSDISABLE (1UL << 8)
3360 +#endif /* __ASSEMBLY__ */
3362 +#endif /* _SUNXI_CPUCFG_H_ */
3363 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpu.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpu.h
3364 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/cpu.h 1970-01-01 01:00:00.000000000 +0100
3365 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpu.h 2014-03-05 23:14:47.176099871 +0100
3368 + * (C) Copyright 2007-2011
3369 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3370 + * Tom Cubie <tangliang@allwinnertech.com>
3372 + * See file CREDITS for list of people who contributed to this
3375 + * This program is free software; you can redistribute it and/or
3376 + * modify it under the terms of the GNU General Public License as
3377 + * published by the Free Software Foundation; either version 2 of
3378 + * the License, or (at your option) any later version.
3380 + * This program is distributed in the hope that it will be useful,
3381 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3382 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3383 + * GNU General Public License for more details.
3385 + * You should have received a copy of the GNU General Public License
3386 + * along with this program; if not, write to the Free Software
3387 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3388 + * MA 02111-1307 USA
3391 +#ifndef _SUNXI_CPU_H
3392 +#define _SUNXI_CPU_H
3394 +#define SUNXI_SRAM_A1_BASE 0x00000000
3395 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
3397 +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
3398 +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
3399 +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
3400 +#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
3401 +#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
3403 +#define SUNXI_SRAMC_BASE 0x01c00000
3404 +#define SUNXI_DRAMC_BASE 0x01c01000
3405 +#define SUNXI_DMA_BASE 0x01c02000
3406 +#define SUNXI_NFC_BASE 0x01c03000
3407 +#define SUNXI_TS_BASE 0x01c04000
3408 +#define SUNXI_SPI0_BASE 0x01c05000
3409 +#define SUNXI_SPI1_BASE 0x01c06000
3410 +#define SUNXI_MS_BASE 0x01c07000
3411 +#define SUNXI_TVD_BASE 0x01c08000
3412 +#define SUNXI_CSI0_BASE 0x01c09000
3413 +#define SUNXI_TVE0_BASE 0x01c0a000
3414 +#define SUNXI_EMAC_BASE 0x01c0b000
3415 +#define SUNXI_LCD0_BASE 0x01c0C000
3416 +#define SUNXI_LCD1_BASE 0x01c0d000
3417 +#define SUNXI_VE_BASE 0x01c0e000
3418 +#define SUNXI_MMC0_BASE 0x01c0f000
3419 +#define SUNXI_MMC1_BASE 0x01c10000
3420 +#define SUNXI_MMC2_BASE 0x01c11000
3421 +#define SUNXI_MMC3_BASE 0x01c12000
3422 +#define SUNXI_USB0_BASE 0x01c13000
3423 +#define SUNXI_USB1_BASE 0x01c14000
3424 +#define SUNXI_SS_BASE 0x01c15000
3425 +#define SUNXI_HDMI_BASE 0x01c16000
3426 +#define SUNXI_SPI2_BASE 0x01c17000
3427 +#define SUNXI_SATA_BASE 0x01c18000
3428 +#define SUNXI_PATA_BASE 0x01c19000
3429 +#define SUNXI_ACE_BASE 0x01c1a000
3430 +#define SUNXI_TVE1_BASE 0x01c1b000
3431 +#define SUNXI_USB2_BASE 0x01c1c000
3432 +#define SUNXI_CSI1_BASE 0x01c1d000
3433 +#define SUNXI_TZASC_BASE 0x01c1e000
3434 +#define SUNXI_SPI3_BASE 0x01c1f000
3436 +#define SUNXI_CCM_BASE 0x01c20000
3437 +#define SUNXI_INTC_BASE 0x01c20400
3438 +#define SUNXI_PIO_BASE 0x01c20800
3439 +#define SUNXI_TIMER_BASE 0x01c20c00
3440 +#define SUNXI_SPDIF_BASE 0x01c21000
3441 +#define SUNXI_AC97_BASE 0x01c21400
3442 +#define SUNXI_IR0_BASE 0x01c21800
3443 +#define SUNXI_IR1_BASE 0x01c21c00
3445 +#define SUNXI_IIS_BASE 0x01c22400
3446 +#define SUNXI_LRADC_BASE 0x01c22800
3447 +#define SUNXI_AD_DA_BASE 0x01c22c00
3448 +#define SUNXI_KEYPAD_BASE 0x01c23000
3449 +#define SUNXI_TZPC_BASE 0x01c23400
3450 +#define SUNXI_SID_BASE 0x01c23800
3451 +#define SUNXI_SJTAG_BASE 0x01c23c00
3453 +#define SUNXI_TP_BASE 0x01c25000
3454 +#define SUNXI_PMU_BASE 0x01c25400
3455 +#define SUNXI_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */
3457 +#define SUNXI_UART0_BASE 0x01c28000
3458 +#define SUNXI_UART1_BASE 0x01c28400
3459 +#define SUNXI_UART2_BASE 0x01c28800
3460 +#define SUNXI_UART3_BASE 0x01c28c00
3461 +#define SUNXI_UART4_BASE 0x01c29000
3462 +#define SUNXI_UART5_BASE 0x01c29400
3463 +#define SUNXI_UART6_BASE 0x01c29800
3464 +#define SUNXI_UART7_BASE 0x01c29c00
3465 +#define SUNXI_PS2_0_BASE 0x01c2a000
3466 +#define SUNXI_PS2_1_BASE 0x01c2a400
3468 +#define SUNXI_TWI0_BASE 0x01c2ac00
3469 +#define SUNXI_TWI1_BASE 0x01c2b000
3470 +#define SUNXI_TWI2_BASE 0x01c2b400
3472 +#define SUNXI_CAN_BASE 0x01c2bc00
3474 +#define SUNXI_SCR_BASE 0x01c2c400
3476 +#define SUNXI_GPS_BASE 0x01c30000
3477 +#define SUNXI_MALI400_BASE 0x01c40000
3478 +#define SUNXI_GMAC_BASE 0x01c50000
3481 +#define SUNXI_SRAM_C_BASE 0x01d00000
3483 +#define SUNXI_DE_FE0_BASE 0x01e00000
3484 +#define SUNXI_DE_FE1_BASE 0x01e20000
3485 +#define SUNXI_DE_BE0_BASE 0x01e60000
3486 +#define SUNXI_DE_BE1_BASE 0x01e40000
3487 +#define SUNXI_MP_BASE 0x01e80000
3488 +#define SUNXI_AVG_BASE 0x01ea0000
3490 +/* CoreSight Debug Module */
3491 +#define SUNXI_CSDM_BASE 0x3f500000
3493 +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
3495 +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
3497 +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
3499 +#ifndef __ASSEMBLY__
3501 +enum sunxi_boot_type_t {
3502 + SUNXI_BOOT_TYPE_NULL,
3503 + SUNXI_BOOT_TYPE_MMC0,
3504 + SUNXI_BOOT_TYPE_NAND,
3505 + SUNXI_BOOT_TYPE_MMC2,
3506 + SUNXI_BOOT_TYPE_SPI
3509 +void sunxi_board_init(void);
3510 +extern void sunxi_reset(void);
3511 +#endif /* __ASSEMBLY__ */
3513 +#endif /* _CPU_H */
3514 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/dram.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/dram.h
3515 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/dram.h 1970-01-01 01:00:00.000000000 +0100
3516 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/dram.h 2014-03-05 23:14:47.176099871 +0100
3519 + * (C) Copyright 2007-2012
3520 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3521 + * Berg Xing <bergxing@allwinnertech.com>
3522 + * Tom Cubie <tangliang@allwinnertech.com>
3524 + * Sunxi platform dram register definition.
3526 + * See file CREDITS for list of people who contributed to this
3529 + * This program is free software; you can redistribute it and/or
3530 + * modify it under the terms of the GNU General Public License as
3531 + * published by the Free Software Foundation; either version 2 of
3532 + * the License, or (at your option) any later version.
3534 + * This program is distributed in the hope that it will be useful,
3535 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3536 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3537 + * GNU General Public License for more details.
3539 + * You should have received a copy of the GNU General Public License
3540 + * along with this program; if not, write to the Free Software
3541 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3542 + * MA 02111-1307 USA
3545 +#ifndef _SUNXI_DRAM_H
3546 +#define _SUNXI_DRAM_H
3548 +#include <linux/types.h>
3550 +struct sunxi_dram_reg {
3551 + u32 ccr; /* 0x00 controller configuration register */
3552 + u32 dcr; /* 0x04 dram configuration register */
3553 + u32 iocr; /* 0x08 i/o configuration register */
3554 + u32 csr; /* 0x0c controller status register */
3555 + u32 drr; /* 0x10 dram refresh register */
3556 + u32 tpr0; /* 0x14 dram timing parameters register 0 */
3557 + u32 tpr1; /* 0x18 dram timing parameters register 1 */
3558 + u32 tpr2; /* 0x1c dram timing parameters register 2 */
3559 + u32 gdllcr; /* 0x20 global dll control register */
3561 + u32 rslr0; /* 0x4c rank system latency register */
3562 + u32 rslr1; /* 0x50 rank system latency register */
3564 + u32 rdgr0; /* 0x5c rank dqs gating register */
3565 + u32 rdgr1; /* 0x60 rank dqs gating register */
3567 + u32 odtcr; /* 0x98 odt configuration register */
3568 + u32 dtr0; /* 0x9c data training register 0 */
3569 + u32 dtr1; /* 0xa0 data training register 1 */
3570 + u32 dtar; /* 0xa4 data training address register */
3571 + u32 zqcr0; /* 0xa8 zq control register 0 */
3572 + u32 zqcr1; /* 0xac zq control register 1 */
3573 + u32 zqsr; /* 0xb0 zq status register */
3574 + u32 idcr; /* 0xb4 initializaton delay configure reg */
3576 + u32 mr; /* 0x1f0 mode register */
3577 + u32 emr; /* 0x1f4 extended mode register */
3578 + u32 emr2; /* 0x1f8 extended mode register */
3579 + u32 emr3; /* 0x1fc extended mode register */
3580 + u32 dllctr; /* 0x200 dll control register */
3581 + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
3582 + /* 0x208 dll control register 1(byte 1) */
3583 + /* 0x20c dll control register 2(byte 2) */
3584 + /* 0x210 dll control register 3(byte 3) */
3585 + /* 0x214 dll control register 4(byte 4) */
3586 + u32 dqtr0; /* 0x218 dq timing register */
3587 + u32 dqtr1; /* 0x21c dq timing register */
3588 + u32 dqtr2; /* 0x220 dq timing register */
3589 + u32 dqtr3; /* 0x224 dq timing register */
3590 + u32 dqstr; /* 0x228 dqs timing register */
3591 + u32 dqsbtr; /* 0x22c dqsb timing register */
3592 + u32 mcr; /* 0x230 mode configure register */
3594 + u32 ppwrsctl; /* 0x23c pad power save control */
3595 + u32 apr; /* 0x240 arbiter period register */
3596 + u32 pldtr; /* 0x244 priority level data threshold reg */
3598 + u32 hpcr[32]; /* 0x250 host port configure register */
3600 + u32 csel; /* 0x2e0 controller select register */
3625 +#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
3626 +#define DRAM_CCR_DQS_GATE (0x1 << 14)
3627 +#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
3628 +#define DRAM_CCR_ITM_OFF (0x1 << 28)
3629 +#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
3630 +#define DRAM_CCR_INIT (0x1 << 31)
3632 +#define DRAM_MEMORY_TYPE_DDR1 1
3633 +#define DRAM_MEMORY_TYPE_DDR2 2
3634 +#define DRAM_MEMORY_TYPE_DDR3 3
3635 +#define DRAM_MEMORY_TYPE_LPDDR2 4
3636 +#define DRAM_MEMORY_TYPE_LPDDR 5
3637 +#define DRAM_DCR_TYPE (0x1 << 0)
3638 +#define DRAM_DCR_TYPE_DDR2 0x0
3639 +#define DRAM_DCR_TYPE_DDR3 0x1
3640 +#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
3641 +#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
3642 +#define DRAM_DCR_IO_WIDTH_8BIT 0x0
3643 +#define DRAM_DCR_IO_WIDTH_16BIT 0x1
3644 +#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
3645 +#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
3646 +#define DRAM_DCR_CHIP_DENSITY_256M 0x0
3647 +#define DRAM_DCR_CHIP_DENSITY_512M 0x1
3648 +#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
3649 +#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
3650 +#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
3651 +#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
3652 +#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
3653 +#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
3654 +#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
3655 +#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
3656 +#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
3657 +#define DRAM_DCR_NR_DLLCR_32BIT 5
3658 +#define DRAM_DCR_NR_DLLCR_16BIT 3
3659 +#define DRAM_DCR_NR_DLLCR_8BIT 2
3660 +#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
3661 +#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
3662 +#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
3663 +#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
3664 +#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
3665 +#define DRAM_DCR_MODE_SEQ 0x0
3666 +#define DRAM_DCR_MODE_INTERLEAVE 0x1
3668 +#define DRAM_CSR_FAILED (0x1 << 20)
3670 +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
3671 +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
3672 +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
3673 +#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
3674 +#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
3675 +#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
3676 +#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
3677 +#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
3678 +#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
3679 +#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
3680 +#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
3681 +#define DRAM_MCR_RESET (0x1 << 12)
3682 +#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
3683 +#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
3684 +#define DRAM_MCR_DCLK_OUT (0x1 << 16)
3686 +#define DRAM_DLLCR_NRESET (0x1 << 30)
3687 +#define DRAM_DLLCR_DISABLE (0x1 << 31)
3689 +#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
3690 +#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
3692 +#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
3693 +#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
3695 +#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
3696 +#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
3697 +#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
3698 +#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
3699 +#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
3700 +#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
3701 +#define DRAM_MR_POWER_DOWN (0x1 << 12)
3703 +#define DRAM_CSEL_MAGIC 0x16237495
3705 +unsigned long sunxi_dram_init(void);
3706 +unsigned long dramc_init(struct dram_para *para);
3708 +#endif /* _SUNXI_DRAM_H */
3709 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/early_print.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/early_print.h
3710 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/early_print.h 1970-01-01 01:00:00.000000000 +0100
3711 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/early_print.h 2014-03-05 23:14:47.176099871 +0100
3714 + * (C) Copyright 2007-2012
3715 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3716 + * Tom Cubie <tangliang@allwinnertech.com>
3718 + * Early uart print for debugging.
3720 + * See file CREDITS for list of people who contributed to this
3723 + * This program is free software; you can redistribute it and/or
3724 + * modify it under the terms of the GNU General Public License as
3725 + * published by the Free Software Foundation; either version 2 of
3726 + * the License, or (at your option) any later version.
3728 + * This program is distributed in the hope that it will be useful,
3729 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3730 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3731 + * GNU General Public License for more details.
3733 + * You should have received a copy of the GNU General Public License
3734 + * along with this program; if not, write to the Free Software
3735 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3736 + * MA 02111-1307 USA
3739 +#ifndef _SUNXI_EARLY_PRINT_H
3740 +#define _SUNXI_EARLY_PRINT_H
3742 +#include <asm/arch/cpu.h>
3744 +#define SUNXI_UART_BASE SUNXI_UART0_BASE
3746 +#define UART_OFFSET 0x400
3748 +/* receive buffer register */
3749 +#define UART_RBR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x0)
3750 +/* transmit holding register */
3751 +#define UART_THR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x0)
3752 +/* divisor latch low register */
3753 +#define UART_DLL(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x0)
3755 +/* divisor latch high register */
3756 +#define UART_DLH(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x4)
3757 +/* interrupt enable reigster */
3758 +#define UART_IER(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x4)
3760 +/* interrupt identity register */
3761 +#define UART_IIR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x8)
3762 +/* fifo control register */
3763 +#define UART_FCR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x8)
3765 +/* line control register */
3766 +#define UART_LCR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0xc)
3767 +#define UART_LCR_DLAB (0x1 << 7)
3769 +/* line status register */
3770 +#define UART_LSR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x14)
3771 +#define UART_LSR_TEMT (0x1 << 6)
3774 +#define BAUD_115200 (0xd) /* 24 * 1000 * 1000 / 16 / 115200 = 13 */
3775 +#define NO_PARITY (0)
3776 +#define ONE_STOP_BIT (0)
3777 +#define DAT_LEN_8_BITS (3)
3778 +#define LC_8_N_1 (NO_PARITY << 3 | ONE_STOP_BIT << 2 | DAT_LEN_8_BITS)
3780 +#ifndef __ASSEMBLY__
3781 +void uart_init(void);
3782 +void uart_putc(char c);
3783 +void uart_puts(const char *s);
3784 +#endif /* __ASSEMBLY__ */
3786 +#endif /* _SUNXI_EARLY_PRINT_H */
3787 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/gpio.h
3788 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/gpio.h 1970-01-01 01:00:00.000000000 +0100
3789 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/gpio.h 2014-03-05 23:14:47.176099871 +0100
3792 + * (C) Copyright 2007-2012
3793 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3794 + * Tom Cubie <tangliang@allwinnertech.com>
3796 + * See file CREDITS for list of people who contributed to this
3799 + * This program is free software; you can redistribute it and/or
3800 + * modify it under the terms of the GNU General Public License as
3801 + * published by the Free Software Foundation; either version 2 of
3802 + * the License, or (at your option) any later version.
3804 + * This program is distributed in the hope that it will be useful,
3805 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3806 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3807 + * GNU General Public License for more details.
3809 + * You should have received a copy of the GNU General Public License
3810 + * along with this program; if not, write to the Free Software
3811 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3812 + * MA 02111-1307 USA
3815 +#ifndef _SUNXI_GPIO_H
3816 +#define _SUNXI_GPIO_H
3818 +#include <linux/types.h>
3821 + * sunxi has 9 banks of gpio, they are:
3822 + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
3823 + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
3824 + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
3827 +#define SUNXI_GPIO_A 0
3828 +#define SUNXI_GPIO_B 1
3829 +#define SUNXI_GPIO_C 2
3830 +#define SUNXI_GPIO_D 3
3831 +#define SUNXI_GPIO_E 4
3832 +#define SUNXI_GPIO_F 5
3833 +#define SUNXI_GPIO_G 6
3834 +#define SUNXI_GPIO_H 7
3835 +#define SUNXI_GPIO_I 8
3837 +struct sunxi_gpio {
3844 +/* gpio interrupt control */
3845 +struct sunxi_gpio_int {
3849 + u32 deb; /* interrupt debounce */
3852 +struct sunxi_gpio_reg {
3853 + struct sunxi_gpio gpio_bank[9];
3855 + struct sunxi_gpio_int gpio_int;
3858 +#define GPIO_BANK(pin) ((pin) >> 5)
3859 +#define GPIO_NUM(pin) ((pin) & 0x1f)
3861 +#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
3862 +#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
3864 +#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4)
3865 +#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
3867 +#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
3868 +#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
3870 +/* GPIO bank sizes */
3871 +#define SUNXI_GPIO_A_NR 32
3872 +#define SUNXI_GPIO_B_NR 32
3873 +#define SUNXI_GPIO_C_NR 32
3874 +#define SUNXI_GPIO_D_NR 32
3875 +#define SUNXI_GPIO_E_NR 32
3876 +#define SUNXI_GPIO_F_NR 32
3877 +#define SUNXI_GPIO_G_NR 32
3878 +#define SUNXI_GPIO_H_NR 32
3879 +#define SUNXI_GPIO_I_NR 32
3881 +#define SUNXI_GPIO_NEXT(__gpio) \
3882 + ((__gpio##_START) + (__gpio##_NR) + 0)
3884 +enum sunxi_gpio_number {
3885 + SUNXI_GPIO_A_START = 0,
3886 + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
3887 + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
3888 + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
3889 + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
3890 + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
3891 + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
3892 + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
3893 + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
3896 +/* SUNXI GPIO number definitions */
3897 +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
3898 +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
3899 +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
3900 +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
3901 +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
3902 +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
3903 +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
3904 +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
3905 +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
3907 +/* GPIO pin function config */
3908 +#define SUNXI_GPIO_INPUT 0
3909 +#define SUNXI_GPIO_OUTPUT 1
3911 +#define SUNXI_GPA0_ERXD3 2
3912 +#define SUNXI_GPA0_SPI1_CS0 3
3913 +#define SUNXI_GPA0_UART2_RTS 4
3915 +#define SUNXI_GPA1_ERXD2 2
3916 +#define SUNXI_GPA1_SPI1_CLK 3
3917 +#define SUNXI_GPA1_UART2_CTS 4
3919 +#define SUNXI_GPA2_ERXD1 2
3920 +#define SUNXI_GPA2_SPI1_MOSI 3
3921 +#define SUNXI_GPA2_UART2_TX 4
3923 +#define SUNXI_GPA10_UART1_TX 4
3924 +#define SUNXI_GPA11_UART1_RX 4
3926 +#define SUN4I_GPB22_UART0_TX 2
3927 +#define SUN4I_GPB23_UART0_RX 2
3929 +#define SUN5I_GPB19_UART0_TX 2
3930 +#define SUN5I_GPB20_UART0_RX 2
3932 +#define SUN5I_GPG3_UART0_TX 4
3933 +#define SUN5I_GPG4_UART0_RX 4
3935 +#define SUNXI_GPC2_NCLE 2
3936 +#define SUNXI_GPC2_SPI0_CLK 3
3938 +#define SUNXI_GPC6_NRB0 2
3939 +#define SUNXI_GPC6_SDC2_CMD 3
3941 +#define SUNXI_GPC7_NRB1 2
3942 +#define SUNXI_GPC7_SDC2_CLK 3
3944 +#define SUNXI_GPC8_NDQ0 2
3945 +#define SUNXI_GPC8_SDC2_D0 3
3947 +#define SUNXI_GPC9_NDQ1 2
3948 +#define SUNXI_GPC9_SDC2_D1 3
3950 +#define SUNXI_GPC10_NDQ2 2
3951 +#define SUNXI_GPC10_SDC2_D2 3
3953 +#define SUNXI_GPC11_NDQ3 2
3954 +#define SUNXI_GPC11_SDC2_D3 3
3956 +#define SUNXI_GPF2_SDC0_CLK 2
3957 +#define SUNXI_GPF2_UART0_TX 4
3959 +#define SUNXI_GPF4_SDC0_D3 2
3960 +#define SUNXI_GPF4_UART0_RX 4
3962 +int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
3963 +int sunxi_gpio_get_cfgpin(u32 pin);
3964 +int sunxi_gpio_set_drv(u32 pin, u32 val);
3965 +int sunxi_gpio_set_pull(u32 pin, u32 val);
3966 +int name_to_gpio(const char *name);
3967 +#define name_to_gpio name_to_gpio
3969 +#endif /* _SUNXI_GPIO_H */
3970 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/i2c.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/i2c.h
3971 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/i2c.h 1970-01-01 01:00:00.000000000 +0100
3972 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/i2c.h 2014-03-05 23:14:47.176099871 +0100
3975 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
3977 + * Based on sun4i linux kernle i2c.h
3978 + * (C) Copyright 2007-2012
3979 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3980 + * Tom Cubie <tanglaing@allwinnertech.com>
3981 + * Victor Wei <weiziheng@allwinnertech.com>
3983 + * See file CREDITS for list of people who contributed to this
3986 + * This program is free software; you can redistribute it and/or
3987 + * modify it under the terms of the GNU General Public License as
3988 + * published by the Free Software Foundation; either version 2 of
3989 + * the License, or (at your option) any later version.
3991 + * This program is distributed in the hope that it will be useful,
3992 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3993 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3994 + * GNU General Public License for more details.
3996 + * You should have received a copy of the GNU General Public License
3997 + * along with this program; if not, write to the Free Software
3998 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3999 + * MA 02111-1307 USA
4001 +#ifndef _SUNXI_I2C_H_
4002 +#define _SUNXI_I2C_H_
4005 + u32 saddr; /* 31:8bit res,7-1bit for slave addr,0 bit for GCE */
4006 + u32 xsaddr; /* 31:8bit res,7-0bit for second addr in 10bit addr */
4007 + u32 data; /* 31:8bit res, 7-0bit send or receive data byte */
4008 + u32 ctl; /* INT_EN,BUS_EN,M_STA,INT_FLAG,A_ACK */
4009 + u32 status; /* 28 interrupt types + 0xf8 normal type = 29 */
4010 + u32 clkr; /* 31:7bit res,6-3bit,CLK_M,2-0bit CLK_N */
4011 + u32 reset; /* 31:1bit res;0bit,write 1 to clear 0. */
4012 + u32 efr; /* 31:2bit res,1:0 bit data byte follow read comand */
4013 + u32 lctl; /* 31:6bits res 5:0bit for sda&scl control */
4016 +/* TWI address register */
4017 +#define TWI_GCE_EN (0x1 << 0) /* gen call addr enable slave mode */
4018 +#define TWI_ADDR_MASK (0x7f << 1) /* 7:1bits */
4019 +#define TWI_XADDR_MASK 0xff /* 7:0bits for extend slave address */
4021 +#define TWI_DATA_MASK 0xff /* 7:0bits for send or received */
4023 +/* TWI Control Register Bit Fields */
4024 +/* 1:0 bits reserved */
4025 +/* set 1 to send A_ACK,then low level on SDA */
4026 +#define TWI_CTL_ACK (0x1 << 2)
4027 +/* INT_FLAG,interrupt status flag: set '1' when interrupt coming */
4028 +#define TWI_CTL_INTFLG (0x1 << 3)
4029 +#define TWI_CTL_STP (0x1 << 4) /* M_STP,Automatic clear 0 */
4030 +#define TWI_CTL_STA (0x1 << 5) /* M_STA,atutomatic clear 0 */
4031 +#define TWI_CTL_BUSEN (0x1 << 6) /* BUS_EN, mastr mode should be set 1 */
4032 +#define TWI_CTL_INTEN (0x1 << 7) /* INT_EN */
4033 +/* 31:8 bit reserved */
4036 + * TWI Clock Register Bit Fields & Masks,default value:0x0000_0000
4037 + * Fin is APB CLOCK INPUT;
4038 + * Fsample = F0 = Fin/2^CLK_N;
4039 + * F1 = F0/(CLK_M+1);
4041 + * Foscl = F1/10 = Fin/(2^CLK_N * (CLK_M+1)*10);
4042 + * Foscl is clock SCL;standard mode:100KHz or fast mode:400KHz
4045 +#define TWI_CLK_DIV_M (0xf << 3) /* 6:3bit */
4046 +#define TWI_CLK_DIV_N (0x7 << 0) /* 2:0bit */
4047 +#define TWI_CLK_DIV(N, M) ((((N) & 0xf) << 3) | (((M) & 0x7) << 0))
4049 +/* TWI Soft Reset Register Bit Fields & Masks */
4050 +/* write 1 to clear 0, when complete soft reset clear 0 */
4051 +#define TWI_SRST_SRST (0x1 << 0)
4053 +/* TWI Enhance Feature Register Bit Fields & Masks */
4054 +/* default -- 0x0 */
4055 +/* 00:no,01: 1byte, 10:2 bytes, 11: 3bytes */
4056 +#define TWI_EFR_MASK (0x3 << 0)
4057 +#define TWI_EFR_WARC_0 (0x0 << 0)
4058 +#define TWI_EFR_WARC_1 (0x1 << 0)
4059 +#define TWI_EFR_WARC_2 (0x2 << 0)
4060 +#define TWI_EFR_WARC_3 (0x3 << 0)
4062 +/* twi line control register -default value: 0x0000_003a */
4063 +/* SDA line state control enable ,1:enable;0:disable */
4064 +#define TWI_LCR_SDA_EN (0x01 << 0)
4065 +/* SDA line state control bit, 1:high level;0:low level */
4066 +#define TWI_LCR_SDA_CTL (0x01 << 1)
4067 +/* SCL line state control enable ,1:enable;0:disable */
4068 +#define TWI_LCR_SCL_EN (0x01 << 2)
4069 +/* SCL line state control bit, 1:high level;0:low level */
4070 +#define TWI_LCR_SCL_CTL (0x01 << 3)
4071 +/* current state of SDA,readonly bit */
4072 +#define TWI_LCR_SDA_STATE_MASK (0x01 << 4)
4073 +/* current state of SCL,readonly bit */
4074 +#define TWI_LCR_SCL_STATE_MASK (0x01 << 5)
4075 +/* 31:6bits reserved */
4076 +#define TWI_LCR_IDLE_STATUS 0x3a
4078 +/* TWI Status Register Bit Fields & Masks */
4079 +#define TWI_STAT_MASK 0xff
4080 +/* 7:0 bits use only,default is 0xf8 */
4081 +#define TWI_STAT_BUS_ERR 0x00 /* BUS ERROR */
4083 +/* Master mode use only */
4084 +#define TWI_STAT_TX_STA 0x08 /* START condition transmitted */
4085 +/* Repeated START condition transmitted */
4086 +#define TWI_STAT_TX_RESTA 0x10
4087 +/* Address+Write bit transmitted, ACK received */
4088 +#define TWI_STAT_TX_AW_ACK 0x18
4089 +/* Address+Write bit transmitted, ACK not received */
4090 +#define TWI_STAT_TX_AW_NAK 0x20
4091 +/* data byte transmitted in master mode,ack received */
4092 +#define TWI_STAT_TXD_ACK 0x28
4093 +/* data byte transmitted in master mode ,ack not received */
4094 +#define TWI_STAT_TXD_NAK 0x30
4095 +/* arbitration lost in address or data byte */
4096 +#define TWI_STAT_ARBLOST 0x38
4097 +/* Address+Read bit transmitted, ACK received */
4098 +#define TWI_STAT_TX_AR_ACK 0x40
4099 +/* Address+Read bit transmitted, ACK not received */
4100 +#define TWI_STAT_TX_AR_NAK 0x48
4101 +/* Second Address byte + Write bit transmitted, ACK received */
4102 +#define TWI_STAT_TX_2AW_ACK 0xd0
4103 +/* Second Address byte + Write bit transmitted, ACK received */
4104 +#define TWI_STAT_TX_2AW_NAK 0xd8
4105 +/* data byte received in master mode ,ack transmitted */
4106 +#define TWI_STAT_RXD_ACK 0x50
4107 +/* date byte received in master mode,not ack transmitted */
4108 +#define TWI_STAT_RXD_NAK 0x58
4110 +/* Slave mode use only */
4111 +/* Slave address+Write bit received, ACK transmitted */
4112 +#define TWI_STAT_RXWS_ACK 0x60
4114 + * Arbitration lost in address as master, slave address + Write bit received,
4117 +#define TWI_STAT_ARBLOST_RXWS_ACK 0x68
4118 +/* General Call address received, ACK transmitted */
4119 +#define TWI_STAT_RXGCAS_ACK 0x70
4121 + * Arbitration lost in address as master, General Call address received,
4124 +#define TWI_STAT_ARBLOST_RXGCAS_ACK 0x78
4125 +/* Data byte received after slave address received, ACK transmitted */
4126 +#define TWI_STAT_RXDS_ACK 0x80
4127 +/* Data byte received after slave address received, not ACK transmitted */
4128 +#define TWI_STAT_RXDS_NAK 0x88
4129 +/* Data byte received after General Call received, ACK transmitted */
4130 +#define TWI_STAT_RXDGCAS_ACK 0x90
4131 +/* Data byte received after General Call received, not ACK transmitted */
4132 +#define TWI_STAT_RXDGCAS_NAK 0x98
4133 +/* STOP or repeated START condition received in slave */
4134 +#define TWI_STAT_RXSTPS_RXRESTAS 0xa0
4135 +/* Slave address + Read bit received, ACK transmitted */
4136 +#define TWI_STAT_RXRS_ACK 0xa8
4138 + * Arbitration lost in address as master, slave address + Read bit received,
4141 +#define TWI_STAT_ARBLOST_SLAR_ACK 0xb0
4142 +/* Data byte transmitted in slave mode, ACK received */
4143 +#define TWI_STAT_TXDS_ACK 0xb8
4144 +/* Data byte transmitted in slave mode, ACK not received */
4145 +#define TWI_STAT_TXDS_NAK 0xc0
4146 +/* Last byte transmitted in slave mode, ACK received */
4147 +#define TWI_STAT_TXDSL_ACK 0xc8
4149 +/* 10bit Address, second part of address */
4150 +/* Second Address byte+Write bit transmitted,ACK received */
4151 +#define TWI_STAT_TX_SAW_ACK 0xd0
4152 +/* Second Address byte+Write bit transmitted,ACK not received */
4153 +#define TWI_STAT_TX_SAW_NAK 0xd8
4155 +/* No relevant status infomation,INT_FLAG = 0 */
4156 +#define TWI_STAT_IDLE 0xf8
4159 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/key.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/key.h
4160 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/key.h 1970-01-01 01:00:00.000000000 +0100
4161 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/key.h 2014-03-05 23:14:47.176099871 +0100
4164 + * (C) Copyright 2007-2011
4165 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4166 + * Tom Cubie <tangliang@allwinnertech.com>
4168 + * See file CREDITS for list of people who contributed to this
4171 + * This program is free software; you can redistribute it and/or
4172 + * modify it under the terms of the GNU General Public License as
4173 + * published by the Free Software Foundation; either version 2 of
4174 + * the License, or (at your option) any later version.
4176 + * This program is distributed in the hope that it will be useful,
4177 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4178 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4179 + * GNU General Public License for more details.
4181 + * You should have received a copy of the GNU General Public License
4182 + * along with this program; if not, write to the Free Software
4183 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4184 + * MA 02111-1307 USA
4187 +#ifndef _SUNXI_KEY_H
4188 +#define _SUNXI_KEY_H
4190 +#include <linux/types.h>
4192 +struct sunxi_lradc {
4193 + u32 ctrl; /* lradc control */
4194 + u32 intc; /* interrupt control */
4195 + u32 ints; /* interrupt status */
4196 + u32 data0; /* lradc 0 data */
4197 + u32 data1; /* lradc 1 data */
4200 +#define LRADC_EN 0x1 /* LRADC enable */
4201 +#define LRADC_SAMPLE_RATE 0x2 /* 32.25 Hz */
4202 +#define LEVELB_VOL 0x2 /* 0x33(~1.6v) */
4203 +#define LRADC_HOLD_EN 0x1 /* sample hold enable */
4204 +#define KEY_MODE_SELECT 0x0 /* normal mode */
4206 +#define ADC0_DATA_PENDING (0x1 << 0) /* adc0 has data */
4207 +#define ADC0_KEYDOWN_PENDING (0x1 << 1) /* key down */
4208 +#define ADC0_HOLDKEY_PENDING (0x1 << 2) /* key hold */
4209 +#define ADC0_ALRDY_HOLD_PENDING (0x1 << 3) /* key already hold */
4210 +#define ADC0_KEYUP_PENDING (0x1 << 4) /* key up */
4212 +int sunxi_key_init(void);
4213 +u32 sunxi_read_key(void);
4216 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/mmc.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/mmc.h
4217 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/mmc.h 1970-01-01 01:00:00.000000000 +0100
4218 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/mmc.h 2014-03-05 23:14:47.176099871 +0100
4221 + * (C) Copyright 2007-2011
4222 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4223 + * Aaron <leafy.myeh@allwinnertech.com>
4225 + * MMC register definition for allwinner sunxi platform.
4227 + * See file CREDITS for list of people who contributed to this
4230 + * This program is free software; you can redistribute it and/or
4231 + * modify it under the terms of the GNU General Public License as
4232 + * published by the Free Software Foundation; either version 2 of
4233 + * the License, or (at your option) any later version.
4235 + * This program is distributed in the hope that it will be useful,
4236 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4237 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4238 + * GNU General Public License for more details.
4240 + * You should have received a copy of the GNU General Public License
4241 + * along with this program; if not, write to the Free Software
4242 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4243 + * MA 02111-1307 USA
4246 +#ifndef _SUNXI_MMC_H
4247 +#define _SUNXI_MMC_H
4249 +#include <linux/types.h>
4252 + u32 gctrl; /* (0x00) SMC Global Control Register */
4253 + u32 clkcr; /* (0x04) SMC Clock Control Register */
4254 + u32 timeout; /* (0x08) SMC Time Out Register */
4255 + u32 width; /* (0x0c) SMC Bus Width Register */
4256 + u32 blksz; /* (0x10) SMC Block Size Register */
4257 + u32 bytecnt; /* (0x14) SMC Byte Count Register */
4258 + u32 cmd; /* (0x18) SMC Command Register */
4259 + u32 arg; /* (0x1c) SMC Argument Register */
4260 + u32 resp0; /* (0x20) SMC Response Register 0 */
4261 + u32 resp1; /* (0x24) SMC Response Register 1 */
4262 + u32 resp2; /* (0x28) SMC Response Register 2 */
4263 + u32 resp3; /* (0x2c) SMC Response Register 3 */
4264 + u32 imask; /* (0x30) SMC Interrupt Mask Register */
4265 + u32 mint; /* (0x34) SMC Masked Interrupt Status Reg */
4266 + u32 rint; /* (0x38) SMC Raw Interrupt Status Register */
4267 + u32 status; /* (0x3c) SMC Status Register */
4268 + u32 ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Reg */
4269 + u32 funcsel; /* (0x44) SMC Function Select Register */
4270 + u32 cbcr; /* (0x48) SMC CIU Byte Count Register */
4271 + u32 bbcr; /* (0x4c) SMC BIU Byte Count Register */
4272 + u32 dbgc; /* (0x50) SMC Debug Enable Register */
4273 + u32 res0[11]; /* (0x54~0x7c) */
4274 + u32 dmac; /* (0x80) SMC IDMAC Control Register */
4275 + u32 dlba; /* (0x84) SMC IDMAC Descr List Base Addr Reg */
4276 + u32 idst; /* (0x88) SMC IDMAC Status Register */
4277 + u32 idie; /* (0x8c) SMC IDMAC Interrupt Enable Register */
4278 + u32 chda; /* (0x90) */
4279 + u32 cbda; /* (0x94) */
4280 + u32 res1[26]; /* (0x98~0xff) */
4281 + u32 fifo; /* (0x100) SMC FIFO Access Address */
4284 +int sunxi_mmc_init(int sdc_no);
4285 +#endif /* _SUNXI_MMC_H */
4286 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/smp.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/smp.h
4287 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/smp.h 1970-01-01 01:00:00.000000000 +0100
4288 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/smp.h 2014-03-05 23:14:47.176099871 +0100
4291 + * (C) Copyright 2013
4292 + * Carl van Schaik <carl@ok-labs.com>
4294 + * CPU configuration registers for the sun7i (A20).
4296 + * See file CREDITS for list of people who contributed to this
4299 + * This program is free software; you can redistribute it and/or
4300 + * modify it under the terms of the GNU General Public License as
4301 + * published by the Free Software Foundation; either version 2 of
4302 + * the License, or (at your option) any later version.
4304 + * This program is distributed in the hope that it will be useful,
4305 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4306 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4307 + * GNU General Public License for more details.
4309 + * You should have received a copy of the GNU General Public License
4310 + * along with this program; if not, write to the Free Software
4311 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4312 + * MA 02111-1307 USA
4315 +#ifndef _SUNXI_SMP_H_
4316 +#define _SUNXI_SMP_H_
4318 +#ifndef __ASSEMBLY__
4320 +void startup_secondaries(void);
4322 +/* Assembly entry point */
4323 +extern void secondary_init(void);
4325 +#endif /* __ASSEMBLY__ */
4327 +#endif /* _SUNXI_SMP_H_ */
4328 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/spl.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/spl.h
4329 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/spl.h 1970-01-01 01:00:00.000000000 +0100
4330 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/spl.h 2014-03-05 23:14:47.176099871 +0100
4333 + * This is a copy of omap3/spl.h:
4335 + * (C) Copyright 2012
4336 + * Texas Instruments, <www.ti.com>
4338 + * See file CREDITS for list of people who contributed to this
4341 + * This program is free software; you can redistribute it and/or
4342 + * modify it under the terms of the GNU General Public License as
4343 + * published by the Free Software Foundation; either version 2 of
4344 + * the License, or (at your option) any later version.
4346 + * This program is distributed in the hope that it will be useful,
4347 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4348 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4349 + * GNU General Public License for more details.
4351 + * You should have received a copy of the GNU General Public License
4352 + * along with this program; if not, write to the Free Software
4353 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4354 + * MA 02111-1307 USA
4356 +#ifndef _ASM_ARCH_SPL_H_
4357 +#define _ASM_SPL_H_
4359 +#define BOOT_DEVICE_NONE 0
4360 +#define BOOT_DEVICE_XIP 1
4361 +#define BOOT_DEVICE_NAND 2
4362 +#define BOOT_DEVICE_ONE_NAND 3
4363 +#define BOOT_DEVICE_MMC2 5 /*emmc*/
4364 +#define BOOT_DEVICE_MMC1 6
4365 +#define BOOT_DEVICE_XIPWAIT 7
4366 +#define BOOT_DEVICE_MMC2_2 0xff
4368 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/sys_proto.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/sys_proto.h
4369 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/sys_proto.h 1970-01-01 01:00:00.000000000 +0100
4370 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/sys_proto.h 2014-03-05 23:14:47.176099871 +0100
4373 + * (C) Copyright 2007-2012
4374 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4375 + * Tom Cubie <tangliang@allwinnertech.com>
4377 + * See file CREDITS for list of people who contributed to this
4380 + * This program is free software; you can redistribute it and/or
4381 + * modify it under the terms of the GNU General Public License as
4382 + * published by the Free Software Foundation; either version 2 of
4383 + * the License, or (at your option) any later version.
4385 + * This program is distributed in the hope that it will be useful,
4386 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4387 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4388 + * GNU General Public License for more details.
4390 + * You should have received a copy of the GNU General Public License
4391 + * along with this program; if not, write to the Free Software
4392 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4393 + * MA 02111-1307 USA
4396 +#ifndef _SYS_PROTO_H_
4397 +#define _SYS_PROTO_H_
4399 +#include <linux/types.h>
4401 +void sr32(u32 *, u32, u32, u32);
4402 +void sdelay(unsigned long);
4405 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/timer.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/timer.h
4406 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/timer.h 1970-01-01 01:00:00.000000000 +0100
4407 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/timer.h 2014-03-05 23:14:47.176099871 +0100
4410 + * (C) Copyright 2007-2011
4411 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4412 + * Tom Cubie <tangliang@allwinnertech.com>
4414 + * Configuration settings for the Allwinner A10-evb board.
4416 + * See file CREDITS for list of people who contributed to this
4419 + * This program is free software; you can redistribute it and/or
4420 + * modify it under the terms of the GNU General Public License as
4421 + * published by the Free Software Foundation; either version 2 of
4422 + * the License, or (at your option) any later version.
4424 + * This program is distributed in the hope that it will be useful,
4425 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4426 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4427 + * GNU General Public License for more details.
4429 + * You should have received a copy of the GNU General Public License
4430 + * along with this program; if not, write to the Free Software
4431 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4432 + * MA 02111-1307 USA
4435 +#ifndef _SUNXI_TIMER_H_
4436 +#define _SUNXI_TIMER_H_
4438 +#ifndef __ASSEMBLY__
4440 +#include <linux/types.h>
4442 +/* General purpose timer */
4443 +struct sunxi_timer {
4450 +/* Audio video sync*/
4452 + u32 ctl; /* 0x80 */
4453 + u32 cnt0; /* 0x84 */
4454 + u32 cnt1; /* 0x88 */
4455 + u32 div; /* 0x8c */
4458 +/* 64 bit counter */
4459 +struct sunxi_64cnt {
4460 + u32 ctl; /* 0xa0 */
4461 + u32 lo; /* 0xa4 */
4462 + u32 hi; /* 0xa8 */
4466 +struct sunxi_wdog {
4467 + u32 ctl; /* 0x90 */
4468 + u32 mode; /* 0x94 */
4473 + u32 ctl; /* 0x100 */
4474 + u32 yymmdd; /* 0x104 */
4475 + u32 hhmmss; /* 0x108 */
4479 +struct sunxi_alarm {
4480 + u32 ddhhmmss; /* 0x10c */
4481 + u32 hhmmss; /* 0x110 */
4482 + u32 en; /* 0x114 */
4483 + u32 irqen; /* 0x118 */
4484 + u32 irqsta; /* 0x11c */
4487 +/* Timer general purpose register */
4492 +struct sunxi_timer_reg {
4493 + u32 tirqen; /* 0x00 */
4494 + u32 tirqsta; /* 0x04 */
4496 + struct sunxi_timer timer[6]; /* We have 6 timers */
4498 + struct sunxi_avs avs;
4499 + struct sunxi_wdog wdog;
4501 + struct sunxi_64cnt cnt64;
4503 + struct sunxi_rtc rtc;
4504 + struct sunxi_alarm alarm;
4505 + struct sunxi_tgp tgp[4];
4510 +#endif /* __ASSEMBLY__ */
4513 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/watchdog.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/watchdog.h
4514 --- u-boot-2014.01-rc1/arch/arm/include/asm/arch-sunxi/watchdog.h 1970-01-01 01:00:00.000000000 +0100
4515 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/watchdog.h 2014-03-05 23:14:47.176099871 +0100
4518 + * Watchdog driver for the Allwinner sunxi platform.
4519 + * Copyright (C) 2013 Oliver Schinagl <oliver@schinagl.nl>
4520 + * http://www.linux-sunxi.org/
4522 + * This program is free software; you can redistribute it and/or
4523 + * modify it under the terms of the GNU General Public License
4524 + * as published by the Free Software Foundation; either version 2
4525 + * of the License, or (at your option) any later version.
4527 + * This program is distributed in the hope that it will be useful,
4528 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4529 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4530 + * GNU General Public License for more details.
4532 + * You should have received a copy of the GNU General Public License
4533 + * along with this program; if not, write to the Free Software
4534 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
4535 + * MA 02110-1301, USA.
4538 +#ifndef _SUNXI_WATCHDOG_H_
4539 +#define _SUNXI_WATCHDOG_H_
4541 +/* Timeout limits */
4542 +#define WDT_MAX_TIMEOUT 16
4545 +#ifndef __ASSEMBLY__
4546 +void watchdog_reset(void);
4547 +void watchdog_set(int timeout);
4548 +void watchdog_init(void);
4549 +#endif /* __ASSEMBLY__ */
4552 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/armv7.h u-boot-sunxi/arch/arm/include/asm/armv7.h
4553 --- u-boot-2014.01-rc1/arch/arm/include/asm/armv7.h 2013-11-25 22:49:32.000000000 +0100
4554 +++ u-boot-sunxi/arch/arm/include/asm/armv7.h 2014-03-05 23:14:47.184099763 +0100
4557 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
4559 -int armv7_switch_nonsec(void);
4560 -int armv7_switch_hyp(void);
4561 +int armv7_init_nonsec(void);
4562 +int armv7_update_dt(void *fdt);
4564 /* defined in assembly file */
4565 unsigned int _nonsec_init(void);
4566 +void _do_nonsec_entry(void *target_pc, unsigned long r0,
4567 + unsigned long r1, unsigned long r2);
4568 void _smp_pen(void);
4569 -void _switch_to_hyp(void);
4571 +extern char __secure_start[];
4572 +extern char __secure_end[];
4574 #endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
4576 #endif /* ! __ASSEMBLY__ */
4577 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/proc-armv/ptrace.h u-boot-sunxi/arch/arm/include/asm/proc-armv/ptrace.h
4578 --- u-boot-2014.01-rc1/arch/arm/include/asm/proc-armv/ptrace.h 2013-11-25 22:49:32.000000000 +0100
4579 +++ u-boot-sunxi/arch/arm/include/asm/proc-armv/ptrace.h 2014-03-05 23:14:47.196099604 +0100
4581 #define IRQ_MODE 0x12
4582 #define SVC_MODE 0x13
4583 #define ABT_MODE 0x17
4584 +#define HYP_MODE 0x1a
4585 #define UND_MODE 0x1b
4586 #define SYSTEM_MODE 0x1f
4587 #define MODE_MASK 0x1f
4591 +#define A_BIT 0x100
4592 #define CC_V_BIT (1 << 28)
4593 #define CC_C_BIT (1 << 29)
4594 #define CC_Z_BIT (1 << 30)
4595 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/psci.h u-boot-sunxi/arch/arm/include/asm/psci.h
4596 --- u-boot-2014.01-rc1/arch/arm/include/asm/psci.h 1970-01-01 01:00:00.000000000 +0100
4597 +++ u-boot-sunxi/arch/arm/include/asm/psci.h 2014-03-05 23:14:47.196099604 +0100
4600 + * Copyright (C) 2013 - ARM Ltd
4601 + * Author: Marc Zyngier <marc.zyngier@arm.com>
4603 + * This program is free software; you can redistribute it and/or modify
4604 + * it under the terms of the GNU General Public License version 2 as
4605 + * published by the Free Software Foundation.
4607 + * This program is distributed in the hope that it will be useful,
4608 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4609 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4610 + * GNU General Public License for more details.
4612 + * You should have received a copy of the GNU General Public License
4613 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
4616 +#ifndef __ARM_PSCI_H__
4617 +#define __ARM_PSCI_H__
4619 +/* PSCI interface */
4620 +#define ARM_PSCI_FN_BASE 0x95c1ba5e
4621 +#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
4623 +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0)
4624 +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1)
4625 +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2)
4626 +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3)
4628 +#define ARM_PSCI_RET_SUCCESS 0
4629 +#define ARM_PSCI_RET_NI (-1)
4630 +#define ARM_PSCI_RET_INVAL (-2)
4631 +#define ARM_PSCI_RET_DENIED (-3)
4633 +#endif /* __ARM_PSCI_H__ */
4634 diff -ruN u-boot-2014.01-rc1/arch/arm/include/asm/secure.h u-boot-sunxi/arch/arm/include/asm/secure.h
4635 --- u-boot-2014.01-rc1/arch/arm/include/asm/secure.h 1970-01-01 01:00:00.000000000 +0100
4636 +++ u-boot-sunxi/arch/arm/include/asm/secure.h 2014-03-05 23:14:47.196099604 +0100
4638 +#ifndef __ASM_SECURE_H
4639 +#define __ASM_SECURE_H
4641 +#include <config.h>
4643 +#ifdef CONFIG_ARMV7_SECURE_BASE
4645 + * Warning, horror ahead.
4647 + * The target code lives in our "secure ram", but u-boot doesn't know
4648 + * that, and has blindly added reloc_off to every relocation
4649 + * entry. Gahh. Do the opposite conversion. This hack also prevents
4650 + * GCC from generating code veeners, which u-boot doesn't relocate at
4653 +#define secure_ram_addr(_fn) ({ \
4654 + DECLARE_GLOBAL_DATA_PTR; \
4655 + void *__fn = _fn; \
4656 + typeof(_fn) *__tmp = (__fn - gd->reloc_off); \
4660 +#define secure_ram_addr(_fn) (_fn)
4664 diff -ruN u-boot-2014.01-rc1/arch/arm/lib/bootm.c u-boot-sunxi/arch/arm/lib/bootm.c
4665 --- u-boot-2014.01-rc1/arch/arm/lib/bootm.c 2013-11-25 22:49:32.000000000 +0100
4666 +++ u-boot-sunxi/arch/arm/lib/bootm.c 2014-03-05 23:14:47.196099604 +0100
4669 #include <fdt_support.h>
4670 #include <asm/bootm.h>
4671 +#include <asm/secure.h>
4672 #include <linux/compiler.h>
4674 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
4675 @@ -185,19 +186,6 @@
4677 __weak void setup_board_tags(struct tag **in_params) {}
4679 -static void do_nonsec_virt_switch(void)
4681 -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
4682 - if (armv7_switch_nonsec() == 0)
4683 -#ifdef CONFIG_ARMV7_VIRT
4684 - if (armv7_switch_hyp() == 0)
4685 - debug("entered HYP mode\n");
4687 - debug("entered non-secure state\n");
4692 /* Subcommand: PREP */
4693 static void boot_prep_linux(bootm_headers_t *images)
4696 printf("FDT and ATAGS support not compiled in - hanging\n");
4699 - do_nonsec_virt_switch();
4702 /* Subcommand: GO */
4703 @@ -264,8 +251,15 @@
4705 r2 = gd->bd->bi_boot_params;
4709 +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
4710 + armv7_init_nonsec();
4711 + secure_ram_addr(_do_nonsec_entry)(kernel_entry,
4714 kernel_entry(0, machid, r2);
4719 /* Main Entry point for arm bootm implementation
4720 diff -ruN u-boot-2014.01-rc1/arch/arm/lib/bootm-fdt.c u-boot-sunxi/arch/arm/lib/bootm-fdt.c
4721 --- u-boot-2014.01-rc1/arch/arm/lib/bootm-fdt.c 2013-11-25 22:49:32.000000000 +0100
4722 +++ u-boot-sunxi/arch/arm/lib/bootm-fdt.c 2014-03-05 23:14:47.196099604 +0100
4726 #include <fdt_support.h>
4727 +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
4728 +#include <asm/armv7.h>
4731 DECLARE_GLOBAL_DATA_PTR;
4735 return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
4738 +int arch_fixup_fdt(void *blob)
4742 + ret = arch_fixup_memory_node(blob);
4746 +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
4747 + ret = armv7_update_dt(blob);
4752 diff -ruN u-boot-2014.01-rc1/arch/arm/lib/interrupts.c u-boot-sunxi/arch/arm/lib/interrupts.c
4753 --- u-boot-2014.01-rc1/arch/arm/lib/interrupts.c 2013-11-25 22:49:32.000000000 +0100
4754 +++ u-boot-sunxi/arch/arm/lib/interrupts.c 2014-03-05 23:14:47.196099604 +0100
4756 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
4757 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
4758 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
4759 - "UK8_32", "UK9_32", "UK10_32", "UND_32",
4760 + "UK8_32", "UK9_32", "HYP_32", "UND_32",
4761 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
4764 diff -ruN u-boot-2014.01-rc1/arch/arm/lib/sections.c u-boot-sunxi/arch/arm/lib/sections.c
4765 --- u-boot-2014.01-rc1/arch/arm/lib/sections.c 2013-11-25 22:49:32.000000000 +0100
4766 +++ u-boot-sunxi/arch/arm/lib/sections.c 2014-03-05 23:14:47.196099604 +0100
4768 char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
4769 char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
4770 char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
4771 +char __secure_start[0] __attribute__((section(".__secure_start")));
4772 +char __secure_end[0] __attribute__((section(".__secure_end")));
4773 diff -ruN u-boot-2014.01-rc1/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.c
4774 --- u-boot-2014.01-rc1/board/sunxi/board.c 1970-01-01 01:00:00.000000000 +0100
4775 +++ u-boot-sunxi/board/sunxi/board.c 2014-03-05 23:14:47.908090095 +0100
4778 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4779 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4781 + * (C) Copyright 2007-2011
4782 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4783 + * Tom Cubie <tangliang@allwinnertech.com>
4785 + * Some board init for the Allwinner A10-evb board.
4787 + * See file CREDITS for list of people who contributed to this
4790 + * This program is free software; you can redistribute it and/or
4791 + * modify it under the terms of the GNU General Public License as
4792 + * published by the Free Software Foundation; either version 2 of
4793 + * the License, or (at your option) any later version.
4795 + * This program is distributed in the hope that it will be useful,
4796 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4797 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4798 + * GNU General Public License for more details.
4800 + * You should have received a copy of the GNU General Public License
4801 + * along with this program; if not, write to the Free Software
4802 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4803 + * MA 02111-1307 USA
4806 +#include <common.h>
4807 +#ifdef CONFIG_AXP152_POWER
4808 +#include <axp152.h>
4810 +#ifdef CONFIG_AXP209_POWER
4811 +#include <axp209.h>
4813 +#include <asm/arch/clock.h>
4814 +#include <asm/arch/dram.h>
4815 +#include <asm/arch/mmc.h>
4817 +DECLARE_GLOBAL_DATA_PTR;
4819 +/* add board specific code here */
4820 +int board_init(void)
4824 + gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
4826 + asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
4827 + debug("id_pfr1: 0x%08x\n", id_pfr1);
4828 + /* Generic Timer Extension available? */
4829 + if ((id_pfr1 >> 16) & 0xf) {
4830 + debug("Setting CNTFRQ\n");
4831 + /* CNTFRQ == 24 MHz */
4832 + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
4835 +#ifdef CONFIG_STATUS_LED
4836 + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
4841 +#ifdef CONFIG_DISPLAY_BOARDINFO
4842 +int checkboard(void)
4844 + printf("Board: %s\n", CONFIG_SYS_BOARD_NAME);
4850 +int dram_init(void)
4852 + gd->ram_size = get_ram_size((unsigned long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
4857 +#ifdef CONFIG_GENERIC_MMC
4858 +int board_mmc_init(bd_t *bis)
4860 + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
4861 +#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
4862 + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
4869 +#ifdef CONFIG_SPL_BUILD
4870 +void sunxi_board_init(void)
4872 + int power_failed = 0;
4873 + unsigned long ramsize;
4876 + ramsize = sunxi_dram_init();
4879 + ramsize = sunxi_dram_init();
4883 + ramsize = sunxi_dram_init();
4885 + printf(" %lu MiB\n", ramsize >> 20);
4889 +#ifdef CONFIG_AXP152_POWER
4890 + power_failed = axp152_init();
4891 + power_failed |= axp152_set_dcdc2(1400);
4892 + power_failed |= axp152_set_dcdc3(1500);
4893 + power_failed |= axp152_set_dcdc4(1250);
4894 + power_failed |= axp152_set_ldo2(3000);
4896 +#ifdef CONFIG_AXP209_POWER
4897 + power_failed |= axp209_init();
4898 + power_failed |= axp209_set_dcdc2(1400);
4899 +#ifdef CONFIG_FAST_MBUS
4900 + power_failed |= axp209_set_dcdc3(1300);
4902 + power_failed |= axp209_set_dcdc3(1250);
4904 + power_failed |= axp209_set_ldo2(3000);
4905 + power_failed |= axp209_set_ldo3(2800);
4906 + power_failed |= axp209_set_ldo4(2800);
4910 + * Only clock up the CPU to full speed if we are reasonably
4911 + * assured it's being powered with suitable core voltage
4913 + if (!power_failed)
4914 +#ifdef CONFIG_SUN7I
4915 + clock_set_pll1(912000000);
4917 + clock_set_pll1(1008000000);
4920 + printf("Failed to set core voltage! Can't set CPU frequency\n");
4923 +#if defined(CONFIG_SPL_OS_BOOT) && defined(CONFIG_AXP209_POWER)
4924 +int spl_start_uboot(void)
4926 + if (axp209_poweron_by_dc())
4928 + axp209_power_button(); /* Clear any pending button event */
4930 + return axp209_power_button();
4934 +#ifdef CONFIG_SPL_DISPLAY_PRINT
4935 +void spl_display_print(void)
4937 + printf("Board: %s\n", CONFIG_SYS_BOARD_NAME);
4942 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a10_olinuxino_l.c u-boot-sunxi/board/sunxi/dram_a10_olinuxino_l.c
4943 --- u-boot-2014.01-rc1/board/sunxi/dram_a10_olinuxino_l.c 1970-01-01 01:00:00.000000000 +0100
4944 +++ u-boot-sunxi/board/sunxi/dram_a10_olinuxino_l.c 2014-03-05 23:14:47.908090095 +0100
4946 +/* this file is generated, don't edit it yourself */
4948 +#include <common.h>
4949 +#include <asm/arch/dram.h>
4951 +static struct dram_para dram_para = {
4962 + .tpr0 = 0x30926692,
4973 +unsigned long sunxi_dram_init(void)
4975 + return dramc_init(&dram_para);
4977 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a10s_olinuxino_m.c u-boot-sunxi/board/sunxi/dram_a10s_olinuxino_m.c
4978 --- u-boot-2014.01-rc1/board/sunxi/dram_a10s_olinuxino_m.c 1970-01-01 01:00:00.000000000 +0100
4979 +++ u-boot-sunxi/board/sunxi/dram_a10s_olinuxino_m.c 2014-03-05 23:14:47.908090095 +0100
4981 +/* this file is generated, don't edit it yourself */
4983 +#include <common.h>
4984 +#include <asm/arch/dram.h>
4986 +static struct dram_para dram_para = {
4997 + .tpr0 = 0x42d899b7,
5008 +unsigned long sunxi_dram_init(void)
5010 + return dramc_init(&dram_para);
5012 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a13_mid.c u-boot-sunxi/board/sunxi/dram_a13_mid.c
5013 --- u-boot-2014.01-rc1/board/sunxi/dram_a13_mid.c 1970-01-01 01:00:00.000000000 +0100
5014 +++ u-boot-sunxi/board/sunxi/dram_a13_mid.c 2014-03-05 23:14:47.908090095 +0100
5016 +/* this file is generated, don't edit it yourself */
5018 +#include <common.h>
5019 +#include <asm/arch/dram.h>
5021 +static struct dram_para dram_para = {
5032 + .tpr0 = 0x42d899b7,
5043 +unsigned long sunxi_dram_init(void)
5045 + return dramc_init(&dram_para);
5047 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a13_oli_micro.c u-boot-sunxi/board/sunxi/dram_a13_oli_micro.c
5048 --- u-boot-2014.01-rc1/board/sunxi/dram_a13_oli_micro.c 1970-01-01 01:00:00.000000000 +0100
5049 +++ u-boot-sunxi/board/sunxi/dram_a13_oli_micro.c 2014-03-05 23:14:47.908090095 +0100
5051 +/* this file is generated, don't edit it yourself */
5053 +#include <common.h>
5054 +#include <asm/arch/dram.h>
5056 +static struct dram_para dram_para = {
5067 + .tpr0 = 0x42d899b7,
5079 +unsigned long sunxi_dram_init(void)
5081 + return dramc_init(&dram_para);
5083 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a13_olinuxino.c u-boot-sunxi/board/sunxi/dram_a13_olinuxino.c
5084 --- u-boot-2014.01-rc1/board/sunxi/dram_a13_olinuxino.c 1970-01-01 01:00:00.000000000 +0100
5085 +++ u-boot-sunxi/board/sunxi/dram_a13_olinuxino.c 2014-03-05 23:14:47.908090095 +0100
5087 +/* this file is generated, don't edit it yourself */
5089 +#include <common.h>
5090 +#include <asm/arch/dram.h>
5092 +static struct dram_para dram_para = {
5103 + .tpr0 = 0x42d899b7,
5114 +unsigned long sunxi_dram_init(void)
5116 + return dramc_init(&dram_para);
5118 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_a20_olinuxino_m.c u-boot-sunxi/board/sunxi/dram_a20_olinuxino_m.c
5119 --- u-boot-2014.01-rc1/board/sunxi/dram_a20_olinuxino_m.c 1970-01-01 01:00:00.000000000 +0100
5120 +++ u-boot-sunxi/board/sunxi/dram_a20_olinuxino_m.c 2014-03-05 23:14:47.908090095 +0100
5122 +/* this file is generated, don't edit it yourself */
5124 +#include "common.h"
5125 +#include <asm/arch/dram.h>
5127 +static struct dram_para dram_para = {
5138 + .tpr0 = 0x42d899b7,
5149 +unsigned long sunxi_dram_init(void)
5151 + return dramc_init(&dram_para);
5153 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_auxtek_t003.c u-boot-sunxi/board/sunxi/dram_auxtek_t003.c
5154 --- u-boot-2014.01-rc1/board/sunxi/dram_auxtek_t003.c 1970-01-01 01:00:00.000000000 +0100
5155 +++ u-boot-sunxi/board/sunxi/dram_auxtek_t003.c 2014-03-05 23:14:47.908090095 +0100
5157 +/* this file is generated, don't edit it yourself */
5159 +#include <common.h>
5160 +#include <asm/arch/dram.h>
5162 +static struct dram_para dram_para = {
5173 + .tpr0 = 0x42d899b7,
5184 +unsigned long sunxi_dram_init(void)
5186 + return dramc_init(&dram_para);
5188 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard2.c u-boot-sunxi/board/sunxi/dram_cubieboard2.c
5189 --- u-boot-2014.01-rc1/board/sunxi/dram_cubieboard2.c 1970-01-01 01:00:00.000000000 +0100
5190 +++ u-boot-sunxi/board/sunxi/dram_cubieboard2.c 2014-03-05 23:14:47.908090095 +0100
5192 +/* this file is generated, don't edit it yourself */
5194 +#include <common.h>
5195 +#include <asm/arch/dram.h>
5197 +static struct dram_para dram_para = {
5208 + .tpr0 = 0x42d899b7,
5219 +unsigned long sunxi_dram_init(void)
5221 + return dramc_init(&dram_para);
5223 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard_512.c u-boot-sunxi/board/sunxi/dram_cubieboard_512.c
5224 --- u-boot-2014.01-rc1/board/sunxi/dram_cubieboard_512.c 1970-01-01 01:00:00.000000000 +0100
5225 +++ u-boot-sunxi/board/sunxi/dram_cubieboard_512.c 2014-03-05 23:14:47.908090095 +0100
5227 +/* this file is generated, don't edit it yourself */
5229 +#include <common.h>
5230 +#include <asm/arch/dram.h>
5232 +static struct dram_para dram_para = {
5243 + .tpr0 = 0x30926692,
5254 +unsigned long sunxi_dram_init(void)
5256 + return dramc_init(&dram_para);
5258 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubieboard.c u-boot-sunxi/board/sunxi/dram_cubieboard.c
5259 --- u-boot-2014.01-rc1/board/sunxi/dram_cubieboard.c 1970-01-01 01:00:00.000000000 +0100
5260 +++ u-boot-sunxi/board/sunxi/dram_cubieboard.c 2014-03-05 23:14:47.908090095 +0100
5262 +/* this file is generated, don't edit it yourself */
5264 +#include <common.h>
5265 +#include <asm/arch/dram.h>
5267 +static struct dram_para dram_para = {
5278 + .tpr0 = 0x30926692,
5289 +unsigned long sunxi_dram_init(void)
5291 + return dramc_init(&dram_para);
5293 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_cubietruck.c u-boot-sunxi/board/sunxi/dram_cubietruck.c
5294 --- u-boot-2014.01-rc1/board/sunxi/dram_cubietruck.c 1970-01-01 01:00:00.000000000 +0100
5295 +++ u-boot-sunxi/board/sunxi/dram_cubietruck.c 2014-03-05 23:14:47.908090095 +0100
5297 +/* this file is generated, don't edit it yourself */
5299 +#include <common.h>
5300 +#include <asm/arch/dram.h>
5302 +static struct dram_para dram_para = {
5313 + .tpr0 = 0x42d899b7,
5324 +unsigned long sunxi_dram_init(void)
5326 + return dramc_init(&dram_para);
5328 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_eoma68_a20.c u-boot-sunxi/board/sunxi/dram_eoma68_a20.c
5329 --- u-boot-2014.01-rc1/board/sunxi/dram_eoma68_a20.c 1970-01-01 01:00:00.000000000 +0100
5330 +++ u-boot-sunxi/board/sunxi/dram_eoma68_a20.c 2014-03-05 23:14:47.908090095 +0100
5332 +/* this file is generated, don't edit it yourself */
5334 +#include "common.h"
5335 +#include <asm/arch/dram.h>
5337 +static struct dram_para dram_para = {
5348 + .tpr0 = 0x42d899b7,
5359 +unsigned long sunxi_dram_init(void)
5361 + return dramc_init(&dram_para);
5363 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_eu3000.c u-boot-sunxi/board/sunxi/dram_eu3000.c
5364 --- u-boot-2014.01-rc1/board/sunxi/dram_eu3000.c 1970-01-01 01:00:00.000000000 +0100
5365 +++ u-boot-sunxi/board/sunxi/dram_eu3000.c 2014-03-05 23:14:47.908090095 +0100
5367 +/* this file is generated, don't edit it yourself */
5369 +#include "common.h"
5370 +#include <asm/arch/dram.h>
5372 +static struct dram_para dram_para = {
5383 + .tpr0 = 0x42d899b7,
5394 +unsigned long sunxi_dram_init(void)
5396 + return dramc_init(&dram_para);
5398 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_gooseberry_a721.c u-boot-sunxi/board/sunxi/dram_gooseberry_a721.c
5399 --- u-boot-2014.01-rc1/board/sunxi/dram_gooseberry_a721.c 1970-01-01 01:00:00.000000000 +0100
5400 +++ u-boot-sunxi/board/sunxi/dram_gooseberry_a721.c 2014-03-05 23:14:47.908090095 +0100
5402 +/* this file is generated, don't edit it yourself */
5404 +#include <common.h>
5405 +#include <asm/arch/dram.h>
5407 +static struct dram_para dram_para = {
5418 + .tpr0 = 0x30926692,
5429 +unsigned long sunxi_dram_init(void)
5431 + return dramc_init(&dram_para);
5433 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_h6.c u-boot-sunxi/board/sunxi/dram_h6.c
5434 --- u-boot-2014.01-rc1/board/sunxi/dram_h6.c 1970-01-01 01:00:00.000000000 +0100
5435 +++ u-boot-sunxi/board/sunxi/dram_h6.c 2014-03-05 23:14:47.908090095 +0100
5437 +/* this file is generated, don't edit it yourself */
5439 +#include <common.h>
5440 +#include <asm/arch/dram.h>
5442 +static struct dram_para dram_para = {
5453 + .tpr0 = 0x30926692,
5464 +unsigned long sunxi_dram_init(void)
5466 + return dramc_init(&dram_para);
5468 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_hackberry.c u-boot-sunxi/board/sunxi/dram_hackberry.c
5469 --- u-boot-2014.01-rc1/board/sunxi/dram_hackberry.c 1970-01-01 01:00:00.000000000 +0100
5470 +++ u-boot-sunxi/board/sunxi/dram_hackberry.c 2014-03-05 23:14:47.908090095 +0100
5472 +/* this file is generated, don't edit it yourself */
5474 +#include <common.h>
5475 +#include <asm/arch/dram.h>
5477 +static struct dram_para dram_para = {
5488 + .tpr0 = 0x30926692,
5499 +unsigned long sunxi_dram_init(void)
5501 + return dramc_init(&dram_para);
5503 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_inet_k70hc.c u-boot-sunxi/board/sunxi/dram_inet_k70hc.c
5504 --- u-boot-2014.01-rc1/board/sunxi/dram_inet_k70hc.c 1970-01-01 01:00:00.000000000 +0100
5505 +++ u-boot-sunxi/board/sunxi/dram_inet_k70hc.c 2014-03-05 23:14:47.908090095 +0100
5507 +/* this file is generated, don't edit it yourself */
5509 +#include <common.h>
5510 +#include <asm/arch/dram.h>
5512 +static struct dram_para dram_para = {
5523 + .tpr0 = 0x42d899b7,
5534 +unsigned long sunxi_dram_init(void)
5536 + return dramc_init(&dram_para);
5538 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_megafeis_a08.c u-boot-sunxi/board/sunxi/dram_megafeis_a08.c
5539 --- u-boot-2014.01-rc1/board/sunxi/dram_megafeis_a08.c 1970-01-01 01:00:00.000000000 +0100
5540 +++ u-boot-sunxi/board/sunxi/dram_megafeis_a08.c 2014-03-05 23:14:47.908090095 +0100
5542 +/* this file is generated, don't edit it yourself */
5544 +#include <common.h>
5545 +#include <asm/arch/dram.h>
5547 +static struct dram_para dram_para = {
5558 + .tpr0 = 0x42d899b7,
5569 +unsigned long sunxi_dram_init(void)
5571 + return dramc_init(&dram_para);
5573 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mini_x_a10s.c u-boot-sunxi/board/sunxi/dram_mini_x_a10s.c
5574 --- u-boot-2014.01-rc1/board/sunxi/dram_mini_x_a10s.c 1970-01-01 01:00:00.000000000 +0100
5575 +++ u-boot-sunxi/board/sunxi/dram_mini_x_a10s.c 2014-03-05 23:14:47.908090095 +0100
5577 +/* this file is generated, don't edit it yourself */
5579 +#include <common.h>
5580 +#include <asm/arch/dram.h>
5582 +static struct dram_para dram_para = {
5593 + .tpr0 = 0x42d899b7,
5604 +unsigned long sunxi_dram_init(void)
5606 + return dramc_init(&dram_para);
5608 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mk802_a10s.c u-boot-sunxi/board/sunxi/dram_mk802_a10s.c
5609 --- u-boot-2014.01-rc1/board/sunxi/dram_mk802_a10s.c 1970-01-01 01:00:00.000000000 +0100
5610 +++ u-boot-sunxi/board/sunxi/dram_mk802_a10s.c 2014-03-05 23:14:47.908090095 +0100
5612 +/* this file is generated, don't edit it yourself */
5614 +#include <common.h>
5615 +#include <asm/arch/dram.h>
5617 +static struct dram_para dram_para = {
5628 + .tpr0 = 0x42d899b7,
5639 +unsigned long sunxi_dram_init(void)
5641 + return dramc_init(&dram_para);
5643 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_mk802ii_a20.c u-boot-sunxi/board/sunxi/dram_mk802ii_a20.c
5644 --- u-boot-2014.01-rc1/board/sunxi/dram_mk802ii_a20.c 1970-01-01 01:00:00.000000000 +0100
5645 +++ u-boot-sunxi/board/sunxi/dram_mk802ii_a20.c 2014-03-05 23:14:47.908090095 +0100
5647 +/* this file is generated, don't edit it yourself */
5649 +#include "common.h"
5650 +#include <asm/arch/dram.h>
5652 +static struct dram_para dram_para = {
5663 + .tpr0 = 0x42d899b7,
5674 +unsigned long sunxi_dram_init(void)
5676 + return dramc_init(&dram_para);
5678 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2.c u-boot-sunxi/board/sunxi/dram_pov_protab2.c
5679 --- u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2.c 1970-01-01 01:00:00.000000000 +0100
5680 +++ u-boot-sunxi/board/sunxi/dram_pov_protab2.c 2014-03-05 23:14:47.908090095 +0100
5682 +/* this file is generated, don't edit it yourself */
5684 +#include <common.h>
5685 +#include <asm/arch/dram.h>
5687 +static struct dram_para dram_para = {
5698 + .tpr0 = 0x30926692,
5709 +unsigned long sunxi_dram_init(void)
5711 + return dramc_init(&dram_para);
5713 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2_xxl.c u-boot-sunxi/board/sunxi/dram_pov_protab2_xxl.c
5714 --- u-boot-2014.01-rc1/board/sunxi/dram_pov_protab2_xxl.c 1970-01-01 01:00:00.000000000 +0100
5715 +++ u-boot-sunxi/board/sunxi/dram_pov_protab2_xxl.c 2014-03-05 23:14:47.908090095 +0100
5717 +/* this file is generated, don't edit it yourself */
5719 +#include <common.h>
5720 +#include <asm/arch/dram.h>
5722 +static struct dram_para dram_para = {
5733 + .tpr0 = 0x30926692,
5744 +unsigned long sunxi_dram_init(void)
5746 + return dramc_init(&dram_para);
5748 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_r7dongle.c u-boot-sunxi/board/sunxi/dram_r7dongle.c
5749 --- u-boot-2014.01-rc1/board/sunxi/dram_r7dongle.c 1970-01-01 01:00:00.000000000 +0100
5750 +++ u-boot-sunxi/board/sunxi/dram_r7dongle.c 2014-03-05 23:14:47.908090095 +0100
5752 +/* this file is generated, don't edit it yourself */
5754 +#include <common.h>
5755 +#include <asm/arch/dram.h>
5757 +static struct dram_para dram_para = {
5768 + .tpr0 = 0x42d899b7,
5779 +unsigned long sunxi_dram_init(void)
5781 + return dramc_init(&dram_para);
5783 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sanei_n90.c u-boot-sunxi/board/sunxi/dram_sanei_n90.c
5784 --- u-boot-2014.01-rc1/board/sunxi/dram_sanei_n90.c 1970-01-01 01:00:00.000000000 +0100
5785 +++ u-boot-sunxi/board/sunxi/dram_sanei_n90.c 2014-03-05 23:14:47.908090095 +0100
5787 +/* this file is generated, don't edit it yourself */
5789 +#include <common.h>
5790 +#include <asm/arch/dram.h>
5792 +static struct dram_para dram_para = {
5803 + .tpr0 = 0x30926692,
5813 +unsigned long sunxi_dram_init(void)
5815 + return dramc_init(&dram_para);
5817 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_312_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_312_1024_iow8.c
5818 --- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_312_1024_iow8.c 1970-01-01 01:00:00.000000000 +0100
5819 +++ u-boot-sunxi/board/sunxi/dram_sun4i_312_1024_iow8.c 2014-03-05 23:14:47.908090095 +0100
5821 +/* this file is generated, don't edit it yourself */
5823 +#include <common.h>
5824 +#include <asm/arch/dram.h>
5826 +static struct dram_para dram_para = {
5837 + .tpr0 = 0x30926692,
5848 +unsigned long sunxi_dram_init(void)
5850 + return dramc_init(&dram_para);
5852 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow16.c
5853 --- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5854 +++ u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow16.c 2014-03-05 23:14:47.908090095 +0100
5856 +/* this file is generated, don't edit it yourself */
5858 +#include <common.h>
5859 +#include <asm/arch/dram.h>
5861 +static struct dram_para dram_para = {
5872 + .tpr0 = 0x30926692,
5883 +unsigned long sunxi_dram_init(void)
5885 + return dramc_init(&dram_para);
5887 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow8.c
5888 --- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_1024_iow8.c 1970-01-01 01:00:00.000000000 +0100
5889 +++ u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow8.c 2014-03-05 23:14:47.908090095 +0100
5891 +/* this file is generated, don't edit it yourself */
5893 +#include <common.h>
5894 +#include <asm/arch/dram.h>
5896 +static struct dram_para dram_para = {
5907 + .tpr0 = 0x30926692,
5918 +unsigned long sunxi_dram_init(void)
5920 + return dramc_init(&dram_para);
5922 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_512.c u-boot-sunxi/board/sunxi/dram_sun4i_360_512.c
5923 --- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_360_512.c 1970-01-01 01:00:00.000000000 +0100
5924 +++ u-boot-sunxi/board/sunxi/dram_sun4i_360_512.c 2014-03-05 23:14:47.908090095 +0100
5926 +/* this file is generated, don't edit it yourself */
5928 +#include <common.h>
5929 +#include <asm/arch/dram.h>
5931 +static struct dram_para dram_para = {
5942 + .tpr0 = 0x30926692,
5953 +unsigned long sunxi_dram_init(void)
5955 + return dramc_init(&dram_para);
5957 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_384_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow8.c
5958 --- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_384_1024_iow8.c 1970-01-01 01:00:00.000000000 +0100
5959 +++ u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow8.c 2014-03-05 23:14:47.908090095 +0100
5961 +/* this file is generated, don't edit it yourself */
5963 +#include <common.h>
5964 +#include <asm/arch/dram.h>
5966 +static struct dram_para dram_para = {
5977 + .tpr0 = 0x30926692,
5988 +unsigned long sunxi_dram_init(void)
5990 + return dramc_init(&dram_para);
5992 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow16.c
5993 --- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5994 +++ u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow16.c 2014-03-05 23:14:47.912090042 +0100
5996 +/* this file is generated, don't edit it yourself */
5998 +#include <common.h>
5999 +#include <asm/arch/dram.h>
6001 +static struct dram_para dram_para = {
6012 + .tpr0 = 0x30926692,
6023 +unsigned long sunxi_dram_init(void)
6025 + return dramc_init(&dram_para);
6027 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow8.c
6028 --- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_1024_iow8.c 1970-01-01 01:00:00.000000000 +0100
6029 +++ u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow8.c 2014-03-05 23:14:47.912090042 +0100
6031 +/* this file is generated, don't edit it yourself */
6033 +#include <common.h>
6034 +#include <asm/arch/dram.h>
6036 +static struct dram_para dram_para = {
6047 + .tpr0 = 0x30926692,
6058 +unsigned long sunxi_dram_init(void)
6060 + return dramc_init(&dram_para);
6062 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_512.c u-boot-sunxi/board/sunxi/dram_sun4i_408_512.c
6063 --- u-boot-2014.01-rc1/board/sunxi/dram_sun4i_408_512.c 1970-01-01 01:00:00.000000000 +0100
6064 +++ u-boot-sunxi/board/sunxi/dram_sun4i_408_512.c 2014-03-05 23:14:47.912090042 +0100
6066 +/* this file is generated, don't edit it yourself */
6068 +#include <common.h>
6069 +#include <asm/arch/dram.h>
6071 +static struct dram_para dram_para = {
6082 + .tpr0 = 0x30926692,
6093 +unsigned long sunxi_dram_init(void)
6095 + return dramc_init(&dram_para);
6097 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_wobo_i5.c u-boot-sunxi/board/sunxi/dram_wobo_i5.c
6098 --- u-boot-2014.01-rc1/board/sunxi/dram_wobo_i5.c 1970-01-01 01:00:00.000000000 +0100
6099 +++ u-boot-sunxi/board/sunxi/dram_wobo_i5.c 2014-03-05 23:14:47.912090042 +0100
6101 +/* this file is generated, don't edit it yourself */
6103 +#include <common.h>
6104 +#include <asm/arch/dram.h>
6106 +static struct dram_para dram_para = {
6117 + .tpr0 = 0x42d899b7,
6128 +unsigned long sunxi_dram_init(void)
6130 + return dramc_init(&dram_para);
6132 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_xzpad700.c u-boot-sunxi/board/sunxi/dram_xzpad700.c
6133 --- u-boot-2014.01-rc1/board/sunxi/dram_xzpad700.c 1970-01-01 01:00:00.000000000 +0100
6134 +++ u-boot-sunxi/board/sunxi/dram_xzpad700.c 2014-03-05 23:14:47.912090042 +0100
6136 +/* this file is generated, don't edit it yourself */
6138 +#include <common.h>
6139 +#include <asm/arch/dram.h>
6141 +static struct dram_para dram_para = {
6152 + .tpr0 = 0x42d899b7,
6163 +unsigned long sunxi_dram_init(void)
6165 + return dramc_init(&dram_para);
6167 diff -ruN u-boot-2014.01-rc1/board/sunxi/dram_zatab.c u-boot-sunxi/board/sunxi/dram_zatab.c
6168 --- u-boot-2014.01-rc1/board/sunxi/dram_zatab.c 1970-01-01 01:00:00.000000000 +0100
6169 +++ u-boot-sunxi/board/sunxi/dram_zatab.c 2014-03-05 23:14:47.912090042 +0100
6171 +/* this file is generated, don't edit it yourself */
6173 +#include <common.h>
6174 +#include <asm/arch/dram.h>
6176 +static struct dram_para dram_para = {
6187 + .tpr0 = 0x30926692,
6198 +unsigned long sunxi_dram_init(void)
6200 + return dramc_init(&dram_para);
6202 diff -ruN u-boot-2014.01-rc1/board/sunxi/Makefile u-boot-sunxi/board/sunxi/Makefile
6203 --- u-boot-2014.01-rc1/board/sunxi/Makefile 1970-01-01 01:00:00.000000000 +0100
6204 +++ u-boot-sunxi/board/sunxi/Makefile 2014-03-05 23:14:47.908090095 +0100
6207 +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
6209 +# Based on some other board Makefile
6211 +# (C) Copyright 2000-2003
6212 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6214 +# See file CREDITS for list of people who contributed to this
6217 +# This program is free software; you can redistribute it and/or
6218 +# modify it under the terms of the GNU General Public License as
6219 +# published by the Free Software Foundation; either version 2 of
6220 +# the License, or (at your option) any later version.
6222 +# This program is distributed in the hope that it will be useful,
6223 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
6224 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6225 +# GNU General Public License for more details.
6227 +# You should have received a copy of the GNU General Public License
6228 +# along with this program; if not, write to the Free Software
6229 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
6230 +# MA 02111-1307 USA
6234 +obj-$(CONFIG_A10_MID_1GB) += dram_sun4i_360_1024_iow16.o
6235 +obj-$(CONFIG_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
6236 +obj-$(CONFIG_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o
6237 +obj-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o
6238 +obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
6239 +obj-$(CONFIG_A13_MID) += dram_a13_mid.o
6240 +obj-$(CONFIG_A20_OLINUXINO_M) += dram_a20_olinuxino_m.o
6241 +obj-$(CONFIG_AUXTEK_T003) += dram_auxtek_t003.o
6242 +# This is not a typo, uses the same mem settings as the a10s-olinuxino-m
6243 +obj-$(CONFIG_AUXTEK_T004) += dram_a10s_olinuxino_m.o
6244 +obj-$(CONFIG_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
6245 +obj-$(CONFIG_COBY_MID7042) += dram_sun4i_408_1024_iow16.o
6246 +obj-$(CONFIG_COBY_MID8042) += dram_sun4i_360_1024_iow16.o
6247 +obj-$(CONFIG_COBY_MID9742) += dram_sun4i_408_1024_iow16.o
6248 +obj-$(CONFIG_MARSBOARD_A10) += dram_sun4i_360_1024_iow16.o
6249 +obj-$(CONFIG_MARSBOARD_A20) += dram_sun4i_360_1024_iow16.o
6250 +obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
6251 +obj-$(CONFIG_CUBIEBOARD_512) += dram_cubieboard_512.o
6252 +obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
6253 +obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
6254 +obj-$(CONFIG_DNS_M82) += dram_sun4i_360_1024_iow16.o
6255 +obj-$(CONFIG_EOMA68_A10) += dram_sun4i_360_1024_iow8.o
6256 +obj-$(CONFIG_EOMA68_A20) += dram_eoma68_a20.o
6257 +obj-$(CONFIG_EU3000) += dram_eu3000.o
6258 +obj-$(CONFIG_GOOSEBERRY_A721) += dram_gooseberry_a721.o
6259 +obj-$(CONFIG_H6) += dram_h6.o
6260 +obj-$(CONFIG_HACKBERRY) += dram_hackberry.o
6261 +obj-$(CONFIG_A7HD) += dram_sun4i_360_1024_iow8.o
6262 +obj-$(CONFIG_INTERRA3) += dram_mk802ii_a20.o
6263 +obj-$(CONFIG_INET_86VZ) += dram_a10s_olinuxino_m.o
6264 +obj-$(CONFIG_INET97F_II) += dram_sun4i_408_512.o
6265 +obj-$(CONFIG_INET_K70HC) += dram_inet_k70hc.o
6266 +obj-$(CONFIG_JESURUN_Q5) += dram_sun4i_312_1024_iow8.o
6267 +obj-$(CONFIG_K1001L1C) += dram_a20_olinuxino_m.o
6268 +obj-$(CONFIG_MEFAFEIS_A08) += dram_megafeis_a08.o
6269 +obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o
6270 +obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
6271 +obj-$(CONFIG_MELE_A3700) += dram_sun4i_360_1024_iow8.o
6272 +obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o
6273 +obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
6274 +obj-$(CONFIG_MINI_X_A10S) += dram_mini_x_a10s.o
6275 +obj-$(CONFIG_MK802) += dram_sun4i_360_512.o
6276 +obj-$(CONFIG_MK802_1GB) += dram_sun4i_360_1024_iow16.o
6277 +obj-$(CONFIG_MK802_A10S) += dram_mk802_a10s.o
6278 +obj-$(CONFIG_MK802II) += dram_sun4i_408_1024_iow8.o
6279 +obj-$(CONFIG_MK802II_A20) += dram_mk802ii_a20.o
6280 +obj-$(CONFIG_PCDUINO) += dram_sun4i_408_1024_iow8.o
6281 +obj-$(CONFIG_PENGPOD700) += dram_sun4i_384_1024_iow8.o
6282 +obj-$(CONFIG_PENGPOD1000) += dram_sun4i_408_1024_iow16.o
6283 +obj-$(CONFIG_POV_PROTAB2) += dram_pov_protab2.o
6284 +obj-$(CONFIG_POV_PROTAB2_XXL) += dram_pov_protab2_xxl.o
6285 +obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
6286 +obj-$(CONFIG_SANEI_N90) += dram_sanei_n90.o
6287 +obj-$(CONFIG_UHOST_U1A) += dram_sun4i_360_1024_iow8.o
6288 +obj-$(CONFIG_WOBO_I5) += dram_wobo_i5.o
6289 +obj-$(CONFIG_XZPAD700) += dram_xzpad700.o
6290 +obj-$(CONFIG_ZATAB) += dram_zatab.o
6291 diff -ruN u-boot-2014.01-rc1/boards.cfg u-boot-sunxi/boards.cfg
6292 --- u-boot-2014.01-rc1/boards.cfg 2013-11-25 22:49:32.000000000 +0100
6293 +++ u-boot-sunxi/boards.cfg 2014-03-05 23:14:47.948089561 +0100
6294 @@ -344,6 +344,82 @@
6295 Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang@samsung.com>
6296 Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
6297 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
6298 +Active arm armv7 sunxi - sunxi A10_MID_1GB sun4i:A10_MID_1GB,SPL -
6299 +Active arm armv7 sunxi - sunxi A10-OLinuXino-Lime sun4i:A10_OLINUXINO_L,STATUSLED=226,SPL,SUNXI_EMAC -
6300 +Active arm armv7 sunxi - sunxi A10s-OLinuXino-M sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL,SUNXI_EMAC -
6301 +Active arm armv7 sunxi - sunxi A10s-OLinuXino-M_FEL sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL_FEL,SUNXI_EMAC -
6302 +Active arm armv7 sunxi - sunxi A13-OLinuXino sun5i:A13_OLINUXINO,SPL,STATUSLED=201,CONS_INDEX=2 -
6303 +Active arm armv7 sunxi - sunxi A13-OLinuXino_FEL sun5i:A13_OLINUXINO,SPL_FEL,STATUSLED=201,CONS_INDEX=2 -
6304 +Active arm armv7 sunxi - sunxi A13-OLinuXino_FEL_sdcon sun5i:A13_OLINUXINO,SPL_FEL,STATUSLED=201,UART0_PORT_F -
6305 +Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,NO_AXP,STATUSLED=201,CONS_INDEX=2 -
6306 +Active arm armv7 sunxi - sunxi A13-OLinuXinoM_FEL sun5i:A13_OLINUXINOM,SPL_FEL,NO_AXP,STATUSLED=201,CONS_INDEX=2 -
6307 +Active arm armv7 sunxi - sunxi A13_MID sun5i:A13_MID,SPL,CONS_INDEX=2 -
6308 +Active arm armv7 sunxi - sunxi A20-OLinuXino_MICRO sun7i:A20_OLINUXINO_M,CONS_INDEX=1,STATUSLED=226,SPL,SUNXI_GMAC,FAST_MBUS -
6309 +Active arm armv7 sunxi - sunxi A20-OLinuXino_MICRO_FEL sun7i:A20_OLINUXINO_M,CONS_INDEX=1,STATUSLED=226,SPL_FEL,SUNXI_GMAC,FAST_MBUS -
6310 +Active arm armv7 sunxi - sunxi Auxtek-T003 sun5i:AUXTEK_T003,SPL,AXP152_POWER,STATUSLED=34 -
6311 +Active arm armv7 sunxi - sunxi Auxtek-T004 sun5i:AUXTEK_T004,SPL,AXP152_POWER,STATUSLED=34 -
6312 +Active arm armv7 sunxi - sunxi ba10_tv_box sun4i:BA10_TV_BOX,SPL,SUNXI_EMAC -
6313 +Active arm armv7 sunxi - sunxi Coby_MID7042 sun4i:COBY_MID7042,SPL -
6314 +Active arm armv7 sunxi - sunxi Coby_MID8042 sun4i:COBY_MID8042,SPL -
6315 +Active arm armv7 sunxi - sunxi Coby_MID9742 sun4i:COBY_MID9742,SPL -
6316 +Active arm armv7 sunxi - sunxi Colombus sun6i:COLOMBUS -
6317 +Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 -
6318 +Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS -
6319 +Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS -
6320 +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS -
6321 +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS -
6322 +Active arm armv7 sunxi - sunxi Cubieboard_512 sun4i:CUBIEBOARD_512,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 -
6323 +Active arm armv7 sunxi - sunxi Cubieboard_FEL sun4i:CUBIEBOARD,SPL_FEL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 -
6324 +Active arm armv7 sunxi - sunxi DNS_M82 sun4i:DNS_M82,SPL -
6325 +Active arm armv7 sunxi - sunxi EOMA68_A10 sun4i:EOMA68_A10,SPL,MMC_SUNXI_SLOT=3,SUNXI_EMAC -
6326 +Active arm armv7 sunxi - sunxi EOMA68_A10_FEL sun4i:EOMA68_A10,SPL_FEL,MMC_SUNXI_SLOT=3,SUNXI_EMAC -
6327 +Active arm armv7 sunxi - sunxi EOMA68_A20 sun7i:EOMA68_A20,SPL,MMC_SUNXI_SLOT=3,SUNXI_EMAC -
6328 +Active arm armv7 sunxi - sunxi EOMA68_A20_FEL sun7i:EOMA68_A20,SPL_FEL,MMC_SUNXI_SLOT=3,SUNXI_EMAC -
6329 +Active arm armv7 sunxi - sunxi EU3000 sun7i:EU3000,SPL -
6330 +Active arm armv7 sunxi - sunxi Gooseberry_A721 sun4i:GOOSEBERRY_A721,SPL -
6331 +Active arm armv7 sunxi - sunxi H6 sun4i:H6,SPL -
6332 +Active arm armv7 sunxi - sunxi Hackberry sun4i:HACKBERRY,SPL -
6333 +Active arm armv7 sunxi - sunxi Hyundai_A7HD sun4i:A7HD,SPL -
6334 +Active arm armv7 sunxi - sunxi Interra-3 sun7i:INTERRA3,SPL,SUNXI_GMAC,FAST_MBUS,MMC_SUNXI_SLOT=2 -
6335 +Active arm armv7 sunxi - sunxi INet_86VZ sun5i:INET_86VZ,SPL -
6336 +Active arm armv7 sunxi - sunxi INet_86VZ_FEL sun5i:INET_86VZ,SPL_FEL,UART0_PORT_F -
6337 +Active arm armv7 sunxi - sunxi INet97F-II sun4i:INET97F_II,SPL -
6338 +Active arm armv7 sunxi - sunxi INet_K70HC sun7i:INET_K70HC,SPL -
6339 +Active arm armv7 sunxi - sunxi Jesurun-Q5 sun4i:JESURUN_Q5,SPL,SUNXI_EMAC,STATUSLED=244 -
6340 +Active arm armv7 sunxi - sunxi K1001L1C sun7i:K1001L1C,SPL -
6341 +Active arm armv7 sunxi - sunxi Marsboard_A10 sun4i:MARSBOARD_A10,SPL,SUNXI_EMAC,NO_AXP -
6342 +Active arm armv7 sunxi - sunxi Marsboard_A20 sun7i:MARSBOARD_A20,SPL,SUNXI_EMAC,NO_AXP -
6343 +Active arm armv7 sunxi - sunxi Marsboard_A20_debug sun7i:MARSBOARD_A20,SPL,SUNXI_EMAC,NO_AXP,SYS_SECONDARY_ON -
6344 +Active arm armv7 sunxi - sunxi Megafeis_A08 sun5i:MEFAFEIS_A08,SPL -
6345 +Active arm armv7 sunxi - sunxi Mele_A1000 sun4i:MELE_A1000,SPL,SUNXI_EMAC,STATUSLED=234 -
6346 +Active arm armv7 sunxi - sunxi Mele_A1000_FEL sun4i:MELE_A1000,SPL_FEL,SUNXI_EMAC,STATUSLED=234 -
6347 +Active arm armv7 sunxi - sunxi Mele_A1000G sun4i:MELE_A1000G,SPL,SUNXI_EMAC,STATUSLED=234 -
6348 +Active arm armv7 sunxi - sunxi Mele_A3700 sun4i:MELE_A3700,SPL,SUNXI_EMAC,STATUSLED=234 -
6349 +Active arm armv7 sunxi - sunxi Mini-X sun4i:MINI_X,SPL -
6350 +Active arm armv7 sunxi - sunxi Mini-X-1Gb sun4i:MINI_X_1GB,SPL -
6351 +Active arm armv7 sunxi - sunxi Mini-X_A10s sun5i:MINI_X_A10S,SPL -
6352 +Active arm armv7 sunxi - sunxi mk802 sun4i:MK802,SPL,NO_AXP -
6353 +Active arm armv7 sunxi - sunxi mk802-1gb sun4i:MK802_1GB,SPL,NO_AXP -
6354 +Active arm armv7 sunxi - sunxi mk802_a10s sun5i:MK802_A10S,SPL,AXP152_POWER,STATUSLED=34 -
6355 +Active arm armv7 sunxi - sunxi mk802ii_A20 sun7i:MK802II_A20,SPL -
6356 +Active arm armv7 sunxi - sunxi mk802ii sun4i:MK802II,SPL -
6357 +Active arm armv7 sunxi - sunxi pcDuino sun4i:PCDUINO,SPL,SUNXI_EMAC -
6358 +Active arm armv7 sunxi - sunxi pengpod1000 sun4i:PENGPOD1000,SPL -
6359 +Active arm armv7 sunxi - sunxi pengpod700 sun4i:PENGPOD700,SPL -
6360 +Active arm armv7 sunxi - sunxi PoV_ProTab2_IPS9 sun4i:POV_PROTAB2,SPL -
6361 +Active arm armv7 sunxi - sunxi PoV_ProTab2_IPS_3g sun4i:POV_PROTAB2,SPL -
6362 +Active arm armv7 sunxi - sunxi PoV_ProTab2_XXL sun4i:POV_PROTAB2_XXL,SPL -
6363 +Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER,STATUSLED=34 -
6364 +Active arm armv7 sunxi - sunxi Sanei_N90 sun4i:SANEI_N90,SPL -
6365 +Active arm armv7 sunxi - sunxi sun4i sun4i:SUNXI_EMAC -
6366 +Active arm armv7 sunxi - sunxi sun4i_sdcon sun4i:UART0_PORT_F,SUNXI_EMAC -
6367 +Active arm armv7 sunxi - sunxi sun5i sun5i:SUNXI_EMAC -
6368 +Active arm armv7 sunxi - sunxi sun5i_sdcon sun5i:UART0_PORT_F,SUNXI_EMAC -
6369 +Active arm armv7 sunxi - sunxi sun5i_uart1 sun5i:CONS_INDEX=2,SUNXI_EMAC -
6370 +Active arm armv7 sunxi - sunxi uhost_u1a sun4i:UHOST_U1A,SPL,STATUSLED=34 -
6371 +Active arm armv7 sunxi - sunxi wobo-i5 sun5i:WOBO_I5,SPL,STATUSLED=34 -
6372 +Active arm armv7 sunxi - sunxi xzpad700 sun5i:XZPAD700,SPL -
6373 +Active arm armv7 sunxi - sunxi zatab sun4i:ZATAB,SPL -
6374 Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
6375 Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
6376 Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
6377 diff -ruN u-boot-2014.01-rc1/common/cmd_gpio.c u-boot-sunxi/common/cmd_gpio.c
6378 --- u-boot-2014.01-rc1/common/cmd_gpio.c 2013-11-25 22:49:32.000000000 +0100
6379 +++ u-boot-sunxi/common/cmd_gpio.c 2014-03-05 23:14:47.952089507 +0100
6387 static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
6389 case 's': sub_cmd = GPIO_SET; break;
6390 case 'c': sub_cmd = GPIO_CLEAR; break;
6391 case 't': sub_cmd = GPIO_TOGGLE; break;
6392 + case 'o': sub_cmd = GPIO_OSCILLATE; break;
6393 default: goto show_usage;
6397 if (sub_cmd == GPIO_INPUT) {
6398 gpio_direction_input(gpio);
6399 value = gpio_get_value(gpio);
6400 + } else if (sub_cmd == GPIO_OSCILLATE) {
6402 + gpio_direction_output(gpio, 0);
6403 + for (i = 0; i < 100000000; i++) {
6404 + gpio_set_value(gpio, i&1);
6406 + gpio_direction_input(gpio);
6410 case GPIO_SET: value = 1; break;
6411 diff -ruN u-boot-2014.01-rc1/common/image-fdt.c u-boot-sunxi/common/image-fdt.c
6412 --- u-boot-2014.01-rc1/common/image-fdt.c 2013-11-25 22:49:32.000000000 +0100
6413 +++ u-boot-sunxi/common/image-fdt.c 2014-03-05 23:14:47.968089294 +0100
6418 -__weak int arch_fixup_memory_node(void *blob)
6419 +__weak int arch_fixup_fdt(void *blob)
6423 @@ -462,7 +462,10 @@
6424 puts(" - must RESET the board to recover.\n");
6427 - arch_fixup_memory_node(blob);
6428 + if (arch_fixup_fdt(blob) < 0) {
6429 + puts("ERROR: arch specific fdt fixup failed");
6432 if (IMAAGE_OF_BOARD_SETUP)
6433 ft_board_setup(blob, gd->bd);
6434 fdt_fixup_ethernet(blob);
6435 diff -ruN u-boot-2014.01-rc1/common/memsize.c u-boot-sunxi/common/memsize.c
6436 --- u-boot-2014.01-rc1/common/memsize.c 2013-11-25 22:49:32.000000000 +0100
6437 +++ u-boot-sunxi/common/memsize.c 2014-03-05 23:14:47.968089294 +0100
6439 * the actually available RAM size between addresses `base' and
6442 -long get_ram_size(long *base, long maxsize)
6443 +unsigned long get_ram_size(unsigned long *base, unsigned long maxsize)
6445 - volatile long *addr;
6451 + volatile unsigned long *addr;
6452 + unsigned long save[32];
6453 + unsigned long cnt;
6454 + unsigned long val;
6455 + unsigned long size;
6458 - for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
6459 + for (cnt = (maxsize / sizeof (unsigned long)) >> 1; cnt > 0; cnt >>= 1) {
6460 addr = base + cnt; /* pointer arith! */
6467 - for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
6468 + for (cnt = 1; cnt < maxsize / sizeof(unsigned long); cnt <<= 1) {
6476 - for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
6477 + for (cnt = 1; cnt < maxsize / sizeof (unsigned long); cnt <<= 1) {
6478 addr = base + cnt; /* pointer arith! */
6482 - size = cnt * sizeof (long);
6483 + size = cnt * sizeof (unsigned long);
6484 /* Restore the original data before leaving the function.
6486 - for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
6487 + for (cnt <<= 1; cnt < maxsize / sizeof (unsigned long); cnt <<= 1) {
6491 diff -ruN u-boot-2014.01-rc1/common/spl/spl_mmc.c u-boot-sunxi/common/spl/spl_mmc.c
6492 --- u-boot-2014.01-rc1/common/spl/spl_mmc.c 2013-11-25 22:49:32.000000000 +0100
6493 +++ u-boot-sunxi/common/spl/spl_mmc.c 2014-03-05 23:14:47.968089294 +0100
6498 - if (image_get_magic(header) != IH_MAGIC)
6499 + if (image_get_magic(header) != IH_MAGIC) {
6500 + printf("spl: not an uImage at %lu\n", sector);
6504 spl_parse_image_header(header);
6506 diff -ruN u-boot-2014.01-rc1/drivers/gpio/Makefile u-boot-sunxi/drivers/gpio/Makefile
6507 --- u-boot-2014.01-rc1/drivers/gpio/Makefile 2013-11-25 22:49:32.000000000 +0100
6508 +++ u-boot-sunxi/drivers/gpio/Makefile 2014-03-05 23:14:47.996088920 +0100
6510 obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
6511 obj-$(CONFIG_TCA642X) += tca642x.o
6512 oby-$(CONFIG_SX151X) += sx151x.o
6513 +obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
6514 diff -ruN u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio/sunxi_gpio.c
6515 --- u-boot-2014.01-rc1/drivers/gpio/sunxi_gpio.c 1970-01-01 01:00:00.000000000 +0100
6516 +++ u-boot-sunxi/drivers/gpio/sunxi_gpio.c 2014-03-05 23:14:47.996088920 +0100
6519 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
6521 + * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
6523 + * (C) Copyright 2007-2011
6524 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6525 + * Tom Cubie <tangliang@allwinnertech.com>
6527 + * See file CREDITS for list of people who contributed to this
6530 + * This program is free software; you can redistribute it and/or
6531 + * modify it under the terms of the GNU General Public License as
6532 + * published by the Free Software Foundation; either version 2 of
6533 + * the License, or (at your option) any later version.
6535 + * This program is distributed in the hope that it will be useful,
6536 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6537 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6538 + * GNU General Public License for more details.
6540 + * You should have received a copy of the GNU General Public License
6541 + * along with this program; if not, write to the Free Software
6542 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
6543 + * MA 02111-1307 USA
6546 +#include <common.h>
6547 +#include <asm/io.h>
6548 +#include <asm/gpio.h>
6550 +static int sunxi_gpio_output(u32 pin, u32 val)
6553 + u32 bank = GPIO_BANK(pin);
6554 + u32 num = GPIO_NUM(pin);
6555 + struct sunxi_gpio *pio =
6556 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
6558 + dat = readl(&pio->dat);
6560 + dat |= 0x1 << num;
6562 + dat &= ~(0x1 << num);
6564 + writel(dat, &pio->dat);
6569 +static int sunxi_gpio_input(u32 pin)
6572 + u32 bank = GPIO_BANK(pin);
6573 + u32 num = GPIO_NUM(pin);
6574 + struct sunxi_gpio *pio =
6575 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
6577 + dat = readl(&pio->dat);
6583 +int gpio_request(unsigned gpio, const char *label)
6588 +int gpio_free(unsigned gpio)
6593 +int gpio_direction_input(unsigned gpio)
6595 + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
6597 + return sunxi_gpio_input(gpio);
6600 +int gpio_direction_output(unsigned gpio, int value)
6602 + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
6604 + return sunxi_gpio_output(gpio, value);
6607 +int gpio_get_value(unsigned gpio)
6609 + return sunxi_gpio_input(gpio);
6612 +int gpio_set_value(unsigned gpio, int value)
6614 + return sunxi_gpio_output(gpio, value);
6617 +int name_to_gpio(const char *name)
6620 + int groupsize = 9 * 32;
6623 + if (*name == 'P' || *name == 'p')
6625 + if (*name >= 'A') {
6626 + group = *name - (*name > 'a' ? 'a' : 'A');
6631 + pin = simple_strtol(name, &eptr, 10);
6632 + if (!*name || *eptr)
6634 + if (pin < 0 || pin > groupsize || group >= 9)
6636 + return group * 32 + pin;
6638 diff -ruN u-boot-2014.01-rc1/drivers/i2c/Makefile u-boot-sunxi/drivers/i2c/Makefile
6639 --- u-boot-2014.01-rc1/drivers/i2c/Makefile 2013-11-25 22:49:32.000000000 +0100
6640 +++ u-boot-sunxi/drivers/i2c/Makefile 2014-03-05 23:14:48.000088867 +0100
6642 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
6643 obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
6644 obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
6645 +obj-$(CONFIG_SUNXI_I2C) += sunxi_i2c.o
6646 obj-$(CONFIG_SYS_I2C) += i2c_core.o
6647 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
6648 obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
6649 diff -ruN u-boot-2014.01-rc1/drivers/i2c/sunxi_i2c.c u-boot-sunxi/drivers/i2c/sunxi_i2c.c
6650 --- u-boot-2014.01-rc1/drivers/i2c/sunxi_i2c.c 1970-01-01 01:00:00.000000000 +0100
6651 +++ u-boot-sunxi/drivers/i2c/sunxi_i2c.c 2014-03-05 23:14:48.000088867 +0100
6654 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
6656 + * See file CREDITS for list of people who contributed to this
6659 + * This program is free software; you can redistribute it and/or
6660 + * modify it under the terms of the GNU General Public License as
6661 + * published by the Free Software Foundation; either version 2 of
6662 + * the License, or (at your option) any later version.
6664 + * This program is distributed in the hope that it will be useful,
6665 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6666 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6667 + * GNU General Public License for more details.
6669 + * You should have received a copy of the GNU General Public License
6670 + * along with this program; if not, write to the Free Software
6671 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
6672 + * MA 02111-1307 USA
6675 +#include <common.h>
6677 +#include <asm/io.h>
6678 +#include <asm/arch/clock.h>
6679 +#include <asm/arch/cpu.h>
6680 +#include <asm/arch/gpio.h>
6681 +#include <asm/arch/i2c.h>
6683 +static struct i2c __attribute__ ((section(".data"))) *i2c_base =
6684 + (struct i2c *)0x1c2ac00;
6686 +void i2c_init(int speed, int slaveaddr)
6688 + int timeout = 0x2ff;
6690 + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), 2);
6691 + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), 2);
6692 + clock_twi_onoff(0, 1);
6694 + /* Enable the i2c bus */
6695 + writel(TWI_CTL_BUSEN, &i2c_base->ctl);
6697 + /* 400KHz operation M=2, N=1, 24MHz APB clock */
6698 + writel(TWI_CLK_DIV(2, 1), &i2c_base->clkr);
6699 + writel(TWI_SRST_SRST, &i2c_base->reset);
6701 + while ((readl(&i2c_base->reset) & TWI_SRST_SRST) && timeout--);
6704 +int i2c_probe(uchar chip)
6709 +static int i2c_wait_ctl(int mask, int state)
6711 + int timeout = 0x2ff;
6712 + int value = state ? mask : 0;
6714 + debug("i2c_wait_ctl(%x == %x), ctl=%x, status=%x\n", mask, value,
6715 + i2c_base->ctl, i2c_base->status);
6717 + while (((readl(&i2c_base->ctl) & mask) != value) && timeout-- > 0);
6719 + debug("i2c_wait_ctl(), timeout=%d, ctl=%x, status=%x\n", timeout,
6720 + i2c_base->ctl, i2c_base->status);
6728 +static void i2c_clear_irq(void)
6730 + writel(readl(&i2c_base->ctl) & ~TWI_CTL_INTFLG, &i2c_base->ctl);
6733 +static int i2c_wait_irq(void)
6735 + return i2c_wait_ctl(TWI_CTL_INTFLG, 1);
6738 +static int i2c_wait_status(int status)
6740 + int timeout = 0x2ff;
6742 + while (readl(&i2c_base->status) != status && timeout-- > 0);
6750 +static int i2c_wait_irq_status(int status)
6752 + if (i2c_wait_irq() != 0)
6755 + if (readl(&i2c_base->status) != status)
6761 +static int i2c_wait_bus_idle(void)
6763 + int timeout = 0x2ff;
6765 + while (readl(&i2c_base->lctl) != 0x3a && timeout-- > 0);
6773 +static int i2c_stop(void)
6777 + ctl = readl(&i2c_base->ctl) & 0xc0;
6778 + ctl |= TWI_CTL_STP;
6780 + writel(ctl, &i2c_base->ctl);
6782 + /* dummy to delay one I/O operation to make sure it's started */
6783 + (void)readl(&i2c_base->ctl);
6785 + if (i2c_wait_ctl(TWI_CTL_STP, 0) != 0)
6787 + if (i2c_wait_status(TWI_STAT_IDLE))
6789 + if (i2c_wait_bus_idle() != 0)
6795 +static int i2c_send_data(u8 data, u8 status)
6797 + debug("i2c_write(%02x, %x), ctl=%x, status=%x\n", data, status,
6798 + i2c_base->ctl, i2c_base->status);
6800 + writel(data, &i2c_base->data);
6803 + if (i2c_wait_irq_status(status) != 0)
6809 +static int i2c_start(int status)
6813 + debug("i2c_start(%x), ctl=%x, status=%x\n", status, i2c_base->ctl,
6814 + i2c_base->status);
6815 + /* Check that the controller is idle */
6816 + if (status == TWI_STAT_TX_STA &&
6817 + readl(&i2c_base->status) != TWI_STAT_IDLE) {
6821 + writel(0, &i2c_base->efr);
6824 + ctl = readl(&i2c_base->ctl);
6825 + ctl |= TWI_CTL_STA; /* Set start bit */
6826 + ctl &= ~TWI_CTL_INTFLG; /* Clear int flag */
6827 + writel(ctl, &i2c_base->ctl);
6829 + if (i2c_wait_ctl(TWI_CTL_STA, 0) != 0)
6831 + if (i2c_wait_irq_status(status) != 0)
6837 +int i2c_do_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
6842 + if (i2c_start(TWI_STAT_TX_STA) != 0)
6845 + /* Send chip address */
6846 + if (i2c_send_data(chip << 1 | 0, TWI_STAT_TX_AW_ACK) != 0)
6849 + /* Send data address */
6850 + if (i2c_send_data(addr, TWI_STAT_TXD_ACK) != 0)
6853 + /* Send restart for read */
6854 + if (i2c_start(TWI_STAT_TX_RESTA) != 0)
6857 + /* Send chip address */
6858 + if (i2c_send_data(chip << 1 | 1, TWI_STAT_TX_AR_ACK) != 0)
6861 + /* Set ACK mode */
6862 + ctl = readl(&i2c_base->ctl);
6863 + ctl |= TWI_CTL_ACK;
6864 + writel(ctl, &i2c_base->ctl);
6865 + status = TWI_STAT_RXD_ACK;
6870 + /* Set NACK mode (last byte) */
6871 + ctl = readl(&i2c_base->ctl);
6872 + ctl &= ~TWI_CTL_ACK;
6873 + writel(ctl, &i2c_base->ctl);
6874 + status = TWI_STAT_RXD_NAK;
6878 + if (i2c_wait_irq_status(status) != 0)
6881 + *buffer++ = readl(&i2c_base->data);
6888 +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
6890 + int rc = i2c_do_read(chip, addr, alen, buffer, len);
6897 +static int i2c_do_write(uchar chip, uint addr, int alen, uchar *buffer,
6900 + if (i2c_start(TWI_STAT_TX_STA) != 0)
6903 + /* Send chip address */
6904 + if (i2c_send_data(chip << 1 | 0, TWI_STAT_TX_AW_ACK) != 0)
6907 + /* Send data address */
6908 + if (i2c_send_data(addr, TWI_STAT_TXD_ACK) != 0)
6913 + if (i2c_send_data(*buffer++, TWI_STAT_TXD_ACK) != 0)
6921 +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
6923 + int rc = i2c_do_write(chip, addr, alen, buffer, len);
6929 diff -ruN u-boot-2014.01-rc1/drivers/mmc/Makefile u-boot-sunxi/drivers/mmc/Makefile
6930 --- u-boot-2014.01-rc1/drivers/mmc/Makefile 2013-11-25 22:49:32.000000000 +0100
6931 +++ u-boot-sunxi/drivers/mmc/Makefile 2014-03-05 23:14:48.004088813 +0100
6933 obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
6934 obj-$(CONFIG_DWMMC) += dw_mmc.o
6935 obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
6936 +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
6937 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
6938 ifdef CONFIG_SPL_BUILD
6939 obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
6940 diff -ruN u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/sunxi_mmc.c
6941 --- u-boot-2014.01-rc1/drivers/mmc/sunxi_mmc.c 1970-01-01 01:00:00.000000000 +0100
6942 +++ u-boot-sunxi/drivers/mmc/sunxi_mmc.c 2014-03-05 23:14:48.008088759 +0100
6945 + * (C) Copyright 2007-2011
6946 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6947 + * Aaron <leafy.myeh@allwinnertech.com>
6949 + * MMC driver for allwinner sunxi platform.
6951 + * See file CREDITS for list of people who contributed to this
6954 + * This program is free software; you can redistribute it and/or
6955 + * modify it under the terms of the GNU General Public License as
6956 + * published by the Free Software Foundation; either version 2 of
6957 + * the License, or (at your option) any later version.
6959 + * This program is distributed in the hope that it will be useful,
6960 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6961 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6962 + * GNU General Public License for more details.
6964 + * You should have received a copy of the GNU General Public License
6965 + * along with this program; if not, write to the Free Software
6966 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
6967 + * MA 02111-1307 USA
6970 +#include <common.h>
6971 +#include <malloc.h>
6973 +#include <asm/io.h>
6974 +#include <asm/arch/clock.h>
6975 +#include <asm/arch/cpu.h>
6976 +#include <asm/arch/gpio.h>
6977 +#include <asm/arch/mmc.h>
6979 +static void dumphex32(char *name, char *base, int len)
6983 + debug("dump %s registers:", name);
6984 + for (i = 0; i < len; i += 4) {
6986 + debug("\n0x%p : ", base + i);
6987 + debug("0x%08x ", readl(base + i));
6992 +static void dumpmmcreg(struct sunxi_mmc *reg)
6994 + debug("dump mmc registers:\n");
6995 + debug("gctrl 0x%08x\n", reg->gctrl);
6996 + debug("clkcr 0x%08x\n", reg->clkcr);
6997 + debug("timeout 0x%08x\n", reg->timeout);
6998 + debug("width 0x%08x\n", reg->width);
6999 + debug("blksz 0x%08x\n", reg->blksz);
7000 + debug("bytecnt 0x%08x\n", reg->bytecnt);
7001 + debug("cmd 0x%08x\n", reg->cmd);
7002 + debug("arg 0x%08x\n", reg->arg);
7003 + debug("resp0 0x%08x\n", reg->resp0);
7004 + debug("resp1 0x%08x\n", reg->resp1);
7005 + debug("resp2 0x%08x\n", reg->resp2);
7006 + debug("resp3 0x%08x\n", reg->resp3);
7007 + debug("imask 0x%08x\n", reg->imask);
7008 + debug("mint 0x%08x\n", reg->mint);
7009 + debug("rint 0x%08x\n", reg->rint);
7010 + debug("status 0x%08x\n", reg->status);
7011 + debug("ftrglevel 0x%08x\n", reg->ftrglevel);
7012 + debug("funcsel 0x%08x\n", reg->funcsel);
7013 + debug("dmac 0x%08x\n", reg->dmac);
7014 + debug("dlba 0x%08x\n", reg->dlba);
7015 + debug("idst 0x%08x\n", reg->idst);
7016 + debug("idie 0x%08x\n", reg->idie);
7019 +struct sunxi_mmc_des {
7020 + u32 reserved1_1:1;
7021 + u32 dic:1; /* disable interrupt on completion */
7022 + u32 last_des:1; /* 1-this data buffer is the last buffer */
7023 + u32 first_des:1; /* 1-data buffer is the first buffer,
7024 + 0-data buffer contained in the next
7025 + descriptor is 1st buffer */
7026 + u32 des_chain:1; /* 1-the 2nd address in the descriptor is the
7027 + next descriptor address */
7028 + u32 end_of_ring:1; /* 1-last descriptor flag when using dual
7029 + data buffer in descriptor */
7030 + u32 reserved1_2:24;
7031 + u32 card_err_sum:1; /* transfer error flag */
7032 + u32 own:1; /* des owner:1-idma owns it, 0-host owns it */
7033 +#ifdef CONFIG_SUN4I
7034 +#define SDXC_DES_NUM_SHIFT 13
7035 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
7036 + u32 data_buf1_sz:13;
7037 + u32 data_buf2_sz:13;
7038 + u32 reserverd2_1:6;
7039 +#elif defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
7040 +#define SDXC_DES_NUM_SHIFT 16
7041 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
7042 + u32 data_buf1_sz:16;
7043 + u32 data_buf2_sz:16;
7045 +#error ">>>> Wrong Platform for MMC <<<<"
7047 + u32 buf_addr_ptr1;
7048 + u32 buf_addr_ptr2;
7051 +struct sunxi_mmc_host {
7053 + uint32_t *mclkreg;
7054 + unsigned database;
7055 + unsigned fatal_err;
7057 + struct sunxi_mmc *reg;
7060 +/* support 4 mmc hosts */
7061 +struct mmc mmc_dev[4];
7062 +struct sunxi_mmc_host mmc_host[4];
7064 +static int mmc_resource_init(int sdc_no)
7066 + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
7067 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
7069 + debug("init mmc %d resource\n", sdc_no);
7073 + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
7074 + mmchost->mclkreg = &ccm->sd0_clk_cfg;
7077 + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
7078 + mmchost->mclkreg = &ccm->sd1_clk_cfg;
7081 + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
7082 + mmchost->mclkreg = &ccm->sd2_clk_cfg;
7085 + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
7086 + mmchost->mclkreg = &ccm->sd3_clk_cfg;
7089 + printf("Wrong mmc number %d\n", sdc_no);
7092 + mmchost->database = (unsigned int)mmchost->reg + 0x100;
7093 + mmchost->mmc_no = sdc_no;
7098 +static int mmc_clk_io_on(int sdc_no)
7100 + unsigned int rval;
7101 + unsigned int pll5_clk;
7102 + unsigned int divider;
7103 + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
7104 + static struct sunxi_gpio *gpio_c =
7105 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_C];
7106 + static struct sunxi_gpio *gpio_f =
7107 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_F];
7109 + static struct sunxi_gpio *gpio_g =
7110 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_G];
7112 + static struct sunxi_gpio *gpio_h =
7113 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_H];
7114 + static struct sunxi_gpio *gpio_i =
7115 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_I];
7116 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
7118 + debug("init mmc %d clock and io\n", sdc_no);
7123 + /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
7124 + writel(0x222222, &gpio_f->cfg[0]);
7125 + writel(0x555, &gpio_f->pull[0]);
7126 + writel(0xaaa, &gpio_f->drv[0]);
7131 + /* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
7132 + writel(0x444444, &gpio_g->cfg[0]);
7133 + writel(0x555, &gpio_g->pull[0]);
7134 + writel(0xaaa, &gpio_g->drv[0]);
7136 + /* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
7137 + writel(0x55 << 24, &gpio_h->cfg[2]);
7138 + writel(0x5555, &gpio_h->cfg[3]);
7139 + writel(0x555 << 12, &gpio_h->pull[1]);
7140 + writel(0xaaa << 12, &gpio_h->drv[1]);
7145 + /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
7146 + writel(0x33 << 24, &gpio_c->cfg[0]);
7147 + writel(0x3333, &gpio_c->cfg[1]);
7148 + writel(0x555 << 12, &gpio_c->pull[0]);
7149 + writel(0xaaa << 12, &gpio_c->drv[0]);
7153 + /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
7154 + writel(0x2222 << 16, &gpio_i->cfg[0]);
7155 + writel(0x22, &gpio_i->cfg[1]);
7156 + writel(0x555 << 8, &gpio_i->pull[0]);
7157 + writel(0x555 << 8, &gpio_i->drv[0]);
7164 + /* config ahb clock */
7165 + rval = readl(&ccm->ahb_gate0);
7166 + rval |= (1 << (8 + sdc_no));
7167 + writel(rval, &ccm->ahb_gate0);
7169 + /* config mod clock */
7170 + pll5_clk = clock_get_pll5();
7171 + if (pll5_clk > 400000000)
7175 + writel((0x1 << 31) | (0x2 << 24) | divider, mmchost->mclkreg);
7176 + mmchost->mod_clk = pll5_clk / (divider + 1);
7178 + dumphex32("ccmu", (char *)SUNXI_CCM_BASE, 0x100);
7179 + dumphex32("gpio", (char *)SUNXI_PIO_BASE, 0x100);
7180 + dumphex32("mmc", (char *)mmchost->reg, 0x100);
7181 + dumpmmcreg(mmchost->reg);
7186 +static int mmc_update_clk(struct mmc *mmc)
7188 + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
7190 + unsigned timeout = 0xfffff;
7192 + cmd = (0x1 << 31) | (0x1 << 21) | (0x1 << 13);
7193 + writel(cmd, &mmchost->reg->cmd);
7194 + while ((readl(&mmchost->reg->cmd) & (0x1 << 31)) && timeout--);
7198 + writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
7203 +static int mmc_config_clock(struct mmc *mmc, unsigned div)
7205 + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
7206 + unsigned rval = readl(&mmchost->reg->clkcr);
7209 + * CLKCREG[7:0]: divider
7210 + * CLKCREG[16]: on/off
7211 + * CLKCREG[17]: power save
7213 + /* Disable Clock */
7214 + rval &= ~(0x1 << 16);
7215 + writel(rval, &mmchost->reg->clkcr);
7216 + if (mmc_update_clk(mmc))
7219 + /* Change Divider Factor */
7222 + writel(rval, &mmchost->reg->clkcr);
7223 + if (mmc_update_clk(mmc))
7225 + /* Re-enable Clock */
7226 + rval |= (0x1 << 16);
7227 + writel(rval, &mmchost->reg->clkcr);
7229 + if (mmc_update_clk(mmc))
7235 +static void mmc_set_ios(struct mmc *mmc)
7237 + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
7238 + unsigned int clkdiv = 0;
7240 + debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
7241 + mmc->bus_width, mmc->clock, mmchost->mod_clk);
7243 + /* Change clock first */
7244 + clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
7246 + if (mmc_config_clock(mmc, clkdiv)) {
7247 + mmchost->fatal_err = 1;
7251 + /* Change bus width */
7252 + if (mmc->bus_width == 8)
7253 + writel(0x2, &mmchost->reg->width);
7254 + else if (mmc->bus_width == 4)
7255 + writel(0x1, &mmchost->reg->width);
7257 + writel(0x0, &mmchost->reg->width);
7260 +static int mmc_core_init(struct mmc *mmc)
7262 + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
7264 + /* Reset controller */
7265 + writel(0x7, &mmchost->reg->gctrl);
7270 +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
7272 + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
7274 + unsigned byte_cnt = data->blocksize * data->blocks;
7276 + unsigned timeout = 0xfffff;
7278 + if (data->flags & MMC_DATA_READ) {
7279 + buff = (unsigned int *)data->dest;
7280 + for (i = 0; i < (byte_cnt >> 2); i++) {
7281 + while (--timeout &&
7282 + (readl(&mmchost->reg->status) & (0x1 << 2)));
7285 + buff[i] = readl(mmchost->database);
7286 + timeout = 0xfffff;
7289 + buff = (unsigned int *)data->src;
7290 + for (i = 0; i < (byte_cnt >> 2); i++) {
7291 + while (--timeout &&
7292 + (readl(&mmchost->reg->status) & (0x1 << 3)));
7295 + writel(buff[i], mmchost->database);
7296 + timeout = 0xfffff;
7307 +static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
7309 + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
7310 + unsigned byte_cnt = data->blocksize * data->blocks;
7311 + unsigned char *buff;
7312 + unsigned des_idx = 0;
7313 + unsigned buff_frag_num =
7314 + (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
7317 + ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
7319 + buff = data->flags & MMC_DATA_READ ?
7320 + (unsigned char *)data->dest : (unsigned char *)data->src;
7321 + remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
7323 + remain = SDXC_DES_BUFFER_MAX_LEN;
7325 + flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
7326 + for (i = 0; i < buff_frag_num; i++, des_idx++) {
7327 + memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
7328 + pdes[des_idx].des_chain = 1;
7329 + pdes[des_idx].own = 1;
7330 + pdes[des_idx].dic = 1;
7331 + if (buff_frag_num > 1 && i != buff_frag_num - 1)
7332 + pdes[des_idx].data_buf1_sz =
7333 + (SDXC_DES_BUFFER_MAX_LEN -
7334 + 1) & SDXC_DES_BUFFER_MAX_LEN;
7336 + pdes[des_idx].data_buf1_sz = remain;
7338 + pdes[des_idx].buf_addr_ptr1 =
7339 + (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
7341 + pdes[des_idx].first_des = 1;
7343 + if (i == buff_frag_num - 1) {
7344 + pdes[des_idx].dic = 0;
7345 + pdes[des_idx].last_des = 1;
7346 + pdes[des_idx].end_of_ring = 1;
7347 + pdes[des_idx].buf_addr_ptr2 = 0;
7349 + pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
7351 + debug("frag %d, remain %d, des[%d](%08x): ",
7352 + i, remain, des_idx, (u32)&pdes[des_idx]);
7353 + debug("[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n",
7354 + (u32)((u32 *)&pdes[des_idx])[0],
7355 + (u32)((u32 *)&pdes[des_idx])[1],
7356 + (u32)((u32 *)&pdes[des_idx])[2],
7357 + (u32)((u32 *)&pdes[des_idx])[3]);
7359 + flush_cache((unsigned long)pdes,
7360 + sizeof(struct sunxi_mmc_des) * (des_idx + 1));
7364 + * GCTRL[2] : DMA reset
7365 + * GCTRL[5] : DMA enable
7368 + * IDMAC[0] : IDMA soft reset
7369 + * IDMAC[1] : IDMA fix burst flag
7370 + * IDMAC[7] : IDMA on
7373 + * IDIE[0] : IDMA transmit interrupt flag
7374 + * IDIE[1] : IDMA receive interrupt flag
7376 + rval = readl(&mmchost->reg->gctrl);
7378 + writel(rval | (0x1 << 5) | (0x1 << 2), &mmchost->reg->gctrl);
7380 + writel((0x1 << 0), &mmchost->reg->dmac);
7382 + writel((0x1 << 1) | (1 << 7), &mmchost->reg->dmac);
7383 + rval = readl(&mmchost->reg->idie) & (~3);
7384 + if (data->flags & MMC_DATA_WRITE)
7385 + rval |= (0x1 << 0);
7387 + rval |= (0x1 << 1);
7388 + writel(rval, &mmchost->reg->idie);
7389 + writel((u32) pdes, &mmchost->reg->dlba);
7390 + writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
7391 + &mmchost->reg->ftrglevel);
7396 +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
7397 + struct mmc_data *data)
7399 + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
7400 + unsigned int cmdval = 0x80000000;
7401 + signed int timeout = 0;
7403 + unsigned int status = 0;
7404 + unsigned int usedma = 0;
7405 + unsigned int bytecnt = 0;
7407 + if (mmchost->fatal_err)
7409 + if (cmd->resp_type & MMC_RSP_BUSY)
7410 + debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
7411 + if (cmd->cmdidx == 12)
7416 + * CMD[5:0] : Command index
7417 + * CMD[6] : Has response
7418 + * CMD[7] : Long response
7419 + * CMD[8] : Check response CRC
7420 + * CMD[9] : Has data
7422 + * CMD[11] : Steam mode
7423 + * CMD[12] : Auto stop
7424 + * CMD[13] : Wait previous over
7425 + * CMD[14] : About cmd
7426 + * CMD[15] : Send initialization
7427 + * CMD[21] : Update clock
7428 + * CMD[31] : Load cmd
7431 + cmdval |= (0x1 << 15);
7432 + if (cmd->resp_type & MMC_RSP_PRESENT)
7433 + cmdval |= (0x1 << 6);
7434 + if (cmd->resp_type & MMC_RSP_136)
7435 + cmdval |= (0x1 << 7);
7436 + if (cmd->resp_type & MMC_RSP_CRC)
7437 + cmdval |= (0x1 << 8);
7440 + if ((u32) data->dest & 0x3) {
7445 + cmdval |= (0x1 << 9) | (0x1 << 13);
7446 + if (data->flags & MMC_DATA_WRITE)
7447 + cmdval |= (0x1 << 10);
7448 + if (data->blocks > 1)
7449 + cmdval |= (0x1 << 12);
7450 + writel(data->blocksize, &mmchost->reg->blksz);
7451 + writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
7454 + debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
7455 + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
7456 + writel(cmd->cmdarg, &mmchost->reg->arg);
7459 + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
7462 + * transfer data and check status
7463 + * STATREG[2] : FIFO empty
7464 + * STATREG[3] : FIFO full
7469 + bytecnt = data->blocksize * data->blocks;
7470 + debug("trans data %d bytes\n", bytecnt);
7471 +#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
7472 + if (bytecnt > 64) {
7477 + writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 31),
7478 + &mmchost->reg->gctrl);
7479 + ret = mmc_trans_data_by_dma(mmc, data);
7480 + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
7482 + writel(readl(&mmchost->reg->gctrl) | 0x1 << 31,
7483 + &mmchost->reg->gctrl);
7484 + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
7485 + ret = mmc_trans_data_by_cpu(mmc, data);
7488 + error = readl(&mmchost->reg->rint) & 0xbfc2;
7494 + timeout = 0xfffff;
7496 + status = readl(&mmchost->reg->rint);
7497 + if (!timeout-- || (status & 0xbfc2)) {
7498 + error = status & 0xbfc2;
7499 + debug("cmd timeout %x\n", error);
7503 + } while (!(status & 0x4));
7506 + unsigned done = 0;
7507 + timeout = usedma ? 0xffff * bytecnt : 0xffff;
7508 + debug("cacl timeout %x\n", timeout);
7510 + status = readl(&mmchost->reg->rint);
7511 + if (!timeout-- || (status & 0xbfc2)) {
7512 + error = status & 0xbfc2;
7513 + debug("data timeout %x\n", error);
7517 + if (data->blocks > 1)
7518 + done = status & (0x1 << 14);
7520 + done = status & (0x1 << 3);
7524 + if (cmd->resp_type & MMC_RSP_BUSY) {
7525 + timeout = 0xfffff;
7527 + status = readl(&mmchost->reg->status);
7529 + debug("busy timeout\n");
7533 + } while (status & (1 << 9));
7536 + if (cmd->resp_type & MMC_RSP_136) {
7537 + cmd->response[0] = readl(&mmchost->reg->resp3);
7538 + cmd->response[1] = readl(&mmchost->reg->resp2);
7539 + cmd->response[2] = readl(&mmchost->reg->resp1);
7540 + cmd->response[3] = readl(&mmchost->reg->resp0);
7541 + debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
7542 + cmd->response[3], cmd->response[2],
7543 + cmd->response[1], cmd->response[0]);
7545 + cmd->response[0] = readl(&mmchost->reg->resp0);
7546 + debug("mmc resp 0x%08x\n", cmd->response[0]);
7549 + if (data && usedma) {
7551 + * IDST[0] : idma tx int
7552 + * IDST[1] : idma rx int
7553 + * IDST[2] : idma fatal bus error
7554 + * IDST[4] : idma descriptor invalid
7555 + * IDST[5] : idma error summary
7556 + * IDST[8] : idma normal interrupt sumary
7557 + * IDST[9] : idma abnormal interrupt sumary
7559 + status = readl(&mmchost->reg->idst);
7560 + writel(status, &mmchost->reg->idst);
7561 + writel(0, &mmchost->reg->idie);
7562 + writel(0, &mmchost->reg->dmac);
7563 + writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 5),
7564 + &mmchost->reg->gctrl);
7567 + writel(0x7, &mmchost->reg->gctrl);
7568 + mmc_update_clk(mmc);
7570 + writel(0xffffffff, &mmchost->reg->rint);
7571 + writel(readl(&mmchost->reg->gctrl) | (1 << 1), &mmchost->reg->gctrl);
7576 +int sunxi_mmc_init(int sdc_no)
7580 + memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc));
7581 + memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
7582 + mmc = &mmc_dev[sdc_no];
7584 + sprintf(mmc->name, "SUNXI SD/MMC");
7585 + mmc->priv = &mmc_host[sdc_no];
7586 + mmc->send_cmd = mmc_send_cmd;
7587 + mmc->set_ios = mmc_set_ios;
7588 + mmc->init = mmc_core_init;
7590 + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
7591 + mmc->host_caps = MMC_MODE_4BIT;
7592 + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
7594 + mmc->f_min = 400000;
7595 + mmc->f_max = 52000000;
7597 + mmc_resource_init(sdc_no);
7598 + mmc_clk_io_on(sdc_no);
7600 + mmc_register(mmc);
7604 diff -ruN u-boot-2014.01-rc1/drivers/net/designware.c u-boot-sunxi/drivers/net/designware.c
7605 --- u-boot-2014.01-rc1/drivers/net/designware.c 2013-11-25 22:49:32.000000000 +0100
7606 +++ u-boot-sunxi/drivers/net/designware.c 2014-03-05 23:14:48.024088546 +0100
7608 /* Resore the HW MAC address as it has been lost during MAC reset */
7609 dw_write_hwaddr(dev);
7611 - writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
7612 + writel(FIXEDBURST | PRIORXTX_41 | BURST_8,
7615 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
7616 diff -ruN u-boot-2014.01-rc1/drivers/net/Makefile u-boot-sunxi/drivers/net/Makefile
7617 --- u-boot-2014.01-rc1/drivers/net/Makefile 2013-11-25 22:49:32.000000000 +0100
7618 +++ u-boot-sunxi/drivers/net/Makefile 2014-03-05 23:14:48.020088600 +0100
7620 obj-$(CONFIG_SH_ETHER) += sh_eth.o
7621 obj-$(CONFIG_SMC91111) += smc91111.o
7622 obj-$(CONFIG_SMC911X) += smc911x.o
7623 -obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
7624 +obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
7625 +obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
7626 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
7627 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
7628 obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
7629 diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_emac.c u-boot-sunxi/drivers/net/sunxi_emac.c
7630 --- u-boot-2014.01-rc1/drivers/net/sunxi_emac.c 1970-01-01 01:00:00.000000000 +0100
7631 +++ u-boot-sunxi/drivers/net/sunxi_emac.c 2014-03-05 23:14:48.056088119 +0100
7634 + * sunxi_emac.c -- Allwinner A10 ethernet driver
7636 + * (C) Copyright 2012, Stefan Roese <sr@denx.de>
7638 + * SPDX-License-Identifier: GPL-2.0+
7641 +#include <common.h>
7642 +#include <linux/err.h>
7643 +#include <malloc.h>
7644 +#include <miiphy.h>
7646 +#include <asm/io.h>
7647 +#include <asm/arch/clock.h>
7648 +#include <asm/arch/gpio.h>
7650 +/* EMAC register */
7652 + u32 ctl; /* 0x00 */
7653 + u32 tx_mode; /* 0x04 */
7654 + u32 tx_flow; /* 0x08 */
7655 + u32 tx_ctl0; /* 0x0c */
7656 + u32 tx_ctl1; /* 0x10 */
7657 + u32 tx_ins; /* 0x14 */
7658 + u32 tx_pl0; /* 0x18 */
7659 + u32 tx_pl1; /* 0x1c */
7660 + u32 tx_sta; /* 0x20 */
7661 + u32 tx_io_data; /* 0x24 */
7662 + u32 tx_io_data1;/* 0x28 */
7663 + u32 tx_tsvl0; /* 0x2c */
7664 + u32 tx_tsvh0; /* 0x30 */
7665 + u32 tx_tsvl1; /* 0x34 */
7666 + u32 tx_tsvh1; /* 0x38 */
7667 + u32 rx_ctl; /* 0x3c */
7668 + u32 rx_hash0; /* 0x40 */
7669 + u32 rx_hash1; /* 0x44 */
7670 + u32 rx_sta; /* 0x48 */
7671 + u32 rx_io_data; /* 0x4c */
7672 + u32 rx_fbc; /* 0x50 */
7673 + u32 int_ctl; /* 0x54 */
7674 + u32 int_sta; /* 0x58 */
7675 + u32 mac_ctl0; /* 0x5c */
7676 + u32 mac_ctl1; /* 0x60 */
7677 + u32 mac_ipgt; /* 0x64 */
7678 + u32 mac_ipgr; /* 0x68 */
7679 + u32 mac_clrt; /* 0x6c */
7680 + u32 mac_maxf; /* 0x70 */
7681 + u32 mac_supp; /* 0x74 */
7682 + u32 mac_test; /* 0x78 */
7683 + u32 mac_mcfg; /* 0x7c */
7684 + u32 mac_mcmd; /* 0x80 */
7685 + u32 mac_madr; /* 0x84 */
7686 + u32 mac_mwtd; /* 0x88 */
7687 + u32 mac_mrdd; /* 0x8c */
7688 + u32 mac_mind; /* 0x90 */
7689 + u32 mac_ssrr; /* 0x94 */
7690 + u32 mac_a0; /* 0x98 */
7691 + u32 mac_a1; /* 0x9c */
7694 +/* SRAMC register */
7695 +struct sunxi_sramc_regs {
7700 +/* 0: Disable 1: Aborted frame enable(default) */
7701 +#define EMAC_TX_AB_M (0x1 << 0)
7702 +/* 0: CPU 1: DMA(default) */
7703 +#define EMAC_TX_TM (0x1 << 1)
7705 +#define EMAC_TX_SETUP (0)
7707 +/* 0: DRQ asserted 1: DRQ automatically(default) */
7708 +#define EMAC_RX_DRQ_MODE (0x1 << 1)
7709 +/* 0: CPU 1: DMA(default) */
7710 +#define EMAC_RX_TM (0x1 << 2)
7711 +/* 0: Normal(default) 1: Pass all Frames */
7712 +#define EMAC_RX_PA (0x1 << 4)
7713 +/* 0: Normal(default) 1: Pass Control Frames */
7714 +#define EMAC_RX_PCF (0x1 << 5)
7715 +/* 0: Normal(default) 1: Pass Frames with CRC Error */
7716 +#define EMAC_RX_PCRCE (0x1 << 6)
7717 +/* 0: Normal(default) 1: Pass Frames with Length Error */
7718 +#define EMAC_RX_PLE (0x1 << 7)
7719 +/* 0: Normal 1: Pass Frames length out of range(default) */
7720 +#define EMAC_RX_POR (0x1 << 8)
7721 +/* 0: Not accept 1: Accept unicast Packets(default) */
7722 +#define EMAC_RX_UCAD (0x1 << 16)
7723 +/* 0: Normal(default) 1: DA Filtering */
7724 +#define EMAC_RX_DAF (0x1 << 17)
7725 +/* 0: Not accept 1: Accept multicast Packets(default) */
7726 +#define EMAC_RX_MCO (0x1 << 20)
7727 +/* 0: Disable(default) 1: Enable Hash filter */
7728 +#define EMAC_RX_MHF (0x1 << 21)
7729 +/* 0: Not accept 1: Accept Broadcast Packets(default) */
7730 +#define EMAC_RX_BCO (0x1 << 22)
7731 +/* 0: Disable(default) 1: Enable SA Filtering */
7732 +#define EMAC_RX_SAF (0x1 << 24)
7733 +/* 0: Normal(default) 1: Inverse Filtering */
7734 +#define EMAC_RX_SAIF (0x1 << 25)
7736 +#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
7737 + EMAC_RX_MCO | EMAC_RX_BCO)
7739 +/* 0: Disable 1: Enable Receive Flow Control(default) */
7740 +#define EMAC_MAC_CTL0_RFC (0x1 << 2)
7741 +/* 0: Disable 1: Enable Transmit Flow Control(default) */
7742 +#define EMAC_MAC_CTL0_TFC (0x1 << 3)
7744 +#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
7746 +/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
7747 +#define EMAC_MAC_CTL1_FLC (0x1 << 1)
7748 +/* 0: Disable(default) 1: Enable Huge Frame */
7749 +#define EMAC_MAC_CTL1_HF (0x1 << 2)
7750 +/* 0: Disable(default) 1: Enable MAC Delayed CRC */
7751 +#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
7752 +/* 0: Disable 1: Enable MAC CRC(default) */
7753 +#define EMAC_MAC_CTL1_CRC (0x1 << 4)
7754 +/* 0: Disable 1: Enable MAC PAD Short frames(default) */
7755 +#define EMAC_MAC_CTL1_PC (0x1 << 5)
7756 +/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
7757 +#define EMAC_MAC_CTL1_VC (0x1 << 6)
7758 +/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
7759 +#define EMAC_MAC_CTL1_ADP (0x1 << 7)
7760 +/* 0: Disable(default) 1: Enable */
7761 +#define EMAC_MAC_CTL1_PRE (0x1 << 8)
7762 +/* 0: Disable(default) 1: Enable */
7763 +#define EMAC_MAC_CTL1_LPE (0x1 << 9)
7764 +/* 0: Disable(default) 1: Enable no back off */
7765 +#define EMAC_MAC_CTL1_NB (0x1 << 12)
7766 +/* 0: Disable(default) 1: Enable */
7767 +#define EMAC_MAC_CTL1_BNB (0x1 << 13)
7768 +/* 0: Disable(default) 1: Enable */
7769 +#define EMAC_MAC_CTL1_ED (0x1 << 14)
7771 +#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
7774 +#define EMAC_MAC_IPGT 0x15
7776 +#define EMAC_MAC_NBTB_IPG1 0xc
7777 +#define EMAC_MAC_NBTB_IPG2 0x12
7779 +#define EMAC_MAC_CW 0x37
7780 +#define EMAC_MAC_RM 0xf
7782 +#define EMAC_MAC_MFL 0x0600
7784 +/* Receive status */
7785 +#define EMAC_CRCERR (0x1 << 4)
7786 +#define EMAC_LENERR (0x3 << 5)
7788 +#define DMA_CPU_TRRESHOLD 2000
7790 +struct emac_eth_dev {
7793 + u32 phy_configured;
7797 +struct emac_rxhdr {
7802 +static void emac_inblk_32bit(void *reg, void *data, int count)
7804 + int cnt = (count + 3) >> 2;
7810 + u32 x = readl(reg);
7816 +static void emac_outblk_32bit(void *reg, void *data, int count)
7818 + int cnt = (count + 3) >> 2;
7821 + const u32 *buf = data;
7824 + writel(*buf++, reg);
7829 +/* Read a word from phyxcer */
7830 +static int emac_phy_read(const char *devname, unsigned char addr,
7831 + unsigned char reg, unsigned short *value)
7833 + struct eth_device *dev = eth_get_dev_by_name(devname);
7834 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7836 + /* issue the phy address and reg */
7837 + writel(addr << 8 | reg, ®s->mac_madr);
7839 + /* pull up the phy io line */
7840 + writel(0x1, ®s->mac_mcmd);
7842 + /* Wait read complete */
7845 + /* push down the phy io line */
7846 + writel(0x0, ®s->mac_mcmd);
7848 + /* and write data */
7849 + *value = readl(®s->mac_mrdd);
7854 +/* Write a word to phyxcer */
7855 +static int emac_phy_write(const char *devname, unsigned char addr,
7856 + unsigned char reg, unsigned short value)
7858 + struct eth_device *dev = eth_get_dev_by_name(devname);
7859 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7861 + /* issue the phy address and reg */
7862 + writel(addr << 8 | reg, ®s->mac_madr);
7864 + /* pull up the phy io line */
7865 + writel(0x1, ®s->mac_mcmd);
7867 + /* Wait write complete */
7870 + /* push down the phy io line */
7871 + writel(0x0, ®s->mac_mcmd);
7873 + /* and write data */
7874 + writel(value, ®s->mac_mwtd);
7879 +static void emac_setup(struct eth_device *dev)
7881 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7887 + writel(EMAC_TX_SETUP, ®s->tx_mode);
7890 + writel(EMAC_RX_SETUP, ®s->rx_ctl);
7893 + /* Set MAC CTL0 */
7894 + writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
7896 + /* Set MAC CTL1 */
7897 + emac_phy_read(dev->name, 1, 0, &phy_val);
7898 + debug("PHY SETUP, reg 0 value: %x\n", phy_val);
7899 + duplex_flag = !!(phy_val & (1 << 8));
7903 + reg_val = (0x1 << 0);
7904 + writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
7907 + writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
7910 + writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
7912 + /* Set up Collison window */
7913 + writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
7915 + /* Set up Max Frame Length */
7916 + writel(EMAC_MAC_MFL, ®s->mac_maxf);
7919 +static void emac_reset(struct eth_device *dev)
7921 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7923 + debug("resetting device\n");
7925 + /* RESET device */
7926 + writel(0, ®s->ctl);
7929 + writel(1, ®s->ctl);
7933 +static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
7935 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7936 + struct emac_eth_dev *priv = dev->priv;
7941 + /* Flush RX FIFO */
7942 + setbits_le32(®s->rx_ctl, 0x8);
7947 + /* Soft reset MAC */
7948 + clrbits_le32(®s->mac_ctl0, 0x1 << 15);
7950 + /* Clear RX counter */
7951 + writel(0x0, ®s->rx_fbc);
7957 + writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 |
7958 + dev->enetaddr[2], ®s->mac_a1);
7959 + writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 |
7960 + dev->enetaddr[5], ®s->mac_a0);
7966 + /* PHY POWER UP */
7967 + emac_phy_read(dev->name, 1, 0, &phy_reg);
7968 + emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
7971 + emac_phy_read(dev->name, 1, 0, &phy_reg);
7973 + priv->speed = miiphy_speed(dev->name, 0);
7974 + priv->duplex = miiphy_duplex(dev->name, 0);
7976 + /* Print link status only once */
7977 + if (!priv->link_printed) {
7978 + printf("ENET Speed is %d Mbps - %s duplex connection\n",
7979 + priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
7980 + priv->link_printed = 1;
7983 + /* Set EMAC SPEED depend on PHY */
7984 + clrsetbits_le32(®s->mac_supp, 1 << 8,
7985 + ((phy_reg & (0x1 << 13)) >> 13) << 8);
7987 + /* Set duplex depend on phy */
7988 + clrsetbits_le32(®s->mac_ctl1, 1 << 0,
7989 + ((phy_reg & (0x1 << 8)) >> 8) << 0);
7991 + /* Enable RX/TX */
7992 + setbits_le32(®s->ctl, 0x7);
7997 +static void sunxi_emac_eth_halt(struct eth_device *dev)
7999 + /* Nothing to do here */
8002 +static int sunxi_emac_eth_recv(struct eth_device *dev)
8004 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
8005 + struct emac_rxhdr rxhdr;
8012 + /* Check packet ready or not */
8014 + /* Race warning: The first packet might arrive with
8015 + * the interrupts disabled, but the second will fix
8017 + rxcount = readl(®s->rx_fbc);
8019 + /* Had one stuck? */
8020 + rxcount = readl(®s->rx_fbc);
8025 + reg_val = readl(®s->rx_io_data);
8026 + if (reg_val != 0x0143414d) {
8028 + clrbits_le32(®s->ctl, 0x1 << 2);
8030 + /* Flush RX FIFO */
8031 + setbits_le32(®s->rx_ctl, 0x1 << 3);
8032 + while (readl(®s->rx_ctl) & (0x1 << 3))
8036 + setbits_le32(®s->ctl, 0x1 << 2);
8041 + /* A packet ready now
8042 + * Get status/length
8046 + emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
8048 + rx_len = rxhdr.rx_len;
8049 + rx_status = rxhdr.rx_status;
8051 + /* Packet Status check */
8052 + if (rx_len < 0x40) {
8054 + debug("RX: Bad Packet (runt)\n");
8057 + /* rx_status is identical to RSR register. */
8058 + if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
8060 + if (rx_status & EMAC_CRCERR)
8061 + printf("crc error\n");
8062 + if (rx_status & EMAC_LENERR)
8063 + printf("length error\n");
8066 + /* Move data from EMAC */
8067 + if (good_packet) {
8068 + if (rx_len > DMA_CPU_TRRESHOLD) {
8069 + printf("Received packet is too big (len=%d)\n", rx_len);
8071 + emac_inblk_32bit((void *)®s->rx_io_data,
8072 + NetRxPackets[0], rx_len);
8074 + /* Pass to upper layer */
8075 + NetReceive(NetRxPackets[0], rx_len);
8083 +static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
8085 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
8087 + /* Select channel 0 */
8088 + writel(0, ®s->tx_ins);
8090 + /* Write packet */
8091 + emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
8094 + writel(len, ®s->tx_pl0);
8096 + /* Start translate from fifo to phy */
8097 + setbits_le32(®s->tx_ctl0, 1);
8102 +int sunxi_emac_initialize(void)
8104 + struct sunxi_ccm_reg *const ccm =
8105 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
8106 + struct sunxi_sramc_regs *sram =
8107 + (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
8108 + struct emac_regs *regs =
8109 + (struct emac_regs *)SUNXI_EMAC_BASE;
8110 + struct eth_device *dev;
8111 + struct emac_eth_dev *priv;
8114 + dev = malloc(sizeof(*dev));
8118 + priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
8124 + memset(dev, 0, sizeof(*dev));
8125 + memset(priv, 0, sizeof(struct emac_eth_dev));
8127 + /* Map SRAM to EMAC */
8128 + setbits_le32(&sram->ctrl1, 0x5 << 2);
8130 + /* Configure pin mux settings for MII Ethernet */
8131 + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
8132 + sunxi_gpio_set_cfgpin(pin, 2);
8134 + /* Set up clock gating */
8135 + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
8137 + /* Set MII clock */
8138 + clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
8140 + dev->iobase = (int)regs;
8142 + dev->init = sunxi_emac_eth_init;
8143 + dev->halt = sunxi_emac_eth_halt;
8144 + dev->send = sunxi_emac_eth_send;
8145 + dev->recv = sunxi_emac_eth_recv;
8146 + strcpy(dev->name, "emac");
8148 + eth_register(dev);
8150 + miiphy_register(dev->name, emac_phy_read, emac_phy_write);
8154 diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_gmac.c u-boot-sunxi/drivers/net/sunxi_gmac.c
8155 --- u-boot-2014.01-rc1/drivers/net/sunxi_gmac.c 1970-01-01 01:00:00.000000000 +0100
8156 +++ u-boot-sunxi/drivers/net/sunxi_gmac.c 2014-03-05 23:14:48.056088119 +0100
8158 +#include <common.h>
8159 +#include <netdev.h>
8160 +#include <miiphy.h>
8161 +#include <asm/gpio.h>
8162 +#include <asm/io.h>
8163 +#include <asm/arch/clock.h>
8164 +#include <asm/arch/gpio.h>
8166 +int sunxi_gmac_initialize(bd_t *bis)
8169 + struct sunxi_ccm_reg *const ccm =
8170 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
8172 + /* Set up clock gating */
8173 + setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
8175 + /* Set MII clock */
8176 +#ifdef CONFIG_RGMII
8177 + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
8178 + CCM_GMAC_CTRL_GPIT_RGMII);
8180 + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
8181 + CCM_GMAC_CTRL_GPIT_MII);
8184 + /* Configure pin mux settings for GMAC */
8185 + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
8186 +#ifdef CONFIG_RGMII
8187 + /* skip unused pins in RGMII mode */
8188 + if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
8191 + sunxi_gpio_set_cfgpin(pin, 5);
8192 + sunxi_gpio_set_drv(pin, 3);
8195 +#ifdef CONFIG_RGMII
8196 + designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_RGMII);
8198 + designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_MII);
8203 diff -ruN u-boot-2014.01-rc1/drivers/net/sunxi_wemac.c u-boot-sunxi/drivers/net/sunxi_wemac.c
8204 --- u-boot-2014.01-rc1/drivers/net/sunxi_wemac.c 2013-11-25 22:49:32.000000000 +0100
8205 +++ u-boot-sunxi/drivers/net/sunxi_wemac.c 1970-01-01 01:00:00.000000000 +0100
8208 - * sunxi_wemac.c -- Allwinner A10 ethernet driver
8210 - * (C) Copyright 2012, Stefan Roese <sr@denx.de>
8212 - * SPDX-License-Identifier: GPL-2.0+
8215 -#include <common.h>
8216 -#include <malloc.h>
8218 -#include <miiphy.h>
8219 -#include <linux/err.h>
8220 -#include <asm/io.h>
8221 -#include <asm/arch/clock.h>
8222 -#include <asm/arch/gpio.h>
8224 -/* EMAC register */
8225 -struct wemac_regs {
8226 - u32 ctl; /* 0x00 */
8227 - u32 tx_mode; /* 0x04 */
8228 - u32 tx_flow; /* 0x08 */
8229 - u32 tx_ctl0; /* 0x0c */
8230 - u32 tx_ctl1; /* 0x10 */
8231 - u32 tx_ins; /* 0x14 */
8232 - u32 tx_pl0; /* 0x18 */
8233 - u32 tx_pl1; /* 0x1c */
8234 - u32 tx_sta; /* 0x20 */
8235 - u32 tx_io_data; /* 0x24 */
8236 - u32 tx_io_data1; /* 0x28 */
8237 - u32 tx_tsvl0; /* 0x2c */
8238 - u32 tx_tsvh0; /* 0x30 */
8239 - u32 tx_tsvl1; /* 0x34 */
8240 - u32 tx_tsvh1; /* 0x38 */
8241 - u32 rx_ctl; /* 0x3c */
8242 - u32 rx_hash0; /* 0x40 */
8243 - u32 rx_hash1; /* 0x44 */
8244 - u32 rx_sta; /* 0x48 */
8245 - u32 rx_io_data; /* 0x4c */
8246 - u32 rx_fbc; /* 0x50 */
8247 - u32 int_ctl; /* 0x54 */
8248 - u32 int_sta; /* 0x58 */
8249 - u32 mac_ctl0; /* 0x5c */
8250 - u32 mac_ctl1; /* 0x60 */
8251 - u32 mac_ipgt; /* 0x64 */
8252 - u32 mac_ipgr; /* 0x68 */
8253 - u32 mac_clrt; /* 0x6c */
8254 - u32 mac_maxf; /* 0x70 */
8255 - u32 mac_supp; /* 0x74 */
8256 - u32 mac_test; /* 0x78 */
8257 - u32 mac_mcfg; /* 0x7c */
8258 - u32 mac_mcmd; /* 0x80 */
8259 - u32 mac_madr; /* 0x84 */
8260 - u32 mac_mwtd; /* 0x88 */
8261 - u32 mac_mrdd; /* 0x8c */
8262 - u32 mac_mind; /* 0x90 */
8263 - u32 mac_ssrr; /* 0x94 */
8264 - u32 mac_a0; /* 0x98 */
8265 - u32 mac_a1; /* 0x9c */
8268 -/* SRAMC register */
8269 -struct sunxi_sramc_regs {
8274 -/* 0: Disable 1: Aborted frame enable(default) */
8275 -#define EMAC_TX_AB_M (0x1 << 0)
8276 -/* 0: CPU 1: DMA(default) */
8277 -#define EMAC_TX_TM (0x1 << 1)
8279 -#define EMAC_TX_SETUP (0)
8281 -/* 0: DRQ asserted 1: DRQ automatically(default) */
8282 -#define EMAC_RX_DRQ_MODE (0x1 << 1)
8283 -/* 0: CPU 1: DMA(default) */
8284 -#define EMAC_RX_TM (0x1 << 2)
8285 -/* 0: Normal(default) 1: Pass all Frames */
8286 -#define EMAC_RX_PA (0x1 << 4)
8287 -/* 0: Normal(default) 1: Pass Control Frames */
8288 -#define EMAC_RX_PCF (0x1 << 5)
8289 -/* 0: Normal(default) 1: Pass Frames with CRC Error */
8290 -#define EMAC_RX_PCRCE (0x1 << 6)
8291 -/* 0: Normal(default) 1: Pass Frames with Length Error */
8292 -#define EMAC_RX_PLE (0x1 << 7)
8293 -/* 0: Normal 1: Pass Frames length out of range(default) */
8294 -#define EMAC_RX_POR (0x1 << 8)
8295 -/* 0: Not accept 1: Accept unicast Packets(default) */
8296 -#define EMAC_RX_UCAD (0x1 << 16)
8297 -/* 0: Normal(default) 1: DA Filtering */
8298 -#define EMAC_RX_DAF (0x1 << 17)
8299 -/* 0: Not accept 1: Accept multicast Packets(default) */
8300 -#define EMAC_RX_MCO (0x1 << 20)
8301 -/* 0: Disable(default) 1: Enable Hash filter */
8302 -#define EMAC_RX_MHF (0x1 << 21)
8303 -/* 0: Not accept 1: Accept Broadcast Packets(default) */
8304 -#define EMAC_RX_BCO (0x1 << 22)
8305 -/* 0: Disable(default) 1: Enable SA Filtering */
8306 -#define EMAC_RX_SAF (0x1 << 24)
8307 -/* 0: Normal(default) 1: Inverse Filtering */
8308 -#define EMAC_RX_SAIF (0x1 << 25)
8310 -#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
8311 - EMAC_RX_MCO | EMAC_RX_BCO)
8313 -/* 0: Disable 1: Enable Receive Flow Control(default) */
8314 -#define EMAC_MAC_CTL0_RFC (0x1 << 2)
8315 -/* 0: Disable 1: Enable Transmit Flow Control(default) */
8316 -#define EMAC_MAC_CTL0_TFC (0x1 << 3)
8318 -#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
8320 -/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
8321 -#define EMAC_MAC_CTL1_FLC (0x1 << 1)
8322 -/* 0: Disable(default) 1: Enable Huge Frame */
8323 -#define EMAC_MAC_CTL1_HF (0x1 << 2)
8324 -/* 0: Disable(default) 1: Enable MAC Delayed CRC */
8325 -#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
8326 -/* 0: Disable 1: Enable MAC CRC(default) */
8327 -#define EMAC_MAC_CTL1_CRC (0x1 << 4)
8328 -/* 0: Disable 1: Enable MAC PAD Short frames(default) */
8329 -#define EMAC_MAC_CTL1_PC (0x1 << 5)
8330 -/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
8331 -#define EMAC_MAC_CTL1_VC (0x1 << 6)
8332 -/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
8333 -#define EMAC_MAC_CTL1_ADP (0x1 << 7)
8334 -/* 0: Disable(default) 1: Enable */
8335 -#define EMAC_MAC_CTL1_PRE (0x1 << 8)
8336 -/* 0: Disable(default) 1: Enable */
8337 -#define EMAC_MAC_CTL1_LPE (0x1 << 9)
8338 -/* 0: Disable(default) 1: Enable no back off */
8339 -#define EMAC_MAC_CTL1_NB (0x1 << 12)
8340 -/* 0: Disable(default) 1: Enable */
8341 -#define EMAC_MAC_CTL1_BNB (0x1 << 13)
8342 -/* 0: Disable(default) 1: Enable */
8343 -#define EMAC_MAC_CTL1_ED (0x1 << 14)
8345 -#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
8348 -#define EMAC_MAC_IPGT 0x15
8350 -#define EMAC_MAC_NBTB_IPG1 0xC
8351 -#define EMAC_MAC_NBTB_IPG2 0x12
8353 -#define EMAC_MAC_CW 0x37
8354 -#define EMAC_MAC_RM 0xF
8356 -#define EMAC_MAC_MFL 0x0600
8358 -/* Receive status */
8359 -#define EMAC_CRCERR (1 << 4)
8360 -#define EMAC_LENERR (3 << 5)
8362 -#define DMA_CPU_TRRESHOLD 2000
8364 -struct wemac_eth_dev {
8367 - u32 phy_configured;
8371 -struct wemac_rxhdr {
8376 -static void wemac_inblk_32bit(void *reg, void *data, int count)
8378 - int cnt = (count + 3) >> 2;
8384 - u32 x = readl(reg);
8390 -static void wemac_outblk_32bit(void *reg, void *data, int count)
8392 - int cnt = (count + 3) >> 2;
8395 - const u32 *buf = data;
8398 - writel(*buf++, reg);
8404 - * Read a word from phyxcer
8406 -static int wemac_phy_read(const char *devname, unsigned char addr,
8407 - unsigned char reg, unsigned short *value)
8409 - struct eth_device *dev = eth_get_dev_by_name(devname);
8410 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
8412 - /* issue the phy address and reg */
8413 - writel(addr << 8 | reg, ®s->mac_madr);
8415 - /* pull up the phy io line */
8416 - writel(0x1, ®s->mac_mcmd);
8418 - /* Wait read complete */
8421 - /* push down the phy io line */
8422 - writel(0x0, ®s->mac_mcmd);
8424 - /* and write data */
8425 - *value = readl(®s->mac_mrdd);
8431 - * Write a word to phyxcer
8433 -static int wemac_phy_write(const char *devname, unsigned char addr,
8434 - unsigned char reg, unsigned short value)
8436 - struct eth_device *dev = eth_get_dev_by_name(devname);
8437 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
8439 - /* issue the phy address and reg */
8440 - writel(addr << 8 | reg, ®s->mac_madr);
8442 - /* pull up the phy io line */
8443 - writel(0x1, ®s->mac_mcmd);
8445 - /* Wait write complete */
8448 - /* push down the phy io line */
8449 - writel(0x0, ®s->mac_mcmd);
8451 - /* and write data */
8452 - writel(value, ®s->mac_mwtd);
8457 -static void emac_setup(struct eth_device *dev)
8459 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
8465 - writel(EMAC_TX_SETUP, ®s->tx_mode);
8468 - writel(EMAC_RX_SETUP, ®s->rx_ctl);
8471 - /* Set MAC CTL0 */
8472 - writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
8474 - /* Set MAC CTL1 */
8475 - wemac_phy_read(dev->name, 1, 0, &phy_val);
8476 - debug("PHY SETUP, reg 0 value: %x\n", phy_val);
8477 - duplex_flag = !!(phy_val & (1 << 8));
8481 - reg_val = (0x1 << 0);
8482 - writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
8485 - writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
8488 - writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
8490 - /* Set up Collison window */
8491 - writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
8493 - /* Set up Max Frame Length */
8494 - writel(EMAC_MAC_MFL, ®s->mac_maxf);
8497 -static void wemac_reset(struct eth_device *dev)
8499 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
8501 - debug("resetting device\n");
8503 - /* RESET device */
8504 - writel(0, ®s->ctl);
8507 - writel(1, ®s->ctl);
8511 -static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
8513 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
8514 - struct wemac_eth_dev *priv = dev->priv;
8519 - /* Flush RX FIFO */
8520 - setbits_le32(®s->rx_ctl, 0x8);
8525 - /* Soft reset MAC */
8526 - clrbits_le32(®s->mac_ctl0, 1 << 15);
8528 - /* Set MII clock */
8529 - clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
8531 - /* Clear RX counter */
8532 - writel(0x0, ®s->rx_fbc);
8538 - writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 |
8539 - dev->enetaddr[2], ®s->mac_a1);
8540 - writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 |
8541 - dev->enetaddr[5], ®s->mac_a0);
8547 - /* PHY POWER UP */
8548 - wemac_phy_read(dev->name, 1, 0, &phy_reg);
8549 - wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11)));
8552 - wemac_phy_read(dev->name, 1, 0, &phy_reg);
8554 - priv->speed = miiphy_speed(dev->name, 0);
8555 - priv->duplex = miiphy_duplex(dev->name, 0);
8557 - /* Print link status only once */
8558 - if (!priv->link_printed) {
8559 - printf("ENET Speed is %d Mbps - %s duplex connection\n",
8560 - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
8561 - priv->link_printed = 1;
8564 - /* Set EMAC SPEED depend on PHY */
8565 - clrsetbits_le32(®s->mac_supp, 1 << 8,
8566 - ((phy_reg & (1 << 13)) >> 13) << 8);
8568 - /* Set duplex depend on phy */
8569 - clrsetbits_le32(®s->mac_ctl1, 1 << 0,
8570 - ((phy_reg & (1 << 8)) >> 8) << 0);
8572 - /* Enable RX/TX */
8573 - setbits_le32(®s->ctl, 0x7);
8578 -static void sunxi_wemac_eth_halt(struct eth_device *dev)
8580 - /* Nothing to do here */
8583 -static int sunxi_wemac_eth_recv(struct eth_device *dev)
8585 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
8586 - struct wemac_rxhdr rxhdr;
8593 - /* Check packet ready or not */
8596 - * Race warning: The first packet might arrive with
8597 - * the interrupts disabled, but the second will fix
8599 - rxcount = readl(®s->rx_fbc);
8601 - /* Had one stuck? */
8602 - rxcount = readl(®s->rx_fbc);
8607 - reg_val = readl(®s->rx_io_data);
8608 - if (reg_val != 0x0143414d) {
8610 - clrbits_le32(®s->ctl, 1 << 2);
8612 - /* Flush RX FIFO */
8613 - setbits_le32(®s->rx_ctl, 1 << 3);
8614 - while (readl(®s->rx_ctl) & (1 << 3))
8618 - setbits_le32(®s->ctl, 1 << 2);
8624 - * A packet ready now
8625 - * Get status/length
8629 - wemac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
8631 - rx_len = rxhdr.rx_len;
8632 - rx_status = rxhdr.rx_status;
8634 - /* Packet Status check */
8635 - if (rx_len < 0x40) {
8637 - debug("RX: Bad Packet (runt)\n");
8640 - /* rx_status is identical to RSR register. */
8641 - if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
8643 - if (rx_status & EMAC_CRCERR)
8644 - printf("crc error\n");
8645 - if (rx_status & EMAC_LENERR)
8646 - printf("length error\n");
8649 - /* Move data from WEMAC */
8650 - if (good_packet) {
8651 - if (rx_len > DMA_CPU_TRRESHOLD) {
8652 - printf("Received packet is too big (len=%d)\n", rx_len);
8654 - wemac_inblk_32bit((void *)®s->rx_io_data,
8655 - NetRxPackets[0], rx_len);
8657 - /* Pass to upper layer */
8658 - NetReceive(NetRxPackets[0], rx_len);
8666 -static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
8668 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
8670 - /* Select channel 0 */
8671 - writel(0, ®s->tx_ins);
8673 - /* Write packet */
8674 - wemac_outblk_32bit((void *)®s->tx_io_data, packet, len);
8677 - writel(len, ®s->tx_pl0);
8679 - /* Start translate from fifo to phy */
8680 - setbits_le32(®s->tx_ctl0, 1);
8685 -int sunxi_wemac_initialize(void)
8687 - struct sunxi_ccm_reg *const ccm =
8688 - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
8689 - struct sunxi_sramc_regs *sram =
8690 - (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
8691 - struct eth_device *dev;
8692 - struct wemac_eth_dev *priv;
8695 - dev = malloc(sizeof(*dev));
8699 - priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev));
8705 - memset(dev, 0, sizeof(*dev));
8706 - memset(priv, 0, sizeof(struct wemac_eth_dev));
8708 - /* Map SRAM to EMAC */
8709 - setbits_le32(&sram->ctrl1, 0x5 << 2);
8711 - /* Configure pin mux settings for MII Ethernet */
8712 - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
8713 - sunxi_gpio_set_cfgpin(pin, 2);
8715 - /* Set up clock gating */
8716 - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC);
8718 - dev->iobase = SUNXI_EMAC_BASE;
8720 - dev->init = sunxi_wemac_eth_init;
8721 - dev->halt = sunxi_wemac_eth_halt;
8722 - dev->send = sunxi_wemac_eth_send;
8723 - dev->recv = sunxi_wemac_eth_recv;
8724 - strcpy(dev->name, "wemac");
8726 - eth_register(dev);
8728 - miiphy_register(dev->name, wemac_phy_read, wemac_phy_write);
8732 diff -ruN u-boot-2014.01-rc1/drivers/power/axp152.c u-boot-sunxi/drivers/power/axp152.c
8733 --- u-boot-2014.01-rc1/drivers/power/axp152.c 1970-01-01 01:00:00.000000000 +0100
8734 +++ u-boot-sunxi/drivers/power/axp152.c 2014-03-05 23:14:48.060088066 +0100
8737 + * (C) Copyright 2012
8738 + * Henrik Nordstrom <henrik@henriknordstrom.net>
8740 + * See file CREDITS for list of people who contributed to this
8743 + * This program is free software; you can redistribute it and/or
8744 + * modify it under the terms of the GNU General Public License as
8745 + * published by the Free Software Foundation; either version 2 of
8746 + * the License, or (at your option) any later version.
8748 + * This program is distributed in the hope that it will be useful,
8749 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8750 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8751 + * GNU General Public License for more details.
8753 + * You should have received a copy of the GNU General Public License
8754 + * along with this program; if not, write to the Free Software
8755 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
8756 + * MA 02111-1307 USA
8758 +#include <common.h>
8760 +#include <axp152.h>
8763 + AXP152_CHIP_VERSION = 0x3,
8764 + AXP152_DCDC2_VOLTAGE = 0x23,
8765 + AXP152_DCDC3_VOLTAGE = 0x27,
8766 + AXP152_DCDC4_VOLTAGE = 0x2B,
8767 + AXP152_LDO2_VOLTAGE = 0x2A,
8768 + AXP152_SHUTDOWN = 0x32,
8771 +int axp152_write(enum axp152_reg reg, u8 val)
8773 + return i2c_write(0x30, reg, 1, &val, 1);
8776 +int axp152_read(enum axp152_reg reg, u8 *val)
8778 + return i2c_read(0x30, reg, 1, val, 1);
8781 +int axp152_set_dcdc2(int mvolt)
8783 + int target = (mvolt - 700) / 25;
8789 + if (target > (1<<6)-1)
8790 + target = (1<<6)-1;
8791 + /* Do we really need to be this gentle? It has built-in voltage slope */
8792 + while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, ¤t)) == 0 &&
8793 + current != target) {
8794 + if (current < target)
8798 + rc = axp152_write(AXP152_DCDC2_VOLTAGE, current);
8805 +int axp152_set_dcdc3(int mvolt)
8807 + int target = (mvolt - 700) / 50;
8813 + if (target > (1<<6)-1)
8814 + target = (1<<6)-1;
8815 + rc = axp152_write(AXP152_DCDC3_VOLTAGE, target);
8816 + rc |= axp152_read(AXP152_DCDC3_VOLTAGE, ®);
8820 +int axp152_set_dcdc4(int mvolt)
8822 + int target = (mvolt - 700) / 25;
8828 + if (target > (1<<7)-1)
8829 + target = (1<<7)-1;
8830 + rc = axp152_write(AXP152_DCDC4_VOLTAGE, target);
8831 + rc |= axp152_read(AXP152_DCDC4_VOLTAGE, ®);
8835 +int axp152_set_ldo2(int mvolt)
8837 + int target = (mvolt - 700) / 100;
8845 + rc = axp152_write(AXP152_LDO2_VOLTAGE, target);
8846 + rc |= axp152_read(AXP152_LDO2_VOLTAGE, ®);
8850 +void axp152_poweroff(void)
8854 + if (axp152_read(AXP152_SHUTDOWN, &val) != 0)
8857 + if (axp152_write(AXP152_SHUTDOWN, val) != 0)
8859 + udelay(10000); /* wait for power to drain */
8862 +int axp152_init(void)
8867 + rc = axp152_read(AXP152_CHIP_VERSION, &ver);
8874 diff -ruN u-boot-2014.01-rc1/drivers/power/axp209.c u-boot-sunxi/drivers/power/axp209.c
8875 --- u-boot-2014.01-rc1/drivers/power/axp209.c 1970-01-01 01:00:00.000000000 +0100
8876 +++ u-boot-sunxi/drivers/power/axp209.c 2014-03-05 23:14:48.060088066 +0100
8879 + * (C) Copyright 2012
8880 + * Henrik Nordstrom <henrik@henriknordstrom.net>
8882 + * See file CREDITS for list of people who contributed to this
8885 + * This program is free software; you can redistribute it and/or
8886 + * modify it under the terms of the GNU General Public License as
8887 + * published by the Free Software Foundation; either version 2 of
8888 + * the License, or (at your option) any later version.
8890 + * This program is distributed in the hope that it will be useful,
8891 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8892 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8893 + * GNU General Public License for more details.
8895 + * You should have received a copy of the GNU General Public License
8896 + * along with this program; if not, write to the Free Software
8897 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
8898 + * MA 02111-1307 USA
8901 +#include <common.h>
8903 +#include <axp209.h>
8906 + AXP209_POWER_STATUS = 0x00,
8907 + AXP209_CHIP_VERSION = 0x03,
8908 + AXP209_DCDC2_VOLTAGE = 0x23,
8909 + AXP209_DCDC3_VOLTAGE = 0x27,
8910 + AXP209_LDO24_VOLTAGE = 0x28,
8911 + AXP209_LDO3_VOLTAGE = 0x29,
8912 + AXP209_IRQ_STATUS3 = 0x4a,
8913 + AXP209_IRQ_STATUS5 = 0x4c,
8914 + AXP209_SHUTDOWN = 0x32,
8917 +#define AXP209_POWER_STATUS_ON_BY_DC (1<<0)
8919 +#define AXP209_IRQ3_PEK_SHORT (1<<1)
8920 +#define AXP209_IRQ3_PEK_LONG (1<<0)
8922 +#define AXP209_IRQ5_PEK_UP (1<<6)
8923 +#define AXP209_IRQ5_PEK_DOWN (1<<5)
8925 +int axp209_write(enum axp209_reg reg, u8 val)
8927 + return i2c_write(0x34, reg, 1, &val, 1);
8930 +int axp209_read(enum axp209_reg reg, u8 *val)
8932 + return i2c_read(0x34, reg, 1, val, 1);
8935 +int axp209_set_dcdc2(int mvolt)
8937 + int cfg = (mvolt - 700) / 25;
8943 + if (cfg > (1 << 6) - 1)
8944 + cfg = (1 << 6) - 1;
8946 + /* Do we really need to be this gentle? It has built-in voltage slope */
8947 + while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, ¤t)) == 0 &&
8949 + if (current < cfg)
8954 + rc = axp209_write(AXP209_DCDC2_VOLTAGE, current);
8962 +int axp209_set_dcdc3(int mvolt)
8964 + int cfg = (mvolt - 700) / 25;
8970 + if (cfg > (1 << 7) - 1)
8971 + cfg = (1 << 7) - 1;
8973 + rc = axp209_write(AXP209_DCDC3_VOLTAGE, cfg);
8974 + rc |= axp209_read(AXP209_DCDC3_VOLTAGE, ®);
8979 +int axp209_set_ldo2(int mvolt)
8981 + int cfg = (mvolt - 1800) / 100;
8990 + rc = axp209_read(AXP209_LDO24_VOLTAGE, ®);
8994 + reg = (reg & 0x0f) | (cfg << 4);
8995 + rc = axp209_write(AXP209_LDO24_VOLTAGE, reg);
9002 +int axp209_set_ldo3(int mvolt)
9004 + int cfg = (mvolt - 700) / 25;
9011 + cfg = 0x80; /* detemined by LDO3IN pin */
9013 + return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
9016 +int axp209_set_ldo4(int mvolt)
9018 + int cfg = (mvolt - 1800) / 100;
9020 + static const int vindex[] = {
9021 + 1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500,
9022 + 2700, 2800, 3000, 3100, 3200, 3300
9026 + /* Translate mvolt to register cfg value, requested <= selected */
9027 + for (cfg = 0; mvolt < vindex[cfg] && cfg < 15; cfg++);
9029 + rc = axp209_read(AXP209_LDO24_VOLTAGE, ®);
9033 + /* LDO4 configuration is in lower 4 bits */
9034 + reg = (reg & 0xf0) | (cfg << 0);
9035 + rc = axp209_write(AXP209_LDO24_VOLTAGE, reg);
9042 +void axp209_poweroff(void)
9046 + if (axp209_read(AXP209_SHUTDOWN, &val) != 0)
9051 + if (axp209_write(AXP209_SHUTDOWN, val) != 0)
9054 + udelay(10000); /* wait for power to drain */
9057 +int axp209_init(void)
9062 + rc = axp209_read(AXP209_CHIP_VERSION, &ver);
9066 + /* Low 4 bits is chip version */
9075 +int axp209_poweron_by_dc(void)
9079 + if (axp209_read(AXP209_POWER_STATUS, &v))
9081 + return (v & AXP209_POWER_STATUS_ON_BY_DC);
9084 +int axp209_power_button(void)
9088 + if (axp209_read(AXP209_IRQ_STATUS5, &v))
9090 + axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN);
9091 + return v & AXP209_IRQ5_PEK_DOWN;
9093 diff -ruN u-boot-2014.01-rc1/drivers/power/Makefile u-boot-sunxi/drivers/power/Makefile
9094 --- u-boot-2014.01-rc1/drivers/power/Makefile 2013-11-25 22:49:32.000000000 +0100
9095 +++ u-boot-sunxi/drivers/power/Makefile 2014-03-05 23:14:48.060088066 +0100
9097 # SPDX-License-Identifier: GPL-2.0+
9100 +obj-$(CONFIG_AXP152_POWER) += axp152.o
9101 +obj-$(CONFIG_AXP209_POWER) += axp209.o
9102 obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
9103 obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
9104 obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o
9105 diff -ruN u-boot-2014.01-rc1/drivers/serial/arm_dcc.c u-boot-sunxi/drivers/serial/arm_dcc.c
9106 --- u-boot-2014.01-rc1/drivers/serial/arm_dcc.c 2013-11-25 22:49:32.000000000 +0100
9107 +++ u-boot-sunxi/drivers/serial/arm_dcc.c 2014-03-05 23:14:48.068087958 +0100
9112 -#if defined(CONFIG_CPU_V6)
9113 +#if defined(CONFIG_CPU_V6) || 1
9117 diff -ruN u-boot-2014.01-rc1/.git/config u-boot-sunxi/.git/config
9118 --- u-boot-2014.01-rc1/.git/config 1970-01-01 01:00:00.000000000 +0100
9119 +++ u-boot-sunxi/.git/config 2014-03-05 23:14:46.924103235 +0100
9122 + repositoryformatversion = 0
9125 + logallrefupdates = true
9127 + fetch = +refs/heads/*:refs/remotes/origin/*
9128 + url = https://bitbucket.org/zuperman/u-boot-sunxi.git
9129 +[branch "sunxi-openwrt"]
9131 + merge = refs/heads/sunxi-openwrt
9132 diff -ruN u-boot-2014.01-rc1/.git/description u-boot-sunxi/.git/description
9133 --- u-boot-2014.01-rc1/.git/description 1970-01-01 01:00:00.000000000 +0100
9134 +++ u-boot-sunxi/.git/description 2014-03-05 23:14:20.056462031 +0100
9136 +Unnamed repository; edit this file 'description' to name the repository.
9137 diff -ruN u-boot-2014.01-rc1/.git/HEAD u-boot-sunxi/.git/HEAD
9138 --- u-boot-2014.01-rc1/.git/HEAD 1970-01-01 01:00:00.000000000 +0100
9139 +++ u-boot-sunxi/.git/HEAD 2014-03-05 23:14:46.924103235 +0100
9141 +ref: refs/heads/sunxi-openwrt
9142 diff -ruN u-boot-2014.01-rc1/.git/hooks/applypatch-msg.sample u-boot-sunxi/.git/hooks/applypatch-msg.sample
9143 --- u-boot-2014.01-rc1/.git/hooks/applypatch-msg.sample 1970-01-01 01:00:00.000000000 +0100
9144 +++ u-boot-sunxi/.git/hooks/applypatch-msg.sample 2014-03-05 23:14:20.072461819 +0100
9148 +# An example hook script to check the commit log message taken by
9149 +# applypatch from an e-mail message.
9151 +# The hook should exit with non-zero status after issuing an
9152 +# appropriate message if it wants to stop the commit. The hook is
9153 +# allowed to edit the commit message file.
9155 +# To enable this hook, rename this file to "applypatch-msg".
9158 +test -x "$GIT_DIR/hooks/commit-msg" &&
9159 + exec "$GIT_DIR/hooks/commit-msg" ${1+"$@"}
9161 diff -ruN u-boot-2014.01-rc1/.git/hooks/commit-msg.sample u-boot-sunxi/.git/hooks/commit-msg.sample
9162 --- u-boot-2014.01-rc1/.git/hooks/commit-msg.sample 1970-01-01 01:00:00.000000000 +0100
9163 +++ u-boot-sunxi/.git/hooks/commit-msg.sample 2014-03-05 23:14:20.064461925 +0100
9167 +# An example hook script to check the commit log message.
9168 +# Called by "git commit" with one argument, the name of the file
9169 +# that has the commit message. The hook should exit with non-zero
9170 +# status after issuing an appropriate message if it wants to stop the
9171 +# commit. The hook is allowed to edit the commit message file.
9173 +# To enable this hook, rename this file to "commit-msg".
9175 +# Uncomment the below to add a Signed-off-by line to the message.
9176 +# Doing this in a hook is a bad idea in general, but the prepare-commit-msg
9177 +# hook is more suited to it.
9179 +# SOB=$(git var GIT_AUTHOR_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p')
9180 +# grep -qs "^$SOB" "$1" || echo "$SOB" >> "$1"
9182 +# This example catches duplicate Signed-off-by lines.
9184 +test "" = "$(grep '^Signed-off-by: ' "$1" |
9185 + sort | uniq -c | sed -e '/^[ ]*1[ ]/d')" || {
9186 + echo >&2 Duplicate Signed-off-by lines.
9189 diff -ruN u-boot-2014.01-rc1/.git/hooks/post-update.sample u-boot-sunxi/.git/hooks/post-update.sample
9190 --- u-boot-2014.01-rc1/.git/hooks/post-update.sample 1970-01-01 01:00:00.000000000 +0100
9191 +++ u-boot-sunxi/.git/hooks/post-update.sample 2014-03-05 23:14:20.076461764 +0100
9195 +# An example hook script to prepare a packed repository for use over
9198 +# To enable this hook, rename this file to "post-update".
9200 +exec git update-server-info
9201 diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-applypatch.sample u-boot-sunxi/.git/hooks/pre-applypatch.sample
9202 --- u-boot-2014.01-rc1/.git/hooks/pre-applypatch.sample 1970-01-01 01:00:00.000000000 +0100
9203 +++ u-boot-sunxi/.git/hooks/pre-applypatch.sample 2014-03-05 23:14:20.072461819 +0100
9207 +# An example hook script to verify what is about to be committed
9208 +# by applypatch from an e-mail message.
9210 +# The hook should exit with non-zero status after issuing an
9211 +# appropriate message if it wants to stop the commit.
9213 +# To enable this hook, rename this file to "pre-applypatch".
9216 +test -x "$GIT_DIR/hooks/pre-commit" &&
9217 + exec "$GIT_DIR/hooks/pre-commit" ${1+"$@"}
9219 diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-commit.sample u-boot-sunxi/.git/hooks/pre-commit.sample
9220 --- u-boot-2014.01-rc1/.git/hooks/pre-commit.sample 1970-01-01 01:00:00.000000000 +0100
9221 +++ u-boot-sunxi/.git/hooks/pre-commit.sample 2014-03-05 23:14:20.076461764 +0100
9225 +# An example hook script to verify what is about to be committed.
9226 +# Called by "git commit" with no arguments. The hook should
9227 +# exit with non-zero status after issuing an appropriate message if
9228 +# it wants to stop the commit.
9230 +# To enable this hook, rename this file to "pre-commit".
9232 +if git rev-parse --verify HEAD >/dev/null 2>&1
9236 + # Initial commit: diff against an empty tree object
9237 + against=4b825dc642cb6eb9a060e54bf8d69288fbee4904
9240 +# If you want to allow non-ascii filenames set this variable to true.
9241 +allownonascii=$(git config hooks.allownonascii)
9243 +# Redirect output to stderr.
9246 +# Cross platform projects tend to avoid non-ascii filenames; prevent
9247 +# them from being added to the repository. We exploit the fact that the
9248 +# printable range starts at the space character and ends with tilde.
9249 +if [ "$allownonascii" != "true" ] &&
9250 + # Note that the use of brackets around a tr range is ok here, (it's
9251 + # even required, for portability to Solaris 10's /usr/bin/tr), since
9252 + # the square bracket bytes happen to fall in the designated range.
9253 + test $(git diff --cached --name-only --diff-filter=A -z $against |
9254 + LC_ALL=C tr -d '[ -~]\0' | wc -c) != 0
9256 + echo "Error: Attempt to add a non-ascii file name."
9258 + echo "This can cause problems if you want to work"
9259 + echo "with people on other platforms."
9261 + echo "To be portable it is advisable to rename the file ..."
9263 + echo "If you know what you are doing you can disable this"
9264 + echo "check using:"
9266 + echo " git config hooks.allownonascii true"
9271 +# If there are whitespace errors, print the offending file names and fail.
9272 +exec git diff-index --check --cached $against --
9273 diff -ruN u-boot-2014.01-rc1/.git/hooks/prepare-commit-msg.sample u-boot-sunxi/.git/hooks/prepare-commit-msg.sample
9274 --- u-boot-2014.01-rc1/.git/hooks/prepare-commit-msg.sample 1970-01-01 01:00:00.000000000 +0100
9275 +++ u-boot-sunxi/.git/hooks/prepare-commit-msg.sample 2014-03-05 23:14:20.076461764 +0100
9279 +# An example hook script to prepare the commit log message.
9280 +# Called by "git commit" with the name of the file that has the
9281 +# commit message, followed by the description of the commit
9282 +# message's source. The hook's purpose is to edit the commit
9283 +# message file. If the hook fails with a non-zero status,
9284 +# the commit is aborted.
9286 +# To enable this hook, rename this file to "prepare-commit-msg".
9288 +# This hook includes three examples. The first comments out the
9289 +# "Conflicts:" part of a merge commit.
9291 +# The second includes the output of "git diff --name-status -r"
9292 +# into the message, just before the "git status" output. It is
9293 +# commented because it doesn't cope with --amend or with squashed
9296 +# The third example adds a Signed-off-by line to the message, that can
9297 +# still be edited. This is rarely a good idea.
9301 + /usr/bin/perl -i.bak -ne 's/^/# /, s/^# #/#/ if /^Conflicts/ .. /#/; print' "$1" ;;
9304 +# /usr/bin/perl -i.bak -pe '
9305 +# print "\n" . `git diff --cached --name-status -r`
9306 +# if /^#/ && $first++ == 0' "$1" ;;
9311 +# SOB=$(git var GIT_AUTHOR_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p')
9312 +# grep -qs "^$SOB" "$1" || echo "$SOB" >> "$1"
9313 diff -ruN u-boot-2014.01-rc1/.git/hooks/pre-rebase.sample u-boot-sunxi/.git/hooks/pre-rebase.sample
9314 --- u-boot-2014.01-rc1/.git/hooks/pre-rebase.sample 1970-01-01 01:00:00.000000000 +0100
9315 +++ u-boot-sunxi/.git/hooks/pre-rebase.sample 2014-03-05 23:14:20.076461764 +0100
9319 +# Copyright (c) 2006, 2008 Junio C Hamano
9321 +# The "pre-rebase" hook is run just before "git rebase" starts doing
9322 +# its job, and can prevent the command from running by exiting with
9325 +# The hook is called with the following parameters:
9327 +# $1 -- the upstream the series was forked from.
9328 +# $2 -- the branch being rebased (or empty when rebasing the current branch).
9330 +# This sample shows how to prevent topic branches that are already
9331 +# merged to 'next' branch from getting rebased, because allowing it
9332 +# would result in rebasing already published history.
9338 + topic="refs/heads/$2"
9340 + topic=`git symbolic-ref HEAD` ||
9341 + exit 0 ;# we do not interrupt rebasing detached HEAD
9348 + exit 0 ;# we do not interrupt others.
9352 +# Now we are dealing with a topic branch being rebased
9353 +# on top of master. Is it OK to rebase it?
9355 +# Does the topic really exist?
9356 +git show-ref -q "$topic" || {
9357 + echo >&2 "No such branch $topic"
9361 +# Is topic fully merged to master?
9362 +not_in_master=`git rev-list --pretty=oneline ^master "$topic"`
9363 +if test -z "$not_in_master"
9365 + echo >&2 "$topic is fully merged to master; better remove it."
9366 + exit 1 ;# we could allow it, but there is no point.
9369 +# Is topic ever merged to next? If so you should not be rebasing it.
9370 +only_next_1=`git rev-list ^master "^$topic" ${publish} | sort`
9371 +only_next_2=`git rev-list ^master ${publish} | sort`
9372 +if test "$only_next_1" = "$only_next_2"
9374 + not_in_topic=`git rev-list "^$topic" master`
9375 + if test -z "$not_in_topic"
9377 + echo >&2 "$topic is already up-to-date with master"
9378 + exit 1 ;# we could allow it, but there is no point.
9383 + not_in_next=`git rev-list --pretty=oneline ^${publish} "$topic"`
9384 + /usr/bin/perl -e '
9385 + my $topic = $ARGV[0];
9386 + my $msg = "* $topic has commits already merged to public branch:\n";
9387 + my (%not_in_next) = map {
9390 + } split(/\n/, $ARGV[1]);
9391 + for my $elem (map {
9392 + /^([0-9a-f]+) (.*)$/;
9394 + } split(/\n/, $ARGV[2])) {
9395 + if (!exists $not_in_next{$elem->[0]}) {
9397 + print STDERR $msg;
9400 + print STDERR " $elem->[1]\n";
9403 + ' "$topic" "$not_in_next" "$not_in_master"
9409 +This sample hook safeguards topic branches that have been
9410 +published from being rewound.
9412 +The workflow assumed here is:
9414 + * Once a topic branch forks from "master", "master" is never
9415 + merged into it again (either directly or indirectly).
9417 + * Once a topic branch is fully cooked and merged into "master",
9418 + it is deleted. If you need to build on top of it to correct
9419 + earlier mistakes, a new topic branch is created by forking at
9420 + the tip of the "master". This is not strictly necessary, but
9421 + it makes it easier to keep your history simple.
9423 + * Whenever you need to test or publish your changes to topic
9424 + branches, merge them into "next" branch.
9426 +The script, being an example, hardcodes the publish branch name
9427 +to be "next", but it is trivial to make it configurable via
9428 +$GIT_DIR/config mechanism.
9430 +With this workflow, you would want to know:
9432 +(1) ... if a topic branch has ever been merged to "next". Young
9433 + topic branches can have stupid mistakes you would rather
9434 + clean up before publishing, and things that have not been
9435 + merged into other branches can be easily rebased without
9436 + affecting other people. But once it is published, you would
9437 + not want to rewind it.
9439 +(2) ... if a topic branch has been fully merged to "master".
9440 + Then you can delete it. More importantly, you should not
9441 + build on top of it -- other people may already want to
9442 + change things related to the topic as patches against your
9443 + "master", so if you need further changes, it is better to
9444 + fork the topic (perhaps with the same name) afresh from the
9447 +Let's look at this example:
9449 + o---o---o---o---o---o---o---o---o---o "next"
9453 + / / c---c---c---c B /
9457 + ---o---o---o---o---o---o---o---o---o---o---o "master"
9460 +A, B and C are topic branches.
9462 + * A has one fix since it was merged up to "next".
9464 + * B has finished. It has been fully merged up to "master" and "next",
9465 + and is ready to be deleted.
9467 + * C has not merged to "next" at all.
9469 +We would want to allow C to be rebased, refuse A, and encourage
9474 + git rev-list ^master ^topic next
9475 + git rev-list ^master next
9477 + if these match, topic has not merged in next at all.
9481 + git rev-list master..topic
9483 + if this is empty, it is fully merged to "master".
9486 diff -ruN u-boot-2014.01-rc1/.git/hooks/update.sample u-boot-sunxi/.git/hooks/update.sample
9487 --- u-boot-2014.01-rc1/.git/hooks/update.sample 1970-01-01 01:00:00.000000000 +0100
9488 +++ u-boot-sunxi/.git/hooks/update.sample 2014-03-05 23:14:20.068461872 +0100
9492 +# An example hook script to blocks unannotated tags from entering.
9493 +# Called by "git receive-pack" with arguments: refname sha1-old sha1-new
9495 +# To enable this hook, rename this file to "update".
9499 +# hooks.allowunannotated
9500 +# This boolean sets whether unannotated tags will be allowed into the
9501 +# repository. By default they won't be.
9502 +# hooks.allowdeletetag
9503 +# This boolean sets whether deleting tags will be allowed in the
9504 +# repository. By default they won't be.
9505 +# hooks.allowmodifytag
9506 +# This boolean sets whether a tag may be modified after creation. By default
9508 +# hooks.allowdeletebranch
9509 +# This boolean sets whether deleting branches will be allowed in the
9510 +# repository. By default they won't be.
9511 +# hooks.denycreatebranch
9512 +# This boolean sets whether remotely creating branches will be denied
9513 +# in the repository. By default this is allowed.
9522 +if [ -z "$GIT_DIR" ]; then
9523 + echo "Don't run this script from the command line." >&2
9524 + echo " (if you want, you could supply GIT_DIR then run" >&2
9525 + echo " $0 <ref> <oldrev> <newrev>)" >&2
9529 +if [ -z "$refname" -o -z "$oldrev" -o -z "$newrev" ]; then
9530 + echo "Usage: $0 <ref> <oldrev> <newrev>" >&2
9535 +allowunannotated=$(git config --bool hooks.allowunannotated)
9536 +allowdeletebranch=$(git config --bool hooks.allowdeletebranch)
9537 +denycreatebranch=$(git config --bool hooks.denycreatebranch)
9538 +allowdeletetag=$(git config --bool hooks.allowdeletetag)
9539 +allowmodifytag=$(git config --bool hooks.allowmodifytag)
9541 +# check for no description
9542 +projectdesc=$(sed -e '1q' "$GIT_DIR/description")
9543 +case "$projectdesc" in
9544 +"Unnamed repository"* | "")
9545 + echo "*** Project description file hasn't been set" >&2
9551 +# if $newrev is 0000...0000, it's a commit to delete a ref.
9552 +zero="0000000000000000000000000000000000000000"
9553 +if [ "$newrev" = "$zero" ]; then
9554 + newrev_type=delete
9556 + newrev_type=$(git cat-file -t $newrev)
9559 +case "$refname","$newrev_type" in
9560 + refs/tags/*,commit)
9561 + # un-annotated tag
9562 + short_refname=${refname##refs/tags/}
9563 + if [ "$allowunannotated" != "true" ]; then
9564 + echo "*** The un-annotated tag, $short_refname, is not allowed in this repository" >&2
9565 + echo "*** Use 'git tag [ -a | -s ]' for tags you want to propagate." >&2
9569 + refs/tags/*,delete)
9571 + if [ "$allowdeletetag" != "true" ]; then
9572 + echo "*** Deleting a tag is not allowed in this repository" >&2
9578 + if [ "$allowmodifytag" != "true" ] && git rev-parse $refname > /dev/null 2>&1
9580 + echo "*** Tag '$refname' already exists." >&2
9581 + echo "*** Modifying a tag is not allowed in this repository." >&2
9585 + refs/heads/*,commit)
9587 + if [ "$oldrev" = "$zero" -a "$denycreatebranch" = "true" ]; then
9588 + echo "*** Creating a branch is not allowed in this repository" >&2
9592 + refs/heads/*,delete)
9594 + if [ "$allowdeletebranch" != "true" ]; then
9595 + echo "*** Deleting a branch is not allowed in this repository" >&2
9599 + refs/remotes/*,commit)
9602 + refs/remotes/*,delete)
9603 + # delete tracking branch
9604 + if [ "$allowdeletebranch" != "true" ]; then
9605 + echo "*** Deleting a tracking branch is not allowed in this repository" >&2
9610 + # Anything else (is there anything else?)
9611 + echo "*** Update hook: unknown type of update to ref $refname of type $newrev_type" >&2
9618 Binary files u-boot-2014.01-rc1/.git/index and u-boot-sunxi/.git/index differ
9619 diff -ruN u-boot-2014.01-rc1/.git/info/exclude u-boot-sunxi/.git/info/exclude
9620 --- u-boot-2014.01-rc1/.git/info/exclude 1970-01-01 01:00:00.000000000 +0100
9621 +++ u-boot-sunxi/.git/info/exclude 2014-03-05 23:14:20.064461925 +0100
9623 +# git ls-files --others --exclude-from=.git/info/exclude
9624 +# Lines that start with '#' are comments.
9625 +# For a project mostly in C, the following would be a good set of
9626 +# exclude patterns (uncomment them if you want to use them):
9629 diff -ruN u-boot-2014.01-rc1/.git/logs/HEAD u-boot-sunxi/.git/logs/HEAD
9630 --- u-boot-2014.01-rc1/.git/logs/HEAD 1970-01-01 01:00:00.000000000 +0100
9631 +++ u-boot-sunxi/.git/logs/HEAD 2014-03-05 23:14:46.924103235 +0100
9633 +0000000000000000000000000000000000000000 d57e8f49a52e59486f49346975c826cf4c298d7e root <root@trabant.deployis.eu> 1394057686 +0100 clone: from https://bitbucket.org/zuperman/u-boot-sunxi.git
9634 diff -ruN u-boot-2014.01-rc1/.git/logs/refs/heads/sunxi-openwrt u-boot-sunxi/.git/logs/refs/heads/sunxi-openwrt
9635 --- u-boot-2014.01-rc1/.git/logs/refs/heads/sunxi-openwrt 1970-01-01 01:00:00.000000000 +0100
9636 +++ u-boot-sunxi/.git/logs/refs/heads/sunxi-openwrt 2014-03-05 23:14:46.924103235 +0100
9638 +0000000000000000000000000000000000000000 d57e8f49a52e59486f49346975c826cf4c298d7e root <root@trabant.deployis.eu> 1394057686 +0100 clone: from https://bitbucket.org/zuperman/u-boot-sunxi.git
9639 diff -ruN u-boot-2014.01-rc1/.git/logs/refs/remotes/origin/HEAD u-boot-sunxi/.git/logs/refs/remotes/origin/HEAD
9640 --- u-boot-2014.01-rc1/.git/logs/refs/remotes/origin/HEAD 1970-01-01 01:00:00.000000000 +0100
9641 +++ u-boot-sunxi/.git/logs/refs/remotes/origin/HEAD 2014-03-05 23:14:46.924103235 +0100
9643 +0000000000000000000000000000000000000000 a13f6664d65ce9bc68f05f8ecd10333ea9bcb012 root <root@trabant.deployis.eu> 1394057686 +0100 clone: from https://bitbucket.org/zuperman/u-boot-sunxi.git
9644 Binary files u-boot-2014.01-rc1/.git/objects/pack/pack-a93dd7b045423458e5011dfb898f9ee89cdb5828.idx and u-boot-sunxi/.git/objects/pack/pack-a93dd7b045423458e5011dfb898f9ee89cdb5828.idx differ
9645 Binary files u-boot-2014.01-rc1/.git/objects/pack/pack-a93dd7b045423458e5011dfb898f9ee89cdb5828.pack and u-boot-sunxi/.git/objects/pack/pack-a93dd7b045423458e5011dfb898f9ee89cdb5828.pack differ
9646 diff -ruN u-boot-2014.01-rc1/.git/packed-refs u-boot-sunxi/.git/packed-refs
9647 --- u-boot-2014.01-rc1/.git/packed-refs 1970-01-01 01:00:00.000000000 +0100
9648 +++ u-boot-sunxi/.git/packed-refs 2014-03-05 23:14:46.760105425 +0100
9650 +# pack-refs with: peeled
9651 +b83a10f893c1b36b878a4dc992a68879f2d98153 refs/remotes/origin/sunxi-3.12
9652 +d57e8f49a52e59486f49346975c826cf4c298d7e refs/remotes/origin/sunxi-openwrt
9653 +a13f6664d65ce9bc68f05f8ecd10333ea9bcb012 refs/remotes/origin/sunxi-test
9654 +adc9e13225d092362dea4e83c03ee161859f3a94 refs/tags/sunxi-openwrt-1
9655 +^d57e8f49a52e59486f49346975c826cf4c298d7e
9656 diff -ruN u-boot-2014.01-rc1/.git/refs/heads/sunxi-openwrt u-boot-sunxi/.git/refs/heads/sunxi-openwrt
9657 --- u-boot-2014.01-rc1/.git/refs/heads/sunxi-openwrt 1970-01-01 01:00:00.000000000 +0100
9658 +++ u-boot-sunxi/.git/refs/heads/sunxi-openwrt 2014-03-05 23:14:46.924103235 +0100
9660 +d57e8f49a52e59486f49346975c826cf4c298d7e
9661 diff -ruN u-boot-2014.01-rc1/.git/refs/remotes/origin/HEAD u-boot-sunxi/.git/refs/remotes/origin/HEAD
9662 --- u-boot-2014.01-rc1/.git/refs/remotes/origin/HEAD 1970-01-01 01:00:00.000000000 +0100
9663 +++ u-boot-sunxi/.git/refs/remotes/origin/HEAD 2014-03-05 23:14:46.852104197 +0100
9665 +ref: refs/remotes/origin/sunxi-test
9666 diff -ruN u-boot-2014.01-rc1/include/axp152.h u-boot-sunxi/include/axp152.h
9667 --- u-boot-2014.01-rc1/include/axp152.h 1970-01-01 01:00:00.000000000 +0100
9668 +++ u-boot-sunxi/include/axp152.h 2014-03-05 23:14:48.156086783 +0100
9671 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
9673 + * See file CREDITS for list of people who contributed to this
9676 + * This program is free software; you can redistribute it and/or
9677 + * modify it under the terms of the GNU General Public License as
9678 + * published by the Free Software Foundation; either version 2 of
9679 + * the License, or (at your option) any later version.
9681 + * This program is distributed in the hope that it will be useful,
9682 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9683 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9684 + * GNU General Public License for more details.
9686 + * You should have received a copy of the GNU General Public License
9687 + * along with this program; if not, write to the Free Software
9688 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9689 + * MA 02111-1307 USA
9691 +int axp152_set_dcdc2(int mvolt);
9692 +int axp152_set_dcdc3(int mvolt);
9693 +int axp152_set_dcdc4(int mvolt);
9694 +int axp152_set_ldo2(int mvolt);
9695 +void axp152_poweroff(void);
9696 +int axp152_init(void);
9697 diff -ruN u-boot-2014.01-rc1/include/axp209.h u-boot-sunxi/include/axp209.h
9698 --- u-boot-2014.01-rc1/include/axp209.h 1970-01-01 01:00:00.000000000 +0100
9699 +++ u-boot-sunxi/include/axp209.h 2014-03-05 23:14:48.156086783 +0100
9702 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
9704 + * See file CREDITS for list of people who contributed to this
9707 + * This program is free software; you can redistribute it and/or
9708 + * modify it under the terms of the GNU General Public License as
9709 + * published by the Free Software Foundation; either version 2 of
9710 + * the License, or (at your option) any later version.
9712 + * This program is distributed in the hope that it will be useful,
9713 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9714 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9715 + * GNU General Public License for more details.
9717 + * You should have received a copy of the GNU General Public License
9718 + * along with this program; if not, write to the Free Software
9719 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9720 + * MA 02111-1307 USA
9723 +extern int axp209_set_dcdc2(int mvolt);
9724 +extern int axp209_set_dcdc3(int mvolt);
9725 +extern int axp209_set_ldo2(int mvolt);
9726 +extern int axp209_set_ldo3(int mvolt);
9727 +extern int axp209_set_ldo4(int mvolt);
9728 +extern void axp209_poweroff(void);
9729 +extern int axp209_init(void);
9730 +extern int axp209_poweron_by_dc(void);
9731 +extern int axp209_power_button(void);
9732 diff -ruN u-boot-2014.01-rc1/include/common.h u-boot-sunxi/include/common.h
9733 --- u-boot-2014.01-rc1/include/common.h 2013-11-25 22:49:32.000000000 +0100
9734 +++ u-boot-sunxi/include/common.h 2014-03-05 23:14:48.160086731 +0100
9736 void api_init (void);
9738 /* common/memsize.c */
9739 -long get_ram_size (long *, long);
9740 +unsigned long get_ram_size (unsigned long *, unsigned long);
9742 /* $(BOARD)/$(BOARD).c */
9743 void reset_phy (void);
9744 diff -ruN u-boot-2014.01-rc1/include/config_fallbacks.h u-boot-sunxi/include/config_fallbacks.h
9745 --- u-boot-2014.01-rc1/include/config_fallbacks.h 2013-11-25 22:49:32.000000000 +0100
9746 +++ u-boot-sunxi/include/config_fallbacks.h 2014-03-05 23:14:48.160086731 +0100
9748 #define HAVE_BLOCK_DEVICE
9751 +#ifndef CONFIG_SYS_BOARD_NAME
9752 +#define CONFIG_SYS_BOARD_NAME CONFIG_SYS_TARGET
9755 #ifndef CONFIG_SYS_PROMPT
9756 #define CONFIG_SYS_PROMPT "=> "
9758 diff -ruN u-boot-2014.01-rc1/include/configs/sun4i.h u-boot-sunxi/include/configs/sun4i.h
9759 --- u-boot-2014.01-rc1/include/configs/sun4i.h 1970-01-01 01:00:00.000000000 +0100
9760 +++ u-boot-sunxi/include/configs/sun4i.h 2014-03-05 23:14:48.236085715 +0100
9763 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9765 + * Configuration settings for the Allwinner A10 (sun4i) CPU
9767 + * See file CREDITS for list of people who contributed to this
9770 + * This program is free software; you can redistribute it and/or
9771 + * modify it under the terms of the GNU General Public License as
9772 + * published by the Free Software Foundation; either version 2 of
9773 + * the License, or (at your option) any later version.
9775 + * This program is distributed in the hope that it will be useful,
9776 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9777 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9778 + * GNU General Public License for more details.
9780 + * You should have received a copy of the GNU General Public License
9781 + * along with this program; if not, write to the Free Software
9782 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9783 + * MA 02111-1307 USA
9790 + * A10 specific configuration
9792 +#define CONFIG_SUN4I /* sun4i SoC generation */
9794 +#define CONFIG_SYS_PROMPT "sun4i# "
9795 +#define CONFIG_MACH_TYPE 4104
9798 + * Include common sunxi configuration where most the settings are
9800 +#include <configs/sunxi-common.h>
9802 +#endif /* __CONFIG_H */
9803 diff -ruN u-boot-2014.01-rc1/include/configs/sun5i.h u-boot-sunxi/include/configs/sun5i.h
9804 --- u-boot-2014.01-rc1/include/configs/sun5i.h 1970-01-01 01:00:00.000000000 +0100
9805 +++ u-boot-sunxi/include/configs/sun5i.h 2014-03-05 23:14:48.236085715 +0100
9808 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9810 + * Configuration settings for the Allwinner A13 (sun5i) CPU
9812 + * See file CREDITS for list of people who contributed to this
9815 + * This program is free software; you can redistribute it and/or
9816 + * modify it under the terms of the GNU General Public License as
9817 + * published by the Free Software Foundation; either version 2 of
9818 + * the License, or (at your option) any later version.
9820 + * This program is distributed in the hope that it will be useful,
9821 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9822 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9823 + * GNU General Public License for more details.
9825 + * You should have received a copy of the GNU General Public License
9826 + * along with this program; if not, write to the Free Software
9827 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9828 + * MA 02111-1307 USA
9835 + * High Level Configuration Options
9837 +#define CONFIG_SUN5I /* sun5i SoC generation */
9839 +#define CONFIG_SYS_PROMPT "sun5i# "
9840 +#define CONFIG_MACH_TYPE 4138
9843 + * Include common sunxi configuration where most the settings are
9845 +#include <configs/sunxi-common.h>
9847 +#endif /* __CONFIG_H */
9848 diff -ruN u-boot-2014.01-rc1/include/configs/sun6i.h u-boot-sunxi/include/configs/sun6i.h
9849 --- u-boot-2014.01-rc1/include/configs/sun6i.h 1970-01-01 01:00:00.000000000 +0100
9850 +++ u-boot-sunxi/include/configs/sun6i.h 2014-03-05 23:14:48.236085715 +0100
9853 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9854 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
9855 + * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
9857 + * Configuration settings for the Allwinner A31 (sun6i) CPU
9859 + * See file CREDITS for list of people who contributed to this
9862 + * This program is free software; you can redistribute it and/or
9863 + * modify it under the terms of the GNU General Public License as
9864 + * published by the Free Software Foundation; either version 2 of
9865 + * the License, or (at your option) any later version.
9867 + * This program is distributed in the hope that it will be useful,
9868 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9869 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9870 + * GNU General Public License for more details.
9872 + * You should have received a copy of the GNU General Public License
9873 + * along with this program; if not, write to the Free Software
9874 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9875 + * MA 02111-1307 USA
9882 + * A31 specific configuration
9884 +#define CONFIG_SUN6I /* sun6i SoC generation */
9886 +#define CONFIG_SYS_PROMPT "sun6i# "
9887 +#define CONFIG_MACH_TYPE 3892
9890 + * Include common sunxi configuration where most the settings are
9892 +#include <configs/sunxi-common.h>
9894 +#endif /* __CONFIG_H */
9895 diff -ruN u-boot-2014.01-rc1/include/configs/sun7i.h u-boot-sunxi/include/configs/sun7i.h
9896 --- u-boot-2014.01-rc1/include/configs/sun7i.h 1970-01-01 01:00:00.000000000 +0100
9897 +++ u-boot-sunxi/include/configs/sun7i.h 2014-03-05 23:14:48.236085715 +0100
9900 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9901 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
9903 + * Configuration settings for the Allwinner A20 (sun7i) CPU
9905 + * See file CREDITS for list of people who contributed to this
9908 + * This program is free software; you can redistribute it and/or
9909 + * modify it under the terms of the GNU General Public License as
9910 + * published by the Free Software Foundation; either version 2 of
9911 + * the License, or (at your option) any later version.
9913 + * This program is distributed in the hope that it will be useful,
9914 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9915 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9916 + * GNU General Public License for more details.
9918 + * You should have received a copy of the GNU General Public License
9919 + * along with this program; if not, write to the Free Software
9920 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9921 + * MA 02111-1307 USA
9928 + * A20 specific configuration
9930 +#define CONFIG_SUN7I /* sun7i SoC generation */
9932 +#define CONFIG_SYS_PROMPT "sun7i# "
9933 +#define CONFIG_MACH_TYPE 4283
9935 +#if defined(CONFIG_SYS_SECONDARY_ON)
9936 +#define CONFIG_BOARD_POSTCLK_INIT 1
9939 +#define CONFIG_ARMV7_VIRT 1
9940 +#define CONFIG_ARMV7_NONSEC 1
9941 +#define CONFIG_ARMV7_PSCI 1
9942 +#define CONFIG_ARMV7_PSCI_NR_CPUS 2
9943 +#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
9944 +#define CONFIG_SYS_CLK_FREQ 24000000
9947 + * Include common sunxi configuration where most the settings are
9949 +#include <configs/sunxi-common.h>
9951 +#endif /* __CONFIG_H */
9952 diff -ruN u-boot-2014.01-rc1/include/configs/sunxi-common.h u-boot-sunxi/include/configs/sunxi-common.h
9953 --- u-boot-2014.01-rc1/include/configs/sunxi-common.h 1970-01-01 01:00:00.000000000 +0100
9954 +++ u-boot-sunxi/include/configs/sunxi-common.h 2014-03-05 23:14:48.236085715 +0100
9957 + * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
9959 + * (C) Copyright 2007-2011
9960 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9961 + * Tom Cubie <tangliang@allwinnertech.com>
9963 + * Configuration settings for the Allwinner sunxi series of boards.
9965 + * See file CREDITS for list of people who contributed to this
9968 + * This program is free software; you can redistribute it and/or
9969 + * modify it under the terms of the GNU General Public License as
9970 + * published by the Free Software Foundation; either version 2 of
9971 + * the License, or (at your option) any later version.
9973 + * This program is distributed in the hope that it will be useful,
9974 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9975 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9976 + * GNU General Public License for more details.
9978 + * You should have received a copy of the GNU General Public License
9979 + * along with this program; if not, write to the Free Software
9980 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9981 + * MA 02111-1307 USA
9984 +#ifndef _SUNXI_COMMON_CONFIG_H
9985 +#define _SUNXI_COMMON_CONFIG_H
9988 + * High Level Configuration Options
9990 +#define CONFIG_ALLWINNER /* It's a Allwinner chip */
9991 +#define CONFIG_SUNXI /* which is sunxi family */
9992 +#ifdef CONFIG_SPL_BUILD
9993 +#ifndef CONFIG_SPL_FEL
9994 +#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
9998 +#include <asm/arch/cpu.h> /* get chip and board defs */
10000 +#define CONFIG_SYS_TEXT_BASE 0x4a000000
10003 + * Display CPU and Board information
10005 +#define CONFIG_DISPLAY_CPUINFO
10006 +#define CONFIG_DISPLAY_BOARDINFO
10008 +/* Serial & console */
10009 +#define CONFIG_SYS_NS16550
10010 +#define CONFIG_SYS_NS16550_SERIAL
10011 +/* ns16550 reg in the low bits of cpu reg */
10012 +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
10013 +#define CONFIG_SYS_NS16550_CLK (24000000)
10014 +#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
10015 +#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
10016 +#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
10017 +#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
10020 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
10021 +#define CONFIG_SYS_INIT_RAM_ADDR 0x0
10022 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
10024 +#define CONFIG_SYS_INIT_SP_OFFSET \
10025 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
10026 +#define CONFIG_SYS_INIT_SP_ADDR \
10027 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
10029 +/* A10 has 1 banks of DRAM, we use only bank 1 in U-Boot */
10030 +#define CONFIG_NR_DRAM_BANKS 1
10031 +#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
10032 +#ifdef CONFIG_SUN7I
10033 +#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
10035 +#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GiB */
10039 +#define CONFIG_NAND
10040 +#define CONFIG_NAND_SUNXI
10041 +#define CONFIG_CMD_NAND /* NAND support */
10042 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
10043 +#define CONFIG_SYS_NAND_BASE 0x00
10046 +#define CONFIG_CMD_MEMORY
10047 +#define CONFIG_CMD_SETEXPR
10049 +#define CONFIG_SETUP_MEMORY_TAGS
10050 +#define CONFIG_CMDLINE_TAG
10051 +#define CONFIG_INITRD_TAG
10052 +#define CONFIG_CMDLINE_EDITING
10055 +/* Can't use MMC slot 0 if the UART is directed there */
10056 +#ifndef CONFIG_SUN6I
10057 +#if !defined CONFIG_UART0_PORT_F || CONFIG_MMC_SUNXI_SLOT != 0
10058 +#define CONFIG_MMC
10059 +#define CONFIG_GENERIC_MMC
10060 +#define CONFIG_CMD_MMC
10061 +#define CONFIG_MMC_SUNXI
10062 +#ifndef CONFIG_MMC_SUNXI_SLOT
10063 +#define CONFIG_MMC_SUNXI_SLOT 0
10065 +#define CONFIG_MMC_SUNXI_USE_DMA
10066 +#define CONFIG_ENV_IS_IN_MMC
10067 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
10072 + * Size of malloc() pool
10073 + * 1MB = 0x100000, 0x100000 = 1024 * 1024
10075 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
10077 +/* Flat Device Tree (FDT/DT) support */
10078 +#define CONFIG_OF_LIBFDT
10079 +#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
10082 + * Miscellaneous configurable options
10084 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
10085 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
10086 +#define CONFIG_CMD_ECHO
10087 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
10088 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
10089 +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
10090 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
10092 +/* Boot Argument Buffer Size */
10093 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
10095 +/* memtest works on */
10096 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
10097 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (256 << 20))
10098 +#define CONFIG_SYS_LOAD_ADDR 0x50000000 /* default load address */
10100 +/* standalone support */
10101 +#define CONFIG_STANDALONE_LOAD_ADDR 0x50000000
10103 +#define CONFIG_SYS_HZ 1000
10105 +/* valid baudrates */
10106 +#define CONFIG_BAUDRATE 115200
10107 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
10109 +/* The stack sizes are set up in start.S using the settings below */
10110 +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
10112 +/* FLASH and environment organization */
10114 +#define CONFIG_SYS_NO_FLASH
10116 +#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */
10117 +#define CONFIG_IDENT_STRING " Allwinner Technology"
10119 +#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
10120 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
10122 +#ifdef CONFIG_SPL_FEL
10123 +#define RUN_BOOT_RAM "run boot_ram;"
10125 +#define RUN_BOOT_RAM ""
10128 +#define CONFIG_BOOTCOMMAND \
10130 + "if run loadbootenv; then " \
10131 + "echo Loaded environment from ${bootenv};" \
10132 + "env import -t ${scriptaddr} ${filesize};" \
10134 + "if test -n \\\"${uenvcmd}\\\"; then " \
10135 + "echo Running uenvcmd ...;" \
10138 + "if run loadbootscr; then "\
10139 + "echo Jumping to ${bootscr};" \
10140 + "source ${scriptaddr};" \
10142 + "run autoboot;" \
10145 +#ifdef CONFIG_CMD_WATCHDOG
10146 +#define RESET_WATCHDOG "watchdog 0"
10148 +#define RESET_WATCHDOG "true"
10151 +#define CONFIG_EXTRA_ENV_SETTINGS \
10152 + "console=ttyS0,115200\0" \
10153 + "panicarg=panic=10\0" \
10156 + "scriptaddr=0x44000000\0" \
10158 + "partition=0:1\0" \
10160 + "if test -z \\\\\"$root\\\\\"; then"\
10161 + " if test \\\\\"$bootpath\\\\\" = \"/boot/\"; then"\
10162 + " root=\"/dev/mmcblk0p1 rootwait\";"\
10164 + " root=\"/dev/mmcblk0p2 rootwait\";"\
10167 + " setenv bootargs console=${console} root=${root}" \
10168 + " loglevel=${loglevel} ${panicarg} ${extraargs}" \
10170 + "kernel=uImage\0" \
10171 + "bootenv=uEnv.txt\0" \
10172 + "bootscr=boot.scr\0" \
10173 + "script=script.bin\0" \
10175 + "fatload $device $partition $scriptaddr ${bootscr}" \
10177 + "ext2load $device $partition $scriptaddr boot/${bootscr}" \
10179 + "ext2load $device $partition $scriptaddr ${bootscr}" \
10182 + "fatload $device $partition $scriptaddr ${bootenv}" \
10184 + "ext2load $device $partition $scriptaddr boot/${bootenv}" \
10186 + "ext2load $device $partition $scriptaddr ${bootenv}" \
10190 + "bootpath=/boot/" \
10192 + "ext2load $device $partition 0x43000000 ${bootpath}${script}" \
10194 + "ext2load $device $partition 0x48000000 ${bootpath}${kernel}" \
10195 + ";then true; elif " \
10198 + "fatload $device $partition 0x43000000 ${script}" \
10200 + "fatload $device $partition 0x48000000 ${kernel}" \
10201 + ";then true; elif " \
10204 + "ext2load $device $partition 0x43000000 ${bootpath}${script}" \
10206 + "ext2load $device $partition 0x48000000 ${bootpath}${kernel}" \
10207 + ";then true; else "\
10212 + "run loadkernel" \
10218 + "bootm 0x48000000" \
10221 + "saved_stdout=$stdout;setenv stdout nc;"\
10222 + "if iminfo 0x41000000; then" \
10223 + " " RESET_WATCHDOG ";"\
10224 + " setenv stdout $saved_stdout;" \
10225 + " source 0x41000000;" \
10227 + " setenv stdout $saved_stdout;" \
10232 +#define CONFIG_BOOTDELAY 3
10233 +#define CONFIG_SYS_BOOT_GET_CMDLINE
10234 +#define CONFIG_AUTO_COMPLETE
10236 +#include <config_cmd_default.h>
10238 +/* Accept zimage + raw ramdisk without mkimage headers */
10239 +#define CONFIG_CMD_BOOTZ
10240 +#define CONFIG_SUPPORT_RAW_INITRD
10242 +#define CONFIG_DOS_PARTITION
10243 +#define CONFIG_CMD_FAT /* with this we can access fat bootfs */
10244 +#define CONFIG_FAT_WRITE /* enable write access */
10245 +#define CONFIG_CMD_EXT2 /* with this we can access ext2 bootfs */
10246 +#define CONFIG_CMD_EXT4 /* with this we can access ext4 bootfs */
10248 +#define CONFIG_SPL_FRAMEWORK
10249 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
10250 +#define CONFIG_SPL_SERIAL_SUPPORT
10251 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
10252 +#define CONFIG_SPL_DISPLAY_PRINT
10254 +/* Falcon boot mode support */
10255 +/* Disabled by default on sun4i/sun7i. Many GCC versions produces a too
10256 + * large SPL for A10/A20 with this on. sun5i however accepts a much larger
10259 +#if defined( CONFIG_SUN5I ) || defined ( CONFIG_SYS_THUMB_BUILD )
10260 +#define CONFIG_SPL_OS_BOOT
10263 +#ifdef CONFIG_SPL_FEL
10265 +#define CONFIG_SPL
10266 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
10267 +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
10268 +#define CONFIG_SPL_TEXT_BASE 0x2000
10269 +#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */
10271 +#else /* CONFIG_SPL */
10273 +#define CONFIG_SPL_BSS_START_ADDR 0x50000000
10274 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */
10276 +#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */
10277 +#ifdef CONFIG_SUN5I
10278 +#define CONFIG_SPL_MAX_SIZE 0x75e0 /* 7748+ is used */
10280 +#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
10283 +#define CONFIG_SPL_LIBDISK_SUPPORT
10284 +#define CONFIG_SPL_MMC_SUPPORT
10286 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
10288 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
10289 +#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
10291 +#endif /* CONFIG_SPL */
10292 +/* end of 32 KiB in sram */
10293 +#define LOW_LEVEL_SRAM_STACK 0x00008000
10294 +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
10296 +#ifdef CONFIG_SPL_OS_BOOT
10297 +#define CONFIG_CMD_SPL
10298 +#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_0 + 0x100)
10299 +#ifdef CONFIG_SPL_MMC_SUPPORT
10300 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 1344
10301 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 256
10302 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 1600
10306 +#undef CONFIG_CMD_FPGA
10307 +#undef CONFIG_CMD_NET
10308 +#undef CONFIG_CMD_NFS
10311 +#define CONFIG_SPL_I2C_SUPPORT
10312 +#define CONFIG_SYS_I2C_SPEED 400000
10313 +#define CONFIG_HARD_I2C
10314 +#define CONFIG_SUNXI_I2C
10315 +#define CONFIG_SYS_I2C_SLAVE 0x7f
10316 +#define CONFIG_CMD_I2C
10320 +#define CONFIG_WATCHDOG /* automatic watchdog support */
10321 +#define CONFIG_CMD_WATCHDOG /* watchdog command setting the watchdog timeout */
10325 +#define CONFIG_SUNXI_GPIO
10326 +#define CONFIG_CMD_GPIO
10329 +#if !defined CONFIG_AXP152_POWER && !defined CONFIG_NO_AXP
10330 +#define CONFIG_AXP209_POWER
10332 +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER
10333 +#define CONFIG_SPL_POWER_SUPPORT
10336 +#ifdef CONFIG_STATUSLED
10337 +#define STATUS_LED_BIT CONFIG_STATUSLED
10339 +#ifdef CONFIG_STATUSLED1
10340 +#define STATUS_LED_BIT1 CONFIG_STATUSLED1
10342 +#ifdef CONFIG_STATUSLED2
10343 +#define STATUS_LED_BIT2 CONFIG_STATUSLED2
10345 +#ifdef CONFIG_STATUSLED3
10346 +#define STATUS_LED_BIT3 CONFIG_STATUSLED3
10349 +#ifndef CONFIG_SPL_BUILD
10350 +#ifdef STATUS_LED_BIT
10351 +#define CONFIG_GPIO_LED
10352 +#define CONFIG_STATUS_LED
10353 +#ifndef STATUS_LED_BOOT
10354 +#define STATUS_LED_BOOT 0
10356 +#ifndef STATUS_LED_STATE
10357 +#define STATUS_LED_STATE STATUS_LED_ON
10358 +#define STATUS_LED_PERIOD 1
10360 +#ifndef STATUS_LED_STATE1
10361 +#define STATUS_LED_STATE1 STATUS_LED_OFF
10362 +#define STATUS_LED_PERIOD1 1
10364 +#ifndef STATUS_LED_STATE2
10365 +#define STATUS_LED_STATE2 STATUS_LED_OFF
10366 +#define STATUS_LED_PERIOD2 1
10368 +#ifndef STATUS_LED_STATE3
10369 +#define STATUS_LED_STATE3 STATUS_LED_OFF
10370 +#define STATUS_LED_PERIOD3 1
10372 +#define CONFIG_BOARD_SPECIFIC_LED
10373 +#define CONFIG_CMD_LED
10377 +/* Define this to have serial channel 1 (UART0) redirected to SD port */
10378 +/* #define CONFIG_UART0_PORT_F */
10380 +#ifndef CONFIG_CONS_INDEX
10381 +#define CONFIG_CONS_INDEX 1 /* UART0 */
10384 +/* Ethernet support */
10385 +#ifdef CONFIG_SUNXI_EMAC
10386 +#define CONFIG_MII /* MII PHY management */
10387 +#define CONFIG_CMD_MII
10388 +#define CONFIG_CMD_NET
10391 +#ifdef CONFIG_SUNXI_GMAC
10392 +#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */
10393 +#define CONFIG_DW_AUTONEG
10394 +#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
10395 +#define CONFIG_SYS_DCACHE_OFF /* dw driver doesn't support dcache */
10396 +#define CONFIG_MII /* MII PHY management */
10397 +#define CONFIG_CMD_MII
10398 +#define CONFIG_CMD_NET
10401 +#ifdef CONFIG_CMD_NET
10402 +#define CONFIG_CMD_PING
10403 +#define CONFIG_CMD_DHCP
10404 +#define CONFIG_CMD_NFS
10405 +#define CONFIG_CMD_SNTP
10406 +#define CONFIG_TIMESTAMP /* Needed by SNTP */
10407 +#define CONFIG_CMD_DNS
10408 +#define CONFIG_NETCONSOLE
10409 +#define CONFIG_BOOTP_SUBNETMASK
10410 +#define CONFIG_BOOTP_GATEWAY
10411 +#define CONFIG_BOOTP_HOSTNAME
10412 +#define CONFIG_BOOTP_NISDOMAIN
10413 +#define CONFIG_BOOTP_BOOTPATH
10414 +#define CONFIG_BOOTP_BOOTFILESIZE
10415 +#define CONFIG_BOOTP_DNS
10416 +#define CONFIG_BOOTP_DNS2
10417 +#define CONFIG_BOOTP_SEND_HOSTNAME
10418 +#define CONFIG_BOOTP_NTPSERVER
10419 +#define CONFIG_BOOTP_TIMEOFFSET
10420 +#define CONFIG_BOOTP_MAY_FAIL
10421 +#define CONFIG_BOOTP_SERVERIP
10422 +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000
10423 +#define CONFIG_CMD_ELF
10426 +#if !defined CONFIG_ENV_IS_IN_MMC && \
10427 + !defined CONFIG_ENV_IS_IN_NAND && \
10428 + !defined CONFIG_ENV_IS_IN_FAT && \
10429 + !defined CONFIG_ENV_IS_IN_SPI_FLASH
10430 +#define CONFIG_ENV_IS_NOWHERE
10433 +#endif /* _SUNXI_COMMON_CONFIG_H */
10434 diff -ruN u-boot-2014.01-rc1/include/netdev.h u-boot-sunxi/include/netdev.h
10435 --- u-boot-2014.01-rc1/include/netdev.h 2013-11-25 22:49:32.000000000 +0100
10436 +++ u-boot-sunxi/include/netdev.h 2014-03-05 23:14:48.264085341 +0100
10438 int skge_initialize(bd_t *bis);
10439 int smc91111_initialize(u8 dev_num, int base_addr);
10440 int smc911x_initialize(u8 dev_num, int base_addr);
10441 -int sunxi_wemac_initialize(bd_t *bis);
10442 +int sunxi_emac_initialize(bd_t *bis);
10443 +int sunxi_gmac_initialize(bd_t *bis);
10444 int tsi108_eth_initialize(bd_t *bis);
10445 int uec_standard_init(bd_t *bis);
10446 int uli526x_initialize(bd_t *bis);
10447 diff -ruN u-boot-2014.01-rc1/Makefile u-boot-sunxi/Makefile
10448 --- u-boot-2014.01-rc1/Makefile 2013-11-25 22:49:32.000000000 +0100
10449 +++ u-boot-sunxi/Makefile 2014-03-05 23:14:46.988102381 +0100
10450 @@ -486,6 +486,16 @@
10451 conv=notrunc 2>/dev/null
10452 cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
10454 +# sunxi: Combined object with SPL U-Boot with sunxi header (sunxi-spl.bin)
10455 +# and the full-blown U-Boot attached to it
10456 +$(obj)u-boot-sunxi-with-spl.bin: $(obj)spl/sunxi-spl.bin $(obj)u-boot.img
10457 + tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \
10458 + of=$(obj)spl/sunxi-spl-pad.bin 2>/dev/null
10459 + dd if=$(obj)spl/sunxi-spl.bin of=$(obj)spl/sunxi-spl-pad.bin \
10460 + conv=notrunc 2>/dev/null
10461 + cat $(obj)spl/sunxi-spl-pad.bin $(obj)u-boot.img > $@
10462 + rm $(obj)spl/sunxi-spl-pad.bin
10464 ifneq ($(CONFIG_TEGRA),)
10465 $(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
10466 $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
10467 @@ -566,6 +576,9 @@
10468 $(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
10469 $(MAKE) -C spl all CONFIG_TPL_BUILD=y
10471 +$(obj)spl/sunxi-spl.bin: $(SUBDIR_TOOLS) depend
10472 + $(MAKE) -C spl all
10474 # Explicitly make _depend in subdirs containing multiple targets to prevent
10475 # parallel sub-makes creating .depend files simultaneously.
10476 depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
10477 @@ -775,6 +788,8 @@
10478 sinclude $(obj).boards.depend
10479 $(obj).boards.depend: boards.cfg
10480 @awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@
10481 + @awk '(NF && $$1 !~ /^#/ && tolower($$7) != $$7) { print tolower($$7) ": " $$7 "_config; $$(MAKE)" }' $< >> $@
10482 + @awk '(NF && $$1 !~ /^#/ && tolower($$7) != $$7) { print ".PHONY: " tolower($$7) "_config"; print tolower($$7)"_config: " $$7 "_config" }' $< >> $@
10484 #########################################################################
10485 #########################################################################
10486 @@ -798,6 +813,7 @@
10487 $(obj)tools/gen_eth_addr $(obj)tools/img2srec \
10488 $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
10489 $(obj)tools/mk{$(BOARD),}spl \
10490 + $(obj)tools/mksunxiboot \
10491 $(obj)tools/mxsboot \
10492 $(obj)tools/ncb $(obj)tools/ubsha1 \
10493 $(obj)tools/kernel-doc/docproc \
10494 @@ -857,6 +873,7 @@
10495 @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
10496 @rm -f $(obj)dts/*.tmp
10497 @rm -f $(obj)spl/u-boot-spl{,-pad}.ais
10498 + @rm -f $(obj)spl/sun?i-spl.bin
10501 distclean: clobber unconfig
10502 diff -ruN u-boot-2014.01-rc1/mkconfig u-boot-sunxi/mkconfig
10503 --- u-boot-2014.01-rc1/mkconfig 2013-11-25 22:49:32.000000000 +0100
10504 +++ u-boot-sunxi/mkconfig 2014-03-05 23:14:48.292084967 +0100
10505 @@ -165,6 +165,7 @@
10506 echo "#define CONFIG_SYS_ARCH \"${arch}\"" >> config.h
10507 echo "#define CONFIG_SYS_CPU \"${cpu}\"" >> config.h
10508 echo "#define CONFIG_SYS_BOARD \"${board}\"" >> config.h
10509 +echo "#define CONFIG_SYS_TARGET \"${BOARD_NAME}\"" >> config.h
10511 [ "${vendor}" ] && echo "#define CONFIG_SYS_VENDOR \"${vendor}\"" >> config.h
10513 diff -ruN u-boot-2014.01-rc1/snapshot.commit u-boot-sunxi/snapshot.commit
10514 --- u-boot-2014.01-rc1/snapshot.commit 2013-11-25 22:49:32.000000000 +0100
10515 +++ u-boot-sunxi/snapshot.commit 2014-03-05 23:14:48.300084861 +0100
10517 -d19ad726bcd5d9106f7ba9c750462fcc369f1020 Mon, 25 Nov 2013 16:49:32 -0500
10519 diff -ruN u-boot-2014.01-rc1/spl/Makefile u-boot-sunxi/spl/Makefile
10520 --- u-boot-2014.01-rc1/spl/Makefile 2013-11-25 22:49:32.000000000 +0100
10521 +++ u-boot-sunxi/spl/Makefile 2014-03-05 23:14:48.300084861 +0100
10522 @@ -162,6 +162,12 @@
10523 ALL-y += $(obj)$(BOARD)-spl.bin
10526 +ifdef CONFIG_SUNXI
10527 +ifndef CONFIG_SPL_FEL
10528 +ALL-y += $(obj)sunxi-spl.bin
10534 ifdef CONFIG_SAMSUNG
10535 @@ -169,6 +175,12 @@
10536 $(OBJTREE)/tools/mk$(BOARD)spl $< $@
10539 +ifdef CONFIG_SUNXI
10540 +$(obj)sunxi-spl.bin: $(obj)u-boot-spl.bin
10541 + $(OBJTREE)/tools/mksunxiboot \
10542 + $(obj)u-boot-spl.bin $(obj)sunxi-spl.bin
10545 $(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN)
10546 $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
10548 diff -ruN u-boot-2014.01-rc1/tools/.gitignore u-boot-sunxi/tools/.gitignore
10549 --- u-boot-2014.01-rc1/tools/.gitignore 2013-11-25 22:49:32.000000000 +0100
10550 +++ u-boot-sunxi/tools/.gitignore 2014-03-05 23:14:48.300084861 +0100
10559 diff -ruN u-boot-2014.01-rc1/tools/Makefile u-boot-sunxi/tools/Makefile
10560 --- u-boot-2014.01-rc1/tools/Makefile 2013-11-25 22:49:32.000000000 +0100
10561 +++ u-boot-sunxi/tools/Makefile 2014-03-05 23:14:48.300084861 +0100
10563 BIN_FILES-y += mkimage$(SFX)
10564 BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
10565 BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
10566 +BIN_FILES-$(CONFIG_SUNXI) += mksunxiboot$(SFX)
10567 BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
10568 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
10569 BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
10571 OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
10572 OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
10573 OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
10574 +OBJ_FILES-$(CONFIG_SUNXI) += mksunxiboot.o
10575 OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
10576 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
10577 OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
10578 @@ -235,6 +237,10 @@
10579 $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
10582 +$(obj)mksunxiboot$(SFX): $(obj)mksunxiboot.o
10583 + $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
10586 $(obj)mxsboot$(SFX): $(obj)mxsboot.o
10587 $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
10589 diff -ruN u-boot-2014.01-rc1/tools/mksunxiboot.c u-boot-sunxi/tools/mksunxiboot.c
10590 --- u-boot-2014.01-rc1/tools/mksunxiboot.c 1970-01-01 01:00:00.000000000 +0100
10591 +++ u-boot-sunxi/tools/mksunxiboot.c 2014-03-05 23:14:48.312084700 +0100
10594 + * (C) Copyright 2007-2011
10595 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10596 + * Tom Cubie <tangliang@allwinnertech.com>
10598 + * a simple tool to generate bootable image for sunxi platform.
10600 + * This program is free software; you can redistribute it and/or
10601 + * modify it under the terms of the GNU General Public License as
10602 + * published by the Free Software Foundation; either version 2 of
10603 + * the License, or (at your option) any later version.
10605 + * This program is distributed in the hope that it will be useful,
10606 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10607 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10608 + * GNU General Public License for more details.
10610 + * You should have received a copy of the GNU General Public License
10611 + * along with this program; if not, write to the Free Software
10612 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
10613 + * MA 02111-1307 USA
10616 +#include <fcntl.h>
10617 +#include <stdio.h>
10618 +#include <unistd.h>
10619 +#include <stdlib.h>
10620 +#include <string.h>
10621 +#include <errno.h>
10622 +#include <sys/types.h>
10623 +#include <sys/stat.h>
10625 +typedef unsigned char u8;
10626 +typedef unsigned int u32;
10628 +/* boot head definition from sun4i boot code */
10629 +struct boot_file_head {
10630 + u32 jump_instruction; /* one intruction jumping to real code */
10631 + u8 magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
10632 + u32 check_sum; /* generated by PC */
10633 + u32 length; /* generated by PC */
10635 + /* We use a simplified header, only filling in what is needed by the
10636 + * boot ROM. To be compatible with Allwinner tools the larger header
10637 + * below should be used, followed by a custom header if desired. */
10638 + u8 pad[12]; /* align to 32 bytes */
10640 + u32 pub_head_size; /* the size of boot_file_head */
10641 + u8 pub_head_vsn[4]; /* the version of boot_file_head */
10642 + u8 file_head_vsn[4]; /* the version of boot0_file_head or
10643 + boot1_file_head */
10644 + u8 Boot_vsn[4]; /* Boot version */
10645 + u8 eGON_vsn[4]; /* eGON version */
10646 + u8 platform[8]; /* platform information */
10650 +#define BOOT0_MAGIC "eGON.BT0"
10651 +#define STAMP_VALUE 0x5F0A6C39
10653 +/* check sum functon from sun4i boot code */
10654 +int gen_check_sum(void *boot_buf)
10656 + struct boot_file_head *head_p;
10663 + head_p = (struct boot_file_head *)boot_buf;
10664 + length = head_p->length;
10665 + if ((length & 0x3) != 0) /* must 4-byte-aligned */
10667 + buf = (u32 *)boot_buf;
10668 + head_p->check_sum = STAMP_VALUE; /* fill stamp */
10669 + loop = length >> 2;
10671 + /* calculate the sum */
10672 + for (i = 0, sum = 0; i < loop; i++)
10675 + /* write back check sum */
10676 + head_p->check_sum = sum;
10681 +#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
10682 +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
10684 +#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */
10685 +#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
10686 +#define BLOCK_SIZE 512
10689 + struct boot_file_head header;
10690 + char code[SRAM_LOAD_MAX_SIZE];
10691 + char pad[BLOCK_SIZE];
10694 +int main(int argc, char *argv[])
10696 + int fd_in, fd_out;
10697 + struct boot_img img;
10698 + unsigned file_size, load_size;
10702 + printf("\tThis program makes an input bin file to sun4i " \
10703 + "bootable image.\n" \
10704 + "\tUsage: %s input_file out_putfile\n", argv[0]);
10705 + return EXIT_FAILURE;
10708 + fd_in = open(argv[1], O_RDONLY);
10710 + perror("Open input file:");
10711 + return EXIT_FAILURE;
10714 + memset((void *)img.pad, 0, BLOCK_SIZE);
10716 + /* get input file size */
10717 + file_size = lseek(fd_in, 0, SEEK_END);
10718 + printf("File size: 0x%x\n", file_size);
10720 + if (file_size > SRAM_LOAD_MAX_SIZE) {
10721 + fprintf(stderr, "ERROR: File too large!\n");
10722 + return EXIT_FAILURE;
10724 + load_size = ALIGN(file_size, sizeof(int));
10725 + printf("Load size: 0x%x\n", load_size);
10727 + fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666);
10728 + if (fd_out < 0) {
10729 + perror("Open output file:");
10730 + return EXIT_FAILURE;
10733 + /* read file to buffer to calculate checksum */
10734 + lseek(fd_in, 0, SEEK_SET);
10735 + count = read(fd_in, img.code, load_size);
10736 + printf("Read 0x%x bytes\n", count);
10738 + /* fill the header */
10739 + img.header.jump_instruction = /* b instruction */
10740 + 0xEA000000 | /* jump to the first instr after the header */
10741 + ((sizeof(struct boot_file_head) / sizeof(int) - 2)
10743 + memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */
10744 + img.header.length =
10745 + ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE);
10746 + gen_check_sum((void *)&img);
10748 + count = write(fd_out, (void *)&img, img.header.length);
10749 + printf("Write 0x%x bytes\n", count);
10754 + return EXIT_SUCCESS;
10756 diff -ruN u-boot-2014.01-rc1/tools/mksunxiboot.README u-boot-sunxi/tools/mksunxiboot.README
10757 --- u-boot-2014.01-rc1/tools/mksunxiboot.README 1970-01-01 01:00:00.000000000 +0100
10758 +++ u-boot-sunxi/tools/mksunxiboot.README 2014-03-05 23:14:48.312084700 +0100
10760 +This program make a arm binary file can be loaded by Allwinner A10 and related
10761 +chips from storage media such as nand and mmc.
10763 +More information about A10 boot, please refer to
10764 +http://rhombus-tech.net/allwinner_a10/a10_boot_process/
10766 +To compile this program, just type make, you will get 'mksunxiboot'.
10769 +$./mksunxiboot u-boot.bin u-boot-mmc.bin
10770 +then you can write it to a mmc card with dd.
10771 +$sudo dd if=u-boot-mmc.bin of=/dev/sdb bs=1024 seek=8
10772 +then insert your mmc card to your A10 tablet, you can boot from mmc card.
projects / 15.05 / openwrt.git / blob