target/linux/sunxi/patches-4.4/101-dt-sun4i-add-dram-gates.patch

   1 From 82f8582feef4c048ee7ef0155a71c23614a7856d Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Sat, 5 Dec 2015 21:16:44 +0800
   4 Subject: [PATCH] ARM: dts: sun4i: Add DRAM gates
   5
   6 The DRAM gates controls direct memory access for some peripherals.
   7 These peripherals include the display pipeline, so add the required
   8 gates to the simplefb nodes as well.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun4i-a10.dtsi | 36 ++++++++++++++++++++++++++++++++----
  14  1 file changed, 32 insertions(+), 4 deletions(-)
  15
  16 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
  17 index aa90f31..849d024 100644
  18 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  19 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  20 @@ -66,7 +66,7 @@
  21                                      "simple-framebuffer";
  22                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  23                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  24 -                                <&ahb_gates 44>;
  25 +                                <&ahb_gates 44>, <&dram_gates 26>;
  26                         status = "disabled";
  27                 };
  28
  29 @@ -75,7 +75,8 @@
  30                                      "simple-framebuffer";
  31                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  32                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  33 -                                <&ahb_gates 44>, <&ahb_gates 46>;
  34 +                                <&ahb_gates 44>, <&ahb_gates 46>,
  35 +                                <&dram_gates 25>, <&dram_gates 26>;
  36                         status = "disabled";
  37                 };
  38
  39 @@ -84,7 +85,8 @@
  40                                      "simple-framebuffer";
  41                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  42                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  43 -                                <&ahb_gates 46>;
  44 +                                <&ahb_gates 46>, <&dram_gates 25>,
  45 +                                <&dram_gates 26>;
  46                         status = "disabled";
  47                 };
  48
  49 @@ -93,7 +95,8 @@
  50                                      "simple-framebuffer";
  51                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
  52                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  53 -                                <&ahb_gates 44>, <&ahb_gates 46>;
  54 +                                <&ahb_gates 44>, <&ahb_gates 46>,
  55 +                                <&dram_gates 25>, <&dram_gates 26>;
  56                         status = "disabled";
  57                 };
  58         };
  59 @@ -492,6 +495,31 @@
  60                         clock-output-names = "spi3";
  61                 };
  62
  63 +               dram_gates: clk@01c20100 {
  64 +                       #clock-cells = <1>;
  65 +                       compatible = "allwinner,sun4i-a10-dram-gates-clk";
  66 +                       reg = <0x01c20100 0x4>;
  67 +                       clocks = <&pll5 0>;
  68 +                       clock-indices = <0>,
  69 +                                       <1>, <2>,
  70 +                                       <3>,
  71 +                                       <4>,
  72 +                                       <5>, <6>,
  73 +                                       <15>,
  74 +                                       <24>, <25>,
  75 +                                       <26>, <27>,
  76 +                                       <28>, <29>;
  77 +                       clock-output-names = "dram_ve",
  78 +                                            "dram_csi0", "dram_csi1",
  79 +                                            "dram_ts",
  80 +                                            "dram_tvd",
  81 +                                            "dram_tve0", "dram_tve1",
  82 +                                            "dram_output",
  83 +                                            "dram_de_fe1", "dram_de_fe0",
  84 +                                            "dram_de_be0", "dram_de_be1",
  85 +                                            "dram_de_mp", "dram_ace";
  86 +               };
  87 +
  88                 codec_clk: clk@01c20140 {
  89                         #clock-cells = <0>;
  90                         compatible = "allwinner,sun4i-a10-codec-clk";