target/linux/sunxi/patches-4.1/128-1-mtd-nand-store-timing-in-nand_chip.patch

   1 diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
   2 index c2e1232..f561c68 100644
   3 --- a/drivers/mtd/nand/nand_base.c
   4 +++ b/drivers/mtd/nand/nand_base.c
   5 @@ -3611,6 +3611,8 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type)
   6  static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
   7                    struct nand_flash_dev *type, u8 *id_data, int *busw)
   8  {
   9 +       int mode;
  10 +
  11         if (!strncmp(type->id, id_data, type->id_len)) {
  12                 mtd->writesize = type->pagesize;
  13                 mtd->erasesize = type->erasesize;
  14 @@ -3621,8 +3623,9 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
  15                 chip->options |= type->options;
  16                 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
  17                 chip->ecc_step_ds = NAND_ECC_STEP(type);
  18 -               chip->onfi_timing_mode_default =
  19 -                                       type->onfi_timing_mode_default;
  20 +
  21 +               mode = type->onfi_timing_mode_default;
  22 +               chip->sdr_timings = onfi_async_timing_mode_to_sdr_timings(mode);
  23
  24                 *busw = type->options & NAND_BUSWIDTH_16;
  25
  26 diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
  27 index 5095a32..72e4135 100644
  28 --- a/drivers/mtd/nand/sunxi_nand.c
  29 +++ b/drivers/mtd/nand/sunxi_nand.c
  30 @@ -1083,7 +1083,7 @@ static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
  31
  32         mode = onfi_get_async_timing_mode(&chip->nand);
  33         if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  34 -               mode = chip->nand.onfi_timing_mode_default;
  35 +               timings = chip->nand.sdr_timings;
  36         } else {
  37                 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
  38
  39 @@ -1097,9 +1097,10 @@ static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
  40                                                 feature);
  41                 if (ret)
  42                         return ret;
  43 +
  44 +               timings = onfi_async_timing_mode_to_sdr_timings(mode);
  45         }
  46
  47 -       timings = onfi_async_timing_mode_to_sdr_timings(mode);
  48         if (IS_ERR(timings))
  49                 return PTR_ERR(timings);
  50
  51 diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
  52 index 3d4ea7e..2eb92a3 100644
  53 --- a/include/linux/mtd/nand.h
  54 +++ b/include/linux/mtd/nand.h
  55 @@ -536,6 +536,55 @@ struct nand_buffers {
  56         uint8_t *databuf;
  57  };
  58
  59 +/*
  60 + * struct nand_sdr_timings - SDR NAND chip timings
  61 + *
  62 + * This struct defines the timing requirements of a SDR NAND chip.
  63 + * These informations can be found in every NAND datasheets and the timings
  64 + * meaning are described in the ONFI specifications:
  65 + * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
  66 + * Parameters)
  67 + *
  68 + * All these timings are expressed in picoseconds.
  69 + */
  70 +
  71 +struct nand_sdr_timings {
  72 +       u32 tALH_min;
  73 +       u32 tADL_min;
  74 +       u32 tALS_min;
  75 +       u32 tAR_min;
  76 +       u32 tCEA_max;
  77 +       u32 tCEH_min;
  78 +       u32 tCH_min;
  79 +       u32 tCHZ_max;
  80 +       u32 tCLH_min;
  81 +       u32 tCLR_min;
  82 +       u32 tCLS_min;
  83 +       u32 tCOH_min;
  84 +       u32 tCS_min;
  85 +       u32 tDH_min;
  86 +       u32 tDS_min;
  87 +       u32 tFEAT_max;
  88 +       u32 tIR_min;
  89 +       u32 tITC_max;
  90 +       u32 tRC_min;
  91 +       u32 tREA_max;
  92 +       u32 tREH_min;
  93 +       u32 tRHOH_min;
  94 +       u32 tRHW_min;
  95 +       u32 tRHZ_max;
  96 +       u32 tRLOH_min;
  97 +       u32 tRP_min;
  98 +       u32 tRR_min;
  99 +       u64 tRST_max;
 100 +       u32 tWB_max;
 101 +       u32 tWC_min;
 102 +       u32 tWH_min;
 103 +       u32 tWHR_min;
 104 +       u32 tWP_min;
 105 +       u32 tWW_min;
 106 +};
 107 +
 108  /**
 109   * struct nand_chip - NAND Private Flash Chip Data
 110   * @IO_ADDR_R:         [BOARDSPECIFIC] address to read the 8 I/O lines of the
 111 @@ -600,11 +649,7 @@ struct nand_buffers {
 112   * @ecc_step_ds:       [INTERN] ECC step required by the @ecc_strength_ds,
 113   *                      also from the datasheet. It is the recommended ECC step
 114   *                     size, if known; if unknown, set to zero.
 115 - * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
 116 - *                           either deduced from the datasheet if the NAND
 117 - *                           chip is not ONFI compliant or set to 0 if it is
 118 - *                           (an ONFI chip is always configured in mode 0
 119 - *                           after a NAND reset)
 120 + * @sdr_timings                [INTERN] Pointer to default timings for SDR NAND.
 121   * @numchips:          [INTERN] number of physical chips
 122   * @chipsize:          [INTERN] the size of one chip for multichip arrays
 123   * @pagemask:          [INTERN] page number mask = number of (pages / chip) - 1
 124 @@ -689,7 +734,7 @@ struct nand_chip {
 125         uint8_t bits_per_cell;
 126         uint16_t ecc_strength_ds;
 127         uint16_t ecc_step_ds;
 128 -       int onfi_timing_mode_default;
 129 +       const struct nand_sdr_timings *sdr_timings;
 130         int badblockpos;
 131         int badblockbits;
 132
 133 @@ -975,55 +1020,6 @@ static inline int jedec_feature(struct nand_chip *chip)
 134                 : 0;
 135  }
 136
 137 -/*
 138 - * struct nand_sdr_timings - SDR NAND chip timings
 139 - *
 140 - * This struct defines the timing requirements of a SDR NAND chip.
 141 - * These informations can be found in every NAND datasheets and the timings
 142 - * meaning are described in the ONFI specifications:
 143 - * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
 144 - * Parameters)
 145 - *
 146 - * All these timings are expressed in picoseconds.
 147 - */
 148 -
 149 -struct nand_sdr_timings {
 150 -       u32 tALH_min;
 151 -       u32 tADL_min;
 152 -       u32 tALS_min;
 153 -       u32 tAR_min;
 154 -       u32 tCEA_max;
 155 -       u32 tCEH_min;
 156 -       u32 tCH_min;
 157 -       u32 tCHZ_max;
 158 -       u32 tCLH_min;
 159 -       u32 tCLR_min;
 160 -       u32 tCLS_min;
 161 -       u32 tCOH_min;
 162 -       u32 tCS_min;
 163 -       u32 tDH_min;
 164 -       u32 tDS_min;
 165 -       u32 tFEAT_max;
 166 -       u32 tIR_min;
 167 -       u32 tITC_max;
 168 -       u32 tRC_min;
 169 -       u32 tREA_max;
 170 -       u32 tREH_min;
 171 -       u32 tRHOH_min;
 172 -       u32 tRHW_min;
 173 -       u32 tRHZ_max;
 174 -       u32 tRLOH_min;
 175 -       u32 tRP_min;
 176 -       u32 tRR_min;
 177 -       u64 tRST_max;
 178 -       u32 tWB_max;
 179 -       u32 tWC_min;
 180 -       u32 tWH_min;
 181 -       u32 tWHR_min;
 182 -       u32 tWP_min;
 183 -       u32 tWW_min;
 184 -};
 185 -
 186  /* get timing characteristics from ONFI timing mode. */
 187  const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
 188  #endif /* __LINUX_MTD_NAND_H */