target/linux/generic/patches-3.3/020-ssb_update.patch

   1 --- a/drivers/ssb/Kconfig
   2 +++ b/drivers/ssb/Kconfig
   3 @@ -160,4 +160,12 @@ config SSB_DRIVER_GIGE
   4
   5           If unsure, say N
   6
   7 +config SSB_DRIVER_GPIO
   8 +       bool "SSB GPIO driver"
   9 +       depends on SSB && GPIOLIB
  10 +       help
  11 +         Driver to provide access to the GPIO pins on the bus.
  12 +
  13 +         If unsure, say N
  14 +
  15  endmenu
  16 --- a/drivers/ssb/Makefile
  17 +++ b/drivers/ssb/Makefile
  18 @@ -15,6 +15,7 @@ ssb-$(CONFIG_SSB_DRIVER_MIPS)         += driver
  19  ssb-$(CONFIG_SSB_DRIVER_EXTIF)         += driver_extif.o
  20  ssb-$(CONFIG_SSB_DRIVER_PCICORE)       += driver_pcicore.o
  21  ssb-$(CONFIG_SSB_DRIVER_GIGE)          += driver_gige.o
  22 +ssb-$(CONFIG_SSB_DRIVER_GPIO)          += driver_gpio.o
  23
  24  # b43 pci-ssb-bridge driver
  25  # Not strictly a part of SSB, but kept here for convenience
  26 --- a/drivers/ssb/b43_pci_bridge.c
  27 +++ b/drivers/ssb/b43_pci_bridge.c
  28 @@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc
  29         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
  30         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
  31         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
  32 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
  33 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
  34         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
  35         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
  36         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
  37         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
  38         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
  39 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
  40 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
  41         { 0, },
  42  };
  43  MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
  44 --- a/drivers/ssb/driver_chipcommon.c
  45 +++ b/drivers/ssb/driver_chipcommon.c
  46 @@ -4,6 +4,7 @@
  47   *
  48   * Copyright 2005, Broadcom Corporation
  49   * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  50 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
  51   *
  52   * Licensed under the GNU/GPL. See COPYING for details.
  53   */
  54 @@ -12,6 +13,7 @@
  55  #include <linux/ssb/ssb_regs.h>
  56  #include <linux/export.h>
  57  #include <linux/pci.h>
  58 +#include <linux/bcm47xx_wdt.h>
  59
  60  #include "ssb_private.h"
  61
  62 @@ -280,13 +282,79 @@ static void calc_fast_powerup_delay(stru
  63         cc->fast_pwrup_delay = tmp;
  64  }
  65
  66 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
  67 +{
  68 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
  69 +               return ssb_pmu_get_alp_clock(cc);
  70 +
  71 +       return 20000000;
  72 +}
  73 +
  74 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
  75 +{
  76 +       u32 nb;
  77 +
  78 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  79 +               if (cc->dev->id.revision < 26)
  80 +                       nb = 16;
  81 +               else
  82 +                       nb = (cc->dev->id.revision >= 37) ? 32 : 24;
  83 +       } else {
  84 +               nb = 28;
  85 +       }
  86 +       if (nb == 32)
  87 +               return 0xffffffff;
  88 +       else
  89 +               return (1 << nb) - 1;
  90 +}
  91 +
  92 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
  93 +{
  94 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
  95 +
  96 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
  97 +               return 0;
  98 +
  99 +       return ssb_chipco_watchdog_timer_set(cc, ticks);
 100 +}
 101 +
 102 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 103 +{
 104 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
 105 +       u32 ticks;
 106 +
 107 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
 108 +               return 0;
 109 +
 110 +       ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
 111 +       return ticks / cc->ticks_per_ms;
 112 +}
 113 +
 114 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
 115 +{
 116 +       struct ssb_bus *bus = cc->dev->bus;
 117 +
 118 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 119 +                       /* based on 32KHz ILP clock */
 120 +                       return 32;
 121 +       } else {
 122 +               if (cc->dev->id.revision < 18)
 123 +                       return ssb_clockspeed(bus) / 1000;
 124 +               else
 125 +                       return ssb_chipco_alp_clock(cc) / 1000;
 126 +       }
 127 +}
 128 +
 129  void ssb_chipcommon_init(struct ssb_chipcommon *cc)
 130  {
 131         if (!cc->dev)
 132                 return; /* We don't have a ChipCommon */
 133 +
 134 +       spin_lock_init(&cc->gpio_lock);
 135 +
 136         if (cc->dev->id.revision >= 11)
 137                 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
 138 -       ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
 139 +       ssb_dbg("chipcommon status is 0x%x\n", cc->status);
 140
 141         if (cc->dev->id.revision >= 20) {
 142                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
 143 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
 144         chipco_powercontrol_init(cc);
 145         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 146         calc_fast_powerup_delay(cc);
 147 +
 148 +       if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
 149 +               cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
 150 +               cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
 151 +       }
 152  }
 153
 154  void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 155 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
 156  }
 157
 158  /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 159 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 160 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 161  {
 162 -       /* instant NMI */
 163 -       chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 164 +       u32 maxt;
 165 +       enum ssb_clkmode clkmode;
 166 +
 167 +       maxt = ssb_chipco_watchdog_get_max_timer(cc);
 168 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 169 +               if (ticks == 1)
 170 +                       ticks = 2;
 171 +               else if (ticks > maxt)
 172 +                       ticks = maxt;
 173 +               chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
 174 +       } else {
 175 +               clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
 176 +               ssb_chipco_set_clockmode(cc, clkmode);
 177 +               if (ticks > maxt)
 178 +                       ticks = maxt;
 179 +               /* instant NMI */
 180 +               chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 181 +       }
 182 +       return ticks;
 183  }
 184
 185  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 186 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
 187
 188  u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
 189  {
 190 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 191 +       unsigned long flags;
 192 +       u32 res = 0;
 193 +
 194 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 195 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 196 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 197 +
 198 +       return res;
 199  }
 200
 201  u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
 202  {
 203 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 204 +       unsigned long flags;
 205 +       u32 res = 0;
 206 +
 207 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 208 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 209 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 210 +
 211 +       return res;
 212  }
 213
 214  u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
 215  {
 216 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 217 +       unsigned long flags;
 218 +       u32 res = 0;
 219 +
 220 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 221 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 222 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 223 +
 224 +       return res;
 225  }
 226  EXPORT_SYMBOL(ssb_chipco_gpio_control);
 227
 228  u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 229  {
 230 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 231 +       unsigned long flags;
 232 +       u32 res = 0;
 233 +
 234 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 235 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 236 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 237 +
 238 +       return res;
 239  }
 240
 241  u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
 242  {
 243 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 244 +       unsigned long flags;
 245 +       u32 res = 0;
 246 +
 247 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 248 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 249 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 250 +
 251 +       return res;
 252 +}
 253 +
 254 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
 255 +{
 256 +       unsigned long flags;
 257 +       u32 res = 0;
 258 +
 259 +       if (cc->dev->id.revision < 20)
 260 +               return 0xffffffff;
 261 +
 262 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 263 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
 264 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 265 +
 266 +       return res;
 267 +}
 268 +
 269 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
 270 +{
 271 +       unsigned long flags;
 272 +       u32 res = 0;
 273 +
 274 +       if (cc->dev->id.revision < 20)
 275 +               return 0xffffffff;
 276 +
 277 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 278 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
 279 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 280 +
 281 +       return res;
 282  }
 283
 284  #ifdef CONFIG_SSB_SERIAL
 285 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
 286                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 287                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 288                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 289 -                       /* Fixed ALP clock */
 290 -                       baud_base = 20000000;
 291 -                       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 292 -                               /* FIXME: baud_base is different for devices with a PMU */
 293 -                               SSB_WARN_ON(1);
 294 -                       }
 295 +                       baud_base = ssb_chipco_alp_clock(cc);
 296                         div = 1;
 297                         if (ccrev >= 21) {
 298                                 /* Turn off UART clock before switching clocksource. */
 299 --- a/drivers/ssb/driver_chipcommon_pmu.c
 300 +++ b/drivers/ssb/driver_chipcommon_pmu.c
 301 @@ -13,6 +13,9 @@
 302  #include <linux/ssb/ssb_driver_chipcommon.h>
 303  #include <linux/delay.h>
 304  #include <linux/export.h>
 305 +#ifdef CONFIG_BCM47XX
 306 +#include <nvram.h>
 307 +#endif
 308
 309  #include "ssb_private.h"
 310
 311 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
 312         u32 pmuctl, tmp, pllctl;
 313         unsigned int i;
 314
 315 -       if ((bus->chip_id == 0x5354) && !crystalfreq) {
 316 -               /* The 5354 crystal freq is 25MHz */
 317 -               crystalfreq = 25000;
 318 -       }
 319         if (crystalfreq)
 320                 e = pmu0_plltab_find_entry(crystalfreq);
 321         if (!e)
 322 @@ -111,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s
 323                 return;
 324         }
 325
 326 -       ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
 327 -                  (crystalfreq / 1000), (crystalfreq % 1000));
 328 +       ssb_info("Programming PLL to %u.%03u MHz\n",
 329 +                crystalfreq / 1000, crystalfreq % 1000);
 330
 331         /* First turn the PLL off. */
 332         switch (bus->chip_id) {
 333 @@ -139,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s
 334         }
 335         tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
 336         if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
 337 -               ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
 338 +               ssb_emerg("Failed to turn the PLL off!\n");
 339
 340         /* Set PDIV in PLL control 0. */
 341         pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
 342 @@ -250,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s
 343                 return;
 344         }
 345
 346 -       ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
 347 -                  (crystalfreq / 1000), (crystalfreq % 1000));
 348 +       ssb_info("Programming PLL to %u.%03u MHz\n",
 349 +                crystalfreq / 1000, crystalfreq % 1000);
 350
 351         /* First turn the PLL off. */
 352         switch (bus->chip_id) {
 353 @@ -276,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s
 354         }
 355         tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
 356         if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
 357 -               ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
 358 +               ssb_emerg("Failed to turn the PLL off!\n");
 359
 360         /* Set p1div and p2div. */
 361         pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
 362 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
 363         u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
 364
 365         if (bus->bustype == SSB_BUSTYPE_SSB) {
 366 -               /* TODO: The user may override the crystal frequency. */
 367 +#ifdef CONFIG_BCM47XX
 368 +               char buf[20];
 369 +               if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
 370 +                       crystalfreq = simple_strtoul(buf, NULL, 0);
 371 +#endif
 372         }
 373
 374         switch (bus->chip_id) {
 375 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
 376                 ssb_pmu1_pllinit_r0(cc, crystalfreq);
 377                 break;
 378         case 0x4328:
 379 +               ssb_pmu0_pllinit_r0(cc, crystalfreq);
 380 +               break;
 381         case 0x5354:
 382 +               if (crystalfreq == 0)
 383 +                       crystalfreq = 25000;
 384                 ssb_pmu0_pllinit_r0(cc, crystalfreq);
 385                 break;
 386         case 0x4322:
 387 @@ -339,10 +346,11 @@ static void ssb_pmu_pll_init(struct ssb_
 388                         chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
 389                 }
 390                 break;
 391 +       case 43222:
 392 +               break;
 393         default:
 394 -               ssb_printk(KERN_ERR PFX
 395 -                          "ERROR: PLL init unknown for device %04X\n",
 396 -                          bus->chip_id);
 397 +               ssb_err("ERROR: PLL init unknown for device %04X\n",
 398 +                       bus->chip_id);
 399         }
 400  }
 401
 402 @@ -427,6 +435,7 @@ static void ssb_pmu_resources_init(struc
 403                  min_msk = 0xCBB;
 404                  break;
 405         case 0x4322:
 406 +       case 43222:
 407                 /* We keep the default settings:
 408                  * min_msk = 0xCBB
 409                  * max_msk = 0x7FFFF
 410 @@ -462,9 +471,8 @@ static void ssb_pmu_resources_init(struc
 411                 max_msk = 0xFFFFF;
 412                 break;
 413         default:
 414 -               ssb_printk(KERN_ERR PFX
 415 -                          "ERROR: PMU resource config unknown for device %04X\n",
 416 -                          bus->chip_id);
 417 +               ssb_err("ERROR: PMU resource config unknown for device %04X\n",
 418 +                       bus->chip_id);
 419         }
 420
 421         if (updown_tab) {
 422 @@ -516,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
 423         pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
 424         cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
 425
 426 -       ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
 427 -                   cc->pmu.rev, pmucap);
 428 +       ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
 429 +               cc->pmu.rev, pmucap);
 430
 431         if (cc->pmu.rev == 1)
 432                 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
 433 @@ -607,3 +615,102 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
 434
 435  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
 436  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
 437 +
 438 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
 439 +{
 440 +       u32 crystalfreq;
 441 +       const struct pmu0_plltab_entry *e = NULL;
 442 +
 443 +       crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
 444 +                     SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
 445 +       e = pmu0_plltab_find_entry(crystalfreq);
 446 +       BUG_ON(!e);
 447 +       return e->freq * 1000;
 448 +}
 449 +
 450 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
 451 +{
 452 +       struct ssb_bus *bus = cc->dev->bus;
 453 +
 454 +       switch (bus->chip_id) {
 455 +       case 0x5354:
 456 +               ssb_pmu_get_alp_clock_clk0(cc);
 457 +       default:
 458 +               ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
 459 +                       bus->chip_id);
 460 +               return 0;
 461 +       }
 462 +}
 463 +
 464 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
 465 +{
 466 +       struct ssb_bus *bus = cc->dev->bus;
 467 +
 468 +       switch (bus->chip_id) {
 469 +       case 0x5354:
 470 +               /* 5354 chip uses a non programmable PLL of frequency 240MHz */
 471 +               return 240000000;
 472 +       default:
 473 +               ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
 474 +                       bus->chip_id);
 475 +               return 0;
 476 +       }
 477 +}
 478 +
 479 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
 480 +{
 481 +       struct ssb_bus *bus = cc->dev->bus;
 482 +
 483 +       switch (bus->chip_id) {
 484 +       case 0x5354:
 485 +               return 120000000;
 486 +       default:
 487 +               ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
 488 +                       bus->chip_id);
 489 +               return 0;
 490 +       }
 491 +}
 492 +
 493 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
 494 +{
 495 +       u32 pmu_ctl = 0;
 496 +
 497 +       switch (cc->dev->bus->chip_id) {
 498 +       case 0x4322:
 499 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
 500 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
 501 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
 502 +               if (spuravoid == 1)
 503 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
 504 +               else
 505 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
 506 +               pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
 507 +               break;
 508 +       case 43222:
 509 +               if (spuravoid == 1) {
 510 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
 511 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
 512 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
 513 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
 514 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
 515 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
 516 +               } else {
 517 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
 518 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
 519 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
 520 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
 521 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
 522 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
 523 +               }
 524 +               pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
 525 +               break;
 526 +       default:
 527 +               ssb_printk(KERN_ERR PFX
 528 +                          "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
 529 +                          cc->dev->bus->chip_id);
 530 +               return;
 531 +       }
 532 +
 533 +       chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
 534 +}
 535 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
 536 --- a/drivers/ssb/driver_extif.c
 537 +++ b/drivers/ssb/driver_extif.c
 538 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
 539         *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
 540  }
 541
 542 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 543 -                                 u32 ticks)
 544 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 545  {
 546 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 547 +
 548 +       return ssb_extif_watchdog_timer_set(extif, ticks);
 549 +}
 550 +
 551 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 552 +{
 553 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 554 +       u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
 555 +
 556 +       ticks = ssb_extif_watchdog_timer_set(extif, ticks);
 557 +
 558 +       return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
 559 +}
 560 +
 561 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
 562 +{
 563 +       if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
 564 +               ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
 565         extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
 566 +
 567 +       return ticks;
 568 +}
 569 +
 570 +void ssb_extif_init(struct ssb_extif *extif)
 571 +{
 572 +       if (!extif->dev)
 573 +               return; /* We don't have a Extif core */
 574 +       spin_lock_init(&extif->gpio_lock);
 575  }
 576
 577  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 578 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
 579
 580  u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
 581  {
 582 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
 583 +       unsigned long flags;
 584 +       u32 res = 0;
 585 +
 586 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 587 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
 588                                    mask, value);
 589 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 590 +
 591 +       return res;
 592  }
 593
 594  u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
 595  {
 596 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
 597 +       unsigned long flags;
 598 +       u32 res = 0;
 599 +
 600 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 601 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
 602                                    mask, value);
 603 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 604 +
 605 +       return res;
 606  }
 607
 608  u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
 609  {
 610 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
 611 +       unsigned long flags;
 612 +       u32 res = 0;
 613 +
 614 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 615 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
 616 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 617 +
 618 +       return res;
 619  }
 620
 621  u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
 622  {
 623 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
 624 +       unsigned long flags;
 625 +       u32 res = 0;
 626 +
 627 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 628 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
 629 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 630 +
 631 +       return res;
 632  }
 633 --- /dev/null
 634 +++ b/drivers/ssb/driver_gpio.c
 635 @@ -0,0 +1,210 @@
 636 +/*
 637 + * Sonics Silicon Backplane
 638 + * GPIO driver
 639 + *
 640 + * Copyright 2011, Broadcom Corporation
 641 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 642 + *
 643 + * Licensed under the GNU/GPL. See COPYING for details.
 644 + */
 645 +
 646 +#include <linux/gpio.h>
 647 +#include <linux/export.h>
 648 +#include <linux/ssb/ssb.h>
 649 +
 650 +#include "ssb_private.h"
 651 +
 652 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
 653 +{
 654 +       return container_of(chip, struct ssb_bus, gpio);
 655 +}
 656 +
 657 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
 658 +{
 659 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 660 +
 661 +       return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
 662 +}
 663 +
 664 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
 665 +                                     int value)
 666 +{
 667 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 668 +
 669 +       ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
 670 +}
 671 +
 672 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
 673 +                                          unsigned gpio)
 674 +{
 675 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 676 +
 677 +       ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
 678 +       return 0;
 679 +}
 680 +
 681 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
 682 +                                           unsigned gpio, int value)
 683 +{
 684 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 685 +
 686 +       ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
 687 +       ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
 688 +       return 0;
 689 +}
 690 +
 691 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
 692 +{
 693 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 694 +
 695 +       ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
 696 +       /* clear pulldown */
 697 +       ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
 698 +       /* Set pullup */
 699 +       ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
 700 +
 701 +       return 0;
 702 +}
 703 +
 704 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
 705 +{
 706 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 707 +
 708 +       /* clear pullup */
 709 +       ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
 710 +}
 711 +
 712 +static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
 713 +{
 714 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 715 +
 716 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 717 +               return ssb_mips_irq(bus->chipco.dev) + 2;
 718 +       else
 719 +               return -EINVAL;
 720 +}
 721 +
 722 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
 723 +{
 724 +       struct gpio_chip *chip = &bus->gpio;
 725 +
 726 +       chip->label             = "ssb_chipco_gpio";
 727 +       chip->owner             = THIS_MODULE;
 728 +       chip->request           = ssb_gpio_chipco_request;
 729 +       chip->free              = ssb_gpio_chipco_free;
 730 +       chip->get               = ssb_gpio_chipco_get_value;
 731 +       chip->set               = ssb_gpio_chipco_set_value;
 732 +       chip->direction_input   = ssb_gpio_chipco_direction_input;
 733 +       chip->direction_output  = ssb_gpio_chipco_direction_output;
 734 +       chip->to_irq            = ssb_gpio_chipco_to_irq;
 735 +       chip->ngpio             = 16;
 736 +       /* There is just one SoC in one device and its GPIO addresses should be
 737 +        * deterministic to address them more easily. The other buses could get
 738 +        * a random base number. */
 739 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 740 +               chip->base              = 0;
 741 +       else
 742 +               chip->base              = -1;
 743 +
 744 +       return gpiochip_add(chip);
 745 +}
 746 +
 747 +#ifdef CONFIG_SSB_DRIVER_EXTIF
 748 +
 749 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
 750 +{
 751 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 752 +
 753 +       return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
 754 +}
 755 +
 756 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
 757 +                                    int value)
 758 +{
 759 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 760 +
 761 +       ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
 762 +}
 763 +
 764 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
 765 +                                         unsigned gpio)
 766 +{
 767 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 768 +
 769 +       ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
 770 +       return 0;
 771 +}
 772 +
 773 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
 774 +                                          unsigned gpio, int value)
 775 +{
 776 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 777 +
 778 +       ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
 779 +       ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
 780 +       return 0;
 781 +}
 782 +
 783 +static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
 784 +{
 785 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 786 +
 787 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 788 +               return ssb_mips_irq(bus->extif.dev) + 2;
 789 +       else
 790 +               return -EINVAL;
 791 +}
 792 +
 793 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
 794 +{
 795 +       struct gpio_chip *chip = &bus->gpio;
 796 +
 797 +       chip->label             = "ssb_extif_gpio";
 798 +       chip->owner             = THIS_MODULE;
 799 +       chip->get               = ssb_gpio_extif_get_value;
 800 +       chip->set               = ssb_gpio_extif_set_value;
 801 +       chip->direction_input   = ssb_gpio_extif_direction_input;
 802 +       chip->direction_output  = ssb_gpio_extif_direction_output;
 803 +       chip->to_irq            = ssb_gpio_extif_to_irq;
 804 +       chip->ngpio             = 5;
 805 +       /* There is just one SoC in one device and its GPIO addresses should be
 806 +        * deterministic to address them more easily. The other buses could get
 807 +        * a random base number. */
 808 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 809 +               chip->base              = 0;
 810 +       else
 811 +               chip->base              = -1;
 812 +
 813 +       return gpiochip_add(chip);
 814 +}
 815 +
 816 +#else
 817 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
 818 +{
 819 +       return -ENOTSUPP;
 820 +}
 821 +#endif
 822 +
 823 +int ssb_gpio_init(struct ssb_bus *bus)
 824 +{
 825 +       if (ssb_chipco_available(&bus->chipco))
 826 +               return ssb_gpio_chipco_init(bus);
 827 +       else if (ssb_extif_available(&bus->extif))
 828 +               return ssb_gpio_extif_init(bus);
 829 +       else
 830 +               SSB_WARN_ON(1);
 831 +
 832 +       return -1;
 833 +}
 834 +
 835 +int ssb_gpio_unregister(struct ssb_bus *bus)
 836 +{
 837 +       if (ssb_chipco_available(&bus->chipco) ||
 838 +           ssb_extif_available(&bus->extif)) {
 839 +               return gpiochip_remove(&bus->gpio);
 840 +       } else {
 841 +               SSB_WARN_ON(1);
 842 +       }
 843 +
 844 +       return -1;
 845 +}
 846 --- a/drivers/ssb/driver_mipscore.c
 847 +++ b/drivers/ssb/driver_mipscore.c
 848 @@ -17,7 +17,6 @@
 849
 850  #include "ssb_private.h"
 851
 852 -
 853  static inline u32 mips_read32(struct ssb_mipscore *mcore,
 854                               u16 offset)
 855  {
 856 @@ -147,21 +146,22 @@ static void set_irq(struct ssb_device *d
 857                 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
 858                 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
 859         }
 860 -       ssb_dprintk(KERN_INFO PFX
 861 -                   "set_irq: core 0x%04x, irq %d => %d\n",
 862 -                   dev->id.coreid, oldirq+2, irq+2);
 863 +       ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
 864 +               dev->id.coreid, oldirq+2, irq+2);
 865  }
 866
 867  static void print_irq(struct ssb_device *dev, unsigned int irq)
 868  {
 869 -       int i;
 870         static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
 871 -       ssb_dprintk(KERN_INFO PFX
 872 -               "core 0x%04x, irq :", dev->id.coreid);
 873 -       for (i = 0; i <= 6; i++) {
 874 -               ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
 875 -       }
 876 -       ssb_dprintk("\n");
 877 +       ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
 878 +               dev->id.coreid,
 879 +               irq_name[0], irq == 0 ? "*" : " ",
 880 +               irq_name[1], irq == 1 ? "*" : " ",
 881 +               irq_name[2], irq == 2 ? "*" : " ",
 882 +               irq_name[3], irq == 3 ? "*" : " ",
 883 +               irq_name[4], irq == 4 ? "*" : " ",
 884 +               irq_name[5], irq == 5 ? "*" : " ",
 885 +               irq_name[6], irq == 6 ? "*" : " ");
 886  }
 887
 888  static void dump_irq(struct ssb_bus *bus)
 889 @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
 890  {
 891         struct ssb_bus *bus = mcore->dev->bus;
 892
 893 -       if (bus->extif.dev)
 894 +       if (ssb_extif_available(&bus->extif))
 895                 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
 896 -       else if (bus->chipco.dev)
 897 +       else if (ssb_chipco_available(&bus->chipco))
 898                 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
 899         else
 900                 mcore->nr_serial_ports = 0;
 901 @@ -191,7 +191,7 @@ static void ssb_mips_flash_detect(struct
 902         struct ssb_bus *bus = mcore->dev->bus;
 903
 904         mcore->flash_buswidth = 2;
 905 -       if (bus->chipco.dev) {
 906 +       if (ssb_chipco_available(&bus->chipco)) {
 907                 mcore->flash_window = 0x1c000000;
 908                 mcore->flash_window_size = 0x02000000;
 909                 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
 910 @@ -208,9 +208,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
 911         struct ssb_bus *bus = mcore->dev->bus;
 912         u32 pll_type, n, m, rate = 0;
 913
 914 -       if (bus->extif.dev) {
 915 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 916 +               return ssb_pmu_get_cpu_clock(&bus->chipco);
 917 +
 918 +       if (ssb_extif_available(&bus->extif)) {
 919                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
 920 -       } else if (bus->chipco.dev) {
 921 +       } else if (ssb_chipco_available(&bus->chipco)) {
 922                 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
 923         } else
 924                 return 0;
 925 @@ -238,7 +241,7 @@ void ssb_mipscore_init(struct ssb_mipsco
 926         if (!mcore->dev)
 927                 return; /* We don't have a MIPS core */
 928
 929 -       ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
 930 +       ssb_dbg("Initializing MIPS core...\n");
 931
 932         bus = mcore->dev->bus;
 933         hz = ssb_clockspeed(bus);
 934 @@ -246,9 +249,9 @@ void ssb_mipscore_init(struct ssb_mipsco
 935                 hz = 100000000;
 936         ns = 1000000000 / hz;
 937
 938 -       if (bus->extif.dev)
 939 +       if (ssb_extif_available(&bus->extif))
 940                 ssb_extif_timing_init(&bus->extif, ns);
 941 -       else if (bus->chipco.dev)
 942 +       else if (ssb_chipco_available(&bus->chipco))
 943                 ssb_chipco_timing_init(&bus->chipco, ns);
 944
 945         /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
 946 @@ -286,7 +289,7 @@ void ssb_mipscore_init(struct ssb_mipsco
 947                         break;
 948                 }
 949         }
 950 -       ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
 951 +       ssb_dbg("after irq reconfiguration\n");
 952         dump_irq(bus);
 953
 954         ssb_mips_serial_init(mcore);
 955 --- a/drivers/ssb/driver_pcicore.c
 956 +++ b/drivers/ssb/driver_pcicore.c
 957 @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci
 958                 return -ENODEV;
 959         }
 960
 961 -       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 962 -                  pci_name(d));
 963 +       ssb_info("PCI: Fixing up device %s\n", pci_name(d));
 964
 965         /* Fix up interrupt lines */
 966         d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 967 @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(
 968         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 969                 return;
 970
 971 -       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 972 +       ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
 973
 974         /* Enable PCI bridge bus mastering and memory space */
 975         pci_set_master(dev);
 976         if (pcibios_enable_device(dev, ~0) < 0) {
 977 -               ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
 978 +               ssb_err("PCI: SSB bridge enable failed\n");
 979                 return;
 980         }
 981
 982 @@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge(
 983
 984         /* Make sure our latency is high enough to handle the devices behind us */
 985         lat = 168;
 986 -       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 987 -                  pci_name(dev), lat);
 988 +       ssb_info("PCI: Fixing latency timer of device %s to %u\n",
 989 +                pci_name(dev), lat);
 990         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 991  }
 992  DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
 993 @@ -323,7 +322,7 @@ static void __devinit ssb_pcicore_init_h
 994                 return;
 995         extpci_core = pc;
 996
 997 -       ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
 998 +       ssb_dbg("PCIcore in host mode found\n");
 999         /* Reset devices on the external PCI bus */
1000         val = SSB_PCICORE_CTL_RST_OE;
1001         val |= SSB_PCICORE_CTL_CLK_OE;
1002 @@ -338,7 +337,7 @@ static void __devinit ssb_pcicore_init_h
1003         udelay(1); /* Assertion time demanded by the PCI standard */
1004
1005         if (pc->dev->bus->has_cardbus_slot) {
1006 -               ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
1007 +               ssb_dbg("CardBus slot detected\n");
1008                 pc->cardbusmode = 1;
1009                 /* GPIO 1 resets the bridge */
1010                 ssb_gpio_out(pc->dev->bus, 1, 1);
1011 --- a/drivers/ssb/embedded.c
1012 +++ b/drivers/ssb/embedded.c
1013 @@ -4,11 +4,13 @@
1014   *
1015   * Copyright 2005-2008, Broadcom Corporation
1016   * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1017 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1018   *
1019   * Licensed under the GNU/GPL. See COPYING for details.
1020   */
1021
1022  #include <linux/export.h>
1023 +#include <linux/platform_device.h>
1024  #include <linux/ssb/ssb.h>
1025  #include <linux/ssb/ssb_embedded.h>
1026  #include <linux/ssb/ssb_driver_pci.h>
1027 @@ -32,6 +34,38 @@ int ssb_watchdog_timer_set(struct ssb_bu
1028  }
1029  EXPORT_SYMBOL(ssb_watchdog_timer_set);
1030
1031 +int ssb_watchdog_register(struct ssb_bus *bus)
1032 +{
1033 +       struct bcm47xx_wdt wdt = {};
1034 +       struct platform_device *pdev;
1035 +
1036 +       if (ssb_chipco_available(&bus->chipco)) {
1037 +               wdt.driver_data = &bus->chipco;
1038 +               wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
1039 +               wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
1040 +               wdt.max_timer_ms = bus->chipco.max_timer_ms;
1041 +       } else if (ssb_extif_available(&bus->extif)) {
1042 +               wdt.driver_data = &bus->extif;
1043 +               wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
1044 +               wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
1045 +               wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
1046 +       } else {
1047 +               return -ENODEV;
1048 +       }
1049 +
1050 +       pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
1051 +                                            bus->busnumber, &wdt,
1052 +                                            sizeof(wdt));
1053 +       if (IS_ERR(pdev)) {
1054 +               ssb_dbg("can not register watchdog device, err: %li\n",
1055 +                       PTR_ERR(pdev));
1056 +               return PTR_ERR(pdev);
1057 +       }
1058 +
1059 +       bus->watchdog = pdev;
1060 +       return 0;
1061 +}
1062 +
1063  u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
1064  {
1065         unsigned long flags;
1066 --- a/drivers/ssb/main.c
1067 +++ b/drivers/ssb/main.c
1068 @@ -13,6 +13,7 @@
1069  #include <linux/delay.h>
1070  #include <linux/io.h>
1071  #include <linux/module.h>
1072 +#include <linux/platform_device.h>
1073  #include <linux/ssb/ssb.h>
1074  #include <linux/ssb/ssb_regs.h>
1075  #include <linux/ssb/ssb_driver_gige.h>
1076 @@ -140,19 +141,6 @@ static void ssb_device_put(struct ssb_de
1077                 put_device(dev->dev);
1078  }
1079
1080 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
1081 -{
1082 -       if (drv)
1083 -               get_driver(&drv->drv);
1084 -       return drv;
1085 -}
1086 -
1087 -static inline void ssb_driver_put(struct ssb_driver *drv)
1088 -{
1089 -       if (drv)
1090 -               put_driver(&drv->drv);
1091 -}
1092 -
1093  static int ssb_device_resume(struct device *dev)
1094  {
1095         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1096 @@ -250,11 +238,9 @@ int ssb_devices_freeze(struct ssb_bus *b
1097                         ssb_device_put(sdev);
1098                         continue;
1099                 }
1100 -               sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
1101 -               if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
1102 -                       ssb_device_put(sdev);
1103 +               sdrv = drv_to_ssb_drv(sdev->dev->driver);
1104 +               if (SSB_WARN_ON(!sdrv->remove))
1105                         continue;
1106 -               }
1107                 sdrv->remove(sdev);
1108                 ctx->device_frozen[i] = 1;
1109         }
1110 @@ -289,11 +275,10 @@ int ssb_devices_thaw(struct ssb_freeze_c
1111
1112                 err = sdrv->probe(sdev, &sdev->id);
1113                 if (err) {
1114 -                       ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1115 -                                  dev_name(sdev->dev));
1116 +                       ssb_err("Failed to thaw device %s\n",
1117 +                               dev_name(sdev->dev));
1118                         result = err;
1119                 }
1120 -               ssb_driver_put(sdrv);
1121                 ssb_device_put(sdev);
1122         }
1123
1124 @@ -449,10 +434,23 @@ static void ssb_devices_unregister(struc
1125                 if (sdev->dev)
1126                         device_unregister(sdev->dev);
1127         }
1128 +
1129 +#ifdef CONFIG_SSB_EMBEDDED
1130 +       if (bus->bustype == SSB_BUSTYPE_SSB)
1131 +               platform_device_unregister(bus->watchdog);
1132 +#endif
1133  }
1134
1135  void ssb_bus_unregister(struct ssb_bus *bus)
1136  {
1137 +       int err;
1138 +
1139 +       err = ssb_gpio_unregister(bus);
1140 +       if (err == -EBUSY)
1141 +               ssb_dbg("Some GPIOs are still in use\n");
1142 +       else if (err)
1143 +               ssb_dbg("Can not unregister GPIO driver: %i\n", err);
1144 +
1145         ssb_buses_lock();
1146         ssb_devices_unregister(bus);
1147         list_del(&bus->list);
1148 @@ -498,8 +496,7 @@ static int ssb_devices_register(struct s
1149
1150                 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
1151                 if (!devwrap) {
1152 -                       ssb_printk(KERN_ERR PFX
1153 -                                  "Could not allocate device\n");
1154 +                       ssb_err("Could not allocate device\n");
1155                         err = -ENOMEM;
1156                         goto error;
1157                 }
1158 @@ -538,9 +535,7 @@ static int ssb_devices_register(struct s
1159                 sdev->dev = dev;
1160                 err = device_register(dev);
1161                 if (err) {
1162 -                       ssb_printk(KERN_ERR PFX
1163 -                                  "Could not register %s\n",
1164 -                                  dev_name(dev));
1165 +                       ssb_err("Could not register %s\n", dev_name(dev));
1166                         /* Set dev to NULL to not unregister
1167                          * dev on error unwinding. */
1168                         sdev->dev = NULL;
1169 @@ -577,6 +572,8 @@ static int __devinit ssb_attach_queued_b
1170                 if (err)
1171                         goto error;
1172                 ssb_pcicore_init(&bus->pcicore);
1173 +               if (bus->bustype == SSB_BUSTYPE_SSB)
1174 +                       ssb_watchdog_register(bus);
1175                 ssb_bus_may_powerdown(bus);
1176
1177                 err = ssb_devices_register(bus);
1178 @@ -812,7 +809,13 @@ static int __devinit ssb_bus_register(st
1179         if (err)
1180                 goto err_pcmcia_exit;
1181         ssb_chipcommon_init(&bus->chipco);
1182 +       ssb_extif_init(&bus->extif);
1183         ssb_mipscore_init(&bus->mipscore);
1184 +       err = ssb_gpio_init(bus);
1185 +       if (err == -ENOTSUPP)
1186 +               ssb_dbg("GPIO driver not activated\n");
1187 +       else if (err)
1188 +               ssb_dbg("Error registering GPIO driver: %i\n", err);
1189         err = ssb_fetch_invariants(bus, get_invariants);
1190         if (err) {
1191                 ssb_bus_may_powerdown(bus);
1192 @@ -863,11 +866,11 @@ int __devinit ssb_bus_pcibus_register(st
1193
1194         err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
1195         if (!err) {
1196 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1197 -                          "PCI device %s\n", dev_name(&host_pci->dev));
1198 +               ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
1199 +                        dev_name(&host_pci->dev));
1200         } else {
1201 -               ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1202 -                          " of SSB with error %d\n", err);
1203 +               ssb_err("Failed to register PCI version of SSB with error %d\n",
1204 +                       err);
1205         }
1206
1207         return err;
1208 @@ -888,8 +891,8 @@ int __devinit ssb_bus_pcmciabus_register
1209
1210         err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
1211         if (!err) {
1212 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1213 -                          "PCMCIA device %s\n", pcmcia_dev->devname);
1214 +               ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
1215 +                        pcmcia_dev->devname);
1216         }
1217
1218         return err;
1219 @@ -911,8 +914,8 @@ int __devinit ssb_bus_sdiobus_register(s
1220
1221         err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1222         if (!err) {
1223 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1224 -                          "SDIO device %s\n", sdio_func_id(func));
1225 +               ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
1226 +                        sdio_func_id(func));
1227         }
1228
1229         return err;
1230 @@ -931,8 +934,8 @@ int __devinit ssb_bus_ssbbus_register(st
1231
1232         err = ssb_bus_register(bus, get_invariants, baseaddr);
1233         if (!err) {
1234 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
1235 -                          "address 0x%08lX\n", baseaddr);
1236 +               ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
1237 +                        baseaddr);
1238         }
1239
1240         return err;
1241 @@ -1094,6 +1097,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
1242         u32 plltype;
1243         u32 clkctl_n, clkctl_m;
1244
1245 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1246 +               return ssb_pmu_get_controlclock(&bus->chipco);
1247 +
1248         if (ssb_extif_available(&bus->extif))
1249                 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1250                                            &clkctl_n, &clkctl_m);
1251 @@ -1131,8 +1137,7 @@ static u32 ssb_tmslow_reject_bitmask(str
1252         case SSB_IDLOW_SSBREV_27:     /* same here */
1253                 return SSB_TMSLOW_REJECT;       /* this is a guess */
1254         default:
1255 -               printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1256 -               WARN_ON(1);
1257 +               WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1258         }
1259         return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1260  }
1261 @@ -1324,7 +1329,7 @@ out:
1262  #endif
1263         return err;
1264  error:
1265 -       ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1266 +       ssb_err("Bus powerdown failed\n");
1267         goto out;
1268  }
1269  EXPORT_SYMBOL(ssb_bus_may_powerdown);
1270 @@ -1347,7 +1352,7 @@ int ssb_bus_powerup(struct ssb_bus *bus,
1271
1272         return 0;
1273  error:
1274 -       ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1275 +       ssb_err("Bus powerup failed\n");
1276         return err;
1277  }
1278  EXPORT_SYMBOL(ssb_bus_powerup);
1279 @@ -1455,15 +1460,13 @@ static int __init ssb_modinit(void)
1280
1281         err = b43_pci_ssb_bridge_init();
1282         if (err) {
1283 -               ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1284 -                          "initialization failed\n");
1285 +               ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1286                 /* don't fail SSB init because of this */
1287                 err = 0;
1288         }
1289         err = ssb_gige_init();
1290         if (err) {
1291 -               ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1292 -                          "driver initialization failed\n");
1293 +               ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1294                 /* don't fail SSB init because of this */
1295                 err = 0;
1296         }
1297 --- a/drivers/ssb/pci.c
1298 +++ b/drivers/ssb/pci.c
1299 @@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu
1300         }
1301         return 0;
1302  error:
1303 -       ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1304 +       ssb_err("Failed to switch to core %u\n", coreidx);
1305         return -ENODEV;
1306  }
1307
1308 @@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus *
1309         unsigned long flags;
1310
1311  #if SSB_VERBOSE_PCICORESWITCH_DEBUG
1312 -       ssb_printk(KERN_INFO PFX
1313 -                  "Switching to %s core, index %d\n",
1314 -                  ssb_core_name(dev->id.coreid),
1315 -                  dev->core_index);
1316 +       ssb_info("Switching to %s core, index %d\n",
1317 +                ssb_core_name(dev->id.coreid),
1318 +                dev->core_index);
1319  #endif
1320
1321         spin_lock_irqsave(&bus->bar_lock, flags);
1322 @@ -178,6 +177,18 @@ err_pci:
1323  #define SPEX(_outvar, _offset, _mask, _shift) \
1324         SPEX16(_outvar, _offset, _mask, _shift)
1325
1326 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift)    \
1327 +       do {    \
1328 +               SPEX(_field[0], _offset +  0, _mask, _shift);   \
1329 +               SPEX(_field[1], _offset +  2, _mask, _shift);   \
1330 +               SPEX(_field[2], _offset +  4, _mask, _shift);   \
1331 +               SPEX(_field[3], _offset +  6, _mask, _shift);   \
1332 +               SPEX(_field[4], _offset +  8, _mask, _shift);   \
1333 +               SPEX(_field[5], _offset + 10, _mask, _shift);   \
1334 +               SPEX(_field[6], _offset + 12, _mask, _shift);   \
1335 +               SPEX(_field[7], _offset + 14, _mask, _shift);   \
1336 +       } while (0)
1337 +
1338
1339  static inline u8 ssb_crc8(u8 crc, u8 data)
1340  {
1341 @@ -219,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat
1342         return t[crc ^ data];
1343  }
1344
1345 +static void sprom_get_mac(char *mac, const u16 *in)
1346 +{
1347 +       int i;
1348 +       for (i = 0; i < 3; i++) {
1349 +               *mac++ = in[i] >> 8;
1350 +               *mac++ = in[i];
1351 +       }
1352 +}
1353 +
1354  static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
1355  {
1356         int word;
1357 @@ -266,7 +286,7 @@ static int sprom_do_write(struct ssb_bus
1358         u32 spromctl;
1359         u16 size = bus->sprom_size;
1360
1361 -       ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1362 +       ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1363         err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
1364         if (err)
1365                 goto err_ctlreg;
1366 @@ -274,17 +294,17 @@ static int sprom_do_write(struct ssb_bus
1367         err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
1368         if (err)
1369                 goto err_ctlreg;
1370 -       ssb_printk(KERN_NOTICE PFX "[ 0%%");
1371 +       ssb_notice("[ 0%%");
1372         msleep(500);
1373         for (i = 0; i < size; i++) {
1374                 if (i == size / 4)
1375 -                       ssb_printk("25%%");
1376 +                       ssb_cont("25%%");
1377                 else if (i == size / 2)
1378 -                       ssb_printk("50%%");
1379 +                       ssb_cont("50%%");
1380                 else if (i == (size * 3) / 4)
1381 -                       ssb_printk("75%%");
1382 +                       ssb_cont("75%%");
1383                 else if (i % 2)
1384 -                       ssb_printk(".");
1385 +                       ssb_cont(".");
1386                 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1387                 mmiowb();
1388                 msleep(20);
1389 @@ -297,12 +317,12 @@ static int sprom_do_write(struct ssb_bus
1390         if (err)
1391                 goto err_ctlreg;
1392         msleep(500);
1393 -       ssb_printk("100%% ]\n");
1394 -       ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1395 +       ssb_cont("100%% ]\n");
1396 +       ssb_notice("SPROM written\n");
1397
1398         return 0;
1399  err_ctlreg:
1400 -       ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
1401 +       ssb_err("Could not access SPROM control register.\n");
1402         return err;
1403  }
1404
1405 @@ -327,11 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_
1406         return (s8)gain;
1407  }
1408
1409 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
1410 +{
1411 +       SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1412 +       SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
1413 +       SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
1414 +       SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
1415 +       SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
1416 +       SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
1417 +       SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
1418 +       SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
1419 +       SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
1420 +       SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
1421 +            SSB_SPROM2_MAXP_A_LO_SHIFT);
1422 +}
1423 +
1424  static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
1425  {
1426 -       int i;
1427 -       u16 v;
1428 -       s8 gain;
1429         u16 loc[3];
1430
1431         if (out->revision == 3)                 /* rev 3 moved MAC */
1432 @@ -341,19 +373,10 @@ static void sprom_extract_r123(struct ss
1433                 loc[1] = SSB_SPROM1_ET0MAC;
1434                 loc[2] = SSB_SPROM1_ET1MAC;
1435         }
1436 -       for (i = 0; i < 3; i++) {
1437 -               v = in[SPOFF(loc[0]) + i];
1438 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1439 -       }
1440 +       sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
1441         if (out->revision < 3) {        /* only rev 1-2 have et0, et1 */
1442 -               for (i = 0; i < 3; i++) {
1443 -                       v = in[SPOFF(loc[1]) + i];
1444 -                       *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
1445 -               }
1446 -               for (i = 0; i < 3; i++) {
1447 -                       v = in[SPOFF(loc[2]) + i];
1448 -                       *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
1449 -               }
1450 +               sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
1451 +               sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
1452         }
1453         SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
1454         SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
1455 @@ -361,8 +384,10 @@ static void sprom_extract_r123(struct ss
1456         SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
1457         SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
1458         SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
1459 -       SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1460 -            SSB_SPROM1_BINF_CCODE_SHIFT);
1461 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1462 +       if (out->revision == 1)
1463 +               SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1464 +                    SSB_SPROM1_BINF_CCODE_SHIFT);
1465         SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
1466              SSB_SPROM1_BINF_ANTA_SHIFT);
1467         SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
1468 @@ -386,24 +411,19 @@ static void sprom_extract_r123(struct ss
1469              SSB_SPROM1_ITSSI_A_SHIFT);
1470         SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
1471         SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
1472 -       if (out->revision >= 2)
1473 -               SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1474 +
1475 +       SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
1476 +       SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
1477
1478         /* Extract the antenna gain values. */
1479 -       gain = r123_extract_antgain(out->revision, in,
1480 -                                   SSB_SPROM1_AGAIN_BG,
1481 -                                   SSB_SPROM1_AGAIN_BG_SHIFT);
1482 -       out->antenna_gain.ghz24.a0 = gain;
1483 -       out->antenna_gain.ghz24.a1 = gain;
1484 -       out->antenna_gain.ghz24.a2 = gain;
1485 -       out->antenna_gain.ghz24.a3 = gain;
1486 -       gain = r123_extract_antgain(out->revision, in,
1487 -                                   SSB_SPROM1_AGAIN_A,
1488 -                                   SSB_SPROM1_AGAIN_A_SHIFT);
1489 -       out->antenna_gain.ghz5.a0 = gain;
1490 -       out->antenna_gain.ghz5.a1 = gain;
1491 -       out->antenna_gain.ghz5.a2 = gain;
1492 -       out->antenna_gain.ghz5.a3 = gain;
1493 +       out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
1494 +                                                   SSB_SPROM1_AGAIN_BG,
1495 +                                                   SSB_SPROM1_AGAIN_BG_SHIFT);
1496 +       out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1497 +                                                   SSB_SPROM1_AGAIN_A,
1498 +                                                   SSB_SPROM1_AGAIN_A_SHIFT);
1499 +       if (out->revision >= 2)
1500 +               sprom_extract_r23(out, in);
1501  }
1502
1503  /* Revs 4 5 and 8 have partially shared layout */
1504 @@ -448,30 +468,30 @@ static void sprom_extract_r458(struct ss
1505
1506  static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1507  {
1508 -       int i;
1509 -       u16 v;
1510         u16 il0mac_offset;
1511
1512         if (out->revision == 4)
1513                 il0mac_offset = SSB_SPROM4_IL0MAC;
1514         else
1515                 il0mac_offset = SSB_SPROM5_IL0MAC;
1516 -       /* extract the MAC address */
1517 -       for (i = 0; i < 3; i++) {
1518 -               v = in[SPOFF(il0mac_offset) + i];
1519 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1520 -       }
1521 +
1522 +       sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
1523 +
1524         SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
1525         SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
1526              SSB_SPROM4_ETHPHY_ET1A_SHIFT);
1527 +       SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
1528 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1529         if (out->revision == 4) {
1530 -               SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1531 +               SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
1532 +               SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
1533                 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1534                 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1535                 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1536                 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1537         } else {
1538 -               SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1539 +               SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
1540 +               SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
1541                 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1542                 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1543                 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1544 @@ -504,16 +524,14 @@ static void sprom_extract_r45(struct ssb
1545         }
1546
1547         /* Extract the antenna gain values. */
1548 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
1549 +       SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
1550              SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
1551 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
1552 +       SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
1553              SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
1554 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
1555 +       SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
1556              SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
1557 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
1558 +       SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
1559              SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
1560 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1561 -              sizeof(out->antenna_gain.ghz5));
1562
1563         sprom_extract_r458(out, in);
1564
1565 @@ -523,14 +541,21 @@ static void sprom_extract_r45(struct ssb
1566  static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1567  {
1568         int i;
1569 -       u16 v;
1570 +       u16 o;
1571 +       u16 pwr_info_offset[] = {
1572 +               SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1573 +               SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1574 +       };
1575 +       BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1576 +                       ARRAY_SIZE(out->core_pwr_info));
1577
1578         /* extract the MAC address */
1579 -       for (i = 0; i < 3; i++) {
1580 -               v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1581 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1582 -       }
1583 -       SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
1584 +       sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
1585 +
1586 +       SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
1587 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1588 +       SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
1589 +       SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
1590         SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1591         SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
1592         SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
1593 @@ -596,16 +621,46 @@ static void sprom_extract_r8(struct ssb_
1594         SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1595
1596         /* Extract the antenna gain values. */
1597 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1598 +       SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1599              SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1600 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
1601 +       SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1602              SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1603 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
1604 +       SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1605              SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1606 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
1607 +       SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1608              SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1609 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1610 -              sizeof(out->antenna_gain.ghz5));
1611 +
1612 +       /* Extract cores power info info */
1613 +       for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1614 +               o = pwr_info_offset[i];
1615 +               SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1616 +                       SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1617 +               SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1618 +                       SSB_SPROM8_2G_MAXP, 0);
1619 +
1620 +               SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1621 +               SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1622 +               SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1623 +
1624 +               SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1625 +                       SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1626 +               SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1627 +                       SSB_SPROM8_5G_MAXP, 0);
1628 +               SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1629 +                       SSB_SPROM8_5GH_MAXP, 0);
1630 +               SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1631 +                       SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1632 +
1633 +               SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1634 +               SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1635 +               SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1636 +               SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1637 +               SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1638 +               SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1639 +               SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1640 +               SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1641 +               SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1642 +       }
1643
1644         /* Extract FEM info */
1645         SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1646 @@ -630,6 +685,63 @@ static void sprom_extract_r8(struct ssb_
1647         SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1648                 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1649
1650 +       SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1651 +            SSB_SPROM8_LEDDC_ON_SHIFT);
1652 +       SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
1653 +            SSB_SPROM8_LEDDC_OFF_SHIFT);
1654 +
1655 +       SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
1656 +            SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
1657 +       SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
1658 +            SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
1659 +       SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
1660 +            SSB_SPROM8_TXRXC_SWITCH_SHIFT);
1661 +
1662 +       SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
1663 +
1664 +       SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
1665 +       SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
1666 +       SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
1667 +       SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
1668 +
1669 +       SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
1670 +            SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
1671 +       SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
1672 +            SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
1673 +       SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
1674 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
1675 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
1676 +       SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
1677 +            SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
1678 +       SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
1679 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
1680 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
1681 +       SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
1682 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
1683 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
1684 +       SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
1685 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
1686 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
1687 +       SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
1688 +            SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
1689 +
1690 +       SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
1691 +       SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
1692 +       SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
1693 +       SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
1694 +
1695 +       SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
1696 +            SSB_SPROM8_THERMAL_TRESH_SHIFT);
1697 +       SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
1698 +            SSB_SPROM8_THERMAL_OFFSET_SHIFT);
1699 +       SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
1700 +            SSB_SPROM8_TEMPDELTA_PHYCAL,
1701 +            SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
1702 +       SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
1703 +            SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
1704 +       SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
1705 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS,
1706 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
1707         sprom_extract_r458(out, in);
1708
1709         /* TODO - get remaining rev 8 stuff needed */
1710 @@ -641,7 +753,7 @@ static int sprom_extract(struct ssb_bus
1711         memset(out, 0, sizeof(*out));
1712
1713         out->revision = in[size - 1] & 0x00FF;
1714 -       ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1715 +       ssb_dbg("SPROM revision %d detected\n", out->revision);
1716         memset(out->et0mac, 0xFF, 6);           /* preset et0 and et1 mac */
1717         memset(out->et1mac, 0xFF, 6);
1718
1719 @@ -650,7 +762,7 @@ static int sprom_extract(struct ssb_bus
1720                  * number stored in the SPROM.
1721                  * Always extract r1. */
1722                 out->revision = 1;
1723 -               ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1724 +               ssb_dbg("SPROM treated as revision %d\n", out->revision);
1725         }
1726
1727         switch (out->revision) {
1728 @@ -667,9 +779,8 @@ static int sprom_extract(struct ssb_bus
1729                 sprom_extract_r8(out, in);
1730                 break;
1731         default:
1732 -               ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1733 -                          " revision %d detected. Will extract"
1734 -                          " v1\n", out->revision);
1735 +               ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
1736 +                        out->revision);
1737                 out->revision = 1;
1738                 sprom_extract_r123(out, in);
1739         }
1740 @@ -689,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_
1741         u16 *buf;
1742
1743         if (!ssb_is_sprom_available(bus)) {
1744 -               ssb_printk(KERN_ERR PFX "No SPROM available!\n");
1745 +               ssb_err("No SPROM available!\n");
1746                 return -ENODEV;
1747         }
1748         if (bus->chipco.dev) {  /* can be unavailable! */
1749 @@ -708,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_
1750         } else {
1751                 bus->sprom_offset = SSB_SPROM_BASE1;
1752         }
1753 -       ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
1754 +       ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
1755
1756         buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
1757         if (!buf)
1758 @@ -733,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_
1759                          * available for this device in some other storage */
1760                         err = ssb_fill_sprom_with_fallback(bus, sprom);
1761                         if (err) {
1762 -                               ssb_printk(KERN_WARNING PFX "WARNING: Using"
1763 -                                          " fallback SPROM failed (err %d)\n",
1764 -                                          err);
1765 +                               ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
1766 +                                        err);
1767                         } else {
1768 -                               ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1769 -                                           " revision %d provided by"
1770 -                                           " platform.\n", sprom->revision);
1771 +                               ssb_dbg("Using SPROM revision %d provided by platform\n",
1772 +                                       sprom->revision);
1773                                 err = 0;
1774                                 goto out_free;
1775                         }
1776 -                       ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
1777 -                                  " SPROM CRC (corrupt SPROM)\n");
1778 +                       ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
1779                 }
1780         }
1781         err = sprom_extract(bus, sprom, buf, bus->sprom_size);
1782 @@ -759,7 +867,6 @@ static void ssb_pci_get_boardinfo(struct
1783  {
1784         bi->vendor = bus->host_pci->subsystem_vendor;
1785         bi->type = bus->host_pci->subsystem_device;
1786 -       bi->rev = bus->host_pci->revision;
1787  }
1788
1789  int ssb_pci_get_invariants(struct ssb_bus *bus,
1790 --- a/drivers/ssb/pcmcia.c
1791 +++ b/drivers/ssb/pcmcia.c
1792 @@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb
1793
1794         return 0;
1795  error:
1796 -       ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1797 +       ssb_err("Failed to switch to core %u\n", coreidx);
1798         return err;
1799  }
1800
1801 @@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu
1802         int err;
1803
1804  #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
1805 -       ssb_printk(KERN_INFO PFX
1806 -                  "Switching to %s core, index %d\n",
1807 -                  ssb_core_name(dev->id.coreid),
1808 -                  dev->core_index);
1809 +       ssb_info("Switching to %s core, index %d\n",
1810 +                ssb_core_name(dev->id.coreid),
1811 +                dev->core_index);
1812  #endif
1813
1814         err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
1815 @@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb
1816
1817         return 0;
1818  error:
1819 -       ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
1820 +       ssb_err("Failed to switch pcmcia segment\n");
1821         return err;
1822  }
1823
1824 @@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st
1825         bool failed = 0;
1826         size_t size = SSB_PCMCIA_SPROM_SIZE;
1827
1828 -       ssb_printk(KERN_NOTICE PFX
1829 -                  "Writing SPROM. Do NOT turn off the power! "
1830 -                  "Please stand by...\n");
1831 +       ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1832         err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
1833         if (err) {
1834 -               ssb_printk(KERN_NOTICE PFX
1835 -                          "Could not enable SPROM write access.\n");
1836 +               ssb_notice("Could not enable SPROM write access\n");
1837                 return -EBUSY;
1838         }
1839 -       ssb_printk(KERN_NOTICE PFX "[ 0%%");
1840 +       ssb_notice("[ 0%%");
1841         msleep(500);
1842         for (i = 0; i < size; i++) {
1843                 if (i == size / 4)
1844 -                       ssb_printk("25%%");
1845 +                       ssb_cont("25%%");
1846                 else if (i == size / 2)
1847 -                       ssb_printk("50%%");
1848 +                       ssb_cont("50%%");
1849                 else if (i == (size * 3) / 4)
1850 -                       ssb_printk("75%%");
1851 +                       ssb_cont("75%%");
1852                 else if (i % 2)
1853 -                       ssb_printk(".");
1854 +                       ssb_cont(".");
1855                 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
1856                 if (err) {
1857 -                       ssb_printk(KERN_NOTICE PFX
1858 -                                  "Failed to write to SPROM.\n");
1859 +                       ssb_notice("Failed to write to SPROM\n");
1860                         failed = 1;
1861                         break;
1862                 }
1863         }
1864         err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
1865         if (err) {
1866 -               ssb_printk(KERN_NOTICE PFX
1867 -                          "Could not disable SPROM write access.\n");
1868 +               ssb_notice("Could not disable SPROM write access\n");
1869                 failed = 1;
1870         }
1871         msleep(500);
1872         if (!failed) {
1873 -               ssb_printk("100%% ]\n");
1874 -               ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1875 +               ssb_cont("100%% ]\n");
1876 +               ssb_notice("SPROM written\n");
1877         }
1878
1879         return failed ? -EBUSY : 0;
1880 @@ -676,14 +670,10 @@ static int ssb_pcmcia_do_get_invariants(
1881         case SSB_PCMCIA_CIS_ANTGAIN:
1882                 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1883                         "antg tpl size");
1884 -               sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
1885 -               sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
1886 -               sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
1887 -               sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
1888 -               sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
1889 -               sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
1890 -               sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
1891 -               sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
1892 +               sprom->antenna_gain.a0 = tuple->TupleData[1];
1893 +               sprom->antenna_gain.a1 = tuple->TupleData[1];
1894 +               sprom->antenna_gain.a2 = tuple->TupleData[1];
1895 +               sprom->antenna_gain.a3 = tuple->TupleData[1];
1896                 break;
1897         case SSB_PCMCIA_CIS_BFLAGS:
1898                 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
1899 @@ -704,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants(
1900         return -ENOSPC; /* continue with next entry */
1901
1902  error:
1903 -       ssb_printk(KERN_ERR PFX
1904 +       ssb_err(
1905                    "PCMCIA: Failed to fetch device invariants: %s\n",
1906                    error_description);
1907         return -ENODEV;
1908 @@ -726,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1909         res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
1910                                 ssb_pcmcia_get_mac, sprom);
1911         if (res != 0) {
1912 -               ssb_printk(KERN_ERR PFX
1913 +               ssb_err(
1914                         "PCMCIA: Failed to fetch MAC address\n");
1915                 return -ENODEV;
1916         }
1917 @@ -737,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1918         if ((res == 0) || (res == -ENOSPC))
1919                 return 0;
1920
1921 -       ssb_printk(KERN_ERR PFX
1922 +       ssb_err(
1923                         "PCMCIA: Failed to fetch device invariants\n");
1924         return -ENODEV;
1925  }
1926 @@ -847,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
1927
1928         return 0;
1929  error:
1930 -       ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
1931 +       ssb_err("Failed to initialize PCMCIA host device\n");
1932         return err;
1933  }
1934 --- a/drivers/ssb/scan.c
1935 +++ b/drivers/ssb/scan.c
1936 @@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
1937                 return "ARM 1176";
1938         case SSB_DEV_ARM_7TDMI:
1939                 return "ARM 7TDMI";
1940 +       case SSB_DEV_ARM_CM3:
1941 +               return "ARM Cortex M3";
1942         }
1943         return "UNKNOWN";
1944  }
1945 @@ -123,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d
1946                 chipid_fallback = 0x4401;
1947                 break;
1948         default:
1949 -               ssb_printk(KERN_ERR PFX
1950 -                          "PCI-ID not in fallback list\n");
1951 +               ssb_err("PCI-ID not in fallback list\n");
1952         }
1953
1954         return chipid_fallback;
1955 @@ -150,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid)
1956         case 0x4704:
1957                 return 9;
1958         default:
1959 -               ssb_printk(KERN_ERR PFX
1960 -                          "CHIPID not in nrcores fallback list\n");
1961 +               ssb_err("CHIPID not in nrcores fallback list\n");
1962         }
1963
1964         return 1;
1965 @@ -318,12 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus,
1966                         bus->chip_package = 0;
1967                 }
1968         }
1969 +       ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1970 +                bus->chip_id, bus->chip_rev, bus->chip_package);
1971         if (!bus->nr_devices)
1972                 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
1973         if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
1974 -               ssb_printk(KERN_ERR PFX
1975 -                          "More than %d ssb cores found (%d)\n",
1976 -                          SSB_MAX_NR_CORES, bus->nr_devices);
1977 +               ssb_err("More than %d ssb cores found (%d)\n",
1978 +                       SSB_MAX_NR_CORES, bus->nr_devices);
1979                 goto err_unmap;
1980         }
1981         if (bus->bustype == SSB_BUSTYPE_SSB) {
1982 @@ -365,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1983                         nr_80211_cores++;
1984                         if (nr_80211_cores > 1) {
1985                                 if (!we_support_multiple_80211_cores(bus)) {
1986 -                                       ssb_dprintk(KERN_INFO PFX "Ignoring additional "
1987 -                                                   "802.11 core\n");
1988 +                                       ssb_dbg("Ignoring additional 802.11 core\n");
1989                                         continue;
1990                                 }
1991                         }
1992 @@ -374,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1993                 case SSB_DEV_EXTIF:
1994  #ifdef CONFIG_SSB_DRIVER_EXTIF
1995                         if (bus->extif.dev) {
1996 -                               ssb_printk(KERN_WARNING PFX
1997 -                                          "WARNING: Multiple EXTIFs found\n");
1998 +                               ssb_warn("WARNING: Multiple EXTIFs found\n");
1999                                 break;
2000                         }
2001                         bus->extif.dev = dev;
2002 @@ -383,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2003                         break;
2004                 case SSB_DEV_CHIPCOMMON:
2005                         if (bus->chipco.dev) {
2006 -                               ssb_printk(KERN_WARNING PFX
2007 -                                          "WARNING: Multiple ChipCommon found\n");
2008 +                               ssb_warn("WARNING: Multiple ChipCommon found\n");
2009                                 break;
2010                         }
2011                         bus->chipco.dev = dev;
2012 @@ -393,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2013                 case SSB_DEV_MIPS_3302:
2014  #ifdef CONFIG_SSB_DRIVER_MIPS
2015                         if (bus->mipscore.dev) {
2016 -                               ssb_printk(KERN_WARNING PFX
2017 -                                          "WARNING: Multiple MIPS cores found\n");
2018 +                               ssb_warn("WARNING: Multiple MIPS cores found\n");
2019                                 break;
2020                         }
2021                         bus->mipscore.dev = dev;
2022 @@ -415,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2023                                 }
2024                         }
2025                         if (bus->pcicore.dev) {
2026 -                               ssb_printk(KERN_WARNING PFX
2027 -                                          "WARNING: Multiple PCI(E) cores found\n");
2028 +                               ssb_warn("WARNING: Multiple PCI(E) cores found\n");
2029                                 break;
2030                         }
2031                         bus->pcicore.dev = dev;
2032 --- a/drivers/ssb/sdio.c
2033 +++ b/drivers/ssb/sdio.c
2034 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
2035                         case SSB_SDIO_CIS_ANTGAIN:
2036                                 GOTO_ERROR_ON(tuple->size != 2,
2037                                               "antg tpl size");
2038 -                               sprom->antenna_gain.ghz24.a0 = tuple->data[1];
2039 -                               sprom->antenna_gain.ghz24.a1 = tuple->data[1];
2040 -                               sprom->antenna_gain.ghz24.a2 = tuple->data[1];
2041 -                               sprom->antenna_gain.ghz24.a3 = tuple->data[1];
2042 -                               sprom->antenna_gain.ghz5.a0 = tuple->data[1];
2043 -                               sprom->antenna_gain.ghz5.a1 = tuple->data[1];
2044 -                               sprom->antenna_gain.ghz5.a2 = tuple->data[1];
2045 -                               sprom->antenna_gain.ghz5.a3 = tuple->data[1];
2046 +                               sprom->antenna_gain.a0 = tuple->data[1];
2047 +                               sprom->antenna_gain.a1 = tuple->data[1];
2048 +                               sprom->antenna_gain.a2 = tuple->data[1];
2049 +                               sprom->antenna_gain.a3 = tuple->data[1];
2050                                 break;
2051                         case SSB_SDIO_CIS_BFLAGS:
2052                                 GOTO_ERROR_ON((tuple->size != 3) &&
2053 --- a/drivers/ssb/sprom.c
2054 +++ b/drivers/ssb/sprom.c
2055 @@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2056                 goto out_kfree;
2057         err = ssb_devices_freeze(bus, &freeze);
2058         if (err) {
2059 -               ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
2060 +               ssb_err("SPROM write: Could not freeze all devices\n");
2061                 goto out_unlock;
2062         }
2063         res = sprom_write(bus, sprom);
2064         err = ssb_devices_thaw(&freeze);
2065         if (err)
2066 -               ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
2067 +               ssb_err("SPROM write: Could not thaw all devices\n");
2068  out_unlock:
2069         mutex_unlock(&bus->sprom_mutex);
2070  out_kfree:
2071 --- a/drivers/ssb/ssb_private.h
2072 +++ b/drivers/ssb/ssb_private.h
2073 @@ -3,21 +3,33 @@
2074
2075  #include <linux/ssb/ssb.h>
2076  #include <linux/types.h>
2077 +#include <linux/bcm47xx_wdt.h>
2078
2079
2080  #define PFX    "ssb: "
2081
2082  #ifdef CONFIG_SSB_SILENT
2083 -# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
2084 +# define ssb_printk(fmt, ...)                                  \
2085 +       do { if (0) printk(fmt, ##__VA_ARGS__); } while (0)
2086  #else
2087 -# define ssb_printk            printk
2088 +# define ssb_printk(fmt, ...)                                  \
2089 +       printk(fmt, ##__VA_ARGS__)
2090  #endif /* CONFIG_SSB_SILENT */
2091
2092 +#define ssb_emerg(fmt, ...)    ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__)
2093 +#define ssb_err(fmt, ...)      ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__)
2094 +#define ssb_warn(fmt, ...)     ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__)
2095 +#define ssb_notice(fmt, ...)   ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__)
2096 +#define ssb_info(fmt, ...)     ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__)
2097 +#define ssb_cont(fmt, ...)     ssb_printk(KERN_CONT fmt, ##__VA_ARGS__)
2098 +
2099  /* dprintk: Debugging printk; vanishes for non-debug compilation */
2100  #ifdef CONFIG_SSB_DEBUG
2101 -# define ssb_dprintk(fmt, x...)        ssb_printk(fmt , ##x)
2102 +# define ssb_dbg(fmt, ...)                                     \
2103 +       ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__)
2104  #else
2105 -# define ssb_dprintk(fmt, x...)        do { /* nothing */ } while (0)
2106 +# define ssb_dbg(fmt, ...)                                     \
2107 +       do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0)
2108  #endif
2109
2110  #ifdef CONFIG_SSB_DEBUG
2111 @@ -207,4 +219,60 @@ static inline void b43_pci_ssb_bridge_ex
2112  }
2113  #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
2114
2115 +/* driver_chipcommon_pmu.c */
2116 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2117 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2118 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
2119 +
2120 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2121 +                                            u32 ticks);
2122 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2123 +
2124 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2125 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
2126 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2127 +#else
2128 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2129 +                                                  u32 ticks)
2130 +{
2131 +       return 0;
2132 +}
2133 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
2134 +                                                 u32 ms)
2135 +{
2136 +       return 0;
2137 +}
2138 +#endif
2139 +
2140 +#ifdef CONFIG_SSB_EMBEDDED
2141 +extern int ssb_watchdog_register(struct ssb_bus *bus);
2142 +#else /* CONFIG_SSB_EMBEDDED */
2143 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
2144 +{
2145 +       return 0;
2146 +}
2147 +#endif /* CONFIG_SSB_EMBEDDED */
2148 +
2149 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2150 +extern void ssb_extif_init(struct ssb_extif *extif);
2151 +#else
2152 +static inline void ssb_extif_init(struct ssb_extif *extif)
2153 +{
2154 +}
2155 +#endif
2156 +
2157 +#ifdef CONFIG_SSB_DRIVER_GPIO
2158 +extern int ssb_gpio_init(struct ssb_bus *bus);
2159 +extern int ssb_gpio_unregister(struct ssb_bus *bus);
2160 +#else /* CONFIG_SSB_DRIVER_GPIO */
2161 +static inline int ssb_gpio_init(struct ssb_bus *bus)
2162 +{
2163 +       return -ENOTSUPP;
2164 +}
2165 +static inline int ssb_gpio_unregister(struct ssb_bus *bus)
2166 +{
2167 +       return 0;
2168 +}
2169 +#endif /* CONFIG_SSB_DRIVER_GPIO */
2170 +
2171  #endif /* LINUX_SSB_PRIVATE_H_ */
2172 --- a/include/linux/ssb/ssb.h
2173 +++ b/include/linux/ssb/ssb.h
2174 @@ -6,8 +6,10 @@
2175  #include <linux/types.h>
2176  #include <linux/spinlock.h>
2177  #include <linux/pci.h>
2178 +#include <linux/gpio.h>
2179  #include <linux/mod_devicetable.h>
2180  #include <linux/dma-mapping.h>
2181 +#include <linux/platform_device.h>
2182
2183  #include <linux/ssb/ssb_regs.h>
2184
2185 @@ -16,19 +18,29 @@ struct pcmcia_device;
2186  struct ssb_bus;
2187  struct ssb_driver;
2188
2189 +struct ssb_sprom_core_pwr_info {
2190 +       u8 itssi_2g, itssi_5g;
2191 +       u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
2192 +       u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
2193 +};
2194 +
2195  struct ssb_sprom {
2196         u8 revision;
2197 -       u8 il0mac[6];           /* MAC address for 802.11b/g */
2198 -       u8 et0mac[6];           /* MAC address for Ethernet */
2199 -       u8 et1mac[6];           /* MAC address for 802.11a */
2200 +       u8 il0mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11b/g */
2201 +       u8 et0mac[6] __aligned(sizeof(u16));    /* MAC address for Ethernet */
2202 +       u8 et1mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11a */
2203         u8 et0phyaddr;          /* MII address for enet0 */
2204         u8 et1phyaddr;          /* MII address for enet1 */
2205         u8 et0mdcport;          /* MDIO for enet0 */
2206         u8 et1mdcport;          /* MDIO for enet1 */
2207 +       u16 dev_id;             /* Device ID overriding e.g. PCI ID */
2208         u16 board_rev;          /* Board revision number from SPROM. */
2209 +       u16 board_num;          /* Board number from SPROM. */
2210 +       u16 board_type;         /* Board type from SPROM. */
2211         u8 country_code;        /* Country Code */
2212 -       u16 leddc_on_time;      /* LED Powersave Duty Cycle On Count */
2213 -       u16 leddc_off_time;     /* LED Powersave Duty Cycle Off Count */
2214 +       char alpha2[2];         /* Country Code as two chars like EU or US */
2215 +       u8 leddc_on_time;       /* LED Powersave Duty Cycle On Count */
2216 +       u8 leddc_off_time;      /* LED Powersave Duty Cycle Off Count */
2217         u8 ant_available_a;     /* 2GHz antenna available bits (up to 4) */
2218         u8 ant_available_bg;    /* 5GHz antenna available bits (up to 4) */
2219         u16 pa0b0;
2220 @@ -47,10 +59,10 @@ struct ssb_sprom {
2221         u8 gpio1;               /* GPIO pin 1 */
2222         u8 gpio2;               /* GPIO pin 2 */
2223         u8 gpio3;               /* GPIO pin 3 */
2224 -       u16 maxpwr_bg;          /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
2225 -       u16 maxpwr_al;          /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
2226 -       u16 maxpwr_a;           /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
2227 -       u16 maxpwr_ah;          /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
2228 +       u8 maxpwr_bg;           /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
2229 +       u8 maxpwr_al;           /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
2230 +       u8 maxpwr_a;            /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
2231 +       u8 maxpwr_ah;           /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
2232         u8 itssi_a;             /* Idle TSSI Target for A-PHY */
2233         u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
2234         u8 tri2g;               /* 2.4GHz TX isolation */
2235 @@ -61,8 +73,8 @@ struct ssb_sprom {
2236         u8 txpid5gl[4];         /* 4.9 - 5.1GHz TX power index */
2237         u8 txpid5g[4];          /* 5.1 - 5.5GHz TX power index */
2238         u8 txpid5gh[4];         /* 5.5 - ...GHz TX power index */
2239 -       u8 rxpo2g;              /* 2GHz RX power offset */
2240 -       u8 rxpo5g;              /* 5GHz RX power offset */
2241 +       s8 rxpo2g;              /* 2GHz RX power offset */
2242 +       s8 rxpo5g;              /* 5GHz RX power offset */
2243         u8 rssisav2g;           /* 2GHz RSSI params */
2244         u8 rssismc2g;
2245         u8 rssismf2g;
2246 @@ -82,16 +94,13 @@ struct ssb_sprom {
2247         u16 boardflags2_hi;     /* Board flags (bits 48-63) */
2248         /* TODO store board flags in a single u64 */
2249
2250 +       struct ssb_sprom_core_pwr_info core_pwr_info[4];
2251 +
2252         /* Antenna gain values for up to 4 antennas
2253          * on each band. Values in dBm/4 (Q5.2). Negative gain means the
2254          * loss in the connectors is bigger than the gain. */
2255         struct {
2256 -               struct {
2257 -                       s8 a0, a1, a2, a3;
2258 -               } ghz24;        /* 2.4GHz band */
2259 -               struct {
2260 -                       s8 a0, a1, a2, a3;
2261 -               } ghz5;         /* 5GHz band */
2262 +               s8 a0, a1, a2, a3;
2263         } antenna_gain;
2264
2265         struct {
2266 @@ -103,14 +112,85 @@ struct ssb_sprom {
2267                 } ghz5;
2268         } fem;
2269
2270 -       /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
2271 +       u16 mcs2gpo[8];
2272 +       u16 mcs5gpo[8];
2273 +       u16 mcs5glpo[8];
2274 +       u16 mcs5ghpo[8];
2275 +       u8 opo;
2276 +
2277 +       u8 rxgainerr2ga[3];
2278 +       u8 rxgainerr5gla[3];
2279 +       u8 rxgainerr5gma[3];
2280 +       u8 rxgainerr5gha[3];
2281 +       u8 rxgainerr5gua[3];
2282 +
2283 +       u8 noiselvl2ga[3];
2284 +       u8 noiselvl5gla[3];
2285 +       u8 noiselvl5gma[3];
2286 +       u8 noiselvl5gha[3];
2287 +       u8 noiselvl5gua[3];
2288 +
2289 +       u8 regrev;
2290 +       u8 txchain;
2291 +       u8 rxchain;
2292 +       u8 antswitch;
2293 +       u16 cddpo;
2294 +       u16 stbcpo;
2295 +       u16 bw40po;
2296 +       u16 bwduppo;
2297 +
2298 +       u8 tempthresh;
2299 +       u8 tempoffset;
2300 +       u16 rawtempsense;
2301 +       u8 measpower;
2302 +       u8 tempsense_slope;
2303 +       u8 tempcorrx;
2304 +       u8 tempsense_option;
2305 +       u8 freqoffset_corr;
2306 +       u8 iqcal_swp_dis;
2307 +       u8 hw_iqcal_en;
2308 +       u8 elna2g;
2309 +       u8 elna5g;
2310 +       u8 phycal_tempdelta;
2311 +       u8 temps_period;
2312 +       u8 temps_hysteresis;
2313 +       u8 measpower1;
2314 +       u8 measpower2;
2315 +       u8 pcieingress_war;
2316 +
2317 +       /* power per rate from sromrev 9 */
2318 +       u16 cckbw202gpo;
2319 +       u16 cckbw20ul2gpo;
2320 +       u32 legofdmbw202gpo;
2321 +       u32 legofdmbw20ul2gpo;
2322 +       u32 legofdmbw205glpo;
2323 +       u32 legofdmbw20ul5glpo;
2324 +       u32 legofdmbw205gmpo;
2325 +       u32 legofdmbw20ul5gmpo;
2326 +       u32 legofdmbw205ghpo;
2327 +       u32 legofdmbw20ul5ghpo;
2328 +       u32 mcsbw202gpo;
2329 +       u32 mcsbw20ul2gpo;
2330 +       u32 mcsbw402gpo;
2331 +       u32 mcsbw205glpo;
2332 +       u32 mcsbw20ul5glpo;
2333 +       u32 mcsbw405glpo;
2334 +       u32 mcsbw205gmpo;
2335 +       u32 mcsbw20ul5gmpo;
2336 +       u32 mcsbw405gmpo;
2337 +       u32 mcsbw205ghpo;
2338 +       u32 mcsbw20ul5ghpo;
2339 +       u32 mcsbw405ghpo;
2340 +       u16 mcs32po;
2341 +       u16 legofdm40duppo;
2342 +       u8 sar2g;
2343 +       u8 sar5g;
2344  };
2345
2346  /* Information about the PCB the circuitry is soldered on. */
2347  struct ssb_boardinfo {
2348         u16 vendor;
2349         u16 type;
2350 -       u8  rev;
2351  };
2352
2353
2354 @@ -166,6 +246,7 @@ struct ssb_bus_ops {
2355  #define SSB_DEV_MINI_MACPHY    0x823
2356  #define SSB_DEV_ARM_1176       0x824
2357  #define SSB_DEV_ARM_7TDMI      0x825
2358 +#define SSB_DEV_ARM_CM3                0x82A
2359
2360  /* Vendor-ID values */
2361  #define SSB_VENDOR_BROADCOM    0x4243
2362 @@ -260,13 +341,61 @@ enum ssb_bustype {
2363  #define SSB_BOARDVENDOR_DELL   0x1028  /* Dell */
2364  #define SSB_BOARDVENDOR_HP     0x0E11  /* HP */
2365  /* board_type */
2366 +#define SSB_BOARD_BCM94301CB   0x0406
2367 +#define SSB_BOARD_BCM94301MP   0x0407
2368 +#define SSB_BOARD_BU4309       0x040A
2369 +#define SSB_BOARD_BCM94309CB   0x040B
2370 +#define SSB_BOARD_BCM4309MP    0x040C
2371 +#define SSB_BOARD_BU4306       0x0416
2372  #define SSB_BOARD_BCM94306MP   0x0418
2373  #define SSB_BOARD_BCM4309G     0x0421
2374  #define SSB_BOARD_BCM4306CB    0x0417
2375 -#define SSB_BOARD_BCM4309MP    0x040C
2376 +#define SSB_BOARD_BCM94306PC   0x0425  /* pcmcia 3.3v 4306 card */
2377 +#define SSB_BOARD_BCM94306CBSG 0x042B  /* with SiGe PA */
2378 +#define SSB_BOARD_PCSG94306    0x042D  /* with SiGe PA */
2379 +#define SSB_BOARD_BU4704SD     0x042E  /* with sdram */
2380 +#define SSB_BOARD_BCM94704AGR  0x042F  /* dual 11a/11g Router */
2381 +#define SSB_BOARD_BCM94308MP   0x0430  /* 11a-only minipci */
2382 +#define SSB_BOARD_BU4318       0x0447
2383 +#define SSB_BOARD_CB4318       0x0448
2384 +#define SSB_BOARD_MPG4318      0x0449
2385  #define SSB_BOARD_MP4318       0x044A
2386 -#define SSB_BOARD_BU4306       0x0416
2387 -#define SSB_BOARD_BU4309       0x040A
2388 +#define SSB_BOARD_SD4318       0x044B
2389 +#define SSB_BOARD_BCM94306P    0x044C  /* with SiGe */
2390 +#define SSB_BOARD_BCM94303MP   0x044E
2391 +#define SSB_BOARD_BCM94306MPM  0x0450
2392 +#define SSB_BOARD_BCM94306MPL  0x0453
2393 +#define SSB_BOARD_PC4303       0x0454  /* pcmcia */
2394 +#define SSB_BOARD_BCM94306MPLNA        0x0457
2395 +#define SSB_BOARD_BCM94306MPH  0x045B
2396 +#define SSB_BOARD_BCM94306PCIV 0x045C
2397 +#define SSB_BOARD_BCM94318MPGH 0x0463
2398 +#define SSB_BOARD_BU4311       0x0464
2399 +#define SSB_BOARD_BCM94311MC   0x0465
2400 +#define SSB_BOARD_BCM94311MCAG 0x0466
2401 +/* 4321 boards */
2402 +#define SSB_BOARD_BU4321       0x046B
2403 +#define SSB_BOARD_BU4321E      0x047C
2404 +#define SSB_BOARD_MP4321       0x046C
2405 +#define SSB_BOARD_CB2_4321     0x046D
2406 +#define SSB_BOARD_CB2_4321_AG  0x0066
2407 +#define SSB_BOARD_MC4321       0x046E
2408 +/* 4325 boards */
2409 +#define SSB_BOARD_BCM94325DEVBU        0x0490
2410 +#define SSB_BOARD_BCM94325BGABU        0x0491
2411 +#define SSB_BOARD_BCM94325SDGWB        0x0492
2412 +#define SSB_BOARD_BCM94325SDGMDL       0x04AA
2413 +#define SSB_BOARD_BCM94325SDGMDL2      0x04C6
2414 +#define SSB_BOARD_BCM94325SDGMDL3      0x04C9
2415 +#define SSB_BOARD_BCM94325SDABGWBA     0x04E1
2416 +/* 4322 boards */
2417 +#define SSB_BOARD_BCM94322MC   0x04A4
2418 +#define SSB_BOARD_BCM94322USB  0x04A8  /* dualband */
2419 +#define SSB_BOARD_BCM94322HM   0x04B0
2420 +#define SSB_BOARD_BCM94322USB2D        0x04Bf  /* single band discrete front end */
2421 +/* 4312 boards */
2422 +#define SSB_BOARD_BU4312       0x048A
2423 +#define SSB_BOARD_BCM4312MCGSG 0x04B5
2424  /* chip_package */
2425  #define SSB_CHIPPACK_BCM4712S  1       /* Small 200pin 4712 */
2426  #define SSB_CHIPPACK_BCM4712M  2       /* Medium 225pin 4712 */
2427 @@ -354,7 +483,11 @@ struct ssb_bus {
2428  #ifdef CONFIG_SSB_EMBEDDED
2429         /* Lock for GPIO register access. */
2430         spinlock_t gpio_lock;
2431 +       struct platform_device *watchdog;
2432  #endif /* EMBEDDED */
2433 +#ifdef CONFIG_SSB_DRIVER_GPIO
2434 +       struct gpio_chip gpio;
2435 +#endif /* DRIVER_GPIO */
2436
2437         /* Internal-only stuff follows. Do not touch. */
2438         struct list_head list;
2439 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2440 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2441 @@ -219,6 +219,7 @@
2442  #define SSB_CHIPCO_PMU_CTL                     0x0600 /* PMU control */
2443  #define  SSB_CHIPCO_PMU_CTL_ILP_DIV            0xFFFF0000 /* ILP div mask */
2444  #define  SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT      16
2445 +#define  SSB_CHIPCO_PMU_CTL_PLL_UPD            0x00000400
2446  #define  SSB_CHIPCO_PMU_CTL_NOILPONW           0x00000200 /* No ILP on wait */
2447  #define  SSB_CHIPCO_PMU_CTL_HTREQEN            0x00000100 /* HT req enable */
2448  #define  SSB_CHIPCO_PMU_CTL_ALPREQEN           0x00000080 /* ALP req enable */
2449 @@ -588,7 +589,10 @@ struct ssb_chipcommon {
2450         u32 status;
2451         /* Fast Powerup Delay constant */
2452         u16 fast_pwrup_delay;
2453 +       spinlock_t gpio_lock;
2454         struct ssb_chipcommon_pmu pmu;
2455 +       u32 ticks_per_ms;
2456 +       u32 max_timer_ms;
2457  };
2458
2459  static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
2460 @@ -628,8 +632,7 @@ enum ssb_clkmode {
2461  extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
2462                                      enum ssb_clkmode mode);
2463
2464 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
2465 -                                         u32 ticks);
2466 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
2467
2468  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2469
2470 @@ -642,6 +645,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
2471  u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
2472  u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2473  u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
2474 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
2475 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
2476
2477  #ifdef CONFIG_SSB_SERIAL
2478  extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
2479 @@ -661,5 +666,6 @@ enum ssb_pmu_ldo_volt_id {
2480  void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
2481                              enum ssb_pmu_ldo_volt_id id, u32 voltage);
2482  void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
2483 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
2484
2485  #endif /* LINUX_SSB_CHIPCO_H_ */
2486 --- a/include/linux/ssb/ssb_driver_extif.h
2487 +++ b/include/linux/ssb/ssb_driver_extif.h
2488 @@ -152,12 +152,16 @@
2489  /* watchdog */
2490  #define SSB_EXTIF_WATCHDOG_CLK         48000000        /* Hz */
2491
2492 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER   ((1 << 28) - 1)
2493 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS        (SSB_EXTIF_WATCHDOG_MAX_TIMER \
2494 +                                        / (SSB_EXTIF_WATCHDOG_CLK / 1000))
2495
2496
2497  #ifdef CONFIG_SSB_DRIVER_EXTIF
2498
2499  struct ssb_extif {
2500         struct ssb_device *dev;
2501 +       spinlock_t gpio_lock;
2502  };
2503
2504  static inline bool ssb_extif_available(struct ssb_extif *extif)
2505 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
2506  extern void ssb_extif_timing_init(struct ssb_extif *extif,
2507                                   unsigned long ns);
2508
2509 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2510 -                                        u32 ticks);
2511 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
2512
2513  /* Extif GPIO pin access */
2514  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
2515 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
2516  }
2517
2518  static inline
2519 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2520 -                                 u32 ticks)
2521 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
2522  {
2523  }
2524
2525 +static inline
2526 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
2527 +{
2528 +       return 0;
2529 +}
2530 +
2531 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
2532 +{
2533 +       return 0;
2534 +}
2535 +
2536 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
2537 +                                    u32 value)
2538 +{
2539 +       return 0;
2540 +}
2541 +
2542 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
2543 +                                      u32 value)
2544 +{
2545 +       return 0;
2546 +}
2547 +
2548 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
2549 +                                         u32 value)
2550 +{
2551 +       return 0;
2552 +}
2553 +
2554 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
2555 +                                        u32 value)
2556 +{
2557 +       return 0;
2558 +}
2559 +
2560 +#ifdef CONFIG_SSB_SERIAL
2561 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
2562 +                                       struct ssb_serial_port *ports)
2563 +{
2564 +       return 0;
2565 +}
2566 +#endif /* CONFIG_SSB_SERIAL */
2567 +
2568  #endif /* CONFIG_SSB_DRIVER_EXTIF */
2569  #endif /* LINUX_SSB_EXTIFCORE_H_ */
2570 --- a/include/linux/ssb/ssb_driver_gige.h
2571 +++ b/include/linux/ssb/ssb_driver_gige.h
2572 @@ -2,6 +2,7 @@
2573  #define LINUX_SSB_DRIVER_GIGE_H_
2574
2575  #include <linux/ssb/ssb.h>
2576 +#include <linux/bug.h>
2577  #include <linux/pci.h>
2578  #include <linux/spinlock.h>
2579
2580 @@ -96,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
2581         return 0;
2582  }
2583
2584 -#ifdef CONFIG_BCM47XX
2585 -#include <asm/mach-bcm47xx/nvram.h>
2586  /* Get the device MAC address */
2587 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2588 -{
2589 -       char buf[20];
2590 -       if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
2591 -               return;
2592 -       nvram_parse_macaddr(buf, macaddr);
2593 -}
2594 -#else
2595 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2596 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2597  {
2598 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
2599 +       if (!dev)
2600 +               return -ENODEV;
2601 +
2602 +       memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
2603 +       return 0;
2604  }
2605 -#endif
2606
2607  extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
2608                                           struct pci_dev *pdev);
2609 @@ -174,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
2610  {
2611         return 0;
2612  }
2613 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2614 +{
2615 +       return -ENODEV;
2616 +}
2617
2618  #endif /* CONFIG_SSB_DRIVER_GIGE */
2619  #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
2620 --- a/include/linux/ssb/ssb_driver_mips.h
2621 +++ b/include/linux/ssb/ssb_driver_mips.h
2622 @@ -41,6 +41,11 @@ void ssb_mipscore_init(struct ssb_mipsco
2623  {
2624  }
2625
2626 +static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
2627 +{
2628 +       return 0;
2629 +}
2630 +
2631  #endif /* CONFIG_SSB_DRIVER_MIPS */
2632
2633  #endif /* LINUX_SSB_MIPSCORE_H_ */
2634 --- a/include/linux/ssb/ssb_regs.h
2635 +++ b/include/linux/ssb/ssb_regs.h
2636 @@ -172,6 +172,7 @@
2637  #define SSB_SPROMSIZE_WORDS_R4         220
2638  #define SSB_SPROMSIZE_BYTES_R123       (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
2639  #define SSB_SPROMSIZE_BYTES_R4         (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
2640 +#define SSB_SPROMSIZE_WORDS_R10                230
2641  #define SSB_SPROM_BASE1                        0x1000
2642  #define SSB_SPROM_BASE31               0x0800
2643  #define SSB_SPROM_REVISION             0x007E
2644 @@ -228,6 +229,7 @@
2645  #define  SSB_SPROM1_AGAIN_BG_SHIFT     0
2646  #define  SSB_SPROM1_AGAIN_A            0xFF00  /* A-PHY */
2647  #define  SSB_SPROM1_AGAIN_A_SHIFT      8
2648 +#define SSB_SPROM1_CCODE               0x0076
2649
2650  /* SPROM Revision 2 (inherits from rev 1) */
2651  #define SSB_SPROM2_BFLHI               0x0038  /* Boardflags (high 16 bits) */
2652 @@ -267,6 +269,7 @@
2653  #define  SSB_SPROM3_OFDMGPO            0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
2654
2655  /* SPROM Revision 4 */
2656 +#define SSB_SPROM4_BOARDREV            0x0042  /* Board revision */
2657  #define SSB_SPROM4_BFLLO               0x0044  /* Boardflags (low 16 bits) */
2658  #define SSB_SPROM4_BFLHI               0x0046  /* Board Flags Hi */
2659  #define SSB_SPROM4_BFL2LO              0x0048  /* Board flags 2 (low 16 bits) */
2660 @@ -287,11 +290,11 @@
2661  #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT  5
2662  #define  SSB_SPROM4_ETHPHY_ET0M                (1<<14) /* MDIO for enet0 */
2663  #define  SSB_SPROM4_ETHPHY_ET1M                (1<<15) /* MDIO for enet1 */
2664 -#define SSB_SPROM4_ANTAVAIL            0x005D  /* Antenna available bitfields */
2665 -#define  SSB_SPROM4_ANTAVAIL_A         0x00FF  /* A-PHY bitfield */
2666 -#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   0
2667 -#define  SSB_SPROM4_ANTAVAIL_BG                0xFF00  /* B-PHY and G-PHY bitfield */
2668 -#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  8
2669 +#define SSB_SPROM4_ANTAVAIL            0x005C  /* Antenna available bitfields */
2670 +#define  SSB_SPROM4_ANTAVAIL_BG                0x00FF  /* B-PHY and G-PHY bitfield */
2671 +#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  0
2672 +#define  SSB_SPROM4_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
2673 +#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   8
2674  #define SSB_SPROM4_AGAIN01             0x005E  /* Antenna Gain (in dBm Q5.2) */
2675  #define  SSB_SPROM4_AGAIN0             0x00FF  /* Antenna 0 */
2676  #define  SSB_SPROM4_AGAIN0_SHIFT       0
2677 @@ -389,6 +392,11 @@
2678  #define  SSB_SPROM8_GPIOB_P2           0x00FF  /* Pin 2 */
2679  #define  SSB_SPROM8_GPIOB_P3           0xFF00  /* Pin 3 */
2680  #define  SSB_SPROM8_GPIOB_P3_SHIFT     8
2681 +#define SSB_SPROM8_LEDDC               0x009A
2682 +#define  SSB_SPROM8_LEDDC_ON           0xFF00  /* oncount */
2683 +#define  SSB_SPROM8_LEDDC_ON_SHIFT     8
2684 +#define  SSB_SPROM8_LEDDC_OFF          0x00FF  /* offcount */
2685 +#define  SSB_SPROM8_LEDDC_OFF_SHIFT    0
2686  #define SSB_SPROM8_ANTAVAIL            0x009C  /* Antenna available bitfields*/
2687  #define  SSB_SPROM8_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
2688  #define  SSB_SPROM8_ANTAVAIL_A_SHIFT   8
2689 @@ -404,6 +412,13 @@
2690  #define  SSB_SPROM8_AGAIN2_SHIFT       0
2691  #define  SSB_SPROM8_AGAIN3             0xFF00  /* Antenna 3 */
2692  #define  SSB_SPROM8_AGAIN3_SHIFT       8
2693 +#define SSB_SPROM8_TXRXC               0x00A2
2694 +#define  SSB_SPROM8_TXRXC_TXCHAIN      0x000f
2695 +#define  SSB_SPROM8_TXRXC_TXCHAIN_SHIFT        0
2696 +#define  SSB_SPROM8_TXRXC_RXCHAIN      0x00f0
2697 +#define  SSB_SPROM8_TXRXC_RXCHAIN_SHIFT        4
2698 +#define  SSB_SPROM8_TXRXC_SWITCH       0xff00
2699 +#define  SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
2700  #define SSB_SPROM8_RSSIPARM2G          0x00A4  /* RSSI params for 2GHz */
2701  #define  SSB_SPROM8_RSSISMF2G          0x000F
2702  #define  SSB_SPROM8_RSSISMC2G          0x00F0
2703 @@ -430,6 +445,7 @@
2704  #define  SSB_SPROM8_TRI5GH_SHIFT       8
2705  #define SSB_SPROM8_RXPO                        0x00AC  /* RX power offsets */
2706  #define  SSB_SPROM8_RXPO2G             0x00FF  /* 2GHz RX power offset */
2707 +#define  SSB_SPROM8_RXPO2G_SHIFT       0
2708  #define  SSB_SPROM8_RXPO5G             0xFF00  /* 5GHz RX power offset */
2709  #define  SSB_SPROM8_RXPO5G_SHIFT       8
2710  #define SSB_SPROM8_FEM2G               0x00AE
2711 @@ -445,10 +461,71 @@
2712  #define  SSB_SROM8_FEM_ANTSWLUT                0xF800
2713  #define  SSB_SROM8_FEM_ANTSWLUT_SHIFT  11
2714  #define SSB_SPROM8_THERMAL             0x00B2
2715 -#define SSB_SPROM8_MPWR_RAWTS          0x00B4
2716 -#define SSB_SPROM8_TS_SLP_OPT_CORRX    0x00B6
2717 -#define SSB_SPROM8_FOC_HWIQ_IQSWP      0x00B8
2718 -#define SSB_SPROM8_PHYCAL_TEMPDELTA    0x00BA
2719 +#define  SSB_SPROM8_THERMAL_OFFSET     0x00ff
2720 +#define  SSB_SPROM8_THERMAL_OFFSET_SHIFT       0
2721 +#define  SSB_SPROM8_THERMAL_TRESH      0xff00
2722 +#define  SSB_SPROM8_THERMAL_TRESH_SHIFT        8
2723 +/* Temp sense related entries */
2724 +#define SSB_SPROM8_RAWTS               0x00B4
2725 +#define  SSB_SPROM8_RAWTS_RAWTEMP      0x01ff
2726 +#define  SSB_SPROM8_RAWTS_RAWTEMP_SHIFT        0
2727 +#define  SSB_SPROM8_RAWTS_MEASPOWER    0xfe00
2728 +#define  SSB_SPROM8_RAWTS_MEASPOWER_SHIFT      9
2729 +#define SSB_SPROM8_OPT_CORRX           0x00B6
2730 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE       0x00ff
2731 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
2732 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX        0xfc00
2733 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT  10
2734 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION      0x0300
2735 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT        8
2736 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
2737 +#define SSB_SPROM8_HWIQ_IQSWP          0x00B8
2738 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR       0x000f
2739 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
2740 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP       0x0010
2741 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
2742 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL        0x0020
2743 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT  5
2744 +#define SSB_SPROM8_TEMPDELTA           0x00BC
2745 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL   0x00ff
2746 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT     0
2747 +#define  SSB_SPROM8_TEMPDELTA_PERIOD   0x0f00
2748 +#define  SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT     8
2749 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS       0xf000
2750 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
2751 +
2752 +/* There are 4 blocks with power info sharing the same layout */
2753 +#define SSB_SROM8_PWR_INFO_CORE0       0x00C0
2754 +#define SSB_SROM8_PWR_INFO_CORE1       0x00E0
2755 +#define SSB_SROM8_PWR_INFO_CORE2       0x0100
2756 +#define SSB_SROM8_PWR_INFO_CORE3       0x0120
2757 +
2758 +#define SSB_SROM8_2G_MAXP_ITSSI                0x00
2759 +#define  SSB_SPROM8_2G_MAXP            0x00FF
2760 +#define  SSB_SPROM8_2G_ITSSI           0xFF00
2761 +#define  SSB_SPROM8_2G_ITSSI_SHIFT     8
2762 +#define SSB_SROM8_2G_PA_0              0x02    /* 2GHz power amp settings */
2763 +#define SSB_SROM8_2G_PA_1              0x04
2764 +#define SSB_SROM8_2G_PA_2              0x06
2765 +#define SSB_SROM8_5G_MAXP_ITSSI                0x08    /* 5GHz ITSSI and 5.3GHz Max Power */
2766 +#define  SSB_SPROM8_5G_MAXP            0x00FF
2767 +#define  SSB_SPROM8_5G_ITSSI           0xFF00
2768 +#define  SSB_SPROM8_5G_ITSSI_SHIFT     8
2769 +#define SSB_SPROM8_5GHL_MAXP           0x0A    /* 5.2GHz and 5.8GHz Max Power */
2770 +#define  SSB_SPROM8_5GH_MAXP           0x00FF
2771 +#define  SSB_SPROM8_5GL_MAXP           0xFF00
2772 +#define  SSB_SPROM8_5GL_MAXP_SHIFT     8
2773 +#define SSB_SROM8_5G_PA_0              0x0C    /* 5.3GHz power amp settings */
2774 +#define SSB_SROM8_5G_PA_1              0x0E
2775 +#define SSB_SROM8_5G_PA_2              0x10
2776 +#define SSB_SROM8_5GL_PA_0             0x12    /* 5.2GHz power amp settings */
2777 +#define SSB_SROM8_5GL_PA_1             0x14
2778 +#define SSB_SROM8_5GL_PA_2             0x16
2779 +#define SSB_SROM8_5GH_PA_0             0x18    /* 5.8GHz power amp settings */
2780 +#define SSB_SROM8_5GH_PA_1             0x1A
2781 +#define SSB_SROM8_5GH_PA_2             0x1C
2782 +
2783 +/* TODO: Make it deprecated */
2784  #define SSB_SPROM8_MAXP_BG             0x00C0  /* Max Power 2GHz in path 1 */
2785  #define  SSB_SPROM8_MAXP_BG_MASK       0x00FF  /* Mask for Max Power 2GHz */
2786  #define  SSB_SPROM8_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
2787 @@ -473,12 +550,23 @@
2788  #define SSB_SPROM8_PA1HIB0             0x00D8  /* 5.8GHz power amp settings */
2789  #define SSB_SPROM8_PA1HIB1             0x00DA
2790  #define SSB_SPROM8_PA1HIB2             0x00DC
2791 +
2792  #define SSB_SPROM8_CCK2GPO             0x0140  /* CCK power offset */
2793  #define SSB_SPROM8_OFDM2GPO            0x0142  /* 2.4GHz OFDM power offset */
2794  #define SSB_SPROM8_OFDM5GPO            0x0146  /* 5.3GHz OFDM power offset */
2795  #define SSB_SPROM8_OFDM5GLPO           0x014A  /* 5.2GHz OFDM power offset */
2796  #define SSB_SPROM8_OFDM5GHPO           0x014E  /* 5.8GHz OFDM power offset */
2797
2798 +#define SSB_SPROM8_2G_MCSPO            0x0152
2799 +#define SSB_SPROM8_5G_MCSPO            0x0162
2800 +#define SSB_SPROM8_5GL_MCSPO           0x0172
2801 +#define SSB_SPROM8_5GH_MCSPO           0x0182
2802 +
2803 +#define SSB_SPROM8_CDDPO               0x0192
2804 +#define SSB_SPROM8_STBCPO              0x0194
2805 +#define SSB_SPROM8_BW40PO              0x0196
2806 +#define SSB_SPROM8_BWDUPPO             0x0198
2807 +
2808  /* Values for boardflags_lo read from SPROM */
2809  #define SSB_BFL_BTCOEXIST              0x0001  /* implements Bluetooth coexistance */
2810  #define SSB_BFL_PACTRL                 0x0002  /* GPIO 9 controlling the PA */
2811 --- /dev/null
2812 +++ b/include/linux/bcm47xx_wdt.h
2813 @@ -0,0 +1,19 @@
2814 +#ifndef LINUX_BCM47XX_WDT_H_
2815 +#define LINUX_BCM47XX_WDT_H_
2816 +
2817 +#include <linux/types.h>
2818 +
2819 +
2820 +struct bcm47xx_wdt {
2821 +       u32 (*timer_set)(struct bcm47xx_wdt *, u32);
2822 +       u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
2823 +       u32 max_timer_ms;
2824 +
2825 +       void *driver_data;
2826 +};
2827 +
2828 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
2829 +{
2830 +       return wdt->driver_data;
2831 +}
2832 +#endif /* LINUX_BCM47XX_WDT_H_ */
2833 --- a/drivers/net/wireless/b43/phy_n.c
2834 +++ b/drivers/net/wireless/b43/phy_n.c
2835 @@ -4259,7 +4259,8 @@ static void b43_nphy_pmu_spur_avoid(stru
2836  #endif
2837  #ifdef CONFIG_B43_SSB
2838         case B43_BUS_SSB:
2839 -               /* FIXME */
2840 +               ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
2841 +                                           avoid);
2842                 break;
2843  #endif
2844         }