kernel: refresh patches on linux 3.18

[openwrt.git] / target / linux / ar71xx / patches-3.18 / 707-MIPS-ath79-add-support-for-QCA953x-SoC.patch

diff --git a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index be4f547..f8b1264 100644 (file)
--- a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -22,7 +22,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 
 --- a/arch/mips/ath79/Kconfig
 +++ b/arch/mips/ath79/Kconfig
-@@ -1194,6 +1194,10 @@ config SOC_AR934X
+@@ -1205,6 +1205,10 @@ config SOC_AR934X
        select PCI_AR724X if PCI
        def_bool n
  
@@ -33,7 +33,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  config SOC_QCA955X
        select HW_HAS_PCI
        select PCI_AR724X if PCI
-@@ -1236,7 +1240,7 @@ config ATH79_DEV_USB
+@@ -1247,7 +1251,7 @@ config ATH79_DEV_USB
        def_bool n
  
  config ATH79_DEV_WMAC
@@ -44,7 +44,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  config ATH79_NVRAM
 --- a/arch/mips/ath79/clock.c
 +++ b/arch/mips/ath79/clock.c
-@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(void)
+@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
        iounmap(dpll_base);
  }
  
@@ -177,7 +177,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
                platform_device_register(&ath79_uart_device);
 --- a/arch/mips/ath79/dev-usb.c
 +++ b/arch/mips/ath79/dev-usb.c
-@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void)
+@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
                           &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  }
  
@@ -228,7 +228,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  {
        return ath79_soc_rev;
  }
-@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(void)
+@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
                ath79_wmac_data.is_clk_25mhz = true;
  
        if (ath79_soc_rev == 1)
@@ -237,8 +237,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  
        ath79_wmac_data.external_reset = ar933x_wmac_reset;
  }
-@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void)
-       ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
+@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
+               ath79_wmac_data.is_clk_25mhz = true;
  }
  
 +static void qca953x_wmac_setup(void)
@@ -264,7 +264,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  static void qca955x_wmac_setup(void)
  {
        u32 t;
-@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
                ar933x_wmac_setup();
        else if (soc_is_ar934x())
                ar934x_wmac_setup();
@@ -286,7 +286,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
                _prom_putchar = prom_putchar_ar71xx;
 --- a/arch/mips/ath79/gpio.c
 +++ b/arch/mips/ath79/gpio.c
-@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_function_reg(void)
+@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func
            soc_is_ar913x() ||
            soc_is_ar933x())
                reg = AR71XX_GPIO_REG_FUNC;
@@ -295,7 +295,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
                reg = AR934X_GPIO_REG_FUNC;
        else
                BUG();
-@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(unsigned gpio, u8 val)
+@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns
        unsigned int reg;
        u32 t, s;
  
@@ -324,7 +324,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
        }
 --- a/arch/mips/ath79/irq.c
 +++ b/arch/mips/ath79/irq.c
-@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(void)
+@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
        else if (soc_is_ar724x() ||
                 soc_is_ar933x() ||
                 soc_is_ar934x() ||
@@ -405,7 +405,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  }
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
-@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type(void)
+@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
        u32 major;
        u32 minor;
        u32 rev = 0;
@@ -413,7 +413,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  
        id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
        major = id & REV_ID_MAJOR_MASK;
-@@ -152,6 +153,16 @@ static void __init ath79_detect_sys_type(void)
+@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
                rev = id & AR934X_REV_ID_REVISION_MASK;
                break;
  
@@ -430,7 +430,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
        case REV_ID_MAJOR_QCA9556:
                ath79_soc = ATH79_SOC_QCA9556;
                chip = "9556";
-@@ -170,7 +181,7 @@ static void __init ath79_detect_sys_type(void)
+@@ -169,7 +180,7 @@ static void __init ath79_detect_sys_type
  
        ath79_soc_rev = rev;