X-Git-Url: https://git.archive.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Fipq806x%2Fpatches-3.18%2F112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch;h=4c53d5089f624c068816d1020d540046001be4ff;hb=1617ac941b6451cc2099e91aa6d8834a6edb3239;hp=bdc91fb6b7b5bb4187a8a50e0f8972a9fc5d2ed6;hpb=8bf35bef0833f8bdc3a6fe9c9f5bbc52f313cb48;p=openwrt.git

diff --git a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index bdc91fb6b7..4c53d5089f 100644
--- a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -15,14 +15,15 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -35,6 +35,22 @@
+@@ -35,6 +35,24 @@
  				bias-disable;
  			};
  
 +			pcie0_pins: pcie0_pinmux {
 +				mux {
 +					pins = "gpio3";
-+					drive-strength = <2>;
++					function = "pcie1_rst";
++					drive-strength = <12>;
 +					bias-disable;
 +				};
 +			};
@@ -30,7 +31,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +			pcie1_pins: pcie1_pinmux {
 +				mux {
 +					pins = "gpio48";
-+					drive-strength = <2>;
++					function = "pcie2_rst";
++					drive-strength = <12>;
 +					bias-disable;
 +				};
 +			};
@@ -38,7 +40,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  			spi_pins: spi_pins {
  				mux {
  					pins = "gpio18", "gpio19", "gpio21";
-@@ -138,5 +154,19 @@
+@@ -115,5 +133,19 @@
  		usb30@1 {
  			status = "ok";
  		};
@@ -60,14 +62,15 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  };
 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -30,6 +30,30 @@
+@@ -30,6 +30,33 @@
  				bias-disable;
  			};
  
 +			pcie0_pins: pcie0_pinmux {
 +				mux {
 +					pins = "gpio3";
-+					drive-strength = <2>;
++					function = "pcie1_rst";
++					drive-strength = <12>;
 +					bias-disable;
 +				};
 +			};
@@ -75,7 +78,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +			pcie1_pins: pcie1_pinmux {
 +				mux {
 +					pins = "gpio48";
-+					drive-strength = <2>;
++					function = "pcie2_rst";
++					drive-strength = <12>;
 +					bias-disable;
 +				};
 +			};
@@ -83,7 +87,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +			pcie2_pins: pcie2_pinmux {
 +				mux {
 +					pins = "gpio63";
-+					drive-strength = <2>;
++					function = "pcie3_rst";
++					drive-strength = <12>;
 +					bias-disable;
 +				};
 +			};
@@ -91,7 +96,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  			spi_pins: spi_pins {
  				mux {
  					pins = "gpio18", "gpio19", "gpio21";
-@@ -128,5 +152,26 @@
+@@ -128,5 +155,26 @@
  		usb30@1 {
  			status = "ok";
  		};
@@ -129,8 +134,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  
  / {
  	model = "Qualcomm IPQ8064";
-@@ -306,6 +308,129 @@
- 			#reset-cells = <1>;
+@@ -311,6 +313,129 @@
+ 			reg = <0x01200600 0x100>;
  		};
  
 +		pcie0: pci@1b500000 {
@@ -147,8 +152,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +			#address-cells = <3>;
 +			#size-cells = <2>;
 +
-+			ranges = <0x81000000 0 0	  0x0fe00000 0 0x00100000   /* downstream I/O */
-+				  0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
++			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
++				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 +
 +			interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 +			interrupt-names = "msi";
@@ -188,8 +193,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +			#address-cells = <3>;
 +			#size-cells = <2>;
 +
-+			ranges = <0x81000000 0 0	  0x31e00000 0 0x00100000   /* downstream I/O */
-+				  0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
++			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
++				  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 +
 +			interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 +			interrupt-names = "msi";
@@ -229,8 +234,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +			#address-cells = <3>;
 +			#size-cells = <2>;
 +
-+			ranges = <0x81000000 0 0	  0x35e00000 0 0x00100000   /* downstream I/O */
-+				  0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
++			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
++				  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 +
 +			interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 +			interrupt-names = "msi";