X-Git-Url: https://git.archive.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Fgeneric%2Fpatches-3.14%2F025-bcma_backport.patch;h=436c1cf363e25a5e3e364c74e43296b6c5757716;hb=6e4472e69e89aa56ad8c0e6f90415a2b8da36eba;hp=1c4495f7e1177c0cbda78e47c334009200572e55;hpb=b0270c8109056df626a0af0a8c7a45e62eafa2bd;p=15.05%2Fopenwrt.git diff --git a/target/linux/generic/patches-3.14/025-bcma_backport.patch b/target/linux/generic/patches-3.14/025-bcma_backport.patch index 1c4495f7e1..436c1cf363 100644 --- a/target/linux/generic/patches-3.14/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.14/025-bcma_backport.patch @@ -1,6 +1,9 @@ --- a/drivers/bcma/Makefile +++ b/drivers/bcma/Makefile -@@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver +@@ -1,8 +1,10 @@ + bcma-y += main.o scan.o core.o sprom.o + bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o ++bcma-y += driver_chipcommon_b.o bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o bcma-y += driver_pci.o @@ -8,6 +11,17 @@ bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o +--- a/drivers/bcma/driver_chipcommon.c ++++ b/drivers/bcma/driver_chipcommon.c +@@ -339,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma + return; + } + +- irq = bcma_core_irq(cc->core); ++ irq = bcma_core_irq(cc->core, 0); + + /* Determine the registers of the UARTs */ + cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); --- a/drivers/bcma/driver_chipcommon_pmu.c +++ b/drivers/bcma/driver_chipcommon_pmu.c @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct @@ -21,11 +35,46 @@ case BCMA_CHIP_ID_BCM43428: --- a/drivers/bcma/driver_gpio.c +++ b/drivers/bcma/driver_gpio.c -@@ -218,7 +218,15 @@ int bcma_gpio_init(struct bcma_drv_cc *c - #if IS_BUILTIN(CONFIG_BCMA_HOST_SOC) +@@ -76,7 +76,7 @@ static void bcma_gpio_free(struct gpio_c + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); + } + +-#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC) ++#if IS_BUILTIN(CONFIG_BCM47XX) + static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) + { + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); +@@ -152,7 +152,7 @@ static int bcma_gpio_irq_domain_init(str + handle_simple_irq); + } + +- hwirq = bcma_core_irq(cc->core); ++ hwirq = bcma_core_irq(cc->core, 0); + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio", + cc); + if (err) +@@ -183,7 +183,7 @@ static void bcma_gpio_irq_domain_exit(st + return; + + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO); +- free_irq(bcma_core_irq(cc->core), cc); ++ free_irq(bcma_core_irq(cc->core, 0), cc); + for (gpio = 0; gpio < chip->ngpio; gpio++) { + int irq = irq_find_mapping(cc->irq_domain, gpio); + +@@ -215,10 +215,22 @@ int bcma_gpio_init(struct bcma_drv_cc *c + chip->set = bcma_gpio_set_value; + chip->direction_input = bcma_gpio_direction_input; + chip->direction_output = bcma_gpio_direction_output; +-#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC) ++#if IS_BUILTIN(CONFIG_BCM47XX) chip->to_irq = bcma_gpio_to_irq; #endif - chip->ngpio = 16; ++#if IS_BUILTIN(CONFIG_OF) ++ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) ++ chip->of_node = cc->core->dev.of_node; ++#endif + switch (cc->core->bus->chipinfo.id) { + case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: @@ -38,6 +87,33 @@ /* There is just one SoC in one device and its GPIO addresses should be * deterministic to address them more easily. The other buses could get * a random base number. */ +@@ -243,5 +255,6 @@ int bcma_gpio_init(struct bcma_drv_cc *c + int bcma_gpio_unregister(struct bcma_drv_cc *cc) + { + bcma_gpio_irq_domain_exit(cc); +- return gpiochip_remove(&cc->gpio); ++ gpiochip_remove(&cc->gpio); ++ return 0; + } +--- a/drivers/bcma/driver_pci_host.c ++++ b/drivers/bcma/driver_pci_host.c +@@ -593,7 +593,7 @@ int bcma_core_pci_plat_dev_init(struct p + pr_info("PCI: Fixing up device %s\n", pci_name(dev)); + + /* Fix up interrupt lines */ +- dev->irq = bcma_core_irq(pc_host->pdev->core); ++ dev->irq = bcma_core_irq(pc_host->pdev->core, 0); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + + readrq = pcie_get_readrq(dev); +@@ -617,6 +617,6 @@ int bcma_core_pci_pcibios_map_irq(const + + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, + pci_ops); +- return bcma_core_irq(pc_host->pdev->core); ++ return bcma_core_irq(pc_host->pdev->core, 0); + } + EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); --- /dev/null +++ b/drivers/bcma/driver_pcie2.c @@ -0,0 +1,175 @@ @@ -218,26 +294,301 @@ +} --- a/drivers/bcma/host_pci.c +++ b/drivers/bcma/host_pci.c -@@ -279,6 +279,8 @@ static const struct pci_device_id bcma_p +@@ -208,6 +208,9 @@ static int bcma_host_pci_probe(struct pc + bus->boardinfo.vendor = bus->host_pci->subsystem_vendor; + bus->boardinfo.type = bus->host_pci->subsystem_device; + ++ /* Initialize struct, detect chip */ ++ bcma_init_bus(bus); ++ + /* Register */ + err = bcma_bus_register(bus); + if (err) +@@ -272,14 +275,18 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc + static const struct pci_device_id bcma_pci_bridge_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) }, +- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, /* 0xa8d8 */ + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) }, { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) }, { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) }, { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */ ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */ { 0, }, }; + MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl); --- a/drivers/bcma/main.c +++ b/drivers/bcma/main.c -@@ -132,6 +132,7 @@ static int bcma_register_cores(struct bc +@@ -10,6 +10,8 @@ + #include + #include + #include ++#include ++#include + + MODULE_DESCRIPTION("Broadcom's specific AMBA driver"); + MODULE_LICENSE("GPL"); +@@ -120,56 +122,195 @@ static void bcma_release_core_dev(struct + kfree(core); + } + +-static int bcma_register_cores(struct bcma_bus *bus) ++static bool bcma_is_core_needed_early(u16 core_id) ++{ ++ switch (core_id) { ++ case BCMA_CORE_NS_NAND: ++ case BCMA_CORE_NS_QSPI: ++ return true; ++ } ++ ++ return false; ++} ++ ++#if defined(CONFIG_OF) && defined(CONFIG_OF_ADDRESS) ++static struct device_node *bcma_of_find_child_device(struct platform_device *parent, ++ struct bcma_device *core) ++{ ++ struct device_node *node; ++ u64 size; ++ const __be32 *reg; ++ ++ if (!parent || !parent->dev.of_node) ++ return NULL; ++ ++ for_each_child_of_node(parent->dev.of_node, node) { ++ reg = of_get_address(node, 0, &size, NULL); ++ if (!reg) ++ continue; ++ if (of_translate_address(node, reg) == core->addr) ++ return node; ++ } ++ return NULL; ++} ++ ++static int bcma_of_irq_parse(struct platform_device *parent, ++ struct bcma_device *core, ++ struct of_phandle_args *out_irq, int num) ++{ ++ __be32 laddr[1]; ++ int rc; ++ ++ if (core->dev.of_node) { ++ rc = of_irq_parse_one(core->dev.of_node, num, out_irq); ++ if (!rc) ++ return rc; ++ } ++ ++ out_irq->np = parent->dev.of_node; ++ out_irq->args_count = 1; ++ out_irq->args[0] = num; ++ ++ laddr[0] = cpu_to_be32(core->addr); ++ return of_irq_parse_raw(laddr, out_irq); ++} ++ ++static unsigned int bcma_of_get_irq(struct platform_device *parent, ++ struct bcma_device *core, int num) ++{ ++ struct of_phandle_args out_irq; ++ int ret; ++ ++ if (!parent || !parent->dev.of_node) ++ return 0; ++ ++ ret = bcma_of_irq_parse(parent, core, &out_irq, num); ++ if (ret) { ++ bcma_debug(core->bus, "bcma_of_get_irq() failed with rc=%d\n", ++ ret); ++ return 0; ++ } ++ ++ return irq_create_of_mapping(&out_irq); ++} ++ ++static void bcma_of_fill_device(struct platform_device *parent, ++ struct bcma_device *core) ++{ ++ struct device_node *node; ++ ++ node = bcma_of_find_child_device(parent, core); ++ if (node) ++ core->dev.of_node = node; ++ ++ core->irq = bcma_of_get_irq(parent, core, 0); ++} ++#else ++static void bcma_of_fill_device(struct platform_device *parent, ++ struct bcma_device *core) ++{ ++} ++static inline unsigned int bcma_of_get_irq(struct platform_device *parent, ++ struct bcma_device *core, int num) ++{ ++ return 0; ++} ++#endif /* CONFIG_OF */ ++ ++unsigned int bcma_core_irq(struct bcma_device *core, int num) ++{ ++ struct bcma_bus *bus = core->bus; ++ unsigned int mips_irq; ++ ++ switch (bus->hosttype) { ++ case BCMA_HOSTTYPE_PCI: ++ return bus->host_pci->irq; ++ case BCMA_HOSTTYPE_SOC: ++ if (bus->drv_mips.core && num == 0) { ++ mips_irq = bcma_core_mips_irq(core); ++ return mips_irq <= 4 ? mips_irq + 2 : 0; ++ } ++ if (bus->host_pdev) ++ return bcma_of_get_irq(bus->host_pdev, core, num); ++ return 0; ++ case BCMA_HOSTTYPE_SDIO: ++ return 0; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcma_core_irq); ++ ++void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core) ++{ ++ core->dev.release = bcma_release_core_dev; ++ core->dev.bus = &bcma_bus_type; ++ dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index); ++ ++ switch (bus->hosttype) { ++ case BCMA_HOSTTYPE_PCI: ++ core->dev.parent = &bus->host_pci->dev; ++ core->dma_dev = &bus->host_pci->dev; ++ core->irq = bus->host_pci->irq; ++ break; ++ case BCMA_HOSTTYPE_SOC: ++ core->dev.dma_mask = &core->dev.coherent_dma_mask; ++ if (bus->host_pdev) { ++ core->dma_dev = &bus->host_pdev->dev; ++ core->dev.parent = &bus->host_pdev->dev; ++ bcma_of_fill_device(bus->host_pdev, core); ++ } else { ++ core->dma_dev = &core->dev; ++ } ++ break; ++ case BCMA_HOSTTYPE_SDIO: ++ break; ++ } ++} ++ ++static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core) ++{ ++ int err; ++ ++ err = device_register(&core->dev); ++ if (err) { ++ bcma_err(bus, "Could not register dev for core 0x%03X\n", ++ core->id.id); ++ put_device(&core->dev); ++ return; ++ } ++ core->dev_registered = true; ++} ++ ++static int bcma_register_devices(struct bcma_bus *bus) + { + struct bcma_device *core; +- int err, dev_id = 0; ++ int err; + + list_for_each_entry(core, &bus->cores, list) { + /* We support that cores ourself */ + switch (core->id.id) { + case BCMA_CORE_4706_CHIPCOMMON: case BCMA_CORE_CHIPCOMMON: ++ case BCMA_CORE_NS_CHIPCOMMON_B: case BCMA_CORE_PCI: case BCMA_CORE_PCIE: + case BCMA_CORE_PCIE2: case BCMA_CORE_MIPS_74K: case BCMA_CORE_4706_MAC_GBIT_COMMON: continue; -@@ -281,6 +282,13 @@ int bcma_bus_register(struct bcma_bus *b + } + ++ /* Early cores were already registered */ ++ if (bcma_is_core_needed_early(core->id.id)) ++ continue; ++ + /* Only first GMAC core on BCM4706 is connected and working */ + if (core->id.id == BCMA_CORE_4706_MAC_GBIT && + core->core_unit > 0) + continue; + +- core->dev.release = bcma_release_core_dev; +- core->dev.bus = &bcma_bus_type; +- dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id); +- +- switch (bus->hosttype) { +- case BCMA_HOSTTYPE_PCI: +- core->dev.parent = &bus->host_pci->dev; +- core->dma_dev = &bus->host_pci->dev; +- core->irq = bus->host_pci->irq; +- break; +- case BCMA_HOSTTYPE_SOC: +- core->dev.dma_mask = &core->dev.coherent_dma_mask; +- core->dma_dev = &core->dev; +- break; +- case BCMA_HOSTTYPE_SDIO: +- break; +- } +- +- err = device_register(&core->dev); +- if (err) { +- bcma_err(bus, +- "Could not register dev for core 0x%03X\n", +- core->id.id); +- put_device(&core->dev); +- continue; +- } +- core->dev_registered = true; +- dev_id++; ++ bcma_register_core(bus, core); + } + + #ifdef CONFIG_BCMA_DRIVER_MIPS +@@ -246,6 +387,12 @@ int bcma_bus_register(struct bcma_bus *b + bcma_core_chipcommon_early_init(&bus->drv_cc); + } + ++ /* Cores providing flash access go before SPROM init */ ++ list_for_each_entry(core, &bus->cores, list) { ++ if (bcma_is_core_needed_early(core->id.id)) ++ bcma_register_core(bus, core); ++ } ++ + /* Try to get SPROM */ + err = bcma_sprom_get(bus); + if (err == -ENOENT) { +@@ -260,6 +407,13 @@ int bcma_bus_register(struct bcma_bus *b + bcma_core_chipcommon_init(&bus->drv_cc); + } + ++ /* Init CC core */ ++ core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B); ++ if (core) { ++ bus->drv_cc_b.core = core; ++ bcma_core_chipcommon_b_init(&bus->drv_cc_b); ++ } ++ + /* Init MIPS core */ + core = bcma_find_core(bus, BCMA_CORE_MIPS_74K); + if (core) { +@@ -281,6 +435,13 @@ int bcma_bus_register(struct bcma_bus *b bcma_core_pci_init(&bus->drv_pci[1]); } @@ -251,6 +602,53 @@ /* Init GBIT MAC COMMON core */ core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON); if (core) { +@@ -289,7 +450,7 @@ int bcma_bus_register(struct bcma_bus *b + } + + /* Register found cores */ +- bcma_register_cores(bus); ++ bcma_register_devices(bus); + + bcma_info(bus, "Bus registered\n"); + +@@ -307,6 +468,8 @@ void bcma_bus_unregister(struct bcma_bus + else if (err) + bcma_err(bus, "Can not unregister GPIO driver: %i\n", err); + ++ bcma_core_chipcommon_b_free(&bus->drv_cc_b); ++ + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K); + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE); + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON); +@@ -326,8 +489,6 @@ int __init bcma_bus_early_register(struc + struct bcma_device *core; + struct bcma_device_id match; + +- bcma_init_bus(bus); +- + match.manuf = BCMA_MANUF_BCM; + match.id = bcma_cc_core_id(bus); + match.class = BCMA_CL_SIM; +@@ -486,6 +647,11 @@ static int __init bcma_modinit(void) + if (err) + return err; + ++ err = bcma_host_soc_register_driver(); ++ if (err) { ++ pr_err("SoC host initialization failed\n"); ++ err = 0; ++ } + #ifdef CONFIG_BCMA_HOST_PCI + err = bcma_host_pci_init(); + if (err) { +@@ -503,6 +669,7 @@ static void __exit bcma_modexit(void) + #ifdef CONFIG_BCMA_HOST_PCI + bcma_host_pci_exit(); + #endif ++ bcma_host_soc_unregister_driver(); + bus_unregister(&bcma_bus_type); + } + module_exit(bcma_modexit) --- a/drivers/bcma/sprom.c +++ b/drivers/bcma/sprom.c @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_ @@ -327,6 +725,35 @@ #include #include #include /* SPROM sharing */ +@@ -72,17 +73,17 @@ struct bcma_host_ops { + /* Core-ID values. */ + #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */ + #define BCMA_CORE_4706_CHIPCOMMON 0x500 +-#define BCMA_CORE_PCIEG2 0x501 +-#define BCMA_CORE_DMA 0x502 +-#define BCMA_CORE_SDIO3 0x503 +-#define BCMA_CORE_USB20 0x504 +-#define BCMA_CORE_USB30 0x505 +-#define BCMA_CORE_A9JTAG 0x506 +-#define BCMA_CORE_DDR23 0x507 +-#define BCMA_CORE_ROM 0x508 +-#define BCMA_CORE_NAND 0x509 +-#define BCMA_CORE_QSPI 0x50A +-#define BCMA_CORE_CHIPCOMMON_B 0x50B ++#define BCMA_CORE_NS_PCIEG2 0x501 ++#define BCMA_CORE_NS_DMA 0x502 ++#define BCMA_CORE_NS_SDIO3 0x503 ++#define BCMA_CORE_NS_USB20 0x504 ++#define BCMA_CORE_NS_USB30 0x505 ++#define BCMA_CORE_NS_A9JTAG 0x506 ++#define BCMA_CORE_NS_DDR23 0x507 ++#define BCMA_CORE_NS_ROM 0x508 ++#define BCMA_CORE_NS_NAND 0x509 ++#define BCMA_CORE_NS_QSPI 0x50A ++#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B + #define BCMA_CORE_4706_SOC_RAM 0x50E + #define BCMA_CORE_ARMCA9 0x510 + #define BCMA_CORE_4706_MAC_GBIT 0x52D @@ -157,6 +158,9 @@ struct bcma_host_ops { /* Chip IDs of PCIe devices */ #define BCMA_CHIP_ID_BCM4313 0x4313 @@ -337,14 +764,62 @@ #define BCMA_CHIP_ID_BCM43224 43224 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa -@@ -333,6 +337,7 @@ struct bcma_bus { +@@ -263,7 +267,7 @@ struct bcma_device { + u8 core_unit; + + u32 addr; +- u32 addr1; ++ u32 addr_s[8]; + u32 wrap; + + void __iomem *io_addr; +@@ -319,6 +323,8 @@ struct bcma_bus { + struct pci_dev *host_pci; + /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */ + struct sdio_func *host_sdio; ++ /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */ ++ struct platform_device *host_pdev; + }; + + struct bcma_chipinfo chipinfo; +@@ -328,11 +334,12 @@ struct bcma_bus { + struct bcma_device *mapped_core; + struct list_head cores; + u8 nr_cores; +- u8 init_done:1; + u8 num; struct bcma_drv_cc drv_cc; ++ struct bcma_drv_cc_b drv_cc_b; struct bcma_drv_pci drv_pci[2]; + struct bcma_drv_pcie2 drv_pcie2; struct bcma_drv_mips drv_mips; struct bcma_drv_gmac_cmn drv_gmac_cmn; +@@ -440,4 +447,6 @@ extern u32 bcma_chipco_pll_read(struct b + #define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */ + extern u32 bcma_core_dma_translation(struct bcma_device *core); + ++extern unsigned int bcma_core_irq(struct bcma_device *core, int num); ++ + #endif /* LINUX_BCMA_H_ */ +--- a/include/linux/bcma/bcma_driver_mips.h ++++ b/include/linux/bcma/bcma_driver_mips.h +@@ -43,12 +43,12 @@ struct bcma_drv_mips { + extern void bcma_core_mips_init(struct bcma_drv_mips *mcore); + extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore); + +-extern unsigned int bcma_core_irq(struct bcma_device *core); ++extern unsigned int bcma_core_mips_irq(struct bcma_device *dev); + #else + static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { } + static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { } + +-static inline unsigned int bcma_core_irq(struct bcma_device *core) ++static inline unsigned int bcma_core_mips_irq(struct bcma_device *dev) + { + return 0; + } --- /dev/null +++ b/include/linux/bcma/bcma_driver_pcie2.h @@ -0,0 +1,158 @@ @@ -506,3 +981,626 @@ +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2); + +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */ +--- a/drivers/bcma/scan.c ++++ b/drivers/bcma/scan.c +@@ -32,17 +32,17 @@ static const struct bcma_device_id_name + { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" }, + { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" }, + { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" }, +- { BCMA_CORE_PCIEG2, "PCIe Gen 2" }, +- { BCMA_CORE_DMA, "DMA" }, +- { BCMA_CORE_SDIO3, "SDIO3" }, +- { BCMA_CORE_USB20, "USB 2.0" }, +- { BCMA_CORE_USB30, "USB 3.0" }, +- { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" }, +- { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" }, +- { BCMA_CORE_ROM, "ROM" }, +- { BCMA_CORE_NAND, "NAND flash controller" }, +- { BCMA_CORE_QSPI, "SPI flash controller" }, +- { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" }, ++ { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" }, ++ { BCMA_CORE_NS_DMA, "DMA" }, ++ { BCMA_CORE_NS_SDIO3, "SDIO3" }, ++ { BCMA_CORE_NS_USB20, "USB 2.0" }, ++ { BCMA_CORE_NS_USB30, "USB 3.0" }, ++ { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" }, ++ { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" }, ++ { BCMA_CORE_NS_ROM, "ROM" }, ++ { BCMA_CORE_NS_NAND, "NAND flash controller" }, ++ { BCMA_CORE_NS_QSPI, "SPI flash controller" }, ++ { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" }, + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" }, + { BCMA_CORE_AMEMC, "AMEMC (DDR)" }, + { BCMA_CORE_ALTA, "ALTA (I2S)" }, +@@ -276,7 +276,7 @@ static int bcma_get_next_core(struct bcm + struct bcma_device *core) + { + u32 tmp; +- u8 i, j; ++ u8 i, j, k; + s32 cia, cib; + u8 ports[2], wrappers[2]; + +@@ -314,6 +314,7 @@ static int bcma_get_next_core(struct bcm + /* Some specific cores don't need wrappers */ + switch (core->id.id) { + case BCMA_CORE_4706_MAC_GBIT_COMMON: ++ case BCMA_CORE_NS_CHIPCOMMON_B: + /* Not used yet: case BCMA_CORE_OOB_ROUTER: */ + break; + default: +@@ -367,6 +368,7 @@ static int bcma_get_next_core(struct bcm + core->addr = tmp; + + /* get & parse slave ports */ ++ k = 0; + for (i = 0; i < ports[1]; i++) { + for (j = 0; ; j++) { + tmp = bcma_erom_get_addr_desc(bus, eromptr, +@@ -376,9 +378,9 @@ static int bcma_get_next_core(struct bcm + /* pr_debug("erom: slave port %d " + * "has %d descriptors\n", i, j); */ + break; +- } else { +- if (i == 0 && j == 0) +- core->addr1 = tmp; ++ } else if (k < ARRAY_SIZE(core->addr_s)) { ++ core->addr_s[k] = tmp; ++ k++; + } + } + } +@@ -421,10 +423,13 @@ static int bcma_get_next_core(struct bcm + core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE); + if (!core->io_addr) + return -ENOMEM; +- core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE); +- if (!core->io_wrap) { +- iounmap(core->io_addr); +- return -ENOMEM; ++ if (core->wrap) { ++ core->io_wrap = ioremap_nocache(core->wrap, ++ BCMA_CORE_SIZE); ++ if (!core->io_wrap) { ++ iounmap(core->io_addr); ++ return -ENOMEM; ++ } + } + } + return 0; +@@ -434,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus) + { + s32 tmp; + struct bcma_chipinfo *chipinfo = &(bus->chipinfo); +- +- if (bus->init_done) +- return; ++ char chip_id[8]; + + INIT_LIST_HEAD(&bus->cores); + bus->nr_cores = 0; +@@ -447,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus) + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT; + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT; + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT; +- bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n", +- chipinfo->id, chipinfo->rev, chipinfo->pkg); + +- bus->init_done = true; ++ snprintf(chip_id, ARRAY_SIZE(chip_id), ++ (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id); ++ bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n", ++ chip_id, chipinfo->rev, chipinfo->pkg); + } + + int bcma_bus_scan(struct bcma_bus *bus) +@@ -460,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus) + + int err, core_num = 0; + +- bcma_init_bus(bus); +- + erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM); + if (bus->hosttype == BCMA_HOSTTYPE_SOC) { + eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE); +@@ -503,6 +505,7 @@ int bcma_bus_scan(struct bcma_bus *bus) + bus->nr_cores++; + other_core = bcma_find_core_reverse(bus, core->id.id); + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1; ++ bcma_prepare_core(bus, core); + + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", + core->core_index, bcma_device_name(&core->id), +--- a/drivers/bcma/host_soc.c ++++ b/drivers/bcma/host_soc.c +@@ -7,6 +7,9 @@ + + #include "bcma_private.h" + #include "scan.h" ++#include ++#include ++#include + #include + #include + +@@ -134,12 +137,16 @@ static void bcma_host_soc_block_write(st + + static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset) + { ++ if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n")) ++ return ~0; + return readl(core->io_wrap + offset); + } + + static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset, + u32 value) + { ++ if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n")) ++ return; + writel(value, core->io_wrap + offset); + } + +@@ -161,7 +168,6 @@ static const struct bcma_host_ops bcma_h + int __init bcma_host_soc_register(struct bcma_soc *soc) + { + struct bcma_bus *bus = &soc->bus; +- int err; + + /* iomap only first core. We have to read some register on this core + * to scan the bus. +@@ -173,11 +179,100 @@ int __init bcma_host_soc_register(struct + /* Host specific */ + bus->hosttype = BCMA_HOSTTYPE_SOC; + bus->ops = &bcma_host_soc_ops; ++ bus->host_pdev = NULL; + +- /* Register */ ++ /* Initialize struct, detect chip */ ++ bcma_init_bus(bus); ++ ++ return 0; ++} ++ ++int __init bcma_host_soc_init(struct bcma_soc *soc) ++{ ++ struct bcma_bus *bus = &soc->bus; ++ int err; ++ ++ /* Scan bus and initialize it */ + err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips); + if (err) + iounmap(bus->mmio); + + return err; + } ++ ++#ifdef CONFIG_OF ++static int bcma_host_soc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct bcma_bus *bus; ++ int err; ++ ++ /* Alloc */ ++ bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL); ++ if (!bus) ++ return -ENOMEM; ++ ++ /* Map MMIO */ ++ bus->mmio = of_iomap(np, 0); ++ if (!bus->mmio) ++ return -ENOMEM; ++ ++ /* Host specific */ ++ bus->hosttype = BCMA_HOSTTYPE_SOC; ++ bus->ops = &bcma_host_soc_ops; ++ bus->host_pdev = pdev; ++ ++ /* Initialize struct, detect chip */ ++ bcma_init_bus(bus); ++ ++ /* Register */ ++ err = bcma_bus_register(bus); ++ if (err) ++ goto err_unmap_mmio; ++ ++ platform_set_drvdata(pdev, bus); ++ ++ return err; ++ ++err_unmap_mmio: ++ iounmap(bus->mmio); ++ return err; ++} ++ ++static int bcma_host_soc_remove(struct platform_device *pdev) ++{ ++ struct bcma_bus *bus = platform_get_drvdata(pdev); ++ ++ bcma_bus_unregister(bus); ++ iounmap(bus->mmio); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcma_host_soc_of_match[] = { ++ { .compatible = "brcm,bus-axi", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match); ++ ++static struct platform_driver bcma_host_soc_driver = { ++ .driver = { ++ .name = "bcma-host-soc", ++ .of_match_table = bcma_host_soc_of_match, ++ }, ++ .probe = bcma_host_soc_probe, ++ .remove = bcma_host_soc_remove, ++}; ++ ++int __init bcma_host_soc_register_driver(void) ++{ ++ return platform_driver_register(&bcma_host_soc_driver); ++} ++ ++void __exit bcma_host_soc_unregister_driver(void) ++{ ++ platform_driver_unregister(&bcma_host_soc_driver); ++} ++#endif /* CONFIG_OF */ +--- a/drivers/bcma/driver_mips.c ++++ b/drivers/bcma/driver_mips.c +@@ -21,6 +21,14 @@ + #include + #include + ++enum bcma_boot_dev { ++ BCMA_BOOT_DEV_UNK = 0, ++ BCMA_BOOT_DEV_ROM, ++ BCMA_BOOT_DEV_PARALLEL, ++ BCMA_BOOT_DEV_SERIAL, ++ BCMA_BOOT_DEV_NAND, ++}; ++ + static const char * const part_probes[] = { "bcm47xxpart", NULL }; + + static struct physmap_flash_data bcma_pflash_data = { +@@ -107,7 +115,7 @@ static u32 bcma_core_mips_irqflag(struct + * If disabled, 5 is returned. + * If not supported, 6 is returned. + */ +-static unsigned int bcma_core_mips_irq(struct bcma_device *dev) ++unsigned int bcma_core_mips_irq(struct bcma_device *dev) + { + struct bcma_device *mdev = dev->bus->drv_mips.core; + u32 irqflag; +@@ -125,13 +133,6 @@ static unsigned int bcma_core_mips_irq(s + return 5; + } + +-unsigned int bcma_core_irq(struct bcma_device *dev) +-{ +- unsigned int mips_irq = bcma_core_mips_irq(dev); +- return mips_irq <= 4 ? mips_irq + 2 : 0; +-} +-EXPORT_SYMBOL(bcma_core_irq); +- + static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) + { + unsigned int oldirq = bcma_core_mips_irq(dev); +@@ -229,11 +230,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips + } + EXPORT_SYMBOL(bcma_cpu_clock); + ++static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus) ++{ ++ struct bcma_drv_cc *cc = &bus->drv_cc; ++ u8 cc_rev = cc->core->id.rev; ++ ++ if (cc_rev == 42) { ++ struct bcma_device *core; ++ ++ core = bcma_find_core(bus, BCMA_CORE_NS_ROM); ++ if (core) { ++ switch (bcma_aread32(core, BCMA_IOST) & ++ BCMA_NS_ROM_IOST_BOOT_DEV_MASK) { ++ case BCMA_NS_ROM_IOST_BOOT_DEV_NOR: ++ return BCMA_BOOT_DEV_SERIAL; ++ case BCMA_NS_ROM_IOST_BOOT_DEV_NAND: ++ return BCMA_BOOT_DEV_NAND; ++ case BCMA_NS_ROM_IOST_BOOT_DEV_ROM: ++ default: ++ return BCMA_BOOT_DEV_ROM; ++ } ++ } ++ } else { ++ if (cc_rev == 38) { ++ if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT) ++ return BCMA_BOOT_DEV_NAND; ++ else if (cc->status & BIT(5)) ++ return BCMA_BOOT_DEV_ROM; ++ } ++ ++ if ((cc->capabilities & BCMA_CC_CAP_FLASHT) == ++ BCMA_CC_FLASHT_PARA) ++ return BCMA_BOOT_DEV_PARALLEL; ++ else ++ return BCMA_BOOT_DEV_SERIAL; ++ } ++ ++ return BCMA_BOOT_DEV_SERIAL; ++} ++ + static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) + { + struct bcma_bus *bus = mcore->core->bus; + struct bcma_drv_cc *cc = &bus->drv_cc; + struct bcma_pflash *pflash = &cc->pflash; ++ enum bcma_boot_dev boot_dev; + + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { + case BCMA_CC_FLASHT_STSER: +@@ -269,6 +310,20 @@ static void bcma_core_mips_flash_detect( + bcma_nflash_init(cc); + } + } ++ ++ /* Determine flash type this SoC boots from */ ++ boot_dev = bcma_boot_dev(bus); ++ switch (boot_dev) { ++ case BCMA_BOOT_DEV_PARALLEL: ++ case BCMA_BOOT_DEV_SERIAL: ++ /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */ ++ break; ++ case BCMA_BOOT_DEV_NAND: ++ /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */ ++ break; ++ default: ++ break; ++ } + } + + void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) +@@ -361,7 +416,7 @@ void bcma_core_mips_init(struct bcma_drv + break; + default: + list_for_each_entry(core, &bus->cores, list) { +- core->irq = bcma_core_irq(core); ++ core->irq = bcma_core_irq(core, 0); + } + bcma_err(bus, + "Unknown device (0x%x) found, can not configure IRQs\n", +--- a/include/linux/bcma/bcma_regs.h ++++ b/include/linux/bcma/bcma_regs.h +@@ -39,6 +39,11 @@ + #define BCMA_RESET_CTL_RESET 0x0001 + #define BCMA_RESET_ST 0x0804 + ++#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003 ++#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000 ++#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001 ++#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002 ++ + /* BCMA PCI config space registers. */ + #define BCMA_PCI_PMCSR 0x44 + #define BCMA_PCI_PE 0x100 +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -237,7 +237,7 @@ static int bcma_hcd_probe(struct bcma_de + bcma_hcd_init_chip(dev); + + /* In AI chips EHCI is addrspace 0, OHCI is 1 */ +- ohci_addr = dev->addr1; ++ ohci_addr = dev->addr_s[0]; + if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749) + && chipinfo->rev == 0) + ohci_addr = 0x18009000; +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -24,6 +24,7 @@ struct bcma_bus; + /* main.c */ + bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, + int timeout); ++void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core); + int bcma_bus_register(struct bcma_bus *bus); + void bcma_bus_unregister(struct bcma_bus *bus); + int __init bcma_bus_early_register(struct bcma_bus *bus, +@@ -50,6 +51,10 @@ void bcma_chipco_serial_init(struct bcma + extern struct platform_device bcma_pflash_dev; + #endif /* CONFIG_BCMA_DRIVER_MIPS */ + ++/* driver_chipcommon_b.c */ ++int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb); ++void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb); ++ + /* driver_chipcommon_pmu.c */ + u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc); + u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc); +@@ -84,6 +89,20 @@ extern int __init bcma_host_pci_init(voi + extern void __exit bcma_host_pci_exit(void); + #endif /* CONFIG_BCMA_HOST_PCI */ + ++/* host_soc.c */ ++#if defined(CONFIG_BCMA_HOST_SOC) && defined(CONFIG_OF) ++extern int __init bcma_host_soc_register_driver(void); ++extern void __exit bcma_host_soc_unregister_driver(void); ++#else ++static inline int __init bcma_host_soc_register_driver(void) ++{ ++ return 0; ++} ++static inline void __exit bcma_host_soc_unregister_driver(void) ++{ ++} ++#endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */ ++ + /* driver_pci.c */ + u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); + +--- /dev/null ++++ b/drivers/bcma/driver_chipcommon_b.c +@@ -0,0 +1,61 @@ ++/* ++ * Broadcom specific AMBA ++ * ChipCommon B Unit driver ++ * ++ * Copyright 2014, Hauke Mehrtens ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include "bcma_private.h" ++#include ++#include ++ ++static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, ++ u32 value, int timeout) ++{ ++ unsigned long deadline = jiffies + timeout; ++ u32 val; ++ ++ do { ++ val = readl(addr); ++ if ((val & mask) == value) ++ return true; ++ cpu_relax(); ++ udelay(10); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ bcma_err(bus, "Timeout waiting for register %p\n", addr); ++ ++ return false; ++} ++ ++void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value) ++{ ++ struct bcma_bus *bus = ccb->core->bus; ++ ++ writel(offset, ccb->mii + 0x00); ++ bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100); ++ writel(value, ccb->mii + 0x04); ++ bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100); ++} ++EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write); ++ ++int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb) ++{ ++ if (ccb->setup_done) ++ return 0; ++ ++ ccb->setup_done = 1; ++ ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE); ++ if (!ccb->mii) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb) ++{ ++ if (ccb->mii) ++ iounmap(ccb->mii); ++} +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -644,6 +644,12 @@ struct bcma_drv_cc { + #endif + }; + ++struct bcma_drv_cc_b { ++ struct bcma_device *core; ++ u8 setup_done:1; ++ void __iomem *mii; ++}; ++ + /* Register access */ + #define bcma_cc_read32(cc, offset) \ + bcma_read32((cc)->core, offset) +@@ -699,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate + + extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc); + ++void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value); ++ + #endif /* LINUX_BCMA_DRIVER_CC_H_ */ +--- a/arch/mips/bcm47xx/setup.c ++++ b/arch/mips/bcm47xx/setup.c +@@ -202,6 +202,10 @@ static void __init bcm47xx_register_bcma + + err = bcma_host_soc_register(&bcm47xx_bus.bcma); + if (err) ++ panic("Failed to register BCMA bus (err %d)", err); ++ ++ err = bcma_host_soc_init(&bcm47xx_bus.bcma); ++ if (err) + panic("Failed to initialize BCMA bus (err %d)", err); + + bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL); +--- a/include/linux/bcma/bcma_soc.h ++++ b/include/linux/bcma/bcma_soc.h +@@ -10,6 +10,7 @@ struct bcma_soc { + }; + + int __init bcma_host_soc_register(struct bcma_soc *soc); ++int __init bcma_host_soc_init(struct bcma_soc *soc); + + int bcma_bus_register(struct bcma_bus *bus); + +--- /dev/null ++++ b/Documentation/devicetree/bindings/bus/bcma.txt +@@ -0,0 +1,53 @@ ++Driver for ARM AXI Bus with Broadcom Plugins (bcma) ++ ++Required properties: ++ ++- compatible : brcm,bus-axi ++ ++- reg : iomem address range of chipcommon core ++ ++The cores on the AXI bus are automatically detected by bcma with the ++memory ranges they are using and they get registered afterwards. ++Automatic detection of the IRQ number is not working on ++BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide ++them manually through device tree. Use an interrupt-map to specify the ++IRQ used by the devices on the bus. The first address is just an index, ++because we do not have any special register. ++ ++The top-level axi bus may contain children representing attached cores ++(devices). This is needed since some hardware details can't be auto ++detected (e.g. IRQ numbers). Also some of the cores may be responsible ++for extra things, e.g. ChipCommon providing access to the GPIO chip. ++ ++Example: ++ ++ axi@18000000 { ++ compatible = "brcm,bus-axi"; ++ reg = <0x18000000 0x1000>; ++ ranges = <0x00000000 0x18000000 0x00100000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0x000fffff 0xffff>; ++ interrupt-map = ++ /* Ethernet Controller 0 */ ++ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 1 */ ++ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; ++ ++ /* PCIe Controller 0 */ ++ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; ++ ++ chipcommon { ++ reg = <0x00000000 0x1000>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ };