X-Git-Url: https://git.archive.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Farch%2Fmips%2Finclude%2Fasm%2Fmach-ar71xx%2Far71xx.h;h=a9f288b27d8ccc2ffbe631ceb517810ba67a33d4;hb=0414b8cf78b328c4bbd99c7298b72e8133968b0c;hp=90a3da37e458bb73a414a6f6bc978da03d86f30f;hpb=23dc17551cb9c5ce1f3029223913aa111ac10bd7;p=15.05%2Fopenwrt.git diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 90a3da37e4..a9f288b27d 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -56,19 +56,26 @@ #define AR71XX_DMA_SIZE 0x10000 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) #define AR71XX_STEREO_SIZE 0x10000 + +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR724X_PCI_CRP_SIZE 0x100 + +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) #define AR91XX_WMAC_SIZE 0x30000 #define AR71XX_MEM_SIZE_MIN 0x0200000 -#define AR71XX_MEM_SIZE_MAX 0x8000000 +#define AR71XX_MEM_SIZE_MAX 0x10000000 #define AR71XX_CPU_IRQ_BASE 0 #define AR71XX_MISC_IRQ_BASE 8 #define AR71XX_MISC_IRQ_COUNT 8 #define AR71XX_GPIO_IRQ_BASE 16 -#define AR71XX_GPIO_IRQ_COUNT 16 -#define AR71XX_PCI_IRQ_BASE 32 -#define AR71XX_PCI_IRQ_COUNT 4 +#define AR71XX_GPIO_IRQ_COUNT 32 +#define AR71XX_PCI_IRQ_BASE 48 +#define AR71XX_PCI_IRQ_COUNT 8 #define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2) #define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2) @@ -92,7 +99,7 @@ #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0) #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1) #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2) -#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 3) +#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4) extern u32 ar71xx_ahb_freq; extern u32 ar71xx_cpu_freq; @@ -103,34 +110,47 @@ enum ar71xx_soc_type { AR71XX_SOC_AR7130, AR71XX_SOC_AR7141, AR71XX_SOC_AR7161, + AR71XX_SOC_AR7240, AR71XX_SOC_AR9130, AR71XX_SOC_AR9132 }; extern enum ar71xx_soc_type ar71xx_soc; -extern unsigned long ar71xx_mach_type; - -#define AR71XX_MACH_GENERIC 0 -#define AR71XX_MACH_WP543 1 /* Compex WP543 */ -#define AR71XX_MACH_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */ -#define AR71XX_MACH_RB_433 3 /* MikroTik RouterBOARD 433/433AH */ -#define AR71XX_MACH_RB_450 4 /* MikroTik RouterBOARD 450 */ -#define AR71XX_MACH_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */ -#define AR71XX_MACH_AW_NR580 6 /* AzureWave AW-NR580 */ -#define AR71XX_MACH_AP83 7 /* Atheros AP83 */ -#define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */ -#define AR71XX_MACH_UBNT_RS 9 /* Ubiquiti RouterStation */ -#define AR71XX_MACH_UBNT_LSX 10 /* Ubiquiti LSX */ -#define AR71XX_MACH_WNR2000 11 /* NETGEAR WNR2000 */ -#define AR71XX_MACH_PB42 12 /* Atheros PB42 */ -#define AR71XX_MACH_MZK_W300NH 13 /* Planex MZK-W300NH */ -#define AR71XX_MACH_MZK_W04NU 14 /* Planex MZK-W04NU */ -#define AR71XX_MACH_UBNT_LSSR71 15 /* Ubiquiti LS-SR71 */ -#define AR71XX_MACH_TL_WR941ND 16 /* TP-LINK TL-WR941ND */ -#define AR71XX_MACH_UBNT_RSPRO 17 /* Ubiquiti RouterStation Pro */ -#define AR71XX_MACH_AP81 18 /* Atheros AP81 */ -#define AR71XX_MACH_WRT400N 19 /* Linksys WRT400N */ +enum ar71xx_mach_type { + AR71XX_MACH_GENERIC = 0, + AR71XX_MACH_AP81, /* Atheros AP81 */ + AR71XX_MACH_AP83, /* Atheros AP83 */ + AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */ + AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ + AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ + AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ + AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ + AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */ + AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ + AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ + AR71XX_MACH_PB42, /* Atheros PB42 */ + AR71XX_MACH_PB44, /* Atheros PB44 */ + AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */ + AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */ + AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ + AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ + AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ + AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ + AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */ + AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */ + AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ + AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ + AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ + AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ + AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */ + AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */ + AR71XX_MACH_WP543, /* Compex WP543 */ + AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */ + AR71XX_MACH_WRT400N, /* Linksys WRT400N */ +}; + +extern enum ar71xx_mach_type ar71xx_mach; /* * PLL block @@ -152,6 +172,17 @@ extern unsigned long ar71xx_mach_type; #define AR71XX_ETH0_PLL_SHIFT 17 #define AR71XX_ETH1_PLL_SHIFT 19 +#define AR724X_PLL_REG_CPU_CONFIG 0x00 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + #define AR91XX_PLL_REG_CPU_CONFIG 0x00 #define AR91XX_PLL_REG_ETH_CONFIG 0x04 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 @@ -212,15 +243,29 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) #define GPIO_REG_INT_ENABLE 0x24 #define GPIO_REG_FUNC 0x28 -#define GPIO_FUNC_STEREO_EN BIT(17) -#define GPIO_FUNC_SLIC_EN BIT(16) -#define GPIO_FUNC_SPI_CS2_EN BIT(13) -#define GPIO_FUNC_SPI_CS1_EN BIT(12) -#define GPIO_FUNC_UART_EN BIT(8) -#define GPIO_FUNC_USB_OC_EN BIT(4) -#define GPIO_FUNC_USB_CLK_EN BIT(0) +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) #define AR71XX_GPIO_COUNT 16 + +#define AR724X_GPIO_COUNT 16 + +#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18) +#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17) +#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR91XX_GPIO_FUNC_UART_EN BIT(8) +#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4) + #define AR91XX_GPIO_COUNT 22 extern void __iomem *ar71xx_gpio_base; @@ -235,9 +280,9 @@ static inline u32 ar71xx_gpio_rr(unsigned reg) return __raw_readl(ar71xx_gpio_base + reg); } -extern void ar71xx_gpio_init(void) __init; -extern void ar71xx_gpio_function_enable(u32 mask); -extern void ar71xx_gpio_function_disable(u32 mask); +void ar71xx_gpio_init(void) __init; +void ar71xx_gpio_function_enable(u32 mask); +void ar71xx_gpio_function_disable(u32 mask); /* * DDR_CTRL block @@ -255,6 +300,9 @@ extern void ar71xx_gpio_function_disable(u32 mask); #define AR71XX_DDR_REG_FLUSH_USB 0xa4 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 + #define AR91XX_DDR_REG_FLUSH_GE0 0x7c #define AR91XX_DDR_REG_FLUSH_GE1 0x80 #define AR91XX_DDR_REG_FLUSH_USB 0x84 @@ -281,7 +329,7 @@ static inline u32 ar71xx_ddr_rr(unsigned reg) return __raw_readl(ar71xx_ddr_base + reg); } -extern void ar71xx_ddr_flush(u32 reg); +void ar71xx_ddr_flush(u32 reg); /* * PCI block @@ -308,6 +356,34 @@ extern void ar71xx_ddr_flush(u32 reg); #define PCI_IDSEL_ADL_START 17 +#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000) +#define AR724X_PCI_CFG_SIZE 0x1000 + +#define AR724X_PCI_REG_INT_STATUS 0x4c +#define AR724X_PCI_REG_INT_MASK 0x50 + +#define AR724X_PCI_INT_DEV0 BIT(14) + +static inline void ar724x_pci_wr(unsigned reg, u32 val) +{ + void __iomem *base; + + base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); + __raw_writel(val, base + reg); + iounmap(base); +} + +static inline u32 ar724x_pci_rr(unsigned reg) +{ + void __iomem *base; + u32 ret; + + base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); + ret = __raw_readl(base + reg); + iounmap(base); + return ret; +} + /* * RESET block */ @@ -332,6 +408,8 @@ extern void ar71xx_ddr_flush(u32 reg); #define AR91XX_RESET_REG_PERFC0 0x24 #define AR91XX_RESET_REG_PERFC1 0x28 +#define AR724X_RESET_REG_RESET_MODULE 0x1c + #define WDOG_CTRL_LAST_RESET BIT(31) #define WDOG_CTRL_ACTION_MASK 3 #define WDOG_CTRL_ACTION_NONE 0 /* no action */ @@ -373,16 +451,25 @@ extern void ar71xx_ddr_flush(u32 reg); #define RESET_MODULE_PCI_BUS BIT(1) #define RESET_MODULE_PCI_CORE BIT(0) -#define REV_ID_MASK 0xff -#define REV_ID_CHIP_MASK 0xf3 -#define REV_ID_CHIP_AR7130 0xa0 -#define REV_ID_CHIP_AR7141 0xa1 -#define REV_ID_CHIP_AR7161 0xa2 -#define REV_ID_CHIP_AR9130 0xb0 -#define REV_ID_CHIP_AR9132 0xb1 +#define REV_ID_MAJOR_MASK 0xf0 +#define REV_ID_MAJOR_AR71XX 0xa0 +#define REV_ID_MAJOR_AR913X 0xb0 +#define REV_ID_MAJOR_AR724X 0xc0 -#define REV_ID_REVISION_MASK 0x3 -#define REV_ID_REVISION_SHIFT 2 +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR91XX_REV_ID_MINOR_MASK 0x3 +#define AR91XX_REV_ID_MINOR_AR9130 0x0 +#define AR91XX_REV_ID_MINOR_AR9132 0x1 +#define AR91XX_REV_ID_REVISION_MASK 0x3 +#define AR91XX_REV_ID_REVISION_SHIFT 2 + +#define AR724X_REV_ID_REVISION_MASK 0x3 extern void __iomem *ar71xx_reset_base; @@ -396,8 +483,8 @@ static inline u32 ar71xx_reset_rr(unsigned reg) return __raw_readl(ar71xx_reset_base + reg); } -extern void ar71xx_device_stop(u32 mask); -extern void ar71xx_device_start(u32 mask); +void ar71xx_device_stop(u32 mask); +void ar71xx_device_start(u32 mask); /* * SPI block @@ -420,6 +507,9 @@ extern void ar71xx_device_start(u32 mask); #define SPI_IOC_CS2 SPI_IOC_CS(2) #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2) +void ar71xx_flash_acquire(void); +void ar71xx_flash_release(void); + /* * MII_CTRL block */