X-Git-Url: https://git.archive.openwrt.org/?a=blobdiff_plain;ds=sidebyside;f=target%2Flinux%2Framips%2Fpatches-4.3%2F0001-arch-mips-ralink-add-mt7621-support.patch;fp=target%2Flinux%2Framips%2Fpatches-4.3%2F0001-arch-mips-ralink-add-mt7621-support.patch;h=0000000000000000000000000000000000000000;hb=1ca47c6547b19eeec886ba4a770777885932d211;hp=dab8e8d2b8bb68045382b7f6c0768a1105e09464;hpb=7687c6da505df3ecb9554b42165f4380a58f2bda;p=openwrt.git diff --git a/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch b/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch deleted file mode 100644 index dab8e8d2b8..0000000000 --- a/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch +++ /dev/null @@ -1,437 +0,0 @@ -From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:08:31 +0100 -Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-ralink/irq.h | 9 + - arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++ - arch/mips/kernel/mips-cm.c | 4 +- - arch/mips/kernel/vmlinux.lds.S | 1 + - arch/mips/ralink/Kconfig | 18 ++ - arch/mips/ralink/Makefile | 7 +- - arch/mips/ralink/Platform | 5 + - arch/mips/ralink/irq-gic.c | 268 ++++++++++++++++++++++++++++ - arch/mips/ralink/malta-amon.c | 81 +++++++++ - arch/mips/ralink/mt7621.c | 209 ++++++++++++++++++++++ - 10 files changed, 638 insertions(+), 3 deletions(-) - create mode 100644 arch/mips/include/asm/mach-ralink/irq.h - create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h - create mode 100644 arch/mips/ralink/irq-gic.c - create mode 100644 arch/mips/ralink/malta-amon.c - create mode 100644 arch/mips/ralink/mt7621.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-ralink/irq.h -@@ -0,0 +1,9 @@ -+#ifndef __ASM_MACH_RALINK_IRQ_H -+#define __ASM_MACH_RALINK_IRQ_H -+ -+#define GIC_NUM_INTRS 64 -+#define NR_IRQS 256 -+ -+#include_next -+ -+#endif ---- /dev/null -+++ b/arch/mips/include/asm/mach-ralink/mt7621.h -@@ -0,0 +1,42 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Parts of this file are based on Ralink's 2.6.21 BSP -+ * -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#ifndef _MT7621_REGS_H_ -+#define _MT7621_REGS_H_ -+ -+#define MT7621_PALMBUS_BASE 0x1C000000 -+#define MT7621_PALMBUS_SIZE 0x03FFFFFF -+ -+#define MT7621_SYSC_BASE 0x1E000000 -+ -+#define SYSC_REG_CHIP_NAME0 0x00 -+#define SYSC_REG_CHIP_NAME1 0x04 -+#define SYSC_REG_CHIP_REV 0x0c -+#define SYSC_REG_SYSTEM_CONFIG0 0x10 -+#define SYSC_REG_SYSTEM_CONFIG1 0x14 -+ -+#define CHIP_REV_PKG_MASK 0x1 -+#define CHIP_REV_PKG_SHIFT 16 -+#define CHIP_REV_VER_MASK 0xf -+#define CHIP_REV_VER_SHIFT 8 -+#define CHIP_REV_ECO_MASK 0xf -+ -+#define MT7621_DRAM_BASE 0x0 -+#define MT7621_DDR2_SIZE_MIN 32 -+#define MT7621_DDR2_SIZE_MAX 256 -+ -+#define MT7621_CHIP_NAME0 0x3637544D -+#define MT7621_CHIP_NAME1 0x20203132 -+ -+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) -+ -+#endif ---- a/arch/mips/kernel/vmlinux.lds.S -+++ b/arch/mips/kernel/vmlinux.lds.S -@@ -51,6 +51,7 @@ SECTIONS - /* read-only */ - _text = .; /* Text and read-only data */ - .text : { -+ /*. = . + 0x8000; */ - TEXT_TEXT - SCHED_TEXT - LOCK_TEXT ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -12,6 +12,11 @@ config RALINK_ILL_ACC - depends on SOC_RT305X - default y - -+config IRQ_INTC -+ bool -+ default y -+ depends on !SOC_MT7621 -+ - choice - prompt "Ralink SoC selection" - default SOC_RT305X -@@ -34,6 +39,16 @@ choice - config SOC_MT7620 - bool "MT7620/8" - -+ config SOC_MT7621 -+ bool "MT7621" -+ select MIPS_CPU_SCACHE -+ select SYS_SUPPORTS_MULTITHREADING -+ select SYS_SUPPORTS_SMP -+ select SYS_SUPPORTS_MIPS_CPS -+ select MIPS_GIC -+ select COMMON_CLK -+ select CLKSRC_MIPS_GIC -+ select HW_HAS_PCI - endchoice - - choice -@@ -65,6 +80,10 @@ choice - depends on SOC_MT7620 - select BUILTIN_DTB - -+ config DTB_MT7621_EVAL -+ bool "MT7621 eval kit" -+ depends on SOC_MT7621 -+ - endchoice - - endif ---- a/arch/mips/ralink/Makefile -+++ b/arch/mips/ralink/Makefile -@@ -6,16 +6,24 @@ - # Copyright (C) 2009-2011 Gabor Juhos - # Copyright (C) 2013 John Crispin - --obj-y := prom.o of.o reset.o clk.o irq.o timer.o -+obj-y := prom.o of.o reset.o -+ -+ifndef CONFIG_MIPS_GIC -+ obj-y += clk.o timer.o -+endif - - obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o - - obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o - -+obj-$(CONFIG_IRQ_INTC) += irq.o -+obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o -+ - obj-$(CONFIG_SOC_RT288X) += rt288x.o - obj-$(CONFIG_SOC_RT305X) += rt305x.o - obj-$(CONFIG_SOC_RT3883) += rt3883.o - obj-$(CONFIG_SOC_MT7620) += mt7620.o -+obj-$(CONFIG_SOC_MT7621) += mt7621.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - ---- a/arch/mips/ralink/Platform -+++ b/arch/mips/ralink/Platform -@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr - # - load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000 - cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620 -+ -+# Ralink MT7621 -+# -+load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000 -+cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621 ---- /dev/null -+++ b/arch/mips/ralink/irq-gic.c -@@ -0,0 +1,18 @@ -+#include -+ -+#include -+#include -+#include -+ -+int get_c0_perfcount_int(void) -+{ -+ return gic_get_c0_perfcount_int(); -+} -+EXPORT_SYMBOL_GPL(get_c0_perfcount_int); -+ -+void __init -+arch_init_irq(void) -+{ -+ irqchip_init(); -+} -+ ---- /dev/null -+++ b/arch/mips/ralink/mt7621.c -@@ -0,0 +1,223 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Parts of this file are based on Ralink's 2.6.21 BSP -+ * -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "common.h" -+ -+#define SYSC_REG_SYSCFG 0x10 -+#define SYSC_REG_CPLL_CLKCFG0 0x2c -+#define SYSC_REG_CUR_CLK_STS 0x44 -+#define CPU_CLK_SEL (BIT(30) | BIT(31)) -+ -+#define MT7621_GPIO_MODE_UART1 1 -+#define MT7621_GPIO_MODE_I2C 2 -+#define MT7621_GPIO_MODE_UART3_MASK 0x3 -+#define MT7621_GPIO_MODE_UART3_SHIFT 3 -+#define MT7621_GPIO_MODE_UART3_GPIO 1 -+#define MT7621_GPIO_MODE_UART2_MASK 0x3 -+#define MT7621_GPIO_MODE_UART2_SHIFT 5 -+#define MT7621_GPIO_MODE_UART2_GPIO 1 -+#define MT7621_GPIO_MODE_JTAG 7 -+#define MT7621_GPIO_MODE_WDT_MASK 0x3 -+#define MT7621_GPIO_MODE_WDT_SHIFT 8 -+#define MT7621_GPIO_MODE_WDT_GPIO 1 -+#define MT7621_GPIO_MODE_PCIE_RST 0 -+#define MT7621_GPIO_MODE_PCIE_REF 2 -+#define MT7621_GPIO_MODE_PCIE_MASK 0x3 -+#define MT7621_GPIO_MODE_PCIE_SHIFT 10 -+#define MT7621_GPIO_MODE_PCIE_GPIO 1 -+#define MT7621_GPIO_MODE_MDIO_MASK 0x3 -+#define MT7621_GPIO_MODE_MDIO_SHIFT 12 -+#define MT7621_GPIO_MODE_MDIO_GPIO 1 -+#define MT7621_GPIO_MODE_RGMII1 14 -+#define MT7621_GPIO_MODE_RGMII2 15 -+#define MT7621_GPIO_MODE_SPI_MASK 0x3 -+#define MT7621_GPIO_MODE_SPI_SHIFT 16 -+#define MT7621_GPIO_MODE_SPI_GPIO 1 -+#define MT7621_GPIO_MODE_SDHCI_MASK 0x3 -+#define MT7621_GPIO_MODE_SDHCI_SHIFT 18 -+#define MT7621_GPIO_MODE_SDHCI_GPIO 1 -+ -+static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; -+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -+static struct rt2880_pmx_func uart3_grp[] = { -+ FUNC("uart3", 0, 5, 4), -+ FUNC("i2s", 2, 5, 4), -+ FUNC("spdif3", 3, 5, 4), -+}; -+static struct rt2880_pmx_func uart2_grp[] = { -+ FUNC("uart2", 0, 9, 4), -+ FUNC("pcm", 2, 9, 4), -+ FUNC("spdif2", 3, 9, 4), -+}; -+static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; -+static struct rt2880_pmx_func wdt_grp[] = { -+ FUNC("wdt rst", 0, 18, 1), -+ FUNC("wdt refclk", 2, 18, 1), -+}; -+static struct rt2880_pmx_func pcie_rst_grp[] = { -+ FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), -+ FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) -+}; -+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; -+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; -+static struct rt2880_pmx_func spi_grp[] = { -+ FUNC("spi", 0, 34, 7), -+ FUNC("nand1", 2, 34, 7), -+}; -+static struct rt2880_pmx_func sdhci_grp[] = { -+ FUNC("sdhci", 0, 41, 8), -+ FUNC("nand2", 2, 41, 8), -+}; -+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; -+ -+static struct rt2880_pmx_group mt7621_pinmux_data[] = { -+ GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), -+ GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), -+ GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, -+ MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), -+ GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, -+ MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), -+ GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), -+ GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, -+ MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), -+ GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, -+ MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), -+ GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, -+ MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), -+ GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), -+ GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, -+ MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT), -+ GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK, -+ MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT), -+ GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1), -+ { 0 } -+}; -+ -+phys_addr_t mips_cpc_default_phys_base() { -+ panic("Cannot detect cpc address"); -+} -+ -+void __init ralink_clk_init(void) -+{ -+ int cpu_fdiv = 0; -+ int cpu_ffrac = 0; -+ int fbdiv = 0; -+ u32 clk_sts, syscfg; -+ u8 clk_sel = 0, xtal_mode; -+ u32 cpu_clk; -+ -+ if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) -+ clk_sel = 1; -+ -+ switch (clk_sel) { -+ case 0: -+ clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); -+ cpu_fdiv = ((clk_sts >> 8) & 0x1F); -+ cpu_ffrac = (clk_sts & 0x1F); -+ cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000; -+ break; -+ -+ case 1: -+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; -+ syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); -+ xtal_mode = (syscfg >> 6) & 0x7; -+ if(xtal_mode >= 6) { //25Mhz Xtal -+ cpu_clk = 25 * fbdiv * 1000 * 1000; -+ } else if(xtal_mode >=3) { //40Mhz Xtal -+ cpu_clk = 40 * fbdiv * 1000 * 1000; -+ } else { // 20Mhz Xtal -+ cpu_clk = 20 * fbdiv * 1000 * 1000; -+ } -+ break; -+ } -+} -+ -+void __init ralink_of_remap(void) -+{ -+ rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); -+ rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc"); -+ -+ if (!rt_sysc_membase || !rt_memc_membase) -+ panic("Failed to remap core resources"); -+} -+ -+void prom_soc_init(struct ralink_soc_info *soc_info) -+{ -+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); -+ unsigned char *name = NULL; -+ u32 n0; -+ u32 n1; -+ u32 rev; -+ -+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); -+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); -+ -+ if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) { -+ name = "MT7621"; -+ soc_info->compatible = "mtk,mt7621-soc"; -+ } else { -+ panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1); -+ } -+ -+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); -+ -+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, -+ "MediaTek %s ver:%u eco:%u", -+ name, -+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, -+ (rev & CHIP_REV_ECO_MASK)); -+ -+ soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN; -+ soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX; -+ soc_info->mem_base = MT7621_DRAM_BASE; -+ -+ rt2880_pinmux_data = mt7621_pinmux_data; -+ -+ /* Early detection of CMP support */ -+ mips_cm_probe(); -+ mips_cpc_probe(); -+ -+ if (mips_cm_numiocu()) { -+ /* mips_cm_probe() wipes out bootloader -+ config for CM regions and we have to configure them -+ again. This SoC cannot talk to pamlbus devices -+ witout proper iocu region set up. -+ -+ FIXME: it would be better to do this with values -+ from DT, but we need this very early because -+ without this we cannot talk to pretty much anything -+ including serial. -+ */ -+ write_gcr_reg0_base(MT7621_PALMBUS_BASE); -+ write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | CM_GCR_REGn_MASK_CMTGT_IOCU0); -+ } -+ -+ if (!register_cps_smp_ops()) -+ return; -+ if (!register_cmp_smp_ops()) -+ return; -+ if (!register_vsmp_smp_ops()) -+ return; -+} ---- /dev/null -+++ b/arch/mips/ralink/timer-gic.c -@@ -0,0 +1,15 @@ -+#include -+ -+#include -+#include -+#include -+ -+#include "common.h" -+ -+void __init plat_time_init(void) -+{ -+ ralink_of_remap(); -+ -+ of_clk_init(NULL); -+ clocksource_of_init(); -+}