#include <asm/mach-ar71xx/ar71xx.h>
+static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
+
#ifdef CONFIG_PCI
static void ar71xx_pci_irq_dispatch(void)
{
{
int i;
+ ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
+
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
handle_level_irq);
}
- setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
+ setup_irq(AR71XX_CPU_IRQ_IP2, &ar71xx_pci_irqaction);
}
static void ar724x_pci_irq_dispatch(void)
static void __init ar724x_pci_irq_init(void)
{
+ u32 t;
int i;
+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+ if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
+ AR724X_RESET_PCIE_PHY_SERIAL)) {
+ return;
+ }
+
+ ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
+
ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
handle_level_irq);
}
- setup_irq(AR71XX_CPU_IRQ_PCI, &ar724x_pci_irqaction);
+ setup_irq(AR71XX_CPU_IRQ_IP2, &ar724x_pci_irqaction);
}
+#else
+static inline void ar71xx_pci_irq_init(void) {};
+static inline void ar724x_pci_irq_init(void) {};
#endif /* CONFIG_PCI */
static void ar71xx_gpio_irq_dispatch(void)
ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
}
-static void ar724x_misc_irq_unmask(unsigned int irq)
+static void ar71xx_misc_irq_mask(unsigned int irq)
{
irq -= AR71XX_MISC_IRQ_BASE;
ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
- ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
+ ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
/* flush write */
ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
-
- ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
- ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
-
- /* flush write */
- ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
}
-static void ar71xx_misc_irq_mask(unsigned int irq)
+static void ar724x_misc_irq_ack(unsigned int irq)
{
irq -= AR71XX_MISC_IRQ_BASE;
- ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
- ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
+ ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
+ ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
/* flush write */
- ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
+ ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
}
static struct irq_chip ar71xx_misc_irq_chip = {
.name = "AR71XX MISC",
.unmask = ar71xx_misc_irq_unmask,
.mask = ar71xx_misc_irq_mask,
- .mask_ack = ar71xx_misc_irq_mask,
};
static struct irqaction ar71xx_misc_irqaction = {
ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
if (ar71xx_soc == AR71XX_SOC_AR7240)
- ar71xx_misc_irq_chip.unmask = ar724x_misc_irq_unmask;
+ ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
+ else
+ ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
for (i = AR71XX_MISC_IRQ_BASE;
i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
static void ar913x_wmac_irq_dispatch(void)
{
- do_IRQ(AR71XX_CPU_IRQ_WMAC);
+ do_IRQ(AR71XX_CPU_IRQ_IP2);
}
-static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
-
asmlinkage void plat_irq_dispatch(void)
{
unsigned long pending;
ar71xx_misc_irq_init();
+ cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
+
switch (ar71xx_soc) {
case AR71XX_SOC_AR7130:
case AR71XX_SOC_AR7141:
case AR71XX_SOC_AR7161:
-#ifdef CONFIG_PCI
ar71xx_pci_irq_init();
- ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
-#endif
break;
case AR71XX_SOC_AR7240:
-#ifdef CONFIG_PCI
ar724x_pci_irq_init();
- ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
-#endif
break;
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132: