1 --- a/drivers/pwm/Kconfig
2 +++ b/drivers/pwm/Kconfig
3 @@ -187,6 +187,15 @@ config PWM_SPEAR
4 To compile this driver as a module, choose M here: the module
5 will be called pwm-spear.
8 + tristate "Allwinner PWM support"
9 + depends on ARCH_SUNXI || COMPILE_TEST
11 + Generic PWM framework driver for Allwinner SoCs.
13 + To compile this driver as a module, choose M here: the module
14 + will be called pwm-sunxi.
17 tristate "NVIDIA Tegra PWM support"
19 --- a/drivers/pwm/Makefile
20 +++ b/drivers/pwm/Makefile
21 @@ -16,6 +16,7 @@ obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
22 obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
23 obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
24 obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
25 +obj-$(CONFIG_PWM_SUNXI) += pwm-sunxi.o
26 obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
27 obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
28 obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o
30 +++ b/drivers/pwm/pwm-sunxi.c
33 + * Driver for Allwinner Pulse Width Modulation Controller
35 + * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
37 + * Licensed under GPLv2.
40 +#include <linux/bitops.h>
41 +#include <linux/clk.h>
42 +#include <linux/err.h>
43 +#include <linux/io.h>
44 +#include <linux/of.h>
45 +#include <linux/of_device.h>
46 +#include <linux/platform_device.h>
47 +#include <linux/pwm.h>
48 +#include <linux/module.h>
49 +#include <linux/mutex.h>
50 +#include <linux/slab.h>
52 +#define PWM_CTRL_REG 0x0
54 +#define PWM_CH_PRD_BASE 0x4
55 +#define PWM_CH_PRD_OFF 0x4
56 +#define PWM_CH_PRD(x) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFF * (x))
58 +#define PWMCH_OFFSET 15
59 +#define PWM_PRESCAL_MASK GENMASK(3, 0)
60 +#define PWM_PRESCAL_OFF 0
61 +#define PWM_EN BIT(4)
62 +#define PWM_ACT_STATE BIT(5)
63 +#define PWM_CLK_GATING BIT(6)
64 +#define PWM_MODE BIT(7)
65 +#define PWM_PULSE BIT(8)
66 +#define PWM_BYPASS BIT(9)
68 +#define PWM_RDY_BASE 28
69 +#define PWM_RDY_OFF 1
70 +#define PWM_RDY(x) BIT(PWM_RDY_BASE + PWM_RDY_OFF * (x))
72 +#define PWM_PRD_ACT_MASK GENMASK(7, 0)
73 +#define PWM_PRD(x) ((x - 1) << 16)
74 +#define PWM_PRD_MASK GENMASK(7, 0)
76 +#define BIT_CH(bit, chan) (bit << (chan * PWMCH_OFFSET))
78 +u32 prescal_table[] = { 120, 180, 240, 360, 480, 0, 0, 0,
79 + 12000, 24000, 36000, 48000, 72000,
82 +struct sunxi_pwm_data {
86 +struct sunxi_pwm_chip {
87 + struct pwm_chip chip;
90 + struct mutex ctrl_lock;
91 + const struct sunxi_pwm_data *data;
94 +#define to_sunxi_pwm_chip(chip) container_of(chip, struct sunxi_pwm_chip, chip)
96 +static inline u32 sunxi_pwm_readl(struct sunxi_pwm_chip *chip,
97 + unsigned long offset)
99 + return readl(chip->base + offset);
102 +static inline void sunxi_pwm_writel(struct sunxi_pwm_chip *chip,
103 + unsigned long offset, unsigned long val)
105 + writel(val, chip->base + offset);
108 +static int sunxi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
109 + int duty_ns, int period_ns)
111 + struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
112 + u32 clk_rate, prd, dty;
117 + clk_rate = clk_get_rate(sunxi_pwm->clk);
119 + /* First, test without any divider */
120 + i = PWM_PRESCAL_MASK;
121 + div = clk_rate * period_ns;
122 + do_div(div, 1000000000);
123 + if (div > PWM_PRD_MASK) {
124 + /* Then go up from the first divider */
125 + for (i = 0; i < PWM_PRESCAL_MASK; i++) {
126 + if (!prescal_table[i])
128 + div = clk_rate / prescal_table[i];
129 + div = div * period_ns;
130 + do_div(div, 1000000000);
131 + if (div <= PWM_PRD_MASK)
136 + if (div > PWM_PRD_MASK) {
137 + dev_err(chip->dev, "prescaler exceeds the maximum value\n");
143 + do_div(div, period_ns);
146 + ret = clk_prepare_enable(sunxi_pwm->clk);
148 + dev_err(chip->dev, "failed to enable PWM clock\n");
152 + mutex_lock(&sunxi_pwm->ctrl_lock);
153 + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
155 + if (sunxi_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
156 + mutex_unlock(&sunxi_pwm->ctrl_lock);
157 + clk_disable_unprepare(sunxi_pwm->clk);
161 + clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
163 + val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
164 + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
167 + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
168 + val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
170 + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
172 + sunxi_pwm_writel(sunxi_pwm, PWM_CH_PRD(pwm->hwpwm), dty | PWM_PRD(prd));
175 + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
177 + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
180 + mutex_unlock(&sunxi_pwm->ctrl_lock);
181 + clk_disable_unprepare(sunxi_pwm->clk);
186 +static int sunxi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
187 + enum pwm_polarity polarity)
189 + struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
193 + ret = clk_prepare_enable(sunxi_pwm->clk);
195 + dev_err(chip->dev, "failed to enable PWM clock\n");
199 + mutex_lock(&sunxi_pwm->ctrl_lock);
200 + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
202 + if (polarity != PWM_POLARITY_NORMAL)
203 + val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
205 + val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
208 + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
210 + mutex_unlock(&sunxi_pwm->ctrl_lock);
211 + clk_disable_unprepare(sunxi_pwm->clk);
216 +static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
218 + struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
222 + ret = clk_prepare_enable(sunxi_pwm->clk);
224 + dev_err(chip->dev, "failed to enable PWM clock\n");
228 + mutex_lock(&sunxi_pwm->ctrl_lock);
229 + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
230 + val |= BIT_CH(PWM_EN, pwm->hwpwm);
231 + val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
232 + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
233 + mutex_unlock(&sunxi_pwm->ctrl_lock);
238 +static void sunxi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
240 + struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
243 + mutex_lock(&sunxi_pwm->ctrl_lock);
244 + val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
245 + val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
246 + val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
247 + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
248 + mutex_unlock(&sunxi_pwm->ctrl_lock);
250 + clk_disable_unprepare(sunxi_pwm->clk);
253 +static const struct pwm_ops sunxi_pwm_ops = {
254 + .config = sunxi_pwm_config,
255 + .set_polarity = sunxi_pwm_set_polarity,
256 + .enable = sunxi_pwm_enable,
257 + .disable = sunxi_pwm_disable,
258 + .owner = THIS_MODULE,
261 +static const struct sunxi_pwm_data sunxi_pwm_data_a10 = {
265 +static const struct sunxi_pwm_data sunxi_pwm_data_a20 = {
269 +static const struct of_device_id sunxi_pwm_dt_ids[] = {
271 + .compatible = "allwinner,sun4i-a10-pwm",
272 + .data = &sunxi_pwm_data_a10,
274 + .compatible = "allwinner,sun7i-a20-pwm",
275 + .data = &sunxi_pwm_data_a20,
280 +MODULE_DEVICE_TABLE(of, sunxi_pwm_dt_ids);
282 +static int sunxi_pwm_probe(struct platform_device *pdev)
284 + struct sunxi_pwm_chip *sunxi_pwm;
285 + struct resource *res;
288 + const struct of_device_id *match;
290 + match = of_match_device(sunxi_pwm_dt_ids, &pdev->dev);
291 + if (!match || !match->data)
294 + sunxi_pwm = devm_kzalloc(&pdev->dev, sizeof(*sunxi_pwm), GFP_KERNEL);
298 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299 + sunxi_pwm->base = devm_ioremap_resource(&pdev->dev, res);
300 + if (IS_ERR(sunxi_pwm->base))
301 + return PTR_ERR(sunxi_pwm->base);
303 + sunxi_pwm->clk = devm_clk_get(&pdev->dev, NULL);
304 + if (IS_ERR(sunxi_pwm->clk))
305 + return PTR_ERR(sunxi_pwm->clk);
307 + sunxi_pwm->chip.dev = &pdev->dev;
308 + sunxi_pwm->chip.ops = &sunxi_pwm_ops;
310 + sunxi_pwm->chip.base = -1;
311 + sunxi_pwm->chip.npwm = 2;
312 + sunxi_pwm->chip.can_sleep = true;
313 + sunxi_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
314 + sunxi_pwm->chip.of_pwm_n_cells = 3;
315 + sunxi_pwm->data = match->data;
317 + mutex_init(&sunxi_pwm->ctrl_lock);
319 + ret = clk_prepare_enable(sunxi_pwm->clk);
321 + dev_err(&pdev->dev, "failed to enable PWM clock\n");
325 + /* By default, the polarity is inversed, set it to normal */
326 + sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG,
327 + BIT_CH(PWM_ACT_STATE, 0) |
328 + BIT_CH(PWM_ACT_STATE, 1));
329 + clk_disable_unprepare(sunxi_pwm->clk);
331 + ret = pwmchip_add(&sunxi_pwm->chip);
333 + dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
337 + platform_set_drvdata(pdev, sunxi_pwm);
342 + mutex_destroy(&sunxi_pwm->ctrl_lock);
343 + clk_disable_unprepare(sunxi_pwm->clk);
347 +static int sunxi_pwm_remove(struct platform_device *pdev)
349 + struct sunxi_pwm_chip *sunxi_pwm = platform_get_drvdata(pdev);
351 + mutex_destroy(&sunxi_pwm->ctrl_lock);
353 + return pwmchip_remove(&sunxi_pwm->chip);
356 +static struct platform_driver sunxi_pwm_driver = {
358 + .name = "sunxi-pwm",
359 + .of_match_table = sunxi_pwm_dt_ids,
361 + .probe = sunxi_pwm_probe,
362 + .remove = sunxi_pwm_remove,
364 +module_platform_driver(sunxi_pwm_driver);
366 +MODULE_ALIAS("platform:sunxi-pwm");
367 +MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
368 +MODULE_DESCRIPTION("Allwinner PWM driver");
369 +MODULE_LICENSE("GPL v2");