target/linux/sunxi/patches-3.14/140-dt-sunxi-convert-to-new-clock-compats.patch

   1 From 46b2ee17d7321149b4d48dd86ee2e346624aa141 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Thu, 6 Feb 2014 09:55:58 +0100
   4 Subject: [PATCH] ARM: sunxi: dt: Convert to the new clock compatibles
   5
   6 Switch the device tree to the new compatibles introduced in the clock drivers
   7 to have a common pattern accross all Allwinner SoCs.
   8
   9 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  10 ---
  11  arch/arm/boot/dts/sun4i-a10.dtsi  | 60 +++++++++++++++++++--------------------
  12  arch/arm/boot/dts/sun5i-a10s.dtsi | 48 +++++++++++++++----------------
  13  arch/arm/boot/dts/sun5i-a13.dtsi  | 48 +++++++++++++++----------------
  14  arch/arm/boot/dts/sun6i-a31.dtsi  | 10 +++----
  15  arch/arm/boot/dts/sun7i-a20.dtsi  | 54 +++++++++++++++++------------------
  16  5 files changed, 110 insertions(+), 110 deletions(-)
  17
  18 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
  19 index 2d623d0..f6f41d6 100644
  20 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  21 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  22 @@ -60,7 +60,7 @@
  23
  24                 osc24M: clk@01c20050 {
  25                         #clock-cells = <0>;
  26 -                       compatible = "allwinner,sun4i-osc-clk";
  27 +                       compatible = "allwinner,sun4i-a10-osc-clk";
  28                         reg = <0x01c20050 0x4>;
  29                         clock-frequency = <24000000>;
  30                         clock-output-names = "osc24M";
  31 @@ -75,7 +75,7 @@
  32
  33                 pll1: clk@01c20000 {
  34                         #clock-cells = <0>;
  35 -                       compatible = "allwinner,sun4i-pll1-clk";
  36 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
  37                         reg = <0x01c20000 0x4>;
  38                         clocks = <&osc24M>;
  39                         clock-output-names = "pll1";
  40 @@ -83,7 +83,7 @@
  41
  42                 pll4: clk@01c20018 {
  43                         #clock-cells = <0>;
  44 -                       compatible = "allwinner,sun4i-pll1-clk";
  45 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
  46                         reg = <0x01c20018 0x4>;
  47                         clocks = <&osc24M>;
  48                         clock-output-names = "pll4";
  49 @@ -91,7 +91,7 @@
  50
  51                 pll5: clk@01c20020 {
  52                         #clock-cells = <1>;
  53 -                       compatible = "allwinner,sun4i-pll5-clk";
  54 +                       compatible = "allwinner,sun4i-a10-pll5-clk";
  55                         reg = <0x01c20020 0x4>;
  56                         clocks = <&osc24M>;
  57                         clock-output-names = "pll5_ddr", "pll5_other";
  58 @@ -99,7 +99,7 @@
  59
  60                 pll6: clk@01c20028 {
  61                         #clock-cells = <1>;
  62 -                       compatible = "allwinner,sun4i-pll6-clk";
  63 +                       compatible = "allwinner,sun4i-a10-pll6-clk";
  64                         reg = <0x01c20028 0x4>;
  65                         clocks = <&osc24M>;
  66                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
  67 @@ -108,7 +108,7 @@
  68                 /* dummy is 200M */
  69                 cpu: cpu@01c20054 {
  70                         #clock-cells = <0>;
  71 -                       compatible = "allwinner,sun4i-cpu-clk";
  72 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
  73                         reg = <0x01c20054 0x4>;
  74                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  75                         clock-output-names = "cpu";
  76 @@ -116,7 +116,7 @@
  77
  78                 axi: axi@01c20054 {
  79                         #clock-cells = <0>;
  80 -                       compatible = "allwinner,sun4i-axi-clk";
  81 +                       compatible = "allwinner,sun4i-a10-axi-clk";
  82                         reg = <0x01c20054 0x4>;
  83                         clocks = <&cpu>;
  84                         clock-output-names = "axi";
  85 @@ -124,7 +124,7 @@
  86
  87                 axi_gates: clk@01c2005c {
  88                         #clock-cells = <1>;
  89 -                       compatible = "allwinner,sun4i-axi-gates-clk";
  90 +                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
  91                         reg = <0x01c2005c 0x4>;
  92                         clocks = <&axi>;
  93                         clock-output-names = "axi_dram";
  94 @@ -132,7 +132,7 @@
  95
  96                 ahb: ahb@01c20054 {
  97                         #clock-cells = <0>;
  98 -                       compatible = "allwinner,sun4i-ahb-clk";
  99 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 100                         reg = <0x01c20054 0x4>;
 101                         clocks = <&axi>;
 102                         clock-output-names = "ahb";
 103 @@ -140,7 +140,7 @@
 104
 105                 ahb_gates: clk@01c20060 {
 106                         #clock-cells = <1>;
 107 -                       compatible = "allwinner,sun4i-ahb-gates-clk";
 108 +                       compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 109                         reg = <0x01c20060 0x8>;
 110                         clocks = <&ahb>;
 111                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 112 @@ -158,7 +158,7 @@
 113
 114                 apb0: apb0@01c20054 {
 115                         #clock-cells = <0>;
 116 -                       compatible = "allwinner,sun4i-apb0-clk";
 117 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 118                         reg = <0x01c20054 0x4>;
 119                         clocks = <&ahb>;
 120                         clock-output-names = "apb0";
 121 @@ -166,7 +166,7 @@
 122
 123                 apb0_gates: clk@01c20068 {
 124                         #clock-cells = <1>;
 125 -                       compatible = "allwinner,sun4i-apb0-gates-clk";
 126 +                       compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 127                         reg = <0x01c20068 0x4>;
 128                         clocks = <&apb0>;
 129                         clock-output-names = "apb0_codec", "apb0_spdif",
 130 @@ -176,7 +176,7 @@
 131
 132                 apb1_mux: apb1_mux@01c20058 {
 133                         #clock-cells = <0>;
 134 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 135 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 136                         reg = <0x01c20058 0x4>;
 137                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 138                         clock-output-names = "apb1_mux";
 139 @@ -184,7 +184,7 @@
 140
 141                 apb1: apb1@01c20058 {
 142                         #clock-cells = <0>;
 143 -                       compatible = "allwinner,sun4i-apb1-clk";
 144 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 145                         reg = <0x01c20058 0x4>;
 146                         clocks = <&apb1_mux>;
 147                         clock-output-names = "apb1";
 148 @@ -192,7 +192,7 @@
 149
 150                 apb1_gates: clk@01c2006c {
 151                         #clock-cells = <1>;
 152 -                       compatible = "allwinner,sun4i-apb1-gates-clk";
 153 +                       compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 154                         reg = <0x01c2006c 0x4>;
 155                         clocks = <&apb1>;
 156                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 157 @@ -205,7 +205,7 @@
 158
 159                 nand_clk: clk@01c20080 {
 160                         #clock-cells = <0>;
 161 -                       compatible = "allwinner,sun4i-mod0-clk";
 162 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 163                         reg = <0x01c20080 0x4>;
 164                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 165                         clock-output-names = "nand";
 166 @@ -213,7 +213,7 @@
 167
 168                 ms_clk: clk@01c20084 {
 169                         #clock-cells = <0>;
 170 -                       compatible = "allwinner,sun4i-mod0-clk";
 171 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 172                         reg = <0x01c20084 0x4>;
 173                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 174                         clock-output-names = "ms";
 175 @@ -221,7 +221,7 @@
 176
 177                 mmc0_clk: clk@01c20088 {
 178                         #clock-cells = <0>;
 179 -                       compatible = "allwinner,sun4i-mod0-clk";
 180 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 181                         reg = <0x01c20088 0x4>;
 182                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 183                         clock-output-names = "mmc0";
 184 @@ -229,7 +229,7 @@
 185
 186                 mmc1_clk: clk@01c2008c {
 187                         #clock-cells = <0>;
 188 -                       compatible = "allwinner,sun4i-mod0-clk";
 189 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 190                         reg = <0x01c2008c 0x4>;
 191                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 192                         clock-output-names = "mmc1";
 193 @@ -237,7 +237,7 @@
 194
 195                 mmc2_clk: clk@01c20090 {
 196                         #clock-cells = <0>;
 197 -                       compatible = "allwinner,sun4i-mod0-clk";
 198 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 199                         reg = <0x01c20090 0x4>;
 200                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 201                         clock-output-names = "mmc2";
 202 @@ -245,7 +245,7 @@
 203
 204                 mmc3_clk: clk@01c20094 {
 205                         #clock-cells = <0>;
 206 -                       compatible = "allwinner,sun4i-mod0-clk";
 207 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 208                         reg = <0x01c20094 0x4>;
 209                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 210                         clock-output-names = "mmc3";
 211 @@ -253,7 +253,7 @@
 212
 213                 ts_clk: clk@01c20098 {
 214                         #clock-cells = <0>;
 215 -                       compatible = "allwinner,sun4i-mod0-clk";
 216 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 217                         reg = <0x01c20098 0x4>;
 218                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 219                         clock-output-names = "ts";
 220 @@ -261,7 +261,7 @@
 221
 222                 ss_clk: clk@01c2009c {
 223                         #clock-cells = <0>;
 224 -                       compatible = "allwinner,sun4i-mod0-clk";
 225 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 226                         reg = <0x01c2009c 0x4>;
 227                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 228                         clock-output-names = "ss";
 229 @@ -269,7 +269,7 @@
 230
 231                 spi0_clk: clk@01c200a0 {
 232                         #clock-cells = <0>;
 233 -                       compatible = "allwinner,sun4i-mod0-clk";
 234 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 235                         reg = <0x01c200a0 0x4>;
 236                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 237                         clock-output-names = "spi0";
 238 @@ -277,7 +277,7 @@
 239
 240                 spi1_clk: clk@01c200a4 {
 241                         #clock-cells = <0>;
 242 -                       compatible = "allwinner,sun4i-mod0-clk";
 243 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 244                         reg = <0x01c200a4 0x4>;
 245                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 246                         clock-output-names = "spi1";
 247 @@ -285,7 +285,7 @@
 248
 249                 spi2_clk: clk@01c200a8 {
 250                         #clock-cells = <0>;
 251 -                       compatible = "allwinner,sun4i-mod0-clk";
 252 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 253                         reg = <0x01c200a8 0x4>;
 254                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 255                         clock-output-names = "spi2";
 256 @@ -293,7 +293,7 @@
 257
 258                 pata_clk: clk@01c200ac {
 259                         #clock-cells = <0>;
 260 -                       compatible = "allwinner,sun4i-mod0-clk";
 261 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 262                         reg = <0x01c200ac 0x4>;
 263                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 264                         clock-output-names = "pata";
 265 @@ -301,7 +301,7 @@
 266
 267                 ir0_clk: clk@01c200b0 {
 268                         #clock-cells = <0>;
 269 -                       compatible = "allwinner,sun4i-mod0-clk";
 270 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 271                         reg = <0x01c200b0 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "ir0";
 274 @@ -309,7 +309,7 @@
 275
 276                 ir1_clk: clk@01c200b4 {
 277                         #clock-cells = <0>;
 278 -                       compatible = "allwinner,sun4i-mod0-clk";
 279 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 280                         reg = <0x01c200b4 0x4>;
 281                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 282                         clock-output-names = "ir1";
 283 @@ -326,7 +326,7 @@
 284
 285                 spi3_clk: clk@01c200d4 {
 286                         #clock-cells = <0>;
 287 -                       compatible = "allwinner,sun4i-mod0-clk";
 288 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 289                         reg = <0x01c200d4 0x4>;
 290                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 291                         clock-output-names = "spi3";
 292 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
 293 index 905317e..df90a29 100644
 294 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
 295 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
 296 @@ -53,7 +53,7 @@
 297
 298                 osc24M: clk@01c20050 {
 299                         #clock-cells = <0>;
 300 -                       compatible = "allwinner,sun4i-osc-clk";
 301 +                       compatible = "allwinner,sun4i-a10-osc-clk";
 302                         reg = <0x01c20050 0x4>;
 303                         clock-frequency = <24000000>;
 304                         clock-output-names = "osc24M";
 305 @@ -68,7 +68,7 @@
 306
 307                 pll1: clk@01c20000 {
 308                         #clock-cells = <0>;
 309 -                       compatible = "allwinner,sun4i-pll1-clk";
 310 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 311                         reg = <0x01c20000 0x4>;
 312                         clocks = <&osc24M>;
 313                         clock-output-names = "pll1";
 314 @@ -76,7 +76,7 @@
 315
 316                 pll4: clk@01c20018 {
 317                         #clock-cells = <0>;
 318 -                       compatible = "allwinner,sun4i-pll1-clk";
 319 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 320                         reg = <0x01c20018 0x4>;
 321                         clocks = <&osc24M>;
 322                         clock-output-names = "pll4";
 323 @@ -84,7 +84,7 @@
 324
 325                 pll5: clk@01c20020 {
 326                         #clock-cells = <1>;
 327 -                       compatible = "allwinner,sun4i-pll5-clk";
 328 +                       compatible = "allwinner,sun4i-a10-pll5-clk";
 329                         reg = <0x01c20020 0x4>;
 330                         clocks = <&osc24M>;
 331                         clock-output-names = "pll5_ddr", "pll5_other";
 332 @@ -92,7 +92,7 @@
 333
 334                 pll6: clk@01c20028 {
 335                         #clock-cells = <1>;
 336 -                       compatible = "allwinner,sun4i-pll6-clk";
 337 +                       compatible = "allwinner,sun4i-a10-pll6-clk";
 338                         reg = <0x01c20028 0x4>;
 339                         clocks = <&osc24M>;
 340                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 341 @@ -101,7 +101,7 @@
 342                 /* dummy is 200M */
 343                 cpu: cpu@01c20054 {
 344                         #clock-cells = <0>;
 345 -                       compatible = "allwinner,sun4i-cpu-clk";
 346 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 347                         reg = <0x01c20054 0x4>;
 348                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 349                         clock-output-names = "cpu";
 350 @@ -109,7 +109,7 @@
 351
 352                 axi: axi@01c20054 {
 353                         #clock-cells = <0>;
 354 -                       compatible = "allwinner,sun4i-axi-clk";
 355 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 356                         reg = <0x01c20054 0x4>;
 357                         clocks = <&cpu>;
 358                         clock-output-names = "axi";
 359 @@ -117,7 +117,7 @@
 360
 361                 axi_gates: clk@01c2005c {
 362                         #clock-cells = <1>;
 363 -                       compatible = "allwinner,sun4i-axi-gates-clk";
 364 +                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
 365                         reg = <0x01c2005c 0x4>;
 366                         clocks = <&axi>;
 367                         clock-output-names = "axi_dram";
 368 @@ -125,7 +125,7 @@
 369
 370                 ahb: ahb@01c20054 {
 371                         #clock-cells = <0>;
 372 -                       compatible = "allwinner,sun4i-ahb-clk";
 373 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 374                         reg = <0x01c20054 0x4>;
 375                         clocks = <&axi>;
 376                         clock-output-names = "ahb";
 377 @@ -147,7 +147,7 @@
 378
 379                 apb0: apb0@01c20054 {
 380                         #clock-cells = <0>;
 381 -                       compatible = "allwinner,sun4i-apb0-clk";
 382 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 383                         reg = <0x01c20054 0x4>;
 384                         clocks = <&ahb>;
 385                         clock-output-names = "apb0";
 386 @@ -164,7 +164,7 @@
 387
 388                 apb1_mux: apb1_mux@01c20058 {
 389                         #clock-cells = <0>;
 390 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 391 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 392                         reg = <0x01c20058 0x4>;
 393                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 394                         clock-output-names = "apb1_mux";
 395 @@ -172,7 +172,7 @@
 396
 397                 apb1: apb1@01c20058 {
 398                         #clock-cells = <0>;
 399 -                       compatible = "allwinner,sun4i-apb1-clk";
 400 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 401                         reg = <0x01c20058 0x4>;
 402                         clocks = <&apb1_mux>;
 403                         clock-output-names = "apb1";
 404 @@ -190,7 +190,7 @@
 405
 406                 nand_clk: clk@01c20080 {
 407                         #clock-cells = <0>;
 408 -                       compatible = "allwinner,sun4i-mod0-clk";
 409 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 410                         reg = <0x01c20080 0x4>;
 411                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 412                         clock-output-names = "nand";
 413 @@ -198,7 +198,7 @@
 414
 415                 ms_clk: clk@01c20084 {
 416                         #clock-cells = <0>;
 417 -                       compatible = "allwinner,sun4i-mod0-clk";
 418 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 419                         reg = <0x01c20084 0x4>;
 420                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 421                         clock-output-names = "ms";
 422 @@ -206,7 +206,7 @@
 423
 424                 mmc0_clk: clk@01c20088 {
 425                         #clock-cells = <0>;
 426 -                       compatible = "allwinner,sun4i-mod0-clk";
 427 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 428                         reg = <0x01c20088 0x4>;
 429                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 430                         clock-output-names = "mmc0";
 431 @@ -214,7 +214,7 @@
 432
 433                 mmc1_clk: clk@01c2008c {
 434                         #clock-cells = <0>;
 435 -                       compatible = "allwinner,sun4i-mod0-clk";
 436 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 437                         reg = <0x01c2008c 0x4>;
 438                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 439                         clock-output-names = "mmc1";
 440 @@ -222,7 +222,7 @@
 441
 442                 mmc2_clk: clk@01c20090 {
 443                         #clock-cells = <0>;
 444 -                       compatible = "allwinner,sun4i-mod0-clk";
 445 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 446                         reg = <0x01c20090 0x4>;
 447                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 448                         clock-output-names = "mmc2";
 449 @@ -230,7 +230,7 @@
 450
 451                 ts_clk: clk@01c20098 {
 452                         #clock-cells = <0>;
 453 -                       compatible = "allwinner,sun4i-mod0-clk";
 454 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 455                         reg = <0x01c20098 0x4>;
 456                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 457                         clock-output-names = "ts";
 458 @@ -238,7 +238,7 @@
 459
 460                 ss_clk: clk@01c2009c {
 461                         #clock-cells = <0>;
 462 -                       compatible = "allwinner,sun4i-mod0-clk";
 463 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 464                         reg = <0x01c2009c 0x4>;
 465                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 466                         clock-output-names = "ss";
 467 @@ -246,7 +246,7 @@
 468
 469                 spi0_clk: clk@01c200a0 {
 470                         #clock-cells = <0>;
 471 -                       compatible = "allwinner,sun4i-mod0-clk";
 472 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 473                         reg = <0x01c200a0 0x4>;
 474                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 475                         clock-output-names = "spi0";
 476 @@ -254,7 +254,7 @@
 477
 478                 spi1_clk: clk@01c200a4 {
 479                         #clock-cells = <0>;
 480 -                       compatible = "allwinner,sun4i-mod0-clk";
 481 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 482                         reg = <0x01c200a4 0x4>;
 483                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 484                         clock-output-names = "spi1";
 485 @@ -262,7 +262,7 @@
 486
 487                 spi2_clk: clk@01c200a8 {
 488                         #clock-cells = <0>;
 489 -                       compatible = "allwinner,sun4i-mod0-clk";
 490 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 491                         reg = <0x01c200a8 0x4>;
 492                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 493                         clock-output-names = "spi2";
 494 @@ -270,7 +270,7 @@
 495
 496                 ir0_clk: clk@01c200b0 {
 497                         #clock-cells = <0>;
 498 -                       compatible = "allwinner,sun4i-mod0-clk";
 499 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 500                         reg = <0x01c200b0 0x4>;
 501                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 502                         clock-output-names = "ir0";
 503 @@ -287,7 +287,7 @@
 504
 505                 mbus_clk: clk@01c2015c {
 506                         #clock-cells = <0>;
 507 -                       compatible = "allwinner,sun4i-mod0-clk";
 508 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 509                         reg = <0x01c2015c 0x4>;
 510                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 511                         clock-output-names = "mbus";
 512 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
 513 index d196ebc6..24cd86cb 100644
 514 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 515 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 516 @@ -54,7 +54,7 @@
 517
 518                 osc24M: clk@01c20050 {
 519                         #clock-cells = <0>;
 520 -                       compatible = "allwinner,sun4i-osc-clk";
 521 +                       compatible = "allwinner,sun4i-a10-osc-clk";
 522                         reg = <0x01c20050 0x4>;
 523                         clock-frequency = <24000000>;
 524                         clock-output-names = "osc24M";
 525 @@ -69,7 +69,7 @@
 526
 527                 pll1: clk@01c20000 {
 528                         #clock-cells = <0>;
 529 -                       compatible = "allwinner,sun4i-pll1-clk";
 530 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 531                         reg = <0x01c20000 0x4>;
 532                         clocks = <&osc24M>;
 533                         clock-output-names = "pll1";
 534 @@ -77,7 +77,7 @@
 535
 536                 pll4: clk@01c20018 {
 537                         #clock-cells = <0>;
 538 -                       compatible = "allwinner,sun4i-pll1-clk";
 539 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 540                         reg = <0x01c20018 0x4>;
 541                         clocks = <&osc24M>;
 542                         clock-output-names = "pll4";
 543 @@ -85,7 +85,7 @@
 544
 545                 pll5: clk@01c20020 {
 546                         #clock-cells = <1>;
 547 -                       compatible = "allwinner,sun4i-pll5-clk";
 548 +                       compatible = "allwinner,sun4i-a10-pll5-clk";
 549                         reg = <0x01c20020 0x4>;
 550                         clocks = <&osc24M>;
 551                         clock-output-names = "pll5_ddr", "pll5_other";
 552 @@ -93,7 +93,7 @@
 553
 554                 pll6: clk@01c20028 {
 555                         #clock-cells = <1>;
 556 -                       compatible = "allwinner,sun4i-pll6-clk";
 557 +                       compatible = "allwinner,sun4i-a10-pll6-clk";
 558                         reg = <0x01c20028 0x4>;
 559                         clocks = <&osc24M>;
 560                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 561 @@ -102,7 +102,7 @@
 562                 /* dummy is 200M */
 563                 cpu: cpu@01c20054 {
 564                         #clock-cells = <0>;
 565 -                       compatible = "allwinner,sun4i-cpu-clk";
 566 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 567                         reg = <0x01c20054 0x4>;
 568                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 569                         clock-output-names = "cpu";
 570 @@ -110,7 +110,7 @@
 571
 572                 axi: axi@01c20054 {
 573                         #clock-cells = <0>;
 574 -                       compatible = "allwinner,sun4i-axi-clk";
 575 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 576                         reg = <0x01c20054 0x4>;
 577                         clocks = <&cpu>;
 578                         clock-output-names = "axi";
 579 @@ -118,7 +118,7 @@
 580
 581                 axi_gates: clk@01c2005c {
 582                         #clock-cells = <1>;
 583 -                       compatible = "allwinner,sun4i-axi-gates-clk";
 584 +                       compatible = "allwinner,sun4i-a10-axi-gates-clk";
 585                         reg = <0x01c2005c 0x4>;
 586                         clocks = <&axi>;
 587                         clock-output-names = "axi_dram";
 588 @@ -126,7 +126,7 @@
 589
 590                 ahb: ahb@01c20054 {
 591                         #clock-cells = <0>;
 592 -                       compatible = "allwinner,sun4i-ahb-clk";
 593 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 594                         reg = <0x01c20054 0x4>;
 595                         clocks = <&axi>;
 596                         clock-output-names = "ahb";
 597 @@ -147,7 +147,7 @@
 598
 599                 apb0: apb0@01c20054 {
 600                         #clock-cells = <0>;
 601 -                       compatible = "allwinner,sun4i-apb0-clk";
 602 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 603                         reg = <0x01c20054 0x4>;
 604                         clocks = <&ahb>;
 605                         clock-output-names = "apb0";
 606 @@ -163,7 +163,7 @@
 607
 608                 apb1_mux: apb1_mux@01c20058 {
 609                         #clock-cells = <0>;
 610 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 611 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 612                         reg = <0x01c20058 0x4>;
 613                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 614                         clock-output-names = "apb1_mux";
 615 @@ -171,7 +171,7 @@
 616
 617                 apb1: apb1@01c20058 {
 618                         #clock-cells = <0>;
 619 -                       compatible = "allwinner,sun4i-apb1-clk";
 620 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 621                         reg = <0x01c20058 0x4>;
 622                         clocks = <&apb1_mux>;
 623                         clock-output-names = "apb1";
 624 @@ -188,7 +188,7 @@
 625
 626                 nand_clk: clk@01c20080 {
 627                         #clock-cells = <0>;
 628 -                       compatible = "allwinner,sun4i-mod0-clk";
 629 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 630                         reg = <0x01c20080 0x4>;
 631                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 632                         clock-output-names = "nand";
 633 @@ -196,7 +196,7 @@
 634
 635                 ms_clk: clk@01c20084 {
 636                         #clock-cells = <0>;
 637 -                       compatible = "allwinner,sun4i-mod0-clk";
 638 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 639                         reg = <0x01c20084 0x4>;
 640                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 641                         clock-output-names = "ms";
 642 @@ -204,7 +204,7 @@
 643
 644                 mmc0_clk: clk@01c20088 {
 645                         #clock-cells = <0>;
 646 -                       compatible = "allwinner,sun4i-mod0-clk";
 647 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 648                         reg = <0x01c20088 0x4>;
 649                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 650                         clock-output-names = "mmc0";
 651 @@ -212,7 +212,7 @@
 652
 653                 mmc1_clk: clk@01c2008c {
 654                         #clock-cells = <0>;
 655 -                       compatible = "allwinner,sun4i-mod0-clk";
 656 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 657                         reg = <0x01c2008c 0x4>;
 658                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 659                         clock-output-names = "mmc1";
 660 @@ -220,7 +220,7 @@
 661
 662                 mmc2_clk: clk@01c20090 {
 663                         #clock-cells = <0>;
 664 -                       compatible = "allwinner,sun4i-mod0-clk";
 665 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 666                         reg = <0x01c20090 0x4>;
 667                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 668                         clock-output-names = "mmc2";
 669 @@ -228,7 +228,7 @@
 670
 671                 ts_clk: clk@01c20098 {
 672                         #clock-cells = <0>;
 673 -                       compatible = "allwinner,sun4i-mod0-clk";
 674 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 675                         reg = <0x01c20098 0x4>;
 676                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 677                         clock-output-names = "ts";
 678 @@ -236,7 +236,7 @@
 679
 680                 ss_clk: clk@01c2009c {
 681                         #clock-cells = <0>;
 682 -                       compatible = "allwinner,sun4i-mod0-clk";
 683 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 684                         reg = <0x01c2009c 0x4>;
 685                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 686                         clock-output-names = "ss";
 687 @@ -244,7 +244,7 @@
 688
 689                 spi0_clk: clk@01c200a0 {
 690                         #clock-cells = <0>;
 691 -                       compatible = "allwinner,sun4i-mod0-clk";
 692 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 693                         reg = <0x01c200a0 0x4>;
 694                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 695                         clock-output-names = "spi0";
 696 @@ -252,7 +252,7 @@
 697
 698                 spi1_clk: clk@01c200a4 {
 699                         #clock-cells = <0>;
 700 -                       compatible = "allwinner,sun4i-mod0-clk";
 701 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 702                         reg = <0x01c200a4 0x4>;
 703                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 704                         clock-output-names = "spi1";
 705 @@ -260,7 +260,7 @@
 706
 707                 spi2_clk: clk@01c200a8 {
 708                         #clock-cells = <0>;
 709 -                       compatible = "allwinner,sun4i-mod0-clk";
 710 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 711                         reg = <0x01c200a8 0x4>;
 712                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 713                         clock-output-names = "spi2";
 714 @@ -268,7 +268,7 @@
 715
 716                 ir0_clk: clk@01c200b0 {
 717                         #clock-cells = <0>;
 718 -                       compatible = "allwinner,sun4i-mod0-clk";
 719 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 720                         reg = <0x01c200b0 0x4>;
 721                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 722                         clock-output-names = "ir0";
 723 @@ -285,7 +285,7 @@
 724
 725                 mbus_clk: clk@01c2015c {
 726                         #clock-cells = <0>;
 727 -                       compatible = "allwinner,sun4i-mod0-clk";
 728 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 729                         reg = <0x01c2015c 0x4>;
 730                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 731                         clock-output-names = "mbus";
 732 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
 733 index d3f1995..af6f87c 100644
 734 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
 735 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
 736 @@ -95,7 +95,7 @@
 737
 738                 cpu: cpu@01c20050 {
 739                         #clock-cells = <0>;
 740 -                       compatible = "allwinner,sun4i-cpu-clk";
 741 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 742                         reg = <0x01c20050 0x4>;
 743
 744                         /*
 745 @@ -110,7 +110,7 @@
 746
 747                 axi: axi@01c20050 {
 748                         #clock-cells = <0>;
 749 -                       compatible = "allwinner,sun4i-axi-clk";
 750 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 751                         reg = <0x01c20050 0x4>;
 752                         clocks = <&cpu>;
 753                         clock-output-names = "axi";
 754 @@ -126,7 +126,7 @@
 755
 756                 ahb1: ahb1@01c20054 {
 757                         #clock-cells = <0>;
 758 -                       compatible = "allwinner,sun4i-ahb-clk";
 759 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 760                         reg = <0x01c20054 0x4>;
 761                         clocks = <&ahb1_mux>;
 762                         clock-output-names = "ahb1";
 763 @@ -155,7 +155,7 @@
 764
 765                 apb1: apb1@01c20054 {
 766                         #clock-cells = <0>;
 767 -                       compatible = "allwinner,sun4i-apb0-clk";
 768 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 769                         reg = <0x01c20054 0x4>;
 770                         clocks = <&ahb1>;
 771                         clock-output-names = "apb1";
 772 @@ -173,7 +173,7 @@
 773
 774                 apb2_mux: apb2_mux@01c20058 {
 775                         #clock-cells = <0>;
 776 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 777 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 778                         reg = <0x01c20058 0x4>;
 779                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 780                         clock-output-names = "apb2_mux";
 781 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
 782 index 911d4e4..d00fbf8 100644
 783 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
 784 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
 785 @@ -64,7 +64,7 @@
 786
 787                 osc24M: clk@01c20050 {
 788                         #clock-cells = <0>;
 789 -                       compatible = "allwinner,sun4i-osc-clk";
 790 +                       compatible = "allwinner,sun4i-a10-osc-clk";
 791                         reg = <0x01c20050 0x4>;
 792                         clock-frequency = <24000000>;
 793                         clock-output-names = "osc24M";
 794 @@ -79,7 +79,7 @@
 795
 796                 pll1: clk@01c20000 {
 797                         #clock-cells = <0>;
 798 -                       compatible = "allwinner,sun4i-pll1-clk";
 799 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 800                         reg = <0x01c20000 0x4>;
 801                         clocks = <&osc24M>;
 802                         clock-output-names = "pll1";
 803 @@ -87,7 +87,7 @@
 804
 805                 pll4: clk@01c20018 {
 806                         #clock-cells = <0>;
 807 -                       compatible = "allwinner,sun4i-pll1-clk";
 808 +                       compatible = "allwinner,sun4i-a10-pll1-clk";
 809                         reg = <0x01c20018 0x4>;
 810                         clocks = <&osc24M>;
 811                         clock-output-names = "pll4";
 812 @@ -95,7 +95,7 @@
 813
 814                 pll5: clk@01c20020 {
 815                         #clock-cells = <1>;
 816 -                       compatible = "allwinner,sun4i-pll5-clk";
 817 +                       compatible = "allwinner,sun4i-a10-pll5-clk";
 818                         reg = <0x01c20020 0x4>;
 819                         clocks = <&osc24M>;
 820                         clock-output-names = "pll5_ddr", "pll5_other";
 821 @@ -103,7 +103,7 @@
 822
 823                 pll6: clk@01c20028 {
 824                         #clock-cells = <1>;
 825 -                       compatible = "allwinner,sun4i-pll6-clk";
 826 +                       compatible = "allwinner,sun4i-a10-pll6-clk";
 827                         reg = <0x01c20028 0x4>;
 828                         clocks = <&osc24M>;
 829                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 830 @@ -111,7 +111,7 @@
 831
 832                 cpu: cpu@01c20054 {
 833                         #clock-cells = <0>;
 834 -                       compatible = "allwinner,sun4i-cpu-clk";
 835 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 836                         reg = <0x01c20054 0x4>;
 837                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 838                         clock-output-names = "cpu";
 839 @@ -119,7 +119,7 @@
 840
 841                 axi: axi@01c20054 {
 842                         #clock-cells = <0>;
 843 -                       compatible = "allwinner,sun4i-axi-clk";
 844 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 845                         reg = <0x01c20054 0x4>;
 846                         clocks = <&cpu>;
 847                         clock-output-names = "axi";
 848 @@ -127,7 +127,7 @@
 849
 850                 ahb: ahb@01c20054 {
 851                         #clock-cells = <0>;
 852 -                       compatible = "allwinner,sun4i-ahb-clk";
 853 +                       compatible = "allwinner,sun4i-a10-ahb-clk";
 854                         reg = <0x01c20054 0x4>;
 855                         clocks = <&axi>;
 856                         clock-output-names = "ahb";
 857 @@ -155,7 +155,7 @@
 858
 859                 apb0: apb0@01c20054 {
 860                         #clock-cells = <0>;
 861 -                       compatible = "allwinner,sun4i-apb0-clk";
 862 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 863                         reg = <0x01c20054 0x4>;
 864                         clocks = <&ahb>;
 865                         clock-output-names = "apb0";
 866 @@ -174,7 +174,7 @@
 867
 868                 apb1_mux: apb1_mux@01c20058 {
 869                         #clock-cells = <0>;
 870 -                       compatible = "allwinner,sun4i-apb1-mux-clk";
 871 +                       compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 872                         reg = <0x01c20058 0x4>;
 873                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 874                         clock-output-names = "apb1_mux";
 875 @@ -182,7 +182,7 @@
 876
 877                 apb1: apb1@01c20058 {
 878                         #clock-cells = <0>;
 879 -                       compatible = "allwinner,sun4i-apb1-clk";
 880 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 881                         reg = <0x01c20058 0x4>;
 882                         clocks = <&apb1_mux>;
 883                         clock-output-names = "apb1";
 884 @@ -203,7 +203,7 @@
 885
 886                 nand_clk: clk@01c20080 {
 887                         #clock-cells = <0>;
 888 -                       compatible = "allwinner,sun4i-mod0-clk";
 889 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 890                         reg = <0x01c20080 0x4>;
 891                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 892                         clock-output-names = "nand";
 893 @@ -211,7 +211,7 @@
 894
 895                 ms_clk: clk@01c20084 {
 896                         #clock-cells = <0>;
 897 -                       compatible = "allwinner,sun4i-mod0-clk";
 898 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 899                         reg = <0x01c20084 0x4>;
 900                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 901                         clock-output-names = "ms";
 902 @@ -219,7 +219,7 @@
 903
 904                 mmc0_clk: clk@01c20088 {
 905                         #clock-cells = <0>;
 906 -                       compatible = "allwinner,sun4i-mod0-clk";
 907 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 908                         reg = <0x01c20088 0x4>;
 909                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 910                         clock-output-names = "mmc0";
 911 @@ -227,7 +227,7 @@
 912
 913                 mmc1_clk: clk@01c2008c {
 914                         #clock-cells = <0>;
 915 -                       compatible = "allwinner,sun4i-mod0-clk";
 916 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 917                         reg = <0x01c2008c 0x4>;
 918                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 919                         clock-output-names = "mmc1";
 920 @@ -235,7 +235,7 @@
 921
 922                 mmc2_clk: clk@01c20090 {
 923                         #clock-cells = <0>;
 924 -                       compatible = "allwinner,sun4i-mod0-clk";
 925 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 926                         reg = <0x01c20090 0x4>;
 927                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 928                         clock-output-names = "mmc2";
 929 @@ -243,7 +243,7 @@
 930
 931                 mmc3_clk: clk@01c20094 {
 932                         #clock-cells = <0>;
 933 -                       compatible = "allwinner,sun4i-mod0-clk";
 934 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 935                         reg = <0x01c20094 0x4>;
 936                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 937                         clock-output-names = "mmc3";
 938 @@ -251,7 +251,7 @@
 939
 940                 ts_clk: clk@01c20098 {
 941                         #clock-cells = <0>;
 942 -                       compatible = "allwinner,sun4i-mod0-clk";
 943 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 944                         reg = <0x01c20098 0x4>;
 945                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 946                         clock-output-names = "ts";
 947 @@ -259,7 +259,7 @@
 948
 949                 ss_clk: clk@01c2009c {
 950                         #clock-cells = <0>;
 951 -                       compatible = "allwinner,sun4i-mod0-clk";
 952 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 953                         reg = <0x01c2009c 0x4>;
 954                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 955                         clock-output-names = "ss";
 956 @@ -267,7 +267,7 @@
 957
 958                 spi0_clk: clk@01c200a0 {
 959                         #clock-cells = <0>;
 960 -                       compatible = "allwinner,sun4i-mod0-clk";
 961 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 962                         reg = <0x01c200a0 0x4>;
 963                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 964                         clock-output-names = "spi0";
 965 @@ -275,7 +275,7 @@
 966
 967                 spi1_clk: clk@01c200a4 {
 968                         #clock-cells = <0>;
 969 -                       compatible = "allwinner,sun4i-mod0-clk";
 970 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 971                         reg = <0x01c200a4 0x4>;
 972                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 973                         clock-output-names = "spi1";
 974 @@ -283,7 +283,7 @@
 975
 976                 spi2_clk: clk@01c200a8 {
 977                         #clock-cells = <0>;
 978 -                       compatible = "allwinner,sun4i-mod0-clk";
 979 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 980                         reg = <0x01c200a8 0x4>;
 981                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 982                         clock-output-names = "spi2";
 983 @@ -291,7 +291,7 @@
 984
 985                 pata_clk: clk@01c200ac {
 986                         #clock-cells = <0>;
 987 -                       compatible = "allwinner,sun4i-mod0-clk";
 988 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 989                         reg = <0x01c200ac 0x4>;
 990                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 991                         clock-output-names = "pata";
 992 @@ -299,7 +299,7 @@
 993
 994                 ir0_clk: clk@01c200b0 {
 995                         #clock-cells = <0>;
 996 -                       compatible = "allwinner,sun4i-mod0-clk";
 997 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
 998                         reg = <0x01c200b0 0x4>;
 999                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
1000                         clock-output-names = "ir0";
1001 @@ -307,7 +307,7 @@
1002
1003                 ir1_clk: clk@01c200b4 {
1004                         #clock-cells = <0>;
1005 -                       compatible = "allwinner,sun4i-mod0-clk";
1006 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
1007                         reg = <0x01c200b4 0x4>;
1008                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
1009                         clock-output-names = "ir1";
1010 @@ -324,7 +324,7 @@
1011
1012                 spi3_clk: clk@01c200d4 {
1013                         #clock-cells = <0>;
1014 -                       compatible = "allwinner,sun4i-mod0-clk";
1015 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
1016                         reg = <0x01c200d4 0x4>;
1017                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
1018                         clock-output-names = "spi3";
1019 @@ -332,7 +332,7 @@
1020
1021                 mbus_clk: clk@01c2015c {
1022                         #clock-cells = <0>;
1023 -                       compatible = "allwinner,sun4i-mod0-clk";
1024 +                       compatible = "allwinner,sun4i-a10-mod0-clk";
1025                         reg = <0x01c2015c 0x4>;
1026                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
1027                         clock-output-names = "mbus";
1028 --
1029 2.0.3
1030