1 From 655893a197a5134a371a5c6b579f1bbce03ab413 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Mon, 23 Dec 2013 00:32:37 -0300
4 Subject: [PATCH] clk: sunxi: add PLL5 and PLL6 support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit implements PLL5 and PLL6 support on the sunxi clock driver.
10 These PLLs use a similar factor clock, but differ on their outputs.
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
13 Acked-by: Mike Turquette <mturquette@linaro.org>
15 Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
16 drivers/clk/sunxi/clk-sunxi.c | 230 ++++++++++++++++++++++
17 2 files changed, 232 insertions(+)
19 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
20 index b8c6cc4..80b2a39 100644
21 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
22 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
23 @@ -9,6 +9,8 @@ Required properties:
24 "allwinner,sun4i-osc-clk" - for a gatable oscillator
25 "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
26 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
27 + "allwinner,sun4i-pll5-clk" - for the PLL5 clock
28 + "allwinner,sun4i-pll6-clk" - for the PLL6 clock
29 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
30 "allwinner,sun4i-axi-clk" - for the AXI clock
31 "allwinner,sun4i-axi-gates-clk" - for the AXI gates
32 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
33 index 96ccb3c..649d7c3 100644
34 --- a/drivers/clk/sunxi/clk-sunxi.c
35 +++ b/drivers/clk/sunxi/clk-sunxi.c
36 @@ -218,6 +218,40 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
40 + * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
41 + * PLL5 rate is calculated as follows
42 + * rate = parent_rate * n * (k + 1)
43 + * parent_rate is always 24Mhz
46 +static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
47 + u8 *n, u8 *k, u8 *m, u8 *p)
51 + /* Normalize value to a parent_rate multiple (24M) */
52 + div = *freq / parent_rate;
53 + *freq = parent_rate * div;
55 + /* we were called to round the frequency, we can now return */
61 + else if (div / 2 < 31)
63 + else if (div / 3 < 31)
68 + *n = DIV_ROUND_UP(div, (*k+1));
74 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
75 * APB1 rate is calculated as follows
76 * rate = (parent_rate >> p) / (m + 1);
77 @@ -293,6 +327,13 @@ struct factors_data {
81 +static struct clk_factors_config sun4i_pll5_config = {
88 static struct clk_factors_config sun4i_apb1_config = {
91 @@ -312,6 +353,12 @@ struct factors_data {
92 .getter = sun6i_a31_get_pll1_factors,
95 +static const struct factors_data sun4i_pll5_data __initconst = {
97 + .table = &sun4i_pll5_config,
98 + .getter = sun4i_get_pll5_factors,
101 static const struct factors_data sun4i_apb1_data __initconst = {
102 .table = &sun4i_apb1_config,
103 .getter = sun4i_get_apb1_factors,
104 @@ -627,6 +674,179 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
105 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
111 + * sunxi_divs_clk_setup() helper data
114 +#define SUNXI_DIVS_MAX_QTY 2
115 +#define SUNXI_DIVISOR_WIDTH 2
118 + const struct factors_data *factors; /* data for the factor clock */
120 + u8 fixed; /* is it a fixed divisor? if not... */
121 + struct clk_div_table *table; /* is it a table based divisor? */
122 + u8 shift; /* otherwise it's a normal divisor with this shift */
123 + u8 pow; /* is it power-of-two based? */
124 + u8 gate; /* is it independently gateable? */
125 + } div[SUNXI_DIVS_MAX_QTY];
128 +static struct clk_div_table pll6_sata_tbl[] = {
129 + { .val = 0, .div = 6, },
130 + { .val = 1, .div = 12, },
131 + { .val = 2, .div = 18, },
132 + { .val = 3, .div = 24, },
136 +static const struct divs_data pll5_divs_data __initconst = {
137 + .factors = &sun4i_pll5_data,
139 + { .shift = 0, .pow = 0, }, /* M, DDR */
140 + { .shift = 16, .pow = 1, }, /* P, other */
144 +static const struct divs_data pll6_divs_data __initconst = {
145 + .factors = &sun4i_pll5_data,
147 + { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
148 + { .fixed = 2 }, /* P, other */
153 + * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
155 + * These clocks look something like this
156 + * ________________________
157 + * | ___divisor 1---|----> to consumer
158 + * parent >--| pll___/___divisor 2---|----> to consumer
159 + * | \_______________|____> to consumer
160 + * |________________________|
163 +static void __init sunxi_divs_clk_setup(struct device_node *node,
164 + struct divs_data *data)
166 + struct clk_onecell_data *clk_data;
167 + const char *parent = node->name;
168 + const char *clk_name;
169 + struct clk **clks, *pclk;
170 + struct clk_hw *gate_hw, *rate_hw;
171 + const struct clk_ops *rate_ops;
172 + struct clk_gate *gate = NULL;
173 + struct clk_fixed_factor *fix_factor;
174 + struct clk_divider *divider;
177 + int flags, clkflags;
179 + /* Set up factor clock that we will be dividing */
180 + pclk = sunxi_factors_clk_setup(node, data->factors);
182 + reg = of_iomap(node, 0);
184 + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
188 + clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
192 + clk_data->clks = clks;
194 + /* It's not a good idea to have automatic reparenting changing
195 + * our RAM clock! */
196 + clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
198 + for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
199 + if (of_property_read_string_index(node, "clock-output-names",
200 + i, &clk_name) != 0)
207 + /* If this leaf clock can be gated, create a gate */
208 + if (data->div[i].gate) {
209 + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
214 + gate->bit_idx = data->div[i].gate;
215 + gate->lock = &clk_lock;
217 + gate_hw = &gate->hw;
220 + /* Leaves can be fixed or configurable divisors */
221 + if (data->div[i].fixed) {
222 + fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
226 + fix_factor->mult = 1;
227 + fix_factor->div = data->div[i].fixed;
229 + rate_hw = &fix_factor->hw;
230 + rate_ops = &clk_fixed_factor_ops;
232 + divider = kzalloc(sizeof(*divider), GFP_KERNEL);
236 + flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
238 + divider->reg = reg;
239 + divider->shift = data->div[i].shift;
240 + divider->width = SUNXI_DIVISOR_WIDTH;
241 + divider->flags = flags;
242 + divider->lock = &clk_lock;
243 + divider->table = data->div[i].table;
245 + rate_hw = ÷r->hw;
246 + rate_ops = &clk_divider_ops;
249 + /* Wrap the (potential) gate and the divisor on a composite
250 + * clock to unify them */
251 + clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
254 + gate_hw, &clk_gate_ops,
257 + WARN_ON(IS_ERR(clk_data->clks[i]));
258 + clk_register_clkdev(clks[i], clk_name, NULL);
261 + /* The last clock available on the getter is the parent */
264 + /* Adjust to the real max */
265 + clk_data->clk_num = i;
267 + of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
281 /* Matches for factors clocks */
282 static const struct of_device_id clk_factors_match[] __initconst = {
283 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
284 @@ -644,6 +864,13 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
288 +/* Matches for divided outputs */
289 +static const struct of_device_id clk_divs_match[] __initconst = {
290 + {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
291 + {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
295 /* Matches for mux clocks */
296 static const struct of_device_id clk_mux_match[] __initconst = {
297 {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
298 @@ -721,6 +948,9 @@ static void __init sunxi_init_clocks(struct device_node *np)
299 /* Register divider clocks */
300 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
302 + /* Register divided output clocks */
303 + of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
305 /* Register mux clocks */
306 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);