1 From 3bebf4a4400ab70ccef98c069d240dbd17dd718f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 20 Jun 2013 19:13:25 +0200
4 Subject: [PATCH 76/79] mmc: MIPS: ralink: add sdhci for mt7620a SoC
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/mmc/host/Kconfig | 11 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mt6575_sd.h | 1068 ++++++++++++++++++
11 drivers/mmc/host/sdhci-mt7620.c | 2314 +++++++++++++++++++++++++++++++++++++++
12 4 files changed, 3394 insertions(+)
13 create mode 100644 drivers/mmc/host/mt6575_sd.h
14 create mode 100644 drivers/mmc/host/sdhci-mt7620.c
16 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
17 index 8d13c65..04085b3 100644
18 --- a/drivers/mmc/host/Kconfig
19 +++ b/drivers/mmc/host/Kconfig
20 @@ -241,6 +241,17 @@ config MMC_SDHCI_S3C_DMA
24 +config MMC_SDHCI_MT7620
25 + tristate "SDHCI platform support for the MT7620 SD/MMC Controller"
26 + depends on SOC_MT7620
27 + depends on MMC_SDHCI_PLTFM
28 + select MMC_SDHCI_IO_ACCESSORS
30 + This selects the BCM2835 SD/MMC controller. If you have a BCM2835
31 + platform with SD or MMC devices, say Y or M here.
36 tristate "TI OMAP Multimedia Card Interface support"
38 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
39 index e4e218c..be79804 100644
40 --- a/drivers/mmc/host/Makefile
41 +++ b/drivers/mmc/host/Makefile
42 @@ -58,6 +58,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o
43 obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
44 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
45 obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
46 +obj-$(CONFIG_MMC_SDHCI_MT7620) += sdhci-mt7620.o
48 ifeq ($(CONFIG_CB710_DEBUG),y)
49 CFLAGS-cb710-mmc += -DDEBUG
50 diff --git a/drivers/mmc/host/mt6575_sd.h b/drivers/mmc/host/mt6575_sd.h
52 index 0000000..406382c
54 +++ b/drivers/mmc/host/mt6575_sd.h
56 +/* Copyright Statement:
58 + * This software/firmware and related documentation ("MediaTek Software") are
59 + * protected under relevant copyright laws. The information contained herein
60 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
61 + * Without the prior written permission of MediaTek inc. and/or its licensors,
62 + * any reproduction, modification, use or disclosure of MediaTek Software,
63 + * and information contained herein, in whole or in part, shall be strictly prohibited.
65 +/* MediaTek Inc. (C) 2010. All rights reserved.
67 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
68 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
69 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
70 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
71 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
72 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
73 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
74 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
75 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
76 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
77 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
78 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
79 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
80 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
81 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
82 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
83 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
84 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
86 + * The following software/firmware and/or related documentation ("MediaTek Software")
87 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
88 + * applicable license agreements with MediaTek Inc.
94 +#include <linux/bitops.h>
95 +#include <linux/mmc/host.h>
97 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
99 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
100 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
102 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
103 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
104 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
105 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
106 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
107 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
108 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
109 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
110 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
111 +#define MSDC_DDR (1 << 9) /* ddr mode support */
112 +#define MSDC_SPE (1 << 10) /* special support */
113 +#define MSDC_INTERNAL_CLK (1 << 11) /* Force Internal clock */
114 +#define MSDC_TABDRV (1 << 12) /* TABLET */
117 +#define MSDC_SMPL_RISING (0)
118 +#define MSDC_SMPL_FALLING (1)
120 +#define MSDC_CMD_PIN (0)
121 +#define MSDC_DAT_PIN (1)
122 +#define MSDC_CD_PIN (2)
123 +#define MSDC_WP_PIN (3)
124 +#define MSDC_RST_PIN (4)
127 + MSDC_CLKSRC_26MHZ = 0,
128 + MSDC_CLKSRC_197MHZ = 1,
129 + MSDC_CLKSRC_208MHZ = 2
133 + unsigned char clk_src; /* host clock source */
134 + unsigned char cmd_edge; /* command latch edge */
135 + unsigned char data_edge; /* data latch edge */
136 + unsigned char clk_drv; /* clock pad driving */
137 + unsigned char cmd_drv; /* command pad driving */
138 + unsigned char dat_drv; /* data pad driving */
139 + unsigned long flags; /* hardware capability flags */
140 + unsigned long data_pins; /* data pins */
141 + unsigned long data_offset; /* data address offset */
143 + /* config gpio pull mode */
144 + void (*config_gpio_pin)(int type, int pull);
146 + /* external power control for card */
147 + void (*ext_power_on)(void);
148 + void (*ext_power_off)(void);
150 + /* external sdio irq operations */
151 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
152 + void (*enable_sdio_eirq)(void);
153 + void (*disable_sdio_eirq)(void);
155 + /* external cd irq operations */
156 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
157 + void (*enable_cd_eirq)(void);
158 + void (*disable_cd_eirq)(void);
159 + int (*get_cd_status)(void);
161 + /* power management callback for external module */
162 + void (*register_pm)(pm_callback_t pm_cb, void *data);
165 +extern struct msdc_hw msdc0_hw;
166 +extern struct msdc_hw msdc1_hw;
167 +extern struct msdc_hw msdc2_hw;
168 +extern struct msdc_hw msdc3_hw;
171 +/*--------------------------------------------------------------------------*/
173 +/*--------------------------------------------------------------------------*/
174 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
176 +/*--------------------------------------------------------------------------*/
177 +/* Common Definition */
178 +/*--------------------------------------------------------------------------*/
179 +#define MSDC_FIFO_SZ (128)
180 +#define MSDC_FIFO_THD (64) // (128)
181 +#define MSDC_NUM (4)
184 +#define MSDC_SDMMC (1)
186 +#define MSDC_MODE_UNKNOWN (0)
187 +#define MSDC_MODE_PIO (1)
188 +#define MSDC_MODE_DMA_BASIC (2)
189 +#define MSDC_MODE_DMA_DESC (3)
190 +#define MSDC_MODE_DMA_ENHANCED (4)
191 +#define MSDC_MODE_MMC_STREAM (5)
193 +#define MSDC_BUS_1BITS (0)
194 +#define MSDC_BUS_4BITS (1)
195 +#define MSDC_BUS_8BITS (2)
197 +#define MSDC_BRUST_8B (3)
198 +#define MSDC_BRUST_16B (4)
199 +#define MSDC_BRUST_32B (5)
200 +#define MSDC_BRUST_64B (6)
202 +#define MSDC_PIN_PULL_NONE (0)
203 +#define MSDC_PIN_PULL_DOWN (1)
204 +#define MSDC_PIN_PULL_UP (2)
205 +#define MSDC_PIN_KEEP (3)
207 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
208 +#define MSDC_MIN_SCLK (260000)
210 +#define MSDC_AUTOCMD12 (0x0001)
211 +#define MSDC_AUTOCMD23 (0x0002)
212 +#define MSDC_AUTOCMD19 (0x0003)
214 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
215 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
229 +/*--------------------------------------------------------------------------*/
230 +/* Register Offset */
231 +/*--------------------------------------------------------------------------*/
232 +#define OFFSET_MSDC_CFG (0x0)
233 +#define OFFSET_MSDC_IOCON (0x04)
234 +#define OFFSET_MSDC_PS (0x08)
235 +#define OFFSET_MSDC_INT (0x0c)
236 +#define OFFSET_MSDC_INTEN (0x10)
237 +#define OFFSET_MSDC_FIFOCS (0x14)
238 +#define OFFSET_MSDC_TXDATA (0x18)
239 +#define OFFSET_MSDC_RXDATA (0x1c)
240 +#define OFFSET_SDC_CFG (0x30)
241 +#define OFFSET_SDC_CMD (0x34)
242 +#define OFFSET_SDC_ARG (0x38)
243 +#define OFFSET_SDC_STS (0x3c)
244 +#define OFFSET_SDC_RESP0 (0x40)
245 +#define OFFSET_SDC_RESP1 (0x44)
246 +#define OFFSET_SDC_RESP2 (0x48)
247 +#define OFFSET_SDC_RESP3 (0x4c)
248 +#define OFFSET_SDC_BLK_NUM (0x50)
249 +#define OFFSET_SDC_CSTS (0x58)
250 +#define OFFSET_SDC_CSTS_EN (0x5c)
251 +#define OFFSET_SDC_DCRC_STS (0x60)
252 +#define OFFSET_EMMC_CFG0 (0x70)
253 +#define OFFSET_EMMC_CFG1 (0x74)
254 +#define OFFSET_EMMC_STS (0x78)
255 +#define OFFSET_EMMC_IOCON (0x7c)
256 +#define OFFSET_SDC_ACMD_RESP (0x80)
257 +#define OFFSET_SDC_ACMD19_TRG (0x84)
258 +#define OFFSET_SDC_ACMD19_STS (0x88)
259 +#define OFFSET_MSDC_DMA_SA (0x90)
260 +#define OFFSET_MSDC_DMA_CA (0x94)
261 +#define OFFSET_MSDC_DMA_CTRL (0x98)
262 +#define OFFSET_MSDC_DMA_CFG (0x9c)
263 +#define OFFSET_MSDC_DBG_SEL (0xa0)
264 +#define OFFSET_MSDC_DBG_OUT (0xa4)
265 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
266 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
267 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
268 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
269 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
270 +#define OFFSET_MSDC_PAD_TUNE (0xec)
271 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
272 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
273 +#define OFFSET_MSDC_HW_DBG (0xf8)
274 +#define OFFSET_MSDC_VERSION (0x100)
275 +#define OFFSET_MSDC_ECO_VER (0x104)
277 +/*--------------------------------------------------------------------------*/
278 +/* Register Address */
279 +/*--------------------------------------------------------------------------*/
281 +/* common register */
282 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
283 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
284 +#define MSDC_PS REG_ADDR(MSDC_PS)
285 +#define MSDC_INT REG_ADDR(MSDC_INT)
286 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
287 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
288 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
289 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
290 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
292 +/* sdmmc register */
293 +#define SDC_CFG REG_ADDR(SDC_CFG)
294 +#define SDC_CMD REG_ADDR(SDC_CMD)
295 +#define SDC_ARG REG_ADDR(SDC_ARG)
296 +#define SDC_STS REG_ADDR(SDC_STS)
297 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
298 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
299 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
300 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
301 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
302 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
303 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
304 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
307 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
308 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
309 +#define EMMC_STS REG_ADDR(EMMC_STS)
310 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
312 +/* auto command register */
313 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
314 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
315 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
318 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
319 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
320 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
321 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
323 +/* pad ctrl register */
324 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
325 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
326 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
328 +/* data read delay */
329 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
330 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
332 +/* debug register */
333 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
334 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
337 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
338 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
339 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
340 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
341 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
342 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
344 +/*--------------------------------------------------------------------------*/
346 +/*--------------------------------------------------------------------------*/
349 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
350 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
351 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
352 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
353 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
354 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
355 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
356 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
357 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
358 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
360 +/* MSDC_IOCON mask */
361 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
362 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
363 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
364 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
365 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
366 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
367 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
368 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
369 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
370 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
371 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
372 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
373 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
374 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
375 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
378 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
379 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
380 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
381 +#define MSDC_PS_DAT (0xff << 16) /* R */
382 +#define MSDC_PS_CMD (0x1 << 24) /* R */
383 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
386 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
387 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
388 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
389 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
390 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
391 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
392 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
393 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
394 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
395 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
396 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
397 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
398 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
399 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
400 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
401 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
403 +/* MSDC_INTEN mask */
404 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
405 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
406 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
407 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
408 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
409 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
410 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
411 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
412 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
413 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
414 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
415 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
416 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
417 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
418 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
419 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
421 +/* MSDC_FIFOCS mask */
422 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
423 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
424 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
427 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
428 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
429 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
430 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
431 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
432 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
433 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
436 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
437 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
438 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
439 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
440 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
441 +#define SDC_CMD_RW (0x1 << 13) /* RW */
442 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
443 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
444 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
445 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
446 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
449 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
450 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
451 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
453 +/* SDC_DCRC_STS mask */
454 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
455 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
457 +/* EMMC_CFG0 mask */
458 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
459 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
460 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
461 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
462 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
463 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
465 +/* EMMC_CFG1 mask */
466 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
467 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
470 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
471 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
472 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
473 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
474 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
475 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
476 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
478 +/* EMMC_IOCON mask */
479 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
481 +/* SDC_ACMD19_TRG mask */
482 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
484 +/* MSDC_DMA_CTRL mask */
485 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
486 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
487 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
488 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
489 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
490 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
491 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
493 +/* MSDC_DMA_CFG mask */
494 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
495 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
496 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
497 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
499 +/* MSDC_PATCH_BIT mask */
500 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
501 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
502 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
503 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
504 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
505 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
506 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
507 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
508 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
509 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
510 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
511 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
513 +/* MSDC_PATCH_BIT1 mask */
514 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
515 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
517 +/* MSDC_PAD_CTL0 mask */
518 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
519 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
520 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
521 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
522 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
523 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
524 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
525 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
526 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
528 +/* MSDC_PAD_CTL1 mask */
529 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
530 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
531 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
532 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
533 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
534 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
535 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
536 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
537 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
539 +/* MSDC_PAD_CTL2 mask */
540 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
541 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
542 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
543 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
544 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
545 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
546 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
547 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
548 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
550 +/* MSDC_PAD_TUNE mask */
551 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
552 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
553 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
554 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
555 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
557 +/* MSDC_DAT_RDDLY0/1 mask */
558 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
559 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
560 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
561 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
563 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
564 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
565 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
566 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
568 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
569 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
570 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
571 +#define CARD_READY_FOR_DATA (1<<8)
572 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
574 +/*--------------------------------------------------------------------------*/
575 +/* Descriptor Structure */
576 +/*--------------------------------------------------------------------------*/
578 + u32 hwo:1; /* could be changed by hw */
608 +/*--------------------------------------------------------------------------*/
609 +/* Register Debugging Structure */
610 +/*--------------------------------------------------------------------------*/
671 + u32 atocmd19done:1;
691 + u32 atocmd19done:1;
767 +} sdc_datcrcsts_reg;
798 +} msdc_acmd_resp_reg;
802 +} msdc_acmd19_trg_reg;
805 +} msdc_acmd19_sts_reg;
824 +} msdc_dma_ctrl_reg;
853 +} msdc_pad_ctl0_reg;
867 +} msdc_pad_ctl1_reg;
881 +} msdc_pad_ctl2_reg;
887 +} msdc_pad_tune_reg;
925 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
926 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
927 + msdc_ps_reg msdc_ps; /* base+0x08h */
928 + msdc_int_reg msdc_int; /* base+0x0ch */
929 + msdc_inten_reg msdc_inten; /* base+0x10h */
930 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
931 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
932 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
934 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
935 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
936 + sdc_arg_reg sdc_arg; /* base+0x38h */
937 + sdc_sts_reg sdc_sts; /* base+0x3ch */
938 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
939 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
940 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
941 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
942 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
944 + sdc_csts_reg sdc_csts; /* base+0x58h */
945 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
946 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
948 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
949 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
950 + emmc_sts_reg emmc_sts; /* base+0x78h */
951 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
952 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
953 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
954 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
956 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
957 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
958 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
959 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
960 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
961 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
963 + u32 patch0; /* base+0xb0h */
964 + u32 patch1; /* base+0xb4h */
966 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
967 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
968 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
969 + msdc_pad_tune_reg pad_tune; /* base+0xech */
970 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
971 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
972 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
974 + msdc_version_reg version; /* base+0x100h */
975 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
978 +struct scatterlist_ex {
982 + struct scatterlist *sg;
985 +#define DMA_FLAG_NONE (0x00000000)
986 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
987 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
988 +#define DMA_FLAG_PAD_DWORD (0x00000004)
991 + u32 flags; /* flags */
992 + u32 xfersz; /* xfer size in bytes */
993 + u32 sglen; /* size of scatter list */
994 + u32 blklen; /* block size */
995 + struct scatterlist *sg; /* I/O scatter list */
996 + struct scatterlist_ex *esg; /* extended I/O scatter list */
997 + u8 mode; /* dma mode */
998 + u8 burstsz; /* burst size */
999 + u8 intr; /* dma done interrupt */
1000 + u8 padding; /* padding */
1001 + u32 cmd; /* enhanced mode command */
1002 + u32 arg; /* enhanced mode arg */
1003 + u32 rsp; /* enhanced mode command response */
1004 + u32 autorsp; /* auto command response */
1006 + gpd_t *gpd; /* pointer to gpd array */
1007 + bd_t *bd; /* pointer to bd array */
1008 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1009 + dma_addr_t bd_addr; /* the physical address of bd array */
1010 + u32 used_gpd; /* the number of used gpd elements */
1011 + u32 used_bd; /* the number of used bd elements */
1016 + struct msdc_hw *hw;
1018 + struct mmc_host *mmc; /* mmc structure */
1019 + struct mmc_command *cmd;
1020 + struct mmc_data *data;
1021 + struct mmc_request *mrq;
1027 + spinlock_t lock; /* mutex */
1028 + struct semaphore sem;
1030 + u32 blksz; /* host block size */
1031 + u32 base; /* host base address */
1032 + int id; /* host id */
1033 + int pwr_ref; /* core power reference count */
1035 + u32 xfer_size; /* total transferred size */
1037 + struct msdc_dma dma; /* dma channel */
1038 + u32 dma_addr; /* dma transfer address */
1039 + u32 dma_left_size; /* dma transfer left size */
1040 + u32 dma_xfer_size; /* dma transfer size in bytes */
1041 + int dma_xfer; /* dma transfer mode */
1043 + u32 timeout_ns; /* data timeout ns */
1044 + u32 timeout_clks; /* data timeout clks */
1046 + atomic_t abort; /* abort transfer */
1048 + int irq; /* host interrupt */
1050 + struct tasklet_struct card_tasklet;
1052 + struct completion cmd_done;
1053 + struct completion xfer_done;
1054 + struct pm_message pm_state;
1056 + u32 mclk; /* mmc subsystem clock */
1057 + u32 hclk; /* host clock speed */
1058 + u32 sclk; /* SD/MS clock speed */
1059 + u8 core_clkon; /* Host core clock on ? */
1060 + u8 card_clkon; /* Card clock on ? */
1061 + u8 core_power; /* core power */
1062 + u8 power_mode; /* host power mode */
1063 + u8 card_inserted; /* card inserted ? */
1064 + u8 suspend; /* host suspended ? */
1066 + u8 app_cmd; /* for app command */
1071 +static inline unsigned int uffs(unsigned int x)
1073 + unsigned int r = 1;
1077 + if (!(x & 0xffff)) {
1081 + if (!(x & 0xff)) {
1099 +#define sdr_read8(reg) __raw_readb(reg)
1100 +#define sdr_read16(reg) __raw_readw(reg)
1101 +#define sdr_read32(reg) __raw_readl(reg)
1102 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1103 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1104 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1106 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1107 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1109 +#define sdr_set_field(reg,field,val) \
1111 + volatile unsigned int tv = sdr_read32(reg); \
1113 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1114 + sdr_write32(reg,tv); \
1116 +#define sdr_get_field(reg,field,val) \
1118 + volatile unsigned int tv = sdr_read32(reg); \
1119 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1124 diff --git a/drivers/mmc/host/sdhci-mt7620.c b/drivers/mmc/host/sdhci-mt7620.c
1125 new file mode 100644
1126 index 0000000..a3cb5e4
1128 +++ b/drivers/mmc/host/sdhci-mt7620.c
1130 +/* Copyright Statement:
1132 + * This software/firmware and related documentation ("MediaTek Software") are
1133 + * protected under relevant copyright laws. The information contained herein
1134 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1135 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1136 + * any reproduction, modification, use or disclosure of MediaTek Software,
1137 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1139 + * MediaTek Inc. (C) 2010. All rights reserved.
1141 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1142 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1143 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1144 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1145 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1146 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1147 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1148 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1149 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1150 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1151 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1152 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1153 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1154 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1155 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1156 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1157 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1158 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1160 + * The following software/firmware and/or related documentation ("MediaTek Software")
1161 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1162 + * applicable license agreements with MediaTek Inc.
1165 +#include <linux/module.h>
1166 +#include <linux/moduleparam.h>
1167 +#include <linux/init.h>
1168 +#include <linux/spinlock.h>
1169 +#include <linux/timer.h>
1170 +#include <linux/ioport.h>
1171 +#include <linux/device.h>
1172 +#include <linux/platform_device.h>
1173 +#include <linux/of_platform.h>
1174 +#include <linux/interrupt.h>
1175 +#include <linux/delay.h>
1176 +#include <linux/blkdev.h>
1177 +#include <linux/slab.h>
1178 +#include <linux/mmc/host.h>
1179 +#include <linux/mmc/card.h>
1180 +#include <linux/mmc/core.h>
1181 +#include <linux/mmc/mmc.h>
1182 +#include <linux/mmc/sd.h>
1183 +#include <linux/mmc/sdio.h>
1184 +#include <linux/dma-mapping.h>
1186 +#include <linux/types.h>
1187 +#include <linux/kernel.h>
1188 +#include <linux/version.h>
1189 +#include <linux/pm.h>
1191 +#define MSDC_SMPL_FALLING (1)
1192 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1193 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1194 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1195 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1196 +#define MSDC_HIGHSPEED (1 << 7)
1200 +#include <asm/dma.h>
1202 +#include "mt6575_sd.h"
1204 +#define DRV_NAME "mtk-sd"
1206 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1208 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1209 +#define HOST_MIN_MCLK (260000)
1211 +#define HOST_MAX_BLKSZ (2048)
1213 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1215 +#define GPIO_PULL_DOWN (0)
1216 +#define GPIO_PULL_UP (1)
1218 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1219 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1221 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1222 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1224 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1226 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1227 +#define MAX_BD_NUM (1024)
1228 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1230 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1231 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1232 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1233 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1235 +#ifdef MT6575_SD_DEBUG
1236 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1239 +//=================================
1240 +#define PERI_MSDC0_PDN (15)
1241 +//#define PERI_MSDC1_PDN (16)
1242 +//#define PERI_MSDC2_PDN (17)
1243 +//#define PERI_MSDC3_PDN (18)
1245 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1247 +struct msdc_hw msdc0_hw = {
1249 + .cmd_edge = MSDC_SMPL_FALLING,
1250 + .data_edge = MSDC_SMPL_FALLING,
1256 + .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1259 +static struct resource mtk_sd_resources[] = {
1261 + .start = 0xb0130000,
1262 + .end = 0xb0133fff,
1263 + .flags = IORESOURCE_MEM,
1266 + .start = IRQ_SDC, /*FIXME*/
1267 + .end = IRQ_SDC, /*FIXME*/
1268 + .flags = IORESOURCE_IRQ,
1272 +static struct platform_device mtk_sd_device = {
1275 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
1276 + .resource = mtk_sd_resources,
1280 +static int msdc_rsp[] = {
1281 + 0, /* RESP_NONE */
1292 +/* For Inhanced DMA */
1293 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
1295 + ((gpd_t*)gpd)->extlen = extlen; \
1296 + ((gpd_t*)gpd)->cmd = cmd; \
1297 + ((gpd_t*)gpd)->arg = arg; \
1298 + ((gpd_t*)gpd)->blknum = blknum; \
1301 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
1303 + BUG_ON(dlen > 0xFFFFUL); \
1304 + ((bd_t*)bd)->blkpad = blkpad; \
1305 + ((bd_t*)bd)->dwpad = dwpad; \
1306 + ((bd_t*)bd)->ptr = (void*)dptr; \
1307 + ((bd_t*)bd)->buflen = dlen; \
1310 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
1311 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
1312 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
1313 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
1314 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
1315 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
1318 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
1319 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
1321 +#define msdc_retry(expr,retry,cnt) \
1323 + int backup = cnt; \
1325 + if (!(expr)) break; \
1326 + if (cnt-- == 0) { \
1327 + retry--; mdelay(1); cnt = backup; \
1330 + WARN_ON(retry == 0); \
1333 +#if 0 /* +/- chhung */
1334 +#define msdc_reset() \
1336 + int retry = 3, cnt = 1000; \
1337 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
1339 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
1342 +#define msdc_reset() \
1344 + int retry = 3, cnt = 1000; \
1345 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
1346 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
1348 +#endif /* end of +/- */
1350 +#define msdc_clr_int() \
1352 + volatile u32 val = sdr_read32(MSDC_INT); \
1353 + sdr_write32(MSDC_INT, val); \
1356 +#define msdc_clr_fifo() \
1358 + int retry = 3, cnt = 1000; \
1359 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
1360 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
1363 +#define msdc_irq_save(val) \
1365 + val = sdr_read32(MSDC_INTEN); \
1366 + sdr_clr_bits(MSDC_INTEN, val); \
1369 +#define msdc_irq_restore(val) \
1371 + sdr_set_bits(MSDC_INTEN, val); \
1374 +/* clock source for host: global */
1375 +static u32 hclks[] = {48000000}; /* +/- by chhung */
1377 +//============================================
1378 +// the power for msdc host controller: global
1379 +// always keep the VMC on.
1380 +//============================================
1381 +#define msdc_vcore_on(host) \
1383 + printk("[+]VMC ref. count<%d>\n", ++host->pwr_ref); \
1384 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
1386 +#define msdc_vcore_off(host) \
1388 + printk("[-]VMC ref. count<%d>\n", --host->pwr_ref); \
1389 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
1392 +//====================================
1393 +// the vdd output for card: global
1394 +// always keep the VMCH on.
1395 +//====================================
1396 +#define msdc_vdd_on(host) \
1398 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
1400 +#define msdc_vdd_off(host) \
1402 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
1405 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
1406 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
1408 +#define sdc_send_cmd(cmd,arg) \
1410 + sdr_write32(SDC_ARG, (arg)); \
1411 + sdr_write32(SDC_CMD, (cmd)); \
1414 +// can modify to read h/w register.
1415 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
1416 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
1419 +#ifndef __ASSEMBLY__
1420 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
1422 +#define PHYSADDR(a) ((a) & 0x1fffffff)
1425 +static unsigned int msdc_do_command(struct msdc_host *host,
1426 + struct mmc_command *cmd,
1428 + unsigned long timeout);
1430 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
1432 +#ifdef MT6575_SD_DEBUG
1433 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
1435 + static char *state[] = {
1445 + "Reserved", /* 9 */
1446 + "Reserved", /* 10 */
1447 + "Reserved", /* 11 */
1448 + "Reserved", /* 12 */
1449 + "Reserved", /* 13 */
1450 + "Reserved", /* 14 */
1451 + "I/O mode", /* 15 */
1453 + if (status & R1_OUT_OF_RANGE)
1454 + printk("[CARD_STATUS] Out of Range\n");
1455 + if (status & R1_ADDRESS_ERROR)
1456 + printk("[CARD_STATUS] Address Error\n");
1457 + if (status & R1_BLOCK_LEN_ERROR)
1458 + printk("[CARD_STATUS] Block Len Error\n");
1459 + if (status & R1_ERASE_SEQ_ERROR)
1460 + printk("[CARD_STATUS] Erase Seq Error\n");
1461 + if (status & R1_ERASE_PARAM)
1462 + printk("[CARD_STATUS] Erase Param\n");
1463 + if (status & R1_WP_VIOLATION)
1464 + printk("[CARD_STATUS] WP Violation\n");
1465 + if (status & R1_CARD_IS_LOCKED)
1466 + printk("[CARD_STATUS] Card is Locked\n");
1467 + if (status & R1_LOCK_UNLOCK_FAILED)
1468 + printk("[CARD_STATUS] Lock/Unlock Failed\n");
1469 + if (status & R1_COM_CRC_ERROR)
1470 + printk("[CARD_STATUS] Command CRC Error\n");
1471 + if (status & R1_ILLEGAL_COMMAND)
1472 + printk("[CARD_STATUS] Illegal Command\n");
1473 + if (status & R1_CARD_ECC_FAILED)
1474 + printk("[CARD_STATUS] Card ECC Failed\n");
1475 + if (status & R1_CC_ERROR)
1476 + printk("[CARD_STATUS] CC Error\n");
1477 + if (status & R1_ERROR)
1478 + printk("[CARD_STATUS] Error\n");
1479 + if (status & R1_UNDERRUN)
1480 + printk("[CARD_STATUS] Underrun\n");
1481 + if (status & R1_OVERRUN)
1482 + printk("[CARD_STATUS] Overrun\n");
1483 + if (status & R1_CID_CSD_OVERWRITE)
1484 + printk("[CARD_STATUS] CID/CSD Overwrite\n");
1485 + if (status & R1_WP_ERASE_SKIP)
1486 + printk("[CARD_STATUS] WP Eraser Skip\n");
1487 + if (status & R1_CARD_ECC_DISABLED)
1488 + printk("[CARD_STATUS] Card ECC Disabled\n");
1489 + if (status & R1_ERASE_RESET)
1490 + printk("[CARD_STATUS] Erase Reset\n");
1491 + if (status & R1_READY_FOR_DATA)
1492 + printk("[CARD_STATUS] Ready for Data\n");
1493 + if (status & R1_SWITCH_ERROR)
1494 + printk("[CARD_STATUS] Switch error\n");
1495 + if (status & R1_APP_CMD)
1496 + printk("[CARD_STATUS] App Command\n");
1498 + printk("[CARD_STATUS] '%s' State\n", state[R1_CURRENT_STATE(status)]);
1501 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
1503 + if (resp & (1 << 7))
1504 + printk("[OCR] Low Voltage Range\n");
1505 + if (resp & (1 << 15))
1506 + printk("[OCR] 2.7-2.8 volt\n");
1507 + if (resp & (1 << 16))
1508 + printk("[OCR] 2.8-2.9 volt\n");
1509 + if (resp & (1 << 17))
1510 + printk("[OCR] 2.9-3.0 volt\n");
1511 + if (resp & (1 << 18))
1512 + printk("[OCR] 3.0-3.1 volt\n");
1513 + if (resp & (1 << 19))
1514 + printk("[OCR] 3.1-3.2 volt\n");
1515 + if (resp & (1 << 20))
1516 + printk("[OCR] 3.2-3.3 volt\n");
1517 + if (resp & (1 << 21))
1518 + printk("[OCR] 3.3-3.4 volt\n");
1519 + if (resp & (1 << 22))
1520 + printk("[OCR] 3.4-3.5 volt\n");
1521 + if (resp & (1 << 23))
1522 + printk("[OCR] 3.5-3.6 volt\n");
1523 + if (resp & (1 << 24))
1524 + printk("[OCR] Switching to 1.8V Accepted (S18A)\n");
1525 + if (resp & (1 << 30))
1526 + printk("[OCR] Card Capacity Status (CCS)\n");
1527 + if (resp & (1 << 31))
1528 + printk("[OCR] Card Power Up Status (Idle)\n");
1530 + printk("[OCR] Card Power Up Status (Busy)\n");
1533 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
1535 + u32 status = (((resp >> 15) & 0x1) << 23) |
1536 + (((resp >> 14) & 0x1) << 22) |
1537 + (((resp >> 13) & 0x1) << 19) |
1540 + printk("[RCA] 0x%.4x\n", resp >> 16);
1542 + msdc_dump_card_status(host, status);
1545 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
1547 + u32 flags = (resp >> 8) & 0xFF;
1548 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
1550 + if (flags & (1 << 7))
1551 + printk("[IO] COM_CRC_ERR\n");
1552 + if (flags & (1 << 6))
1553 + printk("[IO] Illgal command\n");
1554 + if (flags & (1 << 3))
1555 + printk("[IO] Error\n");
1556 + if (flags & (1 << 2))
1557 + printk("[IO] RFU\n");
1558 + if (flags & (1 << 1))
1559 + printk("[IO] Function number error\n");
1560 + if (flags & (1 << 0))
1561 + printk("[IO] Out of range\n");
1563 + printk("[IO] State: %s, Data:0x%x\n", state[(resp >> 12) & 0x3], resp & 0xFF);
1567 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
1569 + u32 base = host->base;
1570 + u32 timeout, clk_ns;
1572 + host->timeout_ns = ns;
1573 + host->timeout_clks = clks;
1575 + clk_ns = 1000000000UL / host->sclk;
1576 + timeout = ns / clk_ns + clks;
1577 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
1578 + timeout = timeout > 1 ? timeout - 1 : 0;
1579 + timeout = timeout > 255 ? 255 : timeout;
1581 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
1583 +/* printk("Set read data timeout: %dns %dclks -> %d x 65536 cycles\n",
1584 + ns, clks, timeout + 1);*/
1587 +static void msdc_eirq_sdio(void *data)
1589 + struct msdc_host *host = (struct msdc_host *)data;
1591 +// printk("SDIO EINT\n");
1593 + mmc_signal_sdio_irq(host->mmc);
1596 +static void msdc_eirq_cd(void *data)
1598 + struct msdc_host *host = (struct msdc_host *)data;
1600 +// printk("CD EINT\n");
1602 + tasklet_hi_schedule(&host->card_tasklet);
1605 +static void msdc_tasklet_card(unsigned long arg)
1607 + struct msdc_host *host = (struct msdc_host *)arg;
1608 + struct msdc_hw *hw = host->hw;
1609 + u32 base = host->base;
1613 + spin_lock(&host->lock);
1615 + if (hw->get_cd_status) {
1616 + inserted = hw->get_cd_status();
1618 + status = sdr_read32(MSDC_PS);
1619 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
1622 + host->card_inserted = inserted;
1624 + if (!host->suspend) {
1625 + host->mmc->f_max = HOST_MAX_MCLK;
1626 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
1629 +// printk("card found<%s>\n", inserted ? "inserted" : "removed");
1631 + spin_unlock(&host->lock);
1634 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
1636 + u32 base = host->base;
1637 + u32 hclk = host->hclk;
1638 + u32 mode, flags, div, sclk;
1641 +// printk("set mclk to 0!!!\n");
1646 + msdc_irq_save(flags);
1650 + if (hz >= (hclk >> 2)) {
1654 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
1655 + sclk = (hclk >> 2) / div;
1657 + } else if (hz >= hclk) {
1663 + if (hz >= (hclk >> 1)) {
1667 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
1668 + sclk = (hclk >> 2) / div;
1672 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
1673 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
1675 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
1677 + host->sclk = sclk;
1679 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
1681 +/* printk("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>\n",
1682 + hz / 1000, hclk / 1000, sclk / 1000);
1684 + msdc_irq_restore(flags);
1687 +static void msdc_abort_data(struct msdc_host *host)
1689 + u32 base = host->base;
1690 + struct mmc_command *stop = host->mrq->stop;
1692 +// printk("Need to Abort. dma<%d>\n", host->dma_xfer);
1699 +// printk("stop when abort CMD<%d>\n", stop->opcode);
1700 + msdc_do_command(host, stop, 0, CMD_TIMEOUT);
1704 +static unsigned int msdc_command_start(struct msdc_host *host,
1705 + struct mmc_command *cmd, int tune, unsigned long timeout)
1707 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
1708 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
1709 + MSDC_INT_ACMD19_DONE;
1710 + u32 base = host->base;
1711 + u32 opcode = cmd->opcode;
1714 + unsigned long tmo;
1716 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
1718 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
1719 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
1720 + else if (opcode == MMC_FAST_IO)
1722 + else if (opcode == MMC_GO_IRQ_STATE)
1724 + else if (opcode == MMC_SELECT_CARD)
1725 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
1726 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
1728 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
1731 + switch (mmc_resp_type(cmd)) {
1744 + case MMC_RSP_NONE:
1752 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
1754 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
1755 + rawcmd |= (2 << 11);
1756 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
1757 + rawcmd |= (1 << 11);
1758 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
1759 + rawcmd |= ((2 << 11) | (1 << 13));
1760 + } else if (opcode == MMC_WRITE_BLOCK) {
1761 + rawcmd |= ((1 << 11) | (1 << 13));
1762 + } else if (opcode == SD_IO_RW_EXTENDED) {
1763 + if (cmd->data->flags & MMC_DATA_WRITE)
1764 + rawcmd |= (1 << 13);
1765 + if (cmd->data->blocks > 1)
1766 + rawcmd |= (2 << 11);
1768 + rawcmd |= (1 << 11);
1769 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
1770 + rawcmd |= (1 << 14);
1771 + } else if ((opcode == SD_APP_SEND_SCR) ||
1772 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
1773 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
1774 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
1775 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
1776 + rawcmd |= (1 << 11);
1777 + } else if (opcode == MMC_STOP_TRANSMISSION) {
1778 + rawcmd |= (1 << 14);
1779 + rawcmd &= ~(0x0FFF << 16);
1782 +// printk("CMD<%d><0x%.8x> Arg<0x%.8x>\n", opcode , rawcmd, cmd->arg);
1784 + tmo = jiffies + timeout;
1786 + if (opcode == MMC_SEND_STATUS) {
1788 + if (!sdc_is_cmd_busy())
1791 + if (time_after(jiffies, tmo)) {
1792 + //printk("XXX cmd_busy timeout: before CMD<%d>\n", opcode);
1793 + cmd->error = (unsigned int)-ETIMEDOUT;
1800 + if (!sdc_is_busy())
1802 + if (time_after(jiffies, tmo)) {
1803 + //printk("XXX sdc_busy timeout: before CMD<%d>\n", opcode);
1804 + cmd->error = (unsigned int)-ETIMEDOUT;
1811 + //BUG_ON(in_interrupt());
1813 + host->cmd_rsp = resp;
1814 + init_completion(&host->cmd_done);
1815 + sdr_set_bits(MSDC_INTEN, wints);
1816 + sdc_send_cmd(rawcmd, cmd->arg);
1819 + return cmd->error;
1822 +static unsigned int msdc_command_resp(struct msdc_host *host, struct mmc_command *cmd,
1823 + int tune, unsigned long timeout)
1825 + u32 base = host->base;
1826 + //u32 opcode = cmd->opcode;
1828 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
1829 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
1830 + MSDC_INT_ACMD19_DONE;
1832 + resp = host->cmd_rsp;
1834 + BUG_ON(in_interrupt());
1835 + spin_unlock(&host->lock);
1836 + if (!wait_for_completion_timeout(&host->cmd_done, 10*timeout)) {
1837 + //printk("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>\n", opcode, cmd->arg);
1838 + cmd->error = (unsigned int)-ETIMEDOUT;
1841 + spin_lock(&host->lock);
1843 + sdr_clr_bits(MSDC_INTEN, wints);
1847 + return cmd->error;
1849 + /* memory card CRC */
1850 + if (host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
1851 + if (sdr_read32(SDC_CMD) & 0x1800) {
1852 + msdc_abort_data(host);
1858 + cmd->error = msdc_tune_cmdrsp(host,cmd);
1861 + return cmd->error;
1864 +static unsigned int msdc_do_command(struct msdc_host *host, struct mmc_command *cmd,
1865 + int tune, unsigned long timeout)
1867 + if (!msdc_command_start(host, cmd, tune, timeout))
1868 + msdc_command_resp(host, cmd, tune, timeout);
1870 + //printk(" return<%d> resp<0x%.8x>\n", cmd->error, cmd->resp[0]);
1871 + return cmd->error;
1874 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
1876 + u32 base = host->base;
1879 + if (atomic_read(&host->abort))
1882 + if (time_after(jiffies, tmo)) {
1883 + data->error = (unsigned int)-ETIMEDOUT;
1884 + //printk("XXX PIO Data Timeout: CMD<%d>\n", host->mrq->cmd->opcode);
1892 + //printk("msdc pio find abort\n");
1898 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
1900 + struct scatterlist *sg = data->sg;
1901 + u32 base = host->base;
1902 + u32 num = data->sg_len;
1906 + u32 count, size = 0;
1907 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1908 + unsigned long tmo = jiffies + DAT_TIMEOUT;
1910 + sdr_set_bits(MSDC_INTEN, wints);
1912 + left = sg_dma_len(sg);
1913 + ptr = sg_virt(sg);
1915 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
1916 + count = MSDC_FIFO_THD >> 2;
1918 + *ptr++ = msdc_fifo_read32();
1919 + } while (--count);
1920 + left -= MSDC_FIFO_THD;
1921 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
1922 + while (left > 3) {
1923 + *ptr++ = msdc_fifo_read32();
1927 + u8ptr = (u8 *)ptr;
1929 + * u8ptr++ = msdc_fifo_read8();
1934 + if (msdc_pio_abort(host, data, tmo))
1937 + size += sg_dma_len(sg);
1938 + sg = sg_next(sg); num--;
1941 + data->bytes_xfered += size;
1942 + //printk(" PIO Read<%d>bytes\n", size);
1944 + sdr_clr_bits(MSDC_INTEN, wints);
1946 + printk("read pio data->error<%d> left<%d> size<%d>\n", data->error, left, size);
1948 + return data->error;
1951 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
1953 + u32 base = host->base;
1954 + struct scatterlist *sg = data->sg;
1955 + u32 num = data->sg_len;
1959 + u32 count, size = 0;
1960 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1961 + unsigned long tmo = jiffies + DAT_TIMEOUT;
1963 + sdr_set_bits(MSDC_INTEN, wints);
1965 + left = sg_dma_len(sg);
1966 + ptr = sg_virt(sg);
1969 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
1970 + count = MSDC_FIFO_SZ >> 2;
1972 + msdc_fifo_write32(*ptr); ptr++;
1973 + } while (--count);
1974 + left -= MSDC_FIFO_SZ;
1975 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
1976 + while (left > 3) {
1977 + msdc_fifo_write32(*ptr); ptr++;
1983 + msdc_fifo_write8(*u8ptr);
1989 + if (msdc_pio_abort(host, data, tmo))
1992 + size += sg_dma_len(sg);
1993 + sg = sg_next(sg); num--;
1996 + data->bytes_xfered += size;
1997 + //printk(" PIO Write<%d>bytes\n", size);
1999 + printk("write pio data->error<%d>\n", data->error);
2001 + sdr_clr_bits(MSDC_INTEN, wints);
2003 + return data->error;
2006 +static void msdc_dma_start(struct msdc_host *host)
2008 + u32 base = host->base;
2009 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
2011 + sdr_set_bits(MSDC_INTEN, wints);
2012 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
2014 + //printk("DMA start\n");
2017 +static void msdc_dma_stop(struct msdc_host *host)
2019 + u32 base = host->base;
2020 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
2022 + //printk("DMA status: 0x%.8x\n",sdr_read32(MSDC_DMA_CFG));
2024 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
2025 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
2026 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
2028 + //printk("DMA stop\n");
2031 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
2035 + for (i = 0; i < len; i++)
2038 + return 0xFF - (u8)sum;
2041 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
2043 + u32 base = host->base;
2044 + u32 sglen = dma->sglen;
2045 + u32 j, num, bdlen;
2046 + u8 blkpad, dwpad, chksum;
2047 + struct scatterlist *sg = dma->sg;
2051 + switch (dma->mode) {
2052 + case MSDC_MODE_DMA_BASIC:
2053 + BUG_ON(dma->xfersz > 65535);
2054 + BUG_ON(dma->sglen != 1);
2055 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
2056 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
2057 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
2058 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
2059 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
2062 + case MSDC_MODE_DMA_DESC:
2063 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
2064 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
2065 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
2067 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
2074 + gpd->hwo = 1; /* hw will clear it */
2076 + gpd->chksum = 0; /* need to clear first. */
2077 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
2079 + for (j = 0; j < bdlen; j++) {
2080 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
2081 + if( j == bdlen - 1)
2085 + bd[j].chksum = 0; /* checksume need to clear first */
2086 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
2090 + dma->used_gpd += 2;
2091 + dma->used_bd += bdlen;
2093 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
2094 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
2095 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
2096 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
2100 +// printk("DMA_CTRL = 0x%x\n", sdr_read32(MSDC_DMA_CTRL));
2101 +// printk("DMA_CFG = 0x%x\n", sdr_read32(MSDC_DMA_CFG));
2102 +// printk("DMA_SA = 0x%x\n", sdr_read32(MSDC_DMA_SA));
2107 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
2108 + struct scatterlist *sg, unsigned int sglen)
2110 + BUG_ON(sglen > MAX_BD_NUM);
2113 + dma->flags = DMA_FLAG_EN_CHKSUM;
2114 + dma->sglen = sglen;
2115 + dma->xfersz = host->xfer_size;
2116 + dma->burstsz = MSDC_BRUST_64B;
2118 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
2119 + dma->mode = MSDC_MODE_DMA_BASIC;
2121 + dma->mode = MSDC_MODE_DMA_DESC;
2123 +// printk("DMA mode<%d> sglen<%d> xfersz<%d>\n", dma->mode, dma->sglen, dma->xfersz);
2125 + msdc_dma_config(host, dma);
2128 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
2130 + u32 base = host->base;
2132 + sdr_write32(SDC_BLK_NUM, blknum);
2135 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
2137 + struct msdc_host *host = mmc_priv(mmc);
2138 + struct mmc_command *cmd;
2139 + struct mmc_data *data;
2140 + u32 base = host->base;
2141 + unsigned int left=0;
2142 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
2147 + BUG_ON(mmc == NULL);
2148 + BUG_ON(mrq == NULL);
2151 + atomic_set(&host->abort, 0);
2154 + data = mrq->cmd->data;
2157 + send_type = SND_CMD;
2158 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
2161 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
2162 + send_type=SND_DAT;
2165 + read = data->flags & MMC_DATA_READ ? 1 : 0;
2166 + host->data = data;
2167 + host->xfer_size = data->blocks * data->blksz;
2168 + host->blksz = data->blksz;
2170 + host->dma_xfer = dma = ((host->xfer_size >= 512) ? 1 : 0);
2173 + if ((host->timeout_ns != data->timeout_ns) ||
2174 + (host->timeout_clks != data->timeout_clks))
2175 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
2177 + msdc_set_blknum(host, data->blocks);
2181 + init_completion(&host->xfer_done);
2183 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
2186 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2187 + dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
2188 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
2190 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
2193 + msdc_dma_start(host);
2195 + spin_unlock(&host->lock);
2196 + if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
2197 + /*printk("XXX CMD<%d> wait xfer_done<%d> timeout!!\n", cmd->opcode, data->blocks * data->blksz);
2198 + printk(" DMA_SA = 0x%x\n", sdr_read32(MSDC_DMA_SA));
2199 + printk(" DMA_CA = 0x%x\n", sdr_read32(MSDC_DMA_CA));
2200 + printk(" DMA_CTRL = 0x%x\n", sdr_read32(MSDC_DMA_CTRL));
2201 + printk(" DMA_CFG = 0x%x\n", sdr_read32(MSDC_DMA_CFG));*/
2202 + data->error = (unsigned int)-ETIMEDOUT;
2208 + spin_lock(&host->lock);
2209 + msdc_dma_stop(host);
2211 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
2215 + if (msdc_pio_read(host, data))
2218 + if (msdc_pio_write(host, data))
2224 + left = msdc_txfifocnt();
2228 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
2230 + /* Fix me: what about if data error, when stop ? how to? */
2234 + /* Fix me: read case: need to check CRC error */
2237 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
2238 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
2241 + /* try not to wait xfer_comp interrupt.
2242 + the next command will check SDC_BUSY.
2243 + SDC_BUSY means xfer_comp assert
2248 + /* Last: stop transfer */
2250 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
2257 + if (data != NULL) {
2258 + host->data = NULL;
2259 + host->dma_xfer = 0;
2262 + host->dma.used_bd = 0;
2263 + host->dma.used_gpd = 0;
2264 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
2268 + // printk("CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio\n"),
2269 + // (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
2272 + if (mrq->cmd->error) host->error = 0x001;
2273 + if (mrq->data && mrq->data->error) host->error |= 0x010;
2274 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
2276 + //if (host->error) printk("host->error<%d>\n", host->error);
2278 + return host->error;
2281 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
2283 + struct mmc_command cmd;
2284 + struct mmc_request mrq;
2287 + memset(&cmd, 0, sizeof(struct mmc_command));
2288 + cmd.opcode = MMC_APP_CMD;
2289 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
2290 + cmd.arg = mmc->card->rca << 16;
2292 + cmd.arg = host->app_cmd_arg;
2294 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
2296 + memset(&mrq, 0, sizeof(struct mmc_request));
2297 + mrq.cmd = &cmd; cmd.mrq = &mrq;
2300 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
2304 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
2307 + u32 base = host->base;
2308 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
2309 + u32 rrdly, cur_rrdly = 0, orig_rrdly;
2312 + /* ==== don't support 3.0 now ====
2314 + 2: PAD_CMD_RESP_RXDLY[26:22]
2315 + ==========================*/
2317 + // save the previous tune result
2318 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
2319 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
2323 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
2324 + /* Lv1: R_SMPL[1] */
2325 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
2330 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
2332 + if (host->app_cmd) {
2333 + result = msdc_app_cmd(host->mmc, host);
2335 + //printk("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>\n",
2336 + // host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
2340 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
2341 + //printk("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>\n", cmd->opcode,
2342 +// (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
2344 + if (result == 0) {
2347 + if (result != (unsigned int)(-EIO)) {
2348 + // printk("TUNE_CMD<%d> Error<%d> not -EIO\n", cmd->opcode, result);
2352 + /* should be EIO */
2353 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2354 + msdc_abort_data(host);
2358 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
2359 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
2360 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
2361 + }while (++rrdly < 32);
2366 +/* Support SD2.0 Only */
2367 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
2369 + struct msdc_host *host = mmc_priv(mmc);
2370 + u32 base = host->base;
2373 + u32 rxdly, cur_rxdly0, cur_rxdly1;
2374 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
2375 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
2376 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
2377 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
2378 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
2382 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
2384 + /* Tune Method 2. */
2385 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
2389 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
2390 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
2395 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
2397 + if (host->app_cmd) {
2398 + result = msdc_app_cmd(host->mmc, host);
2400 + //printk("TUNE_BREAD app_cmd<%d> failed\n", host->mrq->cmd->opcode);
2404 + result = msdc_do_request(mmc,mrq);
2406 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
2407 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
2408 + //printk("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>\n",
2409 + // (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
2410 + // sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
2412 + /* Fix me: result is 0, but dcrc is still exist */
2413 + if (result == 0 && dcrc == 0) {
2416 + /* there is a case: command timeout, and data phase not processed */
2417 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
2418 + //printk("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n",
2419 + // result, mrq->cmd->error, mrq->data->error);
2425 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
2426 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
2428 + /* E1 ECO. YD: Reverse */
2429 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2430 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
2431 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
2432 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
2433 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
2434 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
2435 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
2436 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
2437 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
2439 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
2440 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
2441 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
2442 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
2443 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
2444 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
2445 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
2446 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
2450 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
2451 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
2452 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
2453 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
2455 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
2456 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
2457 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
2458 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
2460 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
2461 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
2462 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
2463 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
2465 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
2466 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
2468 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
2469 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
2471 + } while (++rxdly < 32);
2477 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
2479 + struct msdc_host *host = mmc_priv(mmc);
2480 + u32 base = host->base;
2482 + u32 wrrdly, cur_wrrdly = 0, orig_wrrdly;
2483 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
2484 + u32 rxdly, cur_rxdly0;
2485 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
2486 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
2490 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
2492 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
2493 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
2495 + /* Tune Method 2. just DAT0 */
2496 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
2497 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
2499 + /* E1 ECO. YD: Reverse */
2500 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2501 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
2502 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
2503 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
2504 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
2506 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
2507 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
2508 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
2509 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
2516 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
2517 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
2522 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
2524 + if (host->app_cmd) {
2525 + result = msdc_app_cmd(host->mmc, host);
2527 + //printk("TUNE_BWRITE app_cmd<%d> failed\n", host->mrq->cmd->opcode);
2531 + result = msdc_do_request(mmc,mrq);
2533 + //printk("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>\n",
2534 + // result == 0 ? "PASS" : "FAIL",
2535 + // cur_dsmpl, cur_wrrdly, cur_rxdly0);
2537 + if (result == 0) {
2541 + /* there is a case: command timeout, and data phase not processed */
2542 + if (mrq->data->error != (unsigned int)(-EIO)) {
2543 + //printk("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n",
2544 + // && result, mrq->cmd->error, mrq->data->error);
2549 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
2550 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
2551 + } while (++wrrdly < 32);
2553 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
2554 + cur_dat1 = orig_dat1;
2555 + cur_dat2 = orig_dat2;
2556 + cur_dat3 = orig_dat3;
2558 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
2559 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
2560 + } while (++rxdly < 32);
2566 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
2568 + struct mmc_command cmd;
2569 + struct mmc_request mrq;
2572 + memset(&cmd, 0, sizeof(struct mmc_command));
2573 + cmd.opcode = MMC_SEND_STATUS;
2575 + cmd.arg = mmc->card->rca << 16;
2577 + //printk("cmd13 mmc card is null\n");
2578 + cmd.arg = host->app_cmd_arg;
2580 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
2582 + memset(&mrq, 0, sizeof(struct mmc_request));
2583 + mrq.cmd = &cmd; cmd.mrq = &mrq;
2586 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
2589 + *status = cmd.resp[0];
2594 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
2600 + err = msdc_get_card_status(mmc, host, &status);
2604 + //printk("cmd<13> resp<0x%x>\n", status);
2605 + } while (R1_CURRENT_STATE(status) == 7);
2610 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
2612 + struct msdc_host *host = mmc_priv(mmc);
2613 + struct mmc_command *cmd;
2614 + struct mmc_data *data;
2618 + data = mrq->cmd->data;
2620 + read = data->flags & MMC_DATA_READ ? 1 : 0;
2623 + if (data->error == (unsigned int)(-EIO))
2624 + ret = msdc_tune_bread(mmc,mrq);
2626 + ret = msdc_check_busy(mmc, host);
2628 + //printk("XXX cmd13 wait program done failed\n");
2632 + /* Fix me: don't care card status? */
2633 + ret = msdc_tune_bwrite(mmc,mrq);
2639 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
2641 + struct msdc_host *host = mmc_priv(mmc);
2644 + //printk("XXX host->mrq<0x%.8x>\n", (int)host->mrq);
2647 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
2648 + //printk("cmd<%d> card<%d> power<%d>\n", mrq->cmd->opcode, is_card_present(host), host->power_mode);
2649 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
2653 + spin_lock(&host->lock);
2657 + if (msdc_do_request(mmc,mrq))
2658 + if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error)
2659 + msdc_tune_request(mmc,mrq);
2661 + if (mrq->cmd->opcode == MMC_APP_CMD) {
2662 + host->app_cmd = 1;
2663 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
2665 + host->app_cmd = 0;
2670 + spin_unlock(&host->lock);
2672 + mmc_request_done(mmc, mrq);
2675 +/* called by ops.set_ios */
2676 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
2678 + u32 base = host->base;
2679 + u32 val = sdr_read32(SDC_CFG);
2681 + val &= ~SDC_CFG_BUSWIDTH;
2685 + case MMC_BUS_WIDTH_1:
2687 + val |= (MSDC_BUS_1BITS << 16);
2689 + case MMC_BUS_WIDTH_4:
2690 + val |= (MSDC_BUS_4BITS << 16);
2692 + case MMC_BUS_WIDTH_8:
2693 + val |= (MSDC_BUS_8BITS << 16);
2697 + sdr_write32(SDC_CFG, val);
2699 + //printk("Bus Width = %d\n", width);
2703 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2705 + struct msdc_host *host = mmc_priv(mmc);
2706 + struct msdc_hw *hw=host->hw;
2707 + u32 base = host->base;
2710 +#ifdef MT6575_SD_DEBUG
2711 + static char *vdd[] = {
2712 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
2713 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
2714 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
2715 + "3.40v", "3.50v", "3.60v"
2717 + static char *power_mode[] = {
2720 + static char *bus_mode[] = {
2721 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
2723 + static char *timing[] = {
2724 + "LEGACY", "MMC_HS", "SD_HS"
2727 + /*printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)\n",
2728 + ios->clock / 1000, bus_mode[ios->bus_mode],
2729 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
2730 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);*/
2733 + msdc_set_buswidth(host, ios->bus_width);
2735 + /* Power control ??? */
2736 + switch (ios->power_mode) {
2737 + case MMC_POWER_OFF:
2738 + case MMC_POWER_UP:
2739 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
2741 + case MMC_POWER_ON:
2742 + host->power_mode = MMC_POWER_ON;
2748 + /* Clock control */
2749 + if (host->mclk != ios->clock) {
2750 + if(ios->clock > 25000000) {
2751 + //printk("SD data latch edge<%d>\n", hw->data_edge);
2752 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
2753 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
2755 + sdr_write32(MSDC_IOCON, 0x00000000);
2756 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
2757 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
2758 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
2760 + msdc_set_mclk(host, ddr, ios->clock);
2765 +static int msdc_ops_get_ro(struct mmc_host *mmc)
2767 + struct msdc_host *host = mmc_priv(mmc);
2768 + u32 base = host->base;
2769 + unsigned long flags;
2772 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
2773 + spin_lock_irqsave(&host->lock, flags);
2774 + ro = (sdr_read32(MSDC_PS) >> 31);
2775 + spin_unlock_irqrestore(&host->lock, flags);
2781 +static int msdc_ops_get_cd(struct mmc_host *mmc)
2783 + struct msdc_host *host = mmc_priv(mmc);
2784 + u32 base = host->base;
2785 + unsigned long flags;
2788 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
2789 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
2790 + /* For sdio, read H/W always get<1>, but may timeout some times */
2792 + host->card_inserted = 1;
2795 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
2796 + printk("sdio ops_get_cd<%d>\n", host->card_inserted);
2797 + return host->card_inserted;
2801 + /* MSDC_CD_PIN_EN set for card */
2802 + if (host->hw->flags & MSDC_CD_PIN_EN) {
2803 + spin_lock_irqsave(&host->lock, flags);
2805 + present = host->card_inserted; /* why not read from H/W: Fix me*/
2807 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
2808 + host->card_inserted = present;
2810 + spin_unlock_irqrestore(&host->lock, flags);
2812 + present = 0; /* TODO? Check DAT3 pins for card detection */
2815 + //printk("ops_get_cd return<%d>\n", present);
2819 +/* ops.enable_sdio_irq */
2820 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
2822 + struct msdc_host *host = mmc_priv(mmc);
2823 + struct msdc_hw *hw = host->hw;
2824 + u32 base = host->base;
2827 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
2829 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
2831 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
2834 + //printk("XXX \n"); /* so never enter here */
2835 + tmp = sdr_read32(SDC_CFG);
2836 + /* FIXME. Need to interrupt gap detection */
2838 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
2840 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
2842 + sdr_write32(SDC_CFG, tmp);
2846 +static struct mmc_host_ops mt_msdc_ops = {
2847 + .request = msdc_ops_request,
2848 + .set_ios = msdc_ops_set_ios,
2849 + .get_ro = msdc_ops_get_ro,
2850 + .get_cd = msdc_ops_get_cd,
2851 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
2854 +/*--------------------------------------------------------------------------*/
2855 +/* interrupt handler */
2856 +/*--------------------------------------------------------------------------*/
2857 +static irqreturn_t msdc_irq(int irq, void *dev_id)
2859 + struct msdc_host *host = (struct msdc_host *)dev_id;
2860 + struct mmc_data *data = host->data;
2861 + struct mmc_command *cmd = host->cmd;
2862 + u32 base = host->base;
2864 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
2865 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
2866 + MSDC_INT_ACMD19_DONE;
2867 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
2869 + u32 intsts = sdr_read32(MSDC_INT);
2870 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
2872 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
2873 + /* MSG will cause fatal error */
2875 + /* card change interrupt */
2876 + if (intsts & MSDC_INT_CDSC){
2877 + //printk("MSDC_INT_CDSC irq<0x%.8x>\n", intsts);
2878 + tasklet_hi_schedule(&host->card_tasklet);
2879 + /* tuning when plug card ? */
2882 + /* sdio interrupt */
2883 + if (intsts & MSDC_INT_SDIOIRQ){
2884 + //printk("XXX MSDC_INT_SDIOIRQ\n"); /* seems not sdio irq */
2885 + //mmc_signal_sdio_irq(host->mmc);
2888 + /* transfer complete interrupt */
2889 + if (data != NULL) {
2890 + if (inten & MSDC_INT_XFER_COMPL) {
2891 + data->bytes_xfered = host->dma.xfersz;
2892 + complete(&host->xfer_done);
2895 + if (intsts & datsts) {
2896 + /* do basic reset, or stop command will sdc_busy */
2900 + atomic_set(&host->abort, 1); /* For PIO mode exit */
2902 + if (intsts & MSDC_INT_DATTMO){
2903 + //printk("XXX CMD<%d> MSDC_INT_DATTMO\n", host->mrq->cmd->opcode);
2904 + data->error = (unsigned int)-ETIMEDOUT;
2906 + else if (intsts & MSDC_INT_DATCRCERR){
2907 + //printk("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>\n", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
2908 + data->error = (unsigned int)-EIO;
2911 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
2912 + if (host->dma_xfer) {
2913 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
2914 + } /* PIO mode can't do complete, because not init */
2918 + /* command interrupts */
2919 + if ((cmd != NULL) && (intsts & cmdsts)) {
2920 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
2921 + (intsts & MSDC_INT_ACMD19_DONE)) {
2922 + u32 *rsp = &cmd->resp[0];
2924 + switch (host->cmd_rsp) {
2928 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
2929 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
2931 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2932 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
2933 + *rsp = sdr_read32(SDC_ACMD_RESP);
2935 + *rsp = sdr_read32(SDC_RESP0);
2939 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
2940 + if(intsts & MSDC_INT_ACMDCRCERR){
2941 + //printk("XXX CMD<%d> MSDC_INT_ACMDCRCERR\n",cmd->opcode);
2944 + //printk("XXX CMD<%d> MSDC_INT_RSPCRCERR\n",cmd->opcode);
2946 + cmd->error = (unsigned int)-EIO;
2947 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
2948 + if(intsts & MSDC_INT_ACMDTMO){
2949 + //printk("XXX CMD<%d> MSDC_INT_ACMDTMO\n",cmd->opcode);
2952 + //printk("XXX CMD<%d> MSDC_INT_CMDTMO\n",cmd->opcode);
2954 + cmd->error = (unsigned int)-ETIMEDOUT;
2959 + complete(&host->cmd_done);
2962 + /* mmc irq interrupts */
2963 + if (intsts & MSDC_INT_MMCIRQ) {
2964 + //printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
2967 +#ifdef MT6575_SD_DEBUG
2969 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
2970 + /*printk("IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)\n",
2974 + int_reg->atocmdrdy,
2975 + int_reg->atocmdtmo,
2976 + int_reg->atocmdcrc,
2977 + int_reg->atocmd19done);
2978 + printk("IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)\n",
2985 + printk("IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)\n",
2987 + int_reg->xfercomp,
2988 + int_reg->dxferdone,
2991 + int_reg->dmaqempty);*/
2996 + return IRQ_HANDLED;
2999 +/*--------------------------------------------------------------------------*/
3000 +/* platform_driver members */
3001 +/*--------------------------------------------------------------------------*/
3002 +/* called by msdc_drv_probe/remove */
3003 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
3005 + struct msdc_hw *hw = host->hw;
3006 + u32 base = host->base;
3008 + /* for sdio, not set */
3009 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
3010 + /* Pull down card detection pin since it is not avaiable */
3012 + if (hw->config_gpio_pin)
3013 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
3015 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3016 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3017 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
3021 + //printk("CD IRQ Eanable(%d)\n", enable);
3024 + if (hw->enable_cd_eirq) { /* not set, never enter */
3025 + hw->enable_cd_eirq();
3027 + /* card detection circuit relies on the core power so that the core power
3028 + * shouldn't be turned off. Here adds a reference count to keep
3029 + * the core power alive.
3031 + //msdc_vcore_on(host); //did in msdc_init_hw()
3033 + if (hw->config_gpio_pin) /* NULL */
3034 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
3036 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
3037 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
3038 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3039 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
3042 + if (hw->disable_cd_eirq) {
3043 + hw->disable_cd_eirq();
3045 + if (hw->config_gpio_pin) /* NULL */
3046 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
3048 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
3049 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3050 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3052 + /* Here decreases a reference count to core power since card
3053 + * detection circuit is shutdown.
3055 + //msdc_vcore_off(host);
3060 +/* called by msdc_drv_probe */
3061 +static void msdc_init_hw(struct msdc_host *host)
3063 + u32 base = host->base;
3064 + struct msdc_hw *hw = host->hw;
3066 +#ifdef MT6575_SD_DEBUG
3067 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
3071 +#if 0 /* --- chhung */
3072 + msdc_vcore_on(host);
3073 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
3074 + msdc_select_clksrc(host, hw->clk_src);
3075 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
3076 + msdc_vdd_on(host);
3077 +#endif /* end of --- */
3078 + /* Configure to MMC/SD mode */
3079 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
3085 + /* Disable card detection */
3086 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3088 + /* Disable and clear all interrupts */
3089 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
3090 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
3093 + /* reset tuning parameter */
3094 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
3095 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
3096 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
3097 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
3098 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
3099 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
3100 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
3101 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
3102 + sdr_write32(MSDC_IOCON, 0x00000000);
3103 +#if 0 // use MT7620 default value: 0x403c004f
3104 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
3107 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3108 + if (host->id == 1) {
3109 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
3110 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
3112 + /* internal clock: latch read data */
3113 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
3118 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
3119 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
3120 + set when kernel driver wants to use SDIO bus interrupt */
3121 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
3122 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
3124 + /* disable detect SDIO device interupt function */
3125 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
3127 + /* eneable SMT for glitch filter */
3128 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
3129 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
3130 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
3133 + /* set clk, cmd, dat pad driving */
3134 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
3135 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
3136 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
3137 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
3138 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
3139 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
3141 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
3142 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
3143 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
3144 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
3145 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
3146 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
3149 + /* set sampling edge */
3151 + /* write crc timeout detection */
3152 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
3154 + /* Configure to default data timeout */
3155 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
3157 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
3159 + //printk("init hardware done!\n");
3162 +/* called by msdc_drv_remove */
3163 +static void msdc_deinit_hw(struct msdc_host *host)
3165 + u32 base = host->base;
3167 + /* Disable and clear all interrupts */
3168 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
3169 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
3171 + /* Disable card detection */
3172 + msdc_enable_cd_irq(host, 0);
3173 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
3176 +/* init gpd and bd list in msdc_drv_probe */
3177 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
3179 + gpd_t *gpd = dma->gpd;
3180 + bd_t *bd = dma->bd;
3183 + /* we just support one gpd */
3184 + int bdlen = MAX_BD_PER_GPD;
3186 + /* init the 2 gpd */
3187 + memset(gpd, 0, sizeof(gpd_t) * 2);
3188 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
3189 + //gpd->next = (dma->gpd_addr + 1); /* bug */
3190 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
3193 + gpd->bdp = 1; /* hwo, cs, bd pointer */
3194 + //gpd->ptr = (void*)virt_to_phys(bd);
3195 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
3197 + memset(bd, 0, sizeof(bd_t) * bdlen);
3198 + ptr = bd + bdlen - 1;
3199 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
3202 + while (ptr != bd) {
3204 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
3209 +static int msdc_drv_probe(struct platform_device *pdev)
3211 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3212 + __iomem void *base;
3213 + struct mmc_host *mmc;
3214 + struct resource *mem;
3215 + struct msdc_host *host;
3216 + struct msdc_hw *hw;
3218 + pdev->dev.platform_data = &msdc0_hw;
3220 + /* Allocate MMC host for this device */
3221 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
3222 + if (!mmc) return -ENOMEM;
3224 + hw = (struct msdc_hw*)pdev->dev.platform_data;
3225 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3226 + irq = platform_get_irq(pdev, 0);
3228 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
3230 + base = devm_request_and_ioremap(&pdev->dev, res);
3232 + return PTR_ERR(base);
3234 +/* mem = request_mem_region(mem->start - 0xa0000000, (mem->end - mem->start + 1) - 0xa0000000, dev_name(&pdev->dev));
3235 + if (mem == NULL) {
3236 + mmc_free_host(mmc);
3240 + /* Set host parameters to mmc */
3241 + mmc->ops = &mt_msdc_ops;
3242 + mmc->f_min = HOST_MIN_MCLK;
3243 + mmc->f_max = HOST_MAX_MCLK;
3244 + mmc->ocr_avail = MSDC_OCR_AVAIL;
3246 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
3247 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
3248 + if (hw->flags & MSDC_HIGHSPEED) {
3249 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
3251 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
3252 + mmc->caps |= MMC_CAP_4_BIT_DATA;
3253 + } else if (hw->data_pins == 8) {
3254 + mmc->caps |= MMC_CAP_8_BIT_DATA;
3256 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
3257 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
3259 + /* MMC core transfer sizes tunable parameters */
3260 + // mmc->max_hw_segs = MAX_HW_SGMTS;
3261 +// mmc->max_phys_segs = MAX_PHY_SGMTS;
3262 + mmc->max_seg_size = MAX_SGMT_SZ;
3263 + mmc->max_blk_size = HOST_MAX_BLKSZ;
3264 + mmc->max_req_size = MAX_REQ_SZ;
3265 + mmc->max_blk_count = mmc->max_req_size;
3267 + host = mmc_priv(mmc);
3270 + host->id = pdev->id;
3273 + host->base = (unsigned long) base;
3274 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
3275 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
3276 + host->sclk = 0; /* sclk: the really clock after divition */
3277 + host->pm_state = PMSG_RESUME;
3278 + host->suspend = 0;
3279 + host->core_clkon = 0;
3280 + host->card_clkon = 0;
3281 + host->core_power = 0;
3282 + host->power_mode = MMC_POWER_OFF;
3283 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
3284 + host->timeout_ns = 0;
3285 + host->timeout_clks = DEFAULT_DTOC * 65536;
3288 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
3290 + host->dma.used_gpd = 0;
3291 + host->dma.used_bd = 0;
3293 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
3294 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
3295 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
3296 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
3297 + msdc_init_gpd_bd(host, &host->dma);
3299 + msdc_6575_host[pdev->id] = host;
3301 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
3302 + spin_lock_init(&host->lock);
3303 + msdc_init_hw(host);
3305 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
3306 + if (ret) goto release;
3307 + // mt65xx_irq_unmask(irq); /* --- by chhung */
3309 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
3310 + if (hw->request_cd_eirq) { /* not set for MT6575 */
3311 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
3315 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
3316 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
3318 + if (hw->register_pm) {/* yes for sdio */
3319 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
3320 + //printk("MSDC_SYS_SUSPEND and register_pm both set\n");
3322 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
3325 + platform_set_drvdata(pdev, mmc);
3327 + ret = mmc_add_host(mmc);
3328 + if (ret) goto free_irq;
3330 + /* Config card detection pin and enable interrupts */
3331 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
3332 + msdc_enable_cd_irq(host, 1);
3334 + msdc_enable_cd_irq(host, 0);
3340 + free_irq(irq, host);
3342 + platform_set_drvdata(pdev, NULL);
3343 + msdc_deinit_hw(host);
3345 + tasklet_kill(&host->card_tasklet);
3348 + release_mem_region(mem->start, mem->end - mem->start + 1);
3350 + mmc_free_host(mmc);
3355 +/* 4 device share one driver, using "drvdata" to show difference */
3356 +static int msdc_drv_remove(struct platform_device *pdev)
3358 + struct mmc_host *mmc;
3359 + struct msdc_host *host;
3360 + struct resource *mem;
3363 + mmc = platform_get_drvdata(pdev);
3366 + host = mmc_priv(mmc);
3369 + //printk("removed !!!\n");
3371 + platform_set_drvdata(pdev, NULL);
3372 + mmc_remove_host(host->mmc);
3373 + msdc_deinit_hw(host);
3375 + tasklet_kill(&host->card_tasklet);
3376 + free_irq(host->irq, host);
3378 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
3379 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
3381 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3384 + release_mem_region(mem->start, mem->end - mem->start + 1);
3386 + mmc_free_host(host->mmc);
3391 +static const struct of_device_id mt7620a_sdhci_match[] = {
3392 + { .compatible = "ralink,mt7620a-sdhci" },
3395 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
3397 +/* Fix me: Power Flow */
3398 +static struct platform_driver mt_msdc_driver = {
3399 + .probe = msdc_drv_probe,
3400 + .remove = msdc_drv_remove,
3403 + .owner = THIS_MODULE,
3404 + .of_match_table = mt7620a_sdhci_match,
3409 +static int __init mt_msdc_init(void)
3415 + mtk_sd_device.dev.platform_data = &msdc0_hw;
3416 + printk("MTK MSDC device init.\n");
3417 + reg = sdr_read32((__iomem void *) 0xb0000060) & ~(0x3<<18);
3419 + sdr_write32((__iomem void *) 0xb0000060, reg);
3421 + ret = platform_driver_register(&mt_msdc_driver);
3423 + printk(KERN_ERR DRV_NAME ": Can't register driver");
3426 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
3428 + //msdc_debug_proc_init();
3432 +static void __exit mt_msdc_exit(void)
3434 + platform_driver_unregister(&mt_msdc_driver);
3437 +module_init(mt_msdc_init);
3438 +module_exit(mt_msdc_exit);
3439 +MODULE_LICENSE("GPL");
3440 +MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
3441 +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
3443 +EXPORT_SYMBOL(msdc_6575_host);