1 --- a/drivers/usb/core/hcd-pci.c
2 +++ b/drivers/usb/core/hcd-pci.c
3 @@ -223,8 +223,13 @@ int usb_hcd_pci_probe(struct pci_dev *de
8 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
9 + hcd->amd_resume_bug = 0;
11 hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
12 driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
15 if (driver->flags & HCD_MEMORY) {
17 --- a/drivers/usb/core/hub.c
18 +++ b/drivers/usb/core/hub.c
19 @@ -1306,7 +1306,7 @@ static void hub_quiesce(struct usb_hub *
20 if (type != HUB_SUSPEND) {
21 /* Disconnect all the children */
22 for (i = 0; i < hdev->maxchild; ++i) {
23 - if (hub->ports[i]->child)
24 + if (hub->ports[i] && hub->ports[i]->child)
25 usb_disconnect(&hub->ports[i]->child);
28 --- a/drivers/usb/core/port.c
29 +++ b/drivers/usb/core/port.c
30 @@ -480,8 +480,10 @@ void usb_hub_remove_port_device(struct u
31 struct usb_port *port_dev = hub->ports[port1 - 1];
32 struct usb_port *peer;
34 - peer = port_dev->peer;
36 - unlink_peers(port_dev, peer);
37 - device_unregister(&port_dev->dev);
39 + peer = port_dev->peer;
41 + unlink_peers(port_dev, peer);
42 + device_unregister(&port_dev->dev);
45 --- a/drivers/usb/host/Kconfig
46 +++ b/drivers/usb/host/Kconfig
47 @@ -41,6 +41,13 @@ config USB_XHCI_PLATFORM
51 +config USB_MT7621_XHCI_PLATFORM
53 + depends on USB_XHCI_PLATFORM
54 + depends on SOC_MT7621
59 tristate "xHCI support for Marvell Armada 375/38x"
60 select USB_XHCI_PLATFORM
61 @@ -596,7 +603,7 @@ endif # USB_OHCI_HCD
64 tristate "UHCI HCD (most Intel and VIA) support"
65 - depends on PCI || USB_UHCI_SUPPORT_NON_PCI_HC
66 + depends on BROKEN && (PCI || USB_UHCI_SUPPORT_NON_PCI_HC)
68 The Universal Host Controller Interface is a standard by Intel for
69 accessing the USB hardware in the PC (which is also called the USB
70 --- a/drivers/usb/host/Makefile
71 +++ b/drivers/usb/host/Makefile
72 @@ -16,7 +16,12 @@ xhci-hcd-y := xhci.o xhci-mem.o
73 xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
74 xhci-hcd-y += xhci-trace.o
76 +ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
77 +xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
80 xhci-plat-hcd-y := xhci-plat.o
82 ifneq ($(CONFIG_USB_XHCI_MVEBU), )
83 xhci-plat-hcd-y += xhci-mvebu.o
85 @@ -26,9 +31,14 @@ endif
87 obj-$(CONFIG_USB_WHCI_HCD) += whci/
89 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
90 obj-$(CONFIG_PCI) += pci-quirks.o
93 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
94 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
97 obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
99 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
101 +++ b/drivers/usb/host/mtk-phy-7621.c
103 +#include "mtk-phy.h"
105 +#ifdef CONFIG_PROJECT_7621
106 +#include "mtk-phy-7621.h"
109 +PHY_INT32 phy_init(struct u3phy_info *info){
114 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
118 +//--------------------------------------------------------
119 +// Function : fgEyeScanHelper_CheckPtInRegion()
120 +// Description : Check if the test point is in a rectangle region.
121 +// If it is in the rectangle, also check if this point
122 +// is on the multiple of deltaX and deltaY.
123 +// Parameter : strucScanRegion * prEye - the region
126 +// Return : BYTE - TRUE : This point needs to be tested
127 +// FALSE: This point will be omitted
128 +// Note : First check within the rectangle.
129 +// Secondly, use modulous to check if the point will be tested.
130 +//--------------------------------------------------------
131 +static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
133 + PHY_INT8 fgValid = true;
136 + /// Be careful, the axis origin is on the TOP-LEFT corner.
137 + /// Therefore the top-left point has the minimum X and Y
138 + /// Botton-right point is the maximum X and Y
139 + if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
140 + && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
142 + // With the region, now check whether or not the input test point is
143 + // on the multiples of X and Y
144 + // Do not have to worry about negative value, because we have already
145 + // check the input bX, and bY is within the region.
146 + if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
147 + || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
149 + // if the division will have remainder, that means
150 + // the input test point is on the multiples of X and Y
165 +//--------------------------------------------------------
166 +// Function : EyeScanHelper_RunTest()
167 +// Description : Enable the test, and wait til it is completed
171 +//--------------------------------------------------------
172 +static void EyeScanHelper_RunTest(struct u3phy_info *info)
175 + // Disable the test
176 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
177 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
180 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
181 + , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
183 + // Wait til it's done
184 + //RGS_SSUSB_RX_EYE_CNT_RDY
185 + while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
186 + , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
189 +//--------------------------------------------------------
190 +// Function : fgEyeScanHelper_CalNextPoint()
191 +// Description : Calcualte the test point for the measurement
193 +// Return : BOOL - TRUE : the next point is within the
194 +// boundaryof HW limit
195 +// FALSE: the next point is out of the HW limit
196 +// Note : The next point is obtained by calculating
197 +// from the bottom left of the region rectangle
198 +// and then scanning up until it reaches the upper
199 +// limit. At this time, the x will increment, and
200 +// start scanning downwards until the y hits the
202 +//--------------------------------------------------------
203 +static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
205 + if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
206 + || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
209 + /// Reaches the limit of Y axis
213 + _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
215 + if (_bXcurr > MAX_X)
222 + _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
228 +PHY_INT32 eyescan_init(struct u3phy_info *info){
229 + //initial PHY setting
230 + U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
231 + , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
232 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
233 + , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
234 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
235 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
236 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
237 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
241 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
242 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
243 + PHY_INT32 cOfst = 0;
244 + PHY_UINT8 bIdxX = 0;
245 + PHY_UINT8 bIdxY = 0;
246 + //PHY_INT8 bCnt = 0;
247 + PHY_UINT8 bIdxCycCnt = 0;
251 + PHY_UINT8 bExtendCnt;
252 + PHY_INT8 isContinue;
253 + //PHY_INT8 isBreak;
254 + PHY_UINT32 wErr0 = 0, wErr1 = 0;
257 + PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
258 + PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
260 + _rEye1.bX_tl = x_t1;
261 + _rEye1.bY_tl = y_t1;
262 + _rEye1.bX_br = x_br;
263 + _rEye1.bY_br = y_br;
264 + _rEye1.bDeltaX = delta_x;
265 + _rEye1.bDeltaY = delta_y;
267 + _rEye2.bX_tl = x_t1;
268 + _rEye2.bY_tl = y_t1;
269 + _rEye2.bX_br = x_br;
270 + _rEye2.bY_br = y_br;
271 + _rEye2.bDeltaX = delta_x;
272 + _rEye2.bDeltaY = delta_y;
274 + _rTestCycle.wEyeCnt = eye_cnt;
275 + _rTestCycle.bNumOfEyeCnt = num_cnt;
276 + _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
277 + _rTestCycle.bPICalEn = PI_cal_en;
281 + _eScanDir = SCAN_DN;
284 + printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
285 + eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
286 + x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
288 + //force SIGDET to OFF
289 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
290 + , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
291 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
292 + , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
293 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
294 + , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
296 + // RX_TRI_DET_EN to Disable
297 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
298 + , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
300 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
301 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
302 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
303 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
304 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
305 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
306 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
307 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
312 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
313 + , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
314 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
315 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
316 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
317 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
321 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
322 + , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
323 + _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
324 + , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
326 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
328 + // Read Initial DAC
330 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
331 + ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
333 + // Eye Monitor Feature
334 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
335 + , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
336 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
337 + , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
339 + // Move X,Y to the top-left corner
340 + for (cOfst = 0; cOfst >= -64; cOfst--)
342 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
343 + ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
345 + for (cOfst = 0; cOfst < 64; cOfst++)
347 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
348 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
349 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
350 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
353 + for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
354 + for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
356 + for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
357 + pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
358 + pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
364 + //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
365 + // The point is within the boundary, then let's check if it is within
366 + // the testing region.
367 + // The point is only test-able if one of the eye region
368 + // includes this point.
369 + fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
370 + || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
371 + // Translate bX and bY to 2's complement from where the origin was on the
372 + // top left corner.
373 + // 0x40 and 0x3F needs a bit of thinking!!!! >"<
374 + cX = (_bXcurr ^ 0x40);
375 + cY = (_bYcurr ^ 0x3F);
377 + // Set X if necessary
378 + if (_fgXChged == true)
380 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
381 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
384 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
385 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
386 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
387 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
389 + /// Test this point!
391 + for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
394 + EyeScanHelper_RunTest(info);
396 + for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
398 + EyeScanHelper_RunTest(info);
399 + wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
400 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
401 + wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
402 + , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
404 + pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
405 + pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
407 + //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
408 +// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
409 +// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
411 + //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
416 + if (fgEyeScanHelper_CalNextPoint() == false){
418 + printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
419 + printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
421 + printk(KERN_ERR "end of eye scan\n");
422 + isContinue = false;
425 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
426 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
427 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
429 + // Move X,Y to the top-left corner
430 + for (cOfst = 63; cOfst >= 0; cOfst--)
432 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
433 + , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
435 + for (cOfst = 63; cOfst >= 0; cOfst--)
437 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
438 + , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
439 + U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
440 + , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
443 + printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
444 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
445 + , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
447 + printk(KERN_ERR "PI result: %d\n", _bPIResult);
448 + printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
449 + printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
455 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
460 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
464 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
467 + //PHY_INT8 u1SrCalVal = 0;
468 + //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
469 + PHY_INT32 fgRet = 0;
470 + PHY_INT32 u4FmOut = 0;
471 + PHY_INT32 u4Tmp = 0;
474 + // => RG_USB20_HSTX_SRCAL_EN = 1
475 + // enable HS TX SR calibration
476 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
477 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
480 + // => RG_FRCK_EN = 1
481 + // Enable free run clock
482 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
483 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
485 + // MT6290 HS signal quality patch
486 + // => RG_CYCLECNT = 400
487 + // Setting cyclecnt =400
488 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
489 + , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
491 + // => RG_FREQDET_EN = 1
492 + // Enable frequency meter
493 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
494 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
496 + // wait for FM detection done, set 10ms timeout
497 + for(i=0; i<10; i++){
498 + // => u4FmOut = USB_FM_OUT
500 + u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
501 + printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
503 + // check if FM detection done
507 + printk("FM detection done! loop = %d\n", i);
515 + // => RG_FREQDET_EN = 0
516 + // disable frequency meter
517 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
518 + , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
520 + // => RG_FRCK_EN = 0
521 + // disable free run clock
522 + U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
523 + , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
525 + // => RG_USB20_HSTX_SRCAL_EN = 0
526 + // disable HS TX SR calibration
527 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
528 + , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
532 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
533 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
538 + // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
539 + u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
540 + printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
541 + U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
542 + , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
549 +++ b/drivers/usb/host/mtk-phy-7621.h
551 +#ifdef CONFIG_PROJECT_7621
552 +#ifndef __MTK_PHY_7621_H
553 +#define __MTK_PHY_7621_H
555 +#define U2_SR_COEF_7621 28
557 +///////////////////////////////////////////////////////////////////////////////
566 + PHY_LE32 u2phyacr0;
567 + PHY_LE32 u2phyacr1;
568 + PHY_LE32 u2phyacr2;
569 + PHY_LE32 u2phyacr3;
571 + PHY_LE32 u2phyacr4;
572 + PHY_LE32 u2phyamon0;
573 + PHY_LE32 reserve1[2];
575 + PHY_LE32 reserve2[12];
577 + PHY_LE32 u2phydcr0;
578 + PHY_LE32 u2phydcr1;
579 + PHY_LE32 u2phydtm0;
580 + PHY_LE32 u2phydtm1;
582 + PHY_LE32 u2phydmon0;
583 + PHY_LE32 u2phydmon1;
584 + PHY_LE32 u2phydmon2;
585 + PHY_LE32 u2phydmon3;
587 + PHY_LE32 u2phybc12c;
588 + PHY_LE32 u2phybc12c1;
589 + PHY_LE32 reserve3[2];
591 + PHY_LE32 reserve4[24];
593 + PHY_LE32 reserve6[3];
598 +#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
599 +#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
600 +#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
601 +#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
602 +#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
603 +#define RG_USB20_REF_EN (0x1<<15) //15:15
604 +#define RG_USB20_INTR_EN (0x1<<14) //14:14
605 +#define RG_USB20_BG_TRIM (0xf<<8) //11:8
606 +#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
607 +#define RG_USB20_BG_RASEL (0x3<<4) //5:4
608 +#define RG_USB20_BGR_DIV (0x3<<2) //3:2
609 +#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
610 +#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
613 +#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
614 +#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
615 +#define RG_USB20_MPX_SEL (0xff<<16) //23:16
616 +#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
617 +#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
618 +#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
619 +#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
620 +#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
621 +#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
624 +#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
625 +#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
626 +#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
629 +#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
630 +#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
631 +#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
632 +#define RG_USB20_LS_CR (0x7<<12) //14:12
633 +#define RG_USB20_FS_CR (0x7<<8) //10:8
634 +#define RG_USB20_LS_SR (0x7<<4) //6:4
635 +#define RG_USB20_FS_SR (0x7<<0) //2:0
638 +#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
639 +#define RG_USB20_SQD (0x3<<24) //25:24
640 +#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
641 +#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
642 +#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
643 +#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
644 +#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
645 +#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
646 +#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
647 +#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
648 +#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
651 +#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
652 +#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
653 +#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
654 +#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
655 +#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
656 +#define RG_USB20_DISCD (0x3<<20) //21:20
657 +#define RG_USB20_DISCTH (0xf<<16) //19:16
658 +#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
659 +#define RG_USB20_SQCAL (0xf<<8) //11:8
660 +#define RG_USB20_SQTH (0xf<<0) //3:0
663 +#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
664 +#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
665 +#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
666 +#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
667 +#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
668 +#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
669 +#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
670 +#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
671 +#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
672 +#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
673 +#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
674 +#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
675 +#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
676 +#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
677 +#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
678 +#define RG_USB20_PHY_REV (0xff<<0) //7:0
681 +#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
682 +#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
683 +#define USB20_DP_100K_EN (0x1<<16) //16:16
684 +#define USB20_GPIO_DM_I (0x1<<15) //15:15
685 +#define USB20_GPIO_DP_I (0x1<<14) //14:14
686 +#define USB20_GPIO_DM_OE (0x1<<13) //13:13
687 +#define USB20_GPIO_DP_OE (0x1<<12) //12:12
688 +#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
689 +#define USB20_GPIO_MODE (0x1<<8) //8:8
690 +#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
691 +#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
692 +#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
693 +#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
696 +#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
697 +#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
700 +#define RG_USB20_CDR_TST (0x3<<30) //31:30
701 +#define RG_USB20_GATED_ENB (0x1<<29) //29:29
702 +#define RG_USB20_TESTMODE (0x3<<26) //27:26
703 +#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
704 +#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
705 +#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
706 +#define RG_USB20_EBTHRLD (0x1<<7) //7:7
707 +#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
708 +#define RG_USB20_TX_TST (0x1<<5) //5:5
709 +#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
710 +#define RG_USB20_CDR_FILT (0xf<<0) //3:0
713 +#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
714 +#define RG_USB20_DRVVBUS (0x1<<23) //23:23
715 +#define RG_DEBUG_EN (0x1<<22) //22:22
716 +#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
717 +#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
718 +#define RG_USB20_BERTH (0x3<<16) //17:16
719 +#define RG_USB20_LBMODE (0x3<<13) //14:13
720 +#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
721 +#define RG_USB20_TAPSEL (0xfff<<0) //11:0
724 +#define RG_UART_MODE (0x3<<30) //31:30
725 +#define FORCE_UART_I (0x1<<29) //29:29
726 +#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
727 +#define FORCE_UART_TX_OE (0x1<<27) //27:27
728 +#define FORCE_UART_EN (0x1<<26) //26:26
729 +#define FORCE_USB_CLKEN (0x1<<25) //25:25
730 +#define FORCE_DRVVBUS (0x1<<24) //24:24
731 +#define FORCE_DATAIN (0x1<<23) //23:23
732 +#define FORCE_TXVALID (0x1<<22) //22:22
733 +#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
734 +#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
735 +#define FORCE_XCVRSEL (0x1<<19) //19:19
736 +#define FORCE_SUSPENDM (0x1<<18) //18:18
737 +#define FORCE_TERMSEL (0x1<<17) //17:17
738 +#define FORCE_OPMODE (0x1<<16) //16:16
739 +#define UTMI_MUXSEL (0x1<<15) //15:15
740 +#define RG_RESET (0x1<<14) //14:14
741 +#define RG_DATAIN (0xf<<10) //13:10
742 +#define RG_TXVALIDH (0x1<<9) //9:9
743 +#define RG_TXVALID (0x1<<8) //8:8
744 +#define RG_DMPULLDOWN (0x1<<7) //7:7
745 +#define RG_DPPULLDOWN (0x1<<6) //6:6
746 +#define RG_XCVRSEL (0x3<<4) //5:4
747 +#define RG_SUSPENDM (0x1<<3) //3:3
748 +#define RG_TERMSEL (0x1<<2) //2:2
749 +#define RG_OPMODE (0x3<<0) //1:0
752 +#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
753 +#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
754 +#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
755 +#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
756 +#define RG_UART_I (0x1<<19) //19:19
757 +#define RG_UART_BIAS_EN (0x1<<18) //18:18
758 +#define RG_UART_TX_OE (0x1<<17) //17:17
759 +#define RG_UART_EN (0x1<<16) //16:16
760 +#define FORCE_VBUSVALID (0x1<<13) //13:13
761 +#define FORCE_SESSEND (0x1<<12) //12:12
762 +#define FORCE_BVALID (0x1<<11) //11:11
763 +#define FORCE_AVALID (0x1<<10) //10:10
764 +#define FORCE_IDDIG (0x1<<9) //9:9
765 +#define FORCE_IDPULLUP (0x1<<8) //8:8
766 +#define RG_VBUSVALID (0x1<<5) //5:5
767 +#define RG_SESSEND (0x1<<4) //4:4
768 +#define RG_BVALID (0x1<<3) //3:3
769 +#define RG_AVALID (0x1<<2) //2:2
770 +#define RG_IDDIG (0x1<<1) //1:1
771 +#define RG_IDPULLUP (0x1<<0) //0:0
774 +#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
777 +#define USB20_UART_O (0x1<<31) //31:31
778 +#define RGO_USB20_LB_PASS (0x1<<30) //30:30
779 +#define RGO_USB20_LB_DONE (0x1<<29) //29:29
780 +#define AD_USB20_BVALID (0x1<<28) //28:28
781 +#define USB20_IDDIG (0x1<<27) //27:27
782 +#define AD_USB20_VBUSVALID (0x1<<26) //26:26
783 +#define AD_USB20_SESSEND (0x1<<25) //25:25
784 +#define AD_USB20_AVALID (0x1<<24) //24:24
785 +#define USB20_LINE_STATE (0x3<<22) //23:22
786 +#define USB20_HST_DISCON (0x1<<21) //21:21
787 +#define USB20_TX_READY (0x1<<20) //20:20
788 +#define USB20_RX_ERROR (0x1<<19) //19:19
789 +#define USB20_RX_ACTIVE (0x1<<18) //18:18
790 +#define USB20_RX_VALIDH (0x1<<17) //17:17
791 +#define USB20_RX_VALID (0x1<<16) //16:16
792 +#define USB20_DATA_OUT (0xffff<<0) //15:0
795 +#define RGO_TXVALID_CNT (0xff<<24) //31:24
796 +#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
797 +#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
798 +#define USB20_PROBE_OUT (0xff<<0) //7:0
801 +#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
802 +#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
803 +#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
804 +#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
805 +#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
808 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
809 +#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
810 +#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
811 +#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
812 +#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
813 +#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
814 +#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
815 +#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
816 +#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
817 +#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
818 +#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
819 +#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
820 +#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
821 +#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
822 +#define RG_CHGDT_EN (0x1<<0) //0:0
825 +#define RG_CHGDT_REV (0xff<<0) //7:0
828 +#define RG_PAGE (0xff<<24) //31:24
829 +#define I2C_MODE (0x1<<16) //16:16
835 +#define RG_USB20_USBPLL_DIVEN_OFST (28)
836 +#define RG_USB20_USBPLL_CKCTRL_OFST (26)
837 +#define RG_USB20_USBPLL_PREDIV_OFST (24)
838 +#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
839 +#define RG_USB20_USBPLL_FBDIV_OFST (16)
840 +#define RG_USB20_REF_EN_OFST (15)
841 +#define RG_USB20_INTR_EN_OFST (14)
842 +#define RG_USB20_BG_TRIM_OFST (8)
843 +#define RG_USB20_BG_RBSEL_OFST (6)
844 +#define RG_USB20_BG_RASEL_OFST (4)
845 +#define RG_USB20_BGR_DIV_OFST (2)
846 +#define RG_SIFSLV_CHP_EN_OFST (1)
847 +#define RG_SIFSLV_BGR_EN_OFST (0)
850 +#define RG_USB20_VRT_VREF_SEL_OFST (28)
851 +#define RG_USB20_TERM_VREF_SEL_OFST (24)
852 +#define RG_USB20_MPX_SEL_OFST (16)
853 +#define RG_USB20_MPX_OUT_SEL_OFST (12)
854 +#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
855 +#define RG_USB20_USBPLL_ACCEN_OFST (3)
856 +#define RG_USB20_USBPLL_LF_OFST (2)
857 +#define RG_USB20_USBPLL_BR_OFST (1)
858 +#define RG_USB20_USBPLL_BP_OFST (0)
861 +#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
862 +#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
863 +#define RG_USB20_CLKREF_REV_OFST (0)
866 +#define RG_USB20_ICUSB_EN_OFST (24)
867 +#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
868 +#define RG_USB20_HSTX_SRCTRL_OFST (16)
869 +#define RG_USB20_LS_CR_OFST (12)
870 +#define RG_USB20_FS_CR_OFST (8)
871 +#define RG_USB20_LS_SR_OFST (4)
872 +#define RG_USB20_FS_SR_OFST (0)
875 +#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
876 +#define RG_USB20_SQD_OFST (24)
877 +#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
878 +#define RG_USB20_HSTX_TMODE_EN_OFST (19)
879 +#define RG_USB20_PHYD_MONEN_OFST (18)
880 +#define RG_USB20_INLPBK_EN_OFST (17)
881 +#define RG_USB20_CHIRP_EN_OFST (16)
882 +#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
883 +#define RG_USB20_DM_ABIST_SELE_OFST (8)
884 +#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
885 +#define RG_USB20_DP_ABIST_SELE_OFST (0)
888 +#define RG_USB20_OTG_ABIST_SELE_OFST (29)
889 +#define RG_USB20_OTG_ABIST_EN_OFST (28)
890 +#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
891 +#define RG_USB20_OTG_VBUSTH_OFST (24)
892 +#define RG_USB20_DISC_FIT_EN_OFST (22)
893 +#define RG_USB20_DISCD_OFST (20)
894 +#define RG_USB20_DISCTH_OFST (16)
895 +#define RG_USB20_SQCAL_EN_OFST (15)
896 +#define RG_USB20_SQCAL_OFST (8)
897 +#define RG_USB20_SQTH_OFST (0)
900 +#define RG_USB20_HSTX_DBIST_OFST (28)
901 +#define RG_USB20_HSTX_BIST_EN_OFST (26)
902 +#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
903 +#define RG_USB20_HSRX_TMODE_EN_OFST (23)
904 +#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
905 +#define RG_USB20_USB11_TMODE_EN_OFST (19)
906 +#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
907 +#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
908 +#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
909 +#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
910 +#define RG_USB20_PUPD_BIST_EN_OFST (12)
911 +#define RG_USB20_EN_PU_DM_OFST (11)
912 +#define RG_USB20_EN_PD_DM_OFST (10)
913 +#define RG_USB20_EN_PU_DP_OFST (9)
914 +#define RG_USB20_EN_PD_DP_OFST (8)
915 +#define RG_USB20_PHY_REV_OFST (0)
918 +#define RG_USB20_DP_100K_MODE_OFST (18)
919 +#define RG_USB20_DM_100K_EN_OFST (17)
920 +#define USB20_DP_100K_EN_OFST (16)
921 +#define USB20_GPIO_DM_I_OFST (15)
922 +#define USB20_GPIO_DP_I_OFST (14)
923 +#define USB20_GPIO_DM_OE_OFST (13)
924 +#define USB20_GPIO_DP_OE_OFST (12)
925 +#define RG_USB20_GPIO_CTL_OFST (9)
926 +#define USB20_GPIO_MODE_OFST (8)
927 +#define RG_USB20_TX_BIAS_EN_OFST (5)
928 +#define RG_USB20_TX_VCMPDN_EN_OFST (4)
929 +#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
930 +#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
933 +#define RGO_USB20_GPIO_DM_O_OFST (1)
934 +#define RGO_USB20_GPIO_DP_O_OFST (0)
937 +#define RG_USB20_CDR_TST_OFST (30)
938 +#define RG_USB20_GATED_ENB_OFST (29)
939 +#define RG_USB20_TESTMODE_OFST (26)
940 +#define RG_USB20_PLL_STABLE_OFST (25)
941 +#define RG_USB20_PLL_FORCE_ON_OFST (24)
942 +#define RG_USB20_PHYD_RESERVE_OFST (8)
943 +#define RG_USB20_EBTHRLD_OFST (7)
944 +#define RG_USB20_EARLY_HSTX_I_OFST (6)
945 +#define RG_USB20_TX_TST_OFST (5)
946 +#define RG_USB20_NEGEDGE_ENB_OFST (4)
947 +#define RG_USB20_CDR_FILT_OFST (0)
950 +#define RG_USB20_PROBE_SEL_OFST (24)
951 +#define RG_USB20_DRVVBUS_OFST (23)
952 +#define RG_DEBUG_EN_OFST (22)
953 +#define RG_USB20_OTG_PROBE_OFST (20)
954 +#define RG_USB20_SW_PLLMODE_OFST (18)
955 +#define RG_USB20_BERTH_OFST (16)
956 +#define RG_USB20_LBMODE_OFST (13)
957 +#define RG_USB20_FORCE_TAP_OFST (12)
958 +#define RG_USB20_TAPSEL_OFST (0)
961 +#define RG_UART_MODE_OFST (30)
962 +#define FORCE_UART_I_OFST (29)
963 +#define FORCE_UART_BIAS_EN_OFST (28)
964 +#define FORCE_UART_TX_OE_OFST (27)
965 +#define FORCE_UART_EN_OFST (26)
966 +#define FORCE_USB_CLKEN_OFST (25)
967 +#define FORCE_DRVVBUS_OFST (24)
968 +#define FORCE_DATAIN_OFST (23)
969 +#define FORCE_TXVALID_OFST (22)
970 +#define FORCE_DM_PULLDOWN_OFST (21)
971 +#define FORCE_DP_PULLDOWN_OFST (20)
972 +#define FORCE_XCVRSEL_OFST (19)
973 +#define FORCE_SUSPENDM_OFST (18)
974 +#define FORCE_TERMSEL_OFST (17)
975 +#define FORCE_OPMODE_OFST (16)
976 +#define UTMI_MUXSEL_OFST (15)
977 +#define RG_RESET_OFST (14)
978 +#define RG_DATAIN_OFST (10)
979 +#define RG_TXVALIDH_OFST (9)
980 +#define RG_TXVALID_OFST (8)
981 +#define RG_DMPULLDOWN_OFST (7)
982 +#define RG_DPPULLDOWN_OFST (6)
983 +#define RG_XCVRSEL_OFST (4)
984 +#define RG_SUSPENDM_OFST (3)
985 +#define RG_TERMSEL_OFST (2)
986 +#define RG_OPMODE_OFST (0)
989 +#define RG_USB20_PRBS7_EN_OFST (31)
990 +#define RG_USB20_PRBS7_BITCNT_OFST (24)
991 +#define RG_USB20_CLK48M_EN_OFST (23)
992 +#define RG_USB20_CLK60M_EN_OFST (22)
993 +#define RG_UART_I_OFST (19)
994 +#define RG_UART_BIAS_EN_OFST (18)
995 +#define RG_UART_TX_OE_OFST (17)
996 +#define RG_UART_EN_OFST (16)
997 +#define FORCE_VBUSVALID_OFST (13)
998 +#define FORCE_SESSEND_OFST (12)
999 +#define FORCE_BVALID_OFST (11)
1000 +#define FORCE_AVALID_OFST (10)
1001 +#define FORCE_IDDIG_OFST (9)
1002 +#define FORCE_IDPULLUP_OFST (8)
1003 +#define RG_VBUSVALID_OFST (5)
1004 +#define RG_SESSEND_OFST (4)
1005 +#define RG_BVALID_OFST (3)
1006 +#define RG_AVALID_OFST (2)
1007 +#define RG_IDDIG_OFST (1)
1008 +#define RG_IDPULLUP_OFST (0)
1011 +#define RG_USB20_PRBS7_BERTH_OFST (0)
1014 +#define USB20_UART_O_OFST (31)
1015 +#define RGO_USB20_LB_PASS_OFST (30)
1016 +#define RGO_USB20_LB_DONE_OFST (29)
1017 +#define AD_USB20_BVALID_OFST (28)
1018 +#define USB20_IDDIG_OFST (27)
1019 +#define AD_USB20_VBUSVALID_OFST (26)
1020 +#define AD_USB20_SESSEND_OFST (25)
1021 +#define AD_USB20_AVALID_OFST (24)
1022 +#define USB20_LINE_STATE_OFST (22)
1023 +#define USB20_HST_DISCON_OFST (21)
1024 +#define USB20_TX_READY_OFST (20)
1025 +#define USB20_RX_ERROR_OFST (19)
1026 +#define USB20_RX_ACTIVE_OFST (18)
1027 +#define USB20_RX_VALIDH_OFST (17)
1028 +#define USB20_RX_VALID_OFST (16)
1029 +#define USB20_DATA_OUT_OFST (0)
1032 +#define RGO_TXVALID_CNT_OFST (24)
1033 +#define RGO_RXACTIVE_CNT_OFST (16)
1034 +#define RGO_USB20_LB_BERCNT_OFST (8)
1035 +#define USB20_PROBE_OUT_OFST (0)
1038 +#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
1039 +#define RGO_USB20_PRBS7_DONE_OFST (3)
1040 +#define RGO_USB20_PRBS7_LOCK_OFST (2)
1041 +#define RGO_USB20_PRBS7_PASS_OFST (1)
1042 +#define RGO_USB20_PRBS7_PASSTH_OFST (0)
1045 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
1046 +#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
1047 +#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
1048 +#define RG_CHGDT_ISRC_LEV_OFST (14)
1049 +#define RG_CHGDT_VDATSRC_OFST (13)
1050 +#define RG_CHGDT_BGVREF_SEL_OFST (10)
1051 +#define RG_CHGDT_RDVREF_SEL_OFST (8)
1052 +#define RG_CHGDT_ISRC_DP_OFST (7)
1053 +#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
1054 +#define RG_CHGDT_VDAT_DM_OFST (5)
1055 +#define RG_CHGDT_OPOUT_DP_OFST (4)
1056 +#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
1057 +#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
1058 +#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
1059 +#define RG_CHGDT_EN_OFST (0)
1062 +#define RG_CHGDT_REV_OFST (0)
1065 +#define RG_PAGE_OFST (24)
1066 +#define I2C_MODE_OFST (16)
1069 +///////////////////////////////////////////////////////////////////////////////
1071 +struct u3phya_reg {
1094 +#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
1095 +#define RG_SSUSB_CHPEN (0x1<<30) //30:30
1096 +#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
1097 +#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
1098 +#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
1099 +#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
1100 +#define RG_SSUSB_REF_EN (0x1<<15) //15:15
1101 +#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
1102 +#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
1103 +#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
1104 +#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
1105 +#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
1108 +#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
1109 +#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
1110 +#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
1111 +#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
1112 +#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
1113 +#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
1114 +#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
1115 +#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
1116 +#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
1119 +#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
1120 +#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
1121 +#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
1122 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
1123 +#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
1124 +#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
1125 +#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
1126 +#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
1127 +#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
1128 +#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
1129 +#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
1130 +#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
1131 +#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
1132 +#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
1133 +#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
1136 +#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
1139 +#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
1142 +#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
1143 +#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
1144 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
1145 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
1146 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
1147 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
1148 +#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
1149 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
1150 +#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
1151 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
1152 +#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
1155 +#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
1156 +#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
1157 +#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
1158 +#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
1159 +#define RG_SSUSB_TX_SR (0x7<<20) //22:20
1160 +#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
1161 +#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
1162 +#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
1163 +#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
1164 +#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
1165 +#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
1166 +#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
1167 +#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
1168 +#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
1171 +#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
1172 +#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
1173 +#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
1174 +#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
1175 +#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
1176 +#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
1177 +#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
1178 +#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
1179 +#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
1180 +#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
1181 +#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
1184 +#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
1187 +#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
1188 +#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
1191 +#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
1192 +#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
1193 +#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
1194 +#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
1195 +#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
1196 +#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
1197 +#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
1198 +#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
1199 +#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
1200 +#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
1201 +#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
1202 +#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
1203 +#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
1204 +#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
1205 +#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
1206 +#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
1207 +#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
1208 +#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
1209 +#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
1210 +#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
1211 +#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
1214 +#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
1215 +#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
1216 +#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
1217 +#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
1218 +#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
1219 +#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
1220 +#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
1221 +#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
1222 +#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
1223 +#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
1224 +#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
1225 +#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
1226 +#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
1227 +#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
1230 +#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
1231 +#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
1232 +#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
1233 +#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
1236 +#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
1237 +#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
1240 +#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
1241 +#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
1242 +#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
1243 +#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
1244 +#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
1250 +#define RG_SSUSB_BGR_EN_OFST (31)
1251 +#define RG_SSUSB_CHPEN_OFST (30)
1252 +#define RG_SSUSB_BG_DIV_OFST (28)
1253 +#define RG_SSUSB_INTR_EN_OFST (26)
1254 +#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
1255 +#define RG_SSUSB_MPX_SEL_OFST (16)
1256 +#define RG_SSUSB_REF_EN_OFST (15)
1257 +#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
1258 +#define RG_SSUSB_BG_RASEL_OFST (9)
1259 +#define RG_SSUSB_BG_RBSEL_OFST (7)
1260 +#define RG_SSUSB_BG_MONEN_OFST (6)
1261 +#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
1264 +#define RG_PCIE_CLKDRV_SLEW_OFST (30)
1265 +#define RG_PCIE_CLKDRV_AMP_OFST (27)
1266 +#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
1267 +#define RG_SSUSB_XTAL_MON_EN_OFST (25)
1268 +#define RG_SSUSB_XTAL_HYS_OFST (24)
1269 +#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
1270 +#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
1271 +#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
1272 +#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
1275 +#define RG_SSUSB_SYSPLL_LF_OFST (31)
1276 +#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
1277 +#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
1278 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
1279 +#define RG_SSUSB_SYSPLL_BLP_OFST (20)
1280 +#define RG_SSUSB_SYSPLL_BP_OFST (19)
1281 +#define RG_SSUSB_SYSPLL_BR_OFST (18)
1282 +#define RG_SSUSB_SYSPLL_BC_OFST (17)
1283 +#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
1284 +#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
1285 +#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
1286 +#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
1287 +#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
1288 +#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
1289 +#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
1292 +#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
1295 +#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
1298 +#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
1299 +#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
1300 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
1301 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
1302 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
1303 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
1304 +#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
1305 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
1306 +#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
1307 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
1308 +#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
1311 +#define RG_SSUSB_TX250MCK_INVB_OFST (31)
1312 +#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
1313 +#define RG_SSUSB_IDRV_CALIB_OFST (24)
1314 +#define RG_SSUSB_TX_R50_FON_OFST (23)
1315 +#define RG_SSUSB_TX_SR_OFST (20)
1316 +#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
1317 +#define RG_SSUSB_RXDET_RSEL_OFST (14)
1318 +#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
1319 +#define RG_SSUSB_CKMON_EN_OFST (11)
1320 +#define RG_SSUSB_CKMON_SEL_OFST (8)
1321 +#define RG_SSUSB_TX_VLMON_EN_OFST (7)
1322 +#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
1323 +#define RG_SSUSB_RXLBTX_EN_OFST (5)
1324 +#define RG_SSUSB_TXLBRX_EN_OFST (4)
1327 +#define RG_SSUSB_RESERVE_OFST (12)
1328 +#define RG_SSUSB_PLL_CKCTRL_OFST (10)
1329 +#define RG_SSUSB_PLL_POSDIV_OFST (8)
1330 +#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
1331 +#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
1332 +#define RG_SSUSB_PLL_EP_EN_OFST (5)
1333 +#define RG_SSUSB_PLL_VOD_EN_OFST (4)
1334 +#define RG_SSUSB_PLL_V11_EN_OFST (3)
1335 +#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
1336 +#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
1337 +#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
1340 +#define RG_SSUSB_PLL_RESERVE_OFST (0)
1343 +#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
1344 +#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
1347 +#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
1348 +#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
1349 +#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
1350 +#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
1351 +#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
1352 +#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
1353 +#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
1354 +#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
1355 +#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
1356 +#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
1357 +#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
1358 +#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
1359 +#define RG_SSUSB_CDR_MONMUX_OFST (11)
1360 +#define RG_SSUSB_CDR_CKCTRL_OFST (9)
1361 +#define RG_SSUSB_CDR_ACCEN_OFST (8)
1362 +#define RG_SSUSB_CDR_BYPASS_OFST (6)
1363 +#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
1364 +#define RG_SSUSB_CDR_EPEN_OFST (3)
1365 +#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
1366 +#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
1367 +#define RG_SSUSB_CDR_MONEN_OFST (0)
1370 +#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
1371 +#define RG_SSUSB_CDR_REGOD_OFST (29)
1372 +#define RG_SSUSB_RX_DAC_EN_OFST (26)
1373 +#define RG_SSUSB_RX_DAC_PWD_OFST (25)
1374 +#define RG_SSUSB_EQ_CURSEL_OFST (24)
1375 +#define RG_SSUSB_RX_DAC_MUX_OFST (19)
1376 +#define RG_SSUSB_RX_R2T_EN_OFST (18)
1377 +#define RG_SSUSB_RX_T2R_EN_OFST (17)
1378 +#define RG_SSUSB_RX_50_LOWER_OFST (14)
1379 +#define RG_SSUSB_RX_50_TAR_OFST (12)
1380 +#define RG_SSUSB_RX_SW_CTRL_OFST (7)
1381 +#define RG_PCIE_SIGDET_VTH_OFST (5)
1382 +#define RG_PCIE_SIGDET_LPF_OFST (3)
1383 +#define RG_SSUSB_LFPS_MON_EN_OFST (2)
1386 +#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
1387 +#define RG_SSUSB_CDR_RESERVE_OFST (16)
1388 +#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
1389 +#define RG_PCIE_RX_RESERVE_OFST (0)
1392 +#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
1393 +#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
1396 +#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
1397 +#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
1398 +#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
1399 +#define RG_SSUSB_RX_PD_RST_OFST (1)
1400 +#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
1402 +///////////////////////////////////////////////////////////////////////////////
1404 +struct u3phya_da_reg {
1441 +#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
1442 +#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
1443 +#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
1444 +#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
1445 +#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
1446 +#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
1447 +#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
1448 +#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
1449 +#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
1450 +#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
1451 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
1452 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
1453 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
1454 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
1455 +#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
1458 +#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
1459 +#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
1460 +#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
1461 +#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
1462 +#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
1463 +#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
1464 +#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
1465 +#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
1466 +#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
1467 +#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
1468 +#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
1469 +#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
1470 +#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
1471 +#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
1472 +#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
1475 +#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
1476 +#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
1477 +#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
1478 +#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
1479 +#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
1480 +#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
1481 +#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
1482 +#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
1483 +#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
1484 +#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
1487 +#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
1488 +#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
1489 +#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
1490 +#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
1491 +#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
1492 +#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
1493 +#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
1494 +#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
1495 +#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
1496 +#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
1499 +#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
1500 +#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
1501 +#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
1502 +#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
1503 +#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
1506 +#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
1507 +#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
1508 +#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
1509 +#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
1510 +#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
1513 +#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
1514 +#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
1515 +#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
1516 +#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
1517 +#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
1520 +#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
1521 +#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
1522 +#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
1523 +#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
1526 +#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
1527 +#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
1528 +#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
1529 +#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
1530 +#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
1531 +#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
1534 +#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
1537 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
1540 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
1543 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
1546 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
1549 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
1550 +#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
1553 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
1554 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
1557 +#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
1558 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
1561 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
1562 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
1565 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
1566 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
1569 +#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
1570 +#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
1571 +#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
1572 +#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
1573 +#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
1576 +#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
1577 +#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
1578 +#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
1579 +#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
1580 +#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
1583 +#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
1584 +#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
1585 +#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
1586 +#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
1587 +#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
1590 +#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
1591 +#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
1592 +#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
1593 +#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
1594 +#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
1597 +#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
1598 +#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
1599 +#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
1600 +#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
1603 +#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
1604 +#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
1605 +#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
1606 +#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
1607 +#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
1608 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
1609 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
1610 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
1611 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
1612 +#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
1613 +#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
1614 +#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
1615 +#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
1616 +#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
1617 +#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
1618 +#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
1621 +#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
1622 +#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
1623 +#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
1624 +#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
1625 +#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
1626 +#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
1627 +#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
1628 +#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
1629 +#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
1630 +#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
1636 +#define RG_PCIE_SPEED_PE2D_OFST (24)
1637 +#define RG_PCIE_SPEED_PE2H_OFST (23)
1638 +#define RG_PCIE_SPEED_PE1D_OFST (22)
1639 +#define RG_PCIE_SPEED_PE1H_OFST (21)
1640 +#define RG_PCIE_SPEED_U3_OFST (20)
1641 +#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
1642 +#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
1643 +#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
1644 +#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
1645 +#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
1646 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
1647 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
1648 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
1649 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
1650 +#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
1653 +#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
1654 +#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
1655 +#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
1656 +#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
1657 +#define RG_USB20_REFCK_SEL_U3_OFST (26)
1658 +#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
1659 +#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
1660 +#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
1661 +#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
1662 +#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
1663 +#define RG_PCIE_MODE_PE2D_OFST (8)
1664 +#define RG_PCIE_MODE_PE2H_OFST (3)
1665 +#define RG_PCIE_MODE_PE1D_OFST (2)
1666 +#define RG_PCIE_MODE_PE1H_OFST (1)
1667 +#define RG_PCIE_MODE_U3_OFST (0)
1670 +#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
1671 +#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
1672 +#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
1673 +#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
1674 +#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
1675 +#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
1676 +#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
1677 +#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
1678 +#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
1679 +#define RG_SSUSB_PLL_BC_U3_OFST (0)
1682 +#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
1683 +#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
1684 +#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
1685 +#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
1686 +#define RG_SSUSB_PLL_BR_U3_OFST (15)
1687 +#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
1688 +#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
1689 +#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
1690 +#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
1691 +#define RG_SSUSB_PLL_IC_U3_OFST (0)
1694 +#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
1695 +#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
1696 +#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
1697 +#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
1698 +#define RG_SSUSB_PLL_IR_U3_OFST (0)
1701 +#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
1702 +#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
1703 +#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
1704 +#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
1705 +#define RG_SSUSB_PLL_BP_U3_OFST (0)
1708 +#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
1709 +#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
1710 +#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
1711 +#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
1712 +#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
1715 +#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
1716 +#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
1717 +#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
1718 +#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
1721 +#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
1722 +#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
1723 +#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
1724 +#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
1725 +#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
1726 +#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
1729 +#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
1732 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
1735 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
1738 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
1741 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
1744 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
1745 +#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
1748 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
1749 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
1752 +#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
1753 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
1756 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
1757 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
1760 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
1761 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
1764 +#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
1765 +#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
1766 +#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
1767 +#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
1768 +#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
1771 +#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
1772 +#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
1773 +#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
1774 +#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
1775 +#define RG_SSUSB_CDR_BPA_U3_OFST (0)
1778 +#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
1779 +#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
1780 +#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
1781 +#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
1782 +#define RG_SSUSB_CDR_BPB_U3_OFST (0)
1785 +#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
1786 +#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
1787 +#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
1788 +#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
1789 +#define RG_SSUSB_CDR_BR_U3_OFST (0)
1792 +#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
1793 +#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
1794 +#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
1795 +#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
1798 +#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
1799 +#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
1800 +#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
1801 +#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
1802 +#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
1803 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
1804 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
1805 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
1806 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
1807 +#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
1808 +#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
1809 +#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
1810 +#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
1811 +#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
1812 +#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
1813 +#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
1816 +#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
1817 +#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
1818 +#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
1819 +#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
1820 +#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
1821 +#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
1822 +#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
1823 +#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
1824 +#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
1825 +#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
1828 +///////////////////////////////////////////////////////////////////////////////
1830 +struct u3phyd_reg {
1832 + PHY_LE32 phyd_mix0;
1833 + PHY_LE32 phyd_mix1;
1834 + PHY_LE32 phyd_lfps0;
1835 + PHY_LE32 phyd_lfps1;
1837 + PHY_LE32 phyd_impcal0;
1838 + PHY_LE32 phyd_impcal1;
1839 + PHY_LE32 phyd_txpll0;
1840 + PHY_LE32 phyd_txpll1;
1842 + PHY_LE32 phyd_txpll2;
1843 + PHY_LE32 phyd_fl0;
1844 + PHY_LE32 phyd_mix2;
1845 + PHY_LE32 phyd_rx0;
1847 + PHY_LE32 phyd_t2rlb;
1848 + PHY_LE32 phyd_cppat;
1849 + PHY_LE32 phyd_mix3;
1850 + PHY_LE32 phyd_ebufctl;
1852 + PHY_LE32 phyd_pipe0;
1853 + PHY_LE32 phyd_pipe1;
1854 + PHY_LE32 phyd_mix4;
1855 + PHY_LE32 phyd_ckgen0;
1857 + PHY_LE32 phyd_mix5;
1858 + PHY_LE32 phyd_reserved;
1859 + PHY_LE32 phyd_cdr0;
1860 + PHY_LE32 phyd_cdr1;
1862 + PHY_LE32 phyd_pll_0;
1863 + PHY_LE32 phyd_pll_1;
1864 + PHY_LE32 phyd_bcn_det_1;
1865 + PHY_LE32 phyd_bcn_det_2;
1880 + PHY_LE32 reserve0;
1882 + PHY_LE32 phyd_mon0;
1883 + PHY_LE32 phyd_mon1;
1884 + PHY_LE32 phyd_mon2;
1885 + PHY_LE32 phyd_mon3;
1887 + PHY_LE32 phyd_mon4;
1888 + PHY_LE32 phyd_mon5;
1889 + PHY_LE32 phyd_mon6;
1890 + PHY_LE32 phyd_mon7;
1892 + PHY_LE32 phya_rx_mon0;
1893 + PHY_LE32 phya_rx_mon1;
1894 + PHY_LE32 phya_rx_mon2;
1895 + PHY_LE32 phya_rx_mon3;
1897 + PHY_LE32 phya_rx_mon4;
1898 + PHY_LE32 phya_rx_mon5;
1899 + PHY_LE32 phyd_cppat2;
1902 + PHY_LE32 kband_out;
1903 + PHY_LE32 kband_out1;
1907 +#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
1908 +#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
1909 +#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
1910 +#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
1911 +#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
1912 +#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
1913 +#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
1914 +#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
1915 +#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
1916 +#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
1917 +#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
1918 +#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
1919 +#define RG_SSUSB_COMCNT (0xf<<4) //7:4
1920 +#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
1923 +#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
1924 +#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
1925 +#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
1926 +#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
1927 +#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
1928 +#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
1929 +#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
1930 +#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
1931 +#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
1932 +#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
1933 +#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
1934 +#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
1935 +#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
1938 +#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
1939 +#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
1940 +#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
1941 +#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
1942 +#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
1943 +#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
1944 +#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
1945 +#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
1946 +#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
1947 +#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
1948 +#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
1949 +#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
1950 +#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
1951 +#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
1952 +#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
1955 +#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
1956 +#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
1957 +#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
1958 +#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
1959 +#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
1962 +#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
1963 +#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
1964 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
1965 +#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
1966 +#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
1967 +#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
1968 +#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1971 +#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
1972 +#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
1973 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
1974 +#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
1975 +#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
1976 +#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
1977 +#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
1980 +#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
1981 +#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
1982 +#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
1983 +#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
1984 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
1985 +#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
1986 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
1989 +#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
1990 +#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
1991 +#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
1992 +#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
1993 +#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
1994 +#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
1995 +#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
1996 +#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
1997 +#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
1998 +#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
1999 +#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
2000 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
2001 +#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
2002 +#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
2003 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
2004 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
2005 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
2006 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
2007 +#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
2008 +#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
2009 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
2010 +#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
2011 +#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
2014 +#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
2015 +#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
2016 +#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
2017 +#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
2018 +#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
2019 +#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
2020 +#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
2021 +#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
2022 +#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
2023 +#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
2024 +#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
2025 +#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
2026 +#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
2027 +#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
2028 +#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
2029 +#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
2032 +#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
2033 +#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
2036 +#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
2037 +#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
2038 +#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
2039 +#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
2040 +#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
2041 +#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
2042 +#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
2043 +#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
2046 +#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
2047 +#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
2048 +#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
2049 +#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
2050 +#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
2051 +#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
2052 +#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
2053 +#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
2054 +#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
2055 +#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
2056 +#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
2057 +#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
2058 +#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
2059 +#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
2060 +#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
2061 +#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
2062 +#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
2065 +#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
2066 +#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
2067 +#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
2068 +#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
2069 +#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
2070 +#define RG_SSUSB_K_EMP (0xf<<20) //23:20
2071 +#define RG_SSUSB_K_FUL (0xf<<16) //19:16
2072 +#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
2073 +#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
2074 +#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
2075 +#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
2078 +#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
2079 +#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
2080 +#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
2081 +#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
2082 +#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
2083 +#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
2086 +#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
2087 +#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
2088 +#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
2089 +#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
2090 +#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
2091 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
2092 +#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
2093 +#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
2094 +#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
2095 +#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
2096 +#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
2097 +#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
2098 +#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
2099 +#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
2102 +#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
2105 +#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
2106 +#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
2107 +#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
2108 +#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
2109 +#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
2110 +#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
2111 +#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
2112 +#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
2113 +#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
2114 +#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
2115 +#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
2116 +#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
2117 +#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
2118 +#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
2119 +#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
2120 +#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
2121 +#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
2124 +#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
2127 +#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
2128 +#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
2129 +#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
2132 +#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
2133 +#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
2134 +#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
2135 +#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
2138 +#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
2139 +#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
2141 +//U3D_PHYD_RESERVED
2142 +#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
2143 +//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
2144 +//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
2145 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
2146 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
2149 +#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
2150 +#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
2151 +#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
2152 +#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
2153 +#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
2156 +#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
2157 +#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
2158 +#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
2159 +#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
2160 +#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
2163 +#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
2164 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
2165 +#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
2166 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
2167 +#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
2168 +#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
2169 +#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
2170 +#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
2171 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
2172 +#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
2173 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
2176 +#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2177 +#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2178 +#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2179 +#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2181 +//U3D_PHYD_BCN_DET_1
2182 +#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
2183 +#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
2185 +//U3D_PHYD_BCN_DET_2
2186 +#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
2187 +#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
2188 +#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
2191 +#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
2192 +#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
2193 +#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
2194 +#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
2197 +#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
2198 +#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
2199 +#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
2200 +#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
2203 +#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
2204 +#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
2205 +#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
2206 +#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
2207 +#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
2208 +#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
2209 +#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
2210 +#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
2213 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
2214 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
2215 +#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
2216 +#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
2217 +#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
2218 +#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
2221 +#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
2222 +#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
2223 +#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
2224 +#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
2225 +#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
2226 +#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
2227 +#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
2230 +#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
2231 +#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
2234 +#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
2235 +#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
2236 +#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
2237 +#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
2240 +#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
2241 +#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
2242 +#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
2243 +#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
2244 +#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
2245 +#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
2246 +#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
2249 +#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
2250 +#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
2251 +#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
2252 +#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
2253 +#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
2254 +#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
2255 +#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
2256 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
2257 +#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
2260 +#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
2261 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
2262 +#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
2263 +#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
2266 +#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
2269 +#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
2270 +#define RGS_SSUSB_LFPS (0xf<<12) //15:12
2271 +#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
2272 +#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
2275 +#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
2278 +#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
2279 +#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
2280 +#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
2281 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
2282 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
2283 +#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
2286 +#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
2287 +#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
2290 +#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
2291 +#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
2292 +#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
2295 +#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
2296 +#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
2297 +#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
2298 +#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
2299 +#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
2300 +#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
2301 +#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
2302 +#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
2303 +#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
2304 +#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
2305 +#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
2306 +#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
2307 +#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
2308 +#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
2309 +#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
2310 +#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
2313 +#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
2314 +#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
2315 +#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
2316 +#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
2317 +#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
2318 +#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
2319 +#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
2322 +#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
2323 +#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
2326 +#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
2327 +#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
2328 +#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
2329 +#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
2332 +#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
2333 +#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
2334 +#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
2335 +#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
2338 +#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
2339 +#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
2340 +#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
2341 +#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
2342 +#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
2345 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
2348 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
2351 +#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
2352 +#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
2353 +#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
2356 +#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
2357 +#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
2358 +#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
2361 +#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
2362 +#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
2365 +#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
2366 +#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
2367 +#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
2368 +#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
2371 +#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
2372 +#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
2373 +#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
2374 +#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
2380 +#define RG_SSUSB_P_P3_TX_NG_OFST (31)
2381 +#define RG_SSUSB_TSEQ_EN_OFST (30)
2382 +#define RG_SSUSB_TSEQ_POLEN_OFST (29)
2383 +#define RG_SSUSB_TSEQ_POL_OFST (28)
2384 +#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
2385 +#define RG_SSUSB_TSEQ_TH_OFST (24)
2386 +#define RG_SSUSB_PRBS_BERTH_OFST (16)
2387 +#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
2388 +#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
2389 +#define RG_SSUSB_PRBS_EN_OFST (13)
2390 +#define RG_SSUSB_BPSLOCK_OFST (12)
2391 +#define RG_SSUSB_RTCOMCNT_OFST (8)
2392 +#define RG_SSUSB_COMCNT_OFST (4)
2393 +#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
2396 +#define RG_SSUSB_SLEEP_EN_OFST (31)
2397 +#define RG_SSUSB_PRBSEL_PCS_OFST (28)
2398 +#define RG_SSUSB_TXLFPS_PRD_OFST (24)
2399 +#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
2400 +#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
2401 +#define RG_SSUSB_PDNCTL_OFST (16)
2402 +#define RG_SSUSB_TX_DRV_EN_OFST (15)
2403 +#define RG_SSUSB_TX_DRV_SEL_OFST (14)
2404 +#define RG_SSUSB_TX_DRV_DLY_OFST (8)
2405 +#define RG_SSUSB_BERT_EN_OFST (7)
2406 +#define RG_SSUSB_SCP_TH_OFST (4)
2407 +#define RG_SSUSB_SCP_EN_OFST (3)
2408 +#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
2411 +#define RG_SSUSB_LFPS_PWD_OFST (30)
2412 +#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
2413 +#define RG_SSUSB_RXLFPS_OVF_OFST (24)
2414 +#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
2415 +#define RG_SSUSB_P3_ENTRY_OFST (22)
2416 +#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
2417 +#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
2418 +#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
2419 +#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
2420 +#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
2421 +#define RG_SSUSB_RXLFPS_LOB_OFST (8)
2422 +#define RG_SSUSB_TXLFPS_EN_OFST (7)
2423 +#define RG_SSUSB_TXLFPS_SEL_OFST (6)
2424 +#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
2425 +#define RG_SSUSB_RXLFPS_UPB_OFST (0)
2428 +#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
2429 +#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
2430 +#define RG_SSUSB_FWAKE_TH_OFST (16)
2431 +#define RG_SSUSB_RXLFPS_UDF_OFST (8)
2432 +#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
2435 +#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
2436 +#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
2437 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
2438 +#define RG_SSUSB_TX_IMPSEL_OFST (24)
2439 +#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
2440 +#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
2441 +#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
2444 +#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
2445 +#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
2446 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
2447 +#define RG_SSUSB_RX_IMPSEL_OFST (24)
2448 +#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
2449 +#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
2450 +#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
2453 +#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
2454 +#define RG_SSUSB_TXPLL_ON_OFST (26)
2455 +#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
2456 +#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
2457 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
2458 +#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
2459 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
2462 +#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
2463 +#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
2464 +#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
2465 +#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
2466 +#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
2467 +#define RG_SSUSB_PLL_DDSEN_OFST (25)
2468 +#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
2469 +#define RG_SSUSB_PLL_PWD_OFST (23)
2470 +#define RG_SSUSB_RX_AFE_PWD_OFST (22)
2471 +#define RG_SSUSB_PLL_TCADJ_OFST (16)
2472 +#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
2473 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
2474 +#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
2475 +#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
2476 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
2477 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
2478 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
2479 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
2480 +#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
2481 +#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
2482 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
2483 +#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
2484 +#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
2487 +#define RG_SSUSB_TX_LFPS_EN_OFST (31)
2488 +#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
2489 +#define RG_SSUSB_TX_LFPS_OFST (29)
2490 +#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
2491 +#define RG_SSUSB_RXPLL_STB_OFST (27)
2492 +#define RG_SSUSB_TXPLL_STB_OFST (26)
2493 +#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
2494 +#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
2495 +#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
2496 +#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
2497 +#define RG_SSUSB_RXPLL_ON_OFST (10)
2498 +#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
2499 +#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
2500 +#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
2501 +#define RG_SSUSB_CDR_PWD_OFST (6)
2502 +#define RG_SSUSB_CDR_TCADJ_OFST (0)
2505 +#define RG_SSUSB_RX_FL_TARGET_OFST (16)
2506 +#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
2509 +#define RG_SSUSB_RX_EQ_RST_OFST (31)
2510 +#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
2511 +#define RG_SSUSB_RXVAL_RST_OFST (29)
2512 +#define RG_SSUSB_RXVAL_CNT_OFST (24)
2513 +#define RG_SSUSB_CDROS_EN_OFST (18)
2514 +#define RG_SSUSB_CDR_LCKOP_OFST (16)
2515 +#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
2516 +#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
2519 +#define RG_SSUSB_T2RLB_BERTH_OFST (24)
2520 +#define RG_SSUSB_T2RLB_PAT_OFST (16)
2521 +#define RG_SSUSB_T2RLB_EN_OFST (15)
2522 +#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
2523 +#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
2524 +#define RG_SSUSB_T2RLB_MODE_OFST (11)
2525 +#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
2526 +#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
2527 +#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
2528 +#define RG_SSUSB_RX_DFE_EN_OFST (7)
2529 +#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
2530 +#define RG_SSUSB_RX_EQ_EN_OFST (5)
2531 +#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
2532 +#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
2533 +#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
2534 +#define RG_SSUSB_RX_DFE_RST_OFST (1)
2535 +#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
2538 +#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
2539 +#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
2540 +#define RG_SSUSB_BPANSIENC_OFST (26)
2541 +#define RG_SSUSB_VALID_EN_OFST (25)
2542 +#define RG_SSUSB_EBUF_SRST_OFST (24)
2543 +#define RG_SSUSB_K_EMP_OFST (20)
2544 +#define RG_SSUSB_K_FUL_OFST (16)
2545 +#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
2546 +#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
2547 +#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
2548 +#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
2551 +#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
2552 +#define RG_SSUSB_CPPAT_TOZ_OFST (21)
2553 +#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
2554 +#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
2555 +#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
2556 +#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
2559 +#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
2560 +#define RG_SSUSB_P_CDROS_EN_OFST (30)
2561 +#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
2562 +#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
2563 +#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
2564 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
2565 +#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
2566 +#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
2567 +#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
2568 +#define RG_SSUSB_PLL_SSCEN_OFST (14)
2569 +#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
2570 +#define RG_SSUSB_CDR_PI_PWD_OFST (12)
2571 +#define RG_SSUSB_CDR_PI_MODE_OFST (11)
2572 +#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
2575 +#define RG_SSUSB_EBUFCTL_OFST (0)
2578 +#define RG_SSUSB_RXTERMINATION_OFST (30)
2579 +#define RG_SSUSB_RXEQTRAINING_OFST (29)
2580 +#define RG_SSUSB_RXPOLARITY_OFST (28)
2581 +#define RG_SSUSB_TXDEEMPH_OFST (26)
2582 +#define RG_SSUSB_POWERDOWN_OFST (24)
2583 +#define RG_SSUSB_TXONESZEROS_OFST (23)
2584 +#define RG_SSUSB_TXELECIDLE_OFST (22)
2585 +#define RG_SSUSB_TXDETECTRX_OFST (21)
2586 +#define RG_SSUSB_PIPE_SEL_OFST (20)
2587 +#define RG_SSUSB_TXDATAK_OFST (16)
2588 +#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
2589 +#define RG_SSUSB_CDR_STABLE_OFST (14)
2590 +#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
2591 +#define RG_SSUSB_CDR_RSTB_OFST (12)
2592 +#define RG_SSUSB_P_ERROR_SEL_OFST (4)
2593 +#define RG_SSUSB_TXMARGIN_OFST (1)
2594 +#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
2597 +#define RG_SSUSB_TXDATA_OFST (0)
2600 +#define RG_SSUSB_CDROS_CNT_OFST (24)
2601 +#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
2602 +#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
2605 +#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
2606 +#define RG_SSUSB_TFIFO_PSEL_OFST (24)
2607 +#define RG_SSUSB_CKGEN_PSEL_OFST (8)
2608 +#define RG_SSUSB_RXCK_INV_OFST (0)
2611 +#define RG_SSUSB_PRB_SEL_OFST (16)
2612 +#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
2614 +//U3D_PHYD_RESERVED
2615 +#define RG_SSUSB_PHYD_RESERVE_OFST (0)
2616 +//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
2617 +//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
2618 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
2619 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
2622 +#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
2623 +#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
2624 +#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
2625 +#define RG_SSUSB_CDR_BC_LTR_OFST (8)
2626 +#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
2629 +#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
2630 +#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
2631 +#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
2632 +#define RG_SSUSB_CDR_BW_SEL_OFST (6)
2633 +#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
2636 +#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
2637 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
2638 +#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
2639 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
2640 +#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
2641 +#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
2642 +#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
2643 +#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
2644 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
2645 +#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
2646 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
2649 +#define RG_SSUSB_CDR_BAND_5G_OFST (24)
2650 +#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
2651 +#define RG_SSUSB_PLL_BAND_5G_OFST (8)
2652 +#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
2654 +//U3D_PHYD_BCN_DET_1
2655 +#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
2656 +#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
2658 +//U3D_PHYD_BCN_DET_2
2659 +#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
2660 +#define RG_SSUSB_BCN_DET_DIS_OFST (12)
2661 +#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
2664 +#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
2665 +#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
2666 +#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
2667 +#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
2670 +#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
2671 +#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
2672 +#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
2673 +#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
2676 +#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
2677 +#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
2678 +#define RG_SSUSB_EQ_STOPTIME_OFST (14)
2679 +#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
2680 +#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
2681 +#define RG_SSUSB_EQ_STARTTIME_OFST (6)
2682 +#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
2683 +#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
2686 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
2687 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
2688 +#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
2689 +#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
2690 +#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
2691 +#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
2694 +#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
2695 +#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
2696 +#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
2697 +#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
2698 +#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
2699 +#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
2700 +#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
2703 +#define RG_SSUSB_EQ_SIGDET_OFST (24)
2704 +#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
2707 +#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
2708 +#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
2709 +#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
2710 +#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
2713 +#define RG_SSUSB_EQ_LEQMAX_OFST (28)
2714 +#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
2715 +#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
2716 +#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
2717 +#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
2718 +#define RG_SSUSB_EQ_PI90_INI_OFST (8)
2719 +#define RG_SSUSB_EQ_PI0_INI_OFST (0)
2722 +#define RG_SSUSB_EQ_REV_OFST (16)
2723 +#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
2724 +#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
2725 +#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
2726 +#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
2727 +#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
2728 +#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
2729 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
2730 +#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
2733 +#define RG_SSUSB_EQ_MON_SEL_OFST (24)
2734 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
2735 +#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
2736 +#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
2739 +#define RG_SSUSB_EQ_RESERVED_OFST (0)
2742 +#define RGS_SSUSB_BERT_BERC_OFST (16)
2743 +#define RGS_SSUSB_LFPS_OFST (12)
2744 +#define RGS_SSUSB_TRAINDEC_OFST (8)
2745 +#define RGS_SSUSB_SCP_PAT_OFST (0)
2748 +#define RGS_SSUSB_RX_FL_OUT_OFST (0)
2751 +#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
2752 +#define RGS_SSUSB_RETRACK_OFST (12)
2753 +#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
2754 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
2755 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
2756 +#define RGS_SSUSB_PDNCTL_OFST (0)
2759 +#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
2760 +#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
2763 +#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
2764 +#define RGS_SSUSB_SCP_DETCNT_OFST (16)
2765 +#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
2768 +#define RGS_SSUSB_EBUFMSG_OFST (16)
2769 +#define RGS_SSUSB_BERT_LOCK_OFST (15)
2770 +#define RGS_SSUSB_SCP_DET_OFST (14)
2771 +#define RGS_SSUSB_TSEQ_DET_OFST (13)
2772 +#define RGS_SSUSB_EBUF_UDF_OFST (12)
2773 +#define RGS_SSUSB_EBUF_OVF_OFST (11)
2774 +#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
2775 +#define RGS_SSUSB_PRBS_PASS_OFST (9)
2776 +#define RGS_SSUSB_PRBS_LOCK_OFST (8)
2777 +#define RGS_SSUSB_T2RLB_ERR_OFST (6)
2778 +#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
2779 +#define RGS_SSUSB_T2RLB_PASS_OFST (4)
2780 +#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
2781 +#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
2782 +#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
2783 +#define RGS_SSUSB_RXDETECTED_OFST (0)
2786 +#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
2787 +#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
2788 +#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
2789 +#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
2790 +#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
2791 +#define RGS_SSUSB_TFIFO_MSG_OFST (4)
2792 +#define RGS_SSUSB_RFIFO_MSG_OFST (0)
2795 +#define RGS_SSUSB_FT_OUT_OFST (8)
2796 +#define RGS_SSUSB_PRB_OUT_OFST (0)
2799 +#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
2800 +#define RGS_SSUSB_EQ_DCD0H_OFST (16)
2801 +#define RGS_SSUSB_EQ_DCD0L_OFST (8)
2802 +#define RGS_SSUSB_EQ_DCD1H_OFST (0)
2805 +#define RGS_SSUSB_EQ_DCD1L_OFST (24)
2806 +#define RGS_SSUSB_EQ_DCE0_OFST (16)
2807 +#define RGS_SSUSB_EQ_DCE1_OFST (8)
2808 +#define RGS_SSUSB_EQ_DCHHL_OFST (0)
2811 +#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
2812 +#define RGS_SSUSB_EQ_DCLHL_OFST (24)
2813 +#define RGS_SSUSB_EQ_STATUS_OFST (16)
2814 +#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
2815 +#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
2818 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
2821 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
2824 +#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
2825 +#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
2826 +#define RGS_SSUSB_EQ_PILPO_OFST (0)
2829 +#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
2830 +#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
2831 +#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
2834 +#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
2835 +#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
2838 +#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
2839 +#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
2840 +#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
2841 +#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
2844 +#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
2845 +#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
2846 +#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
2847 +#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
2850 +///////////////////////////////////////////////////////////////////////////////
2852 +struct u3phyd_bank2_reg {
2854 + PHY_LE32 b2_phyd_top1;
2855 + PHY_LE32 b2_phyd_top2;
2856 + PHY_LE32 b2_phyd_top3;
2857 + PHY_LE32 b2_phyd_top4;
2859 + PHY_LE32 b2_phyd_top5;
2860 + PHY_LE32 b2_phyd_top6;
2861 + PHY_LE32 b2_phyd_top7;
2862 + PHY_LE32 b2_phyd_p_sigdet1;
2864 + PHY_LE32 b2_phyd_p_sigdet2;
2865 + PHY_LE32 b2_phyd_p_sigdet_cal1;
2866 + PHY_LE32 b2_phyd_rxdet1;
2867 + PHY_LE32 b2_phyd_rxdet2;
2869 + PHY_LE32 b2_phyd_misc0;
2870 + PHY_LE32 b2_phyd_misc2;
2871 + PHY_LE32 b2_phyd_misc3;
2872 + PHY_LE32 reserve0;
2874 + PHY_LE32 b2_rosc_0;
2875 + PHY_LE32 b2_rosc_1;
2876 + PHY_LE32 b2_rosc_2;
2877 + PHY_LE32 b2_rosc_3;
2879 + PHY_LE32 b2_rosc_4;
2880 + PHY_LE32 b2_rosc_5;
2881 + PHY_LE32 b2_rosc_6;
2882 + PHY_LE32 b2_rosc_7;
2884 + PHY_LE32 b2_rosc_8;
2885 + PHY_LE32 b2_rosc_9;
2886 + PHY_LE32 b2_rosc_a;
2887 + PHY_LE32 reserve1;
2889 + PHY_LE32 reserve2[28];
2891 + PHY_LE32 phyd_version;
2892 + PHY_LE32 phyd_model;
2896 +#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
2897 +#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
2898 +#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
2899 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
2900 +#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
2901 +#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
2902 +#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
2903 +#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
2904 +#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
2905 +#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
2906 +#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
2907 +#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
2908 +#define RG_SSUSB_RATE (0x1<<6) //6:6
2909 +#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
2910 +#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
2911 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
2912 +#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
2913 +#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
2916 +#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
2917 +#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
2918 +#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
2919 +#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
2920 +#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
2921 +#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
2922 +#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
2923 +#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
2926 +#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
2927 +#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
2928 +#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
2929 +#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
2930 +#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
2931 +#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
2934 +#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
2935 +#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
2936 +#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
2937 +#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
2938 +#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
2941 +#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
2942 +#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
2943 +#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
2944 +#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
2947 +#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
2948 +#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
2949 +#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
2950 +#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
2951 +#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
2954 +#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
2955 +#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
2956 +#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
2957 +#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
2959 +//U3D_B2_PHYD_P_SIGDET1
2960 +#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
2961 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
2962 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
2963 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
2964 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
2966 +//U3D_B2_PHYD_P_SIGDET2
2967 +#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
2968 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
2969 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
2970 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
2971 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
2972 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
2973 +#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
2974 +#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
2975 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
2976 +#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
2977 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
2978 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
2979 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
2981 +//U3D_B2_PHYD_P_SIGDET_CAL1
2982 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
2983 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
2984 +#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
2985 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
2986 +#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
2987 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
2988 +#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
2990 +//U3D_B2_PHYD_RXDET1
2991 +#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
2992 +#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
2993 +#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
2994 +#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
2995 +#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
2996 +#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
2997 +#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
2998 +#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
3000 +//U3D_B2_PHYD_RXDET2
3001 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
3002 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
3003 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
3004 +#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
3005 +#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
3006 +#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
3008 +//U3D_B2_PHYD_MISC0
3009 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
3010 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
3011 +#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
3012 +#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
3013 +#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
3014 +#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
3015 +#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
3016 +#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
3017 +#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
3018 +#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
3019 +#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
3020 +#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
3021 +#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
3022 +#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
3023 +#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
3024 +#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
3026 +//U3D_B2_PHYD_MISC2
3027 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
3028 +#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
3029 +#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
3030 +#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
3031 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
3032 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
3033 +#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
3034 +#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
3035 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
3036 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
3037 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
3039 +//U3D_B2_PHYD_MISC3
3040 +#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
3041 +#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
3044 +#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
3045 +#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
3046 +#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
3047 +#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
3048 +#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
3049 +#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
3052 +#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
3053 +#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
3054 +#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
3055 +#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
3056 +#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
3057 +#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
3060 +#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
3061 +#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
3064 +#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
3065 +#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
3068 +#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
3069 +#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
3072 +#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
3073 +#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
3076 +#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
3077 +#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
3080 +#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
3081 +#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
3084 +#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
3085 +#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
3086 +#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
3087 +#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
3090 +#define RGS_FM_RING_CNT (0xffff<<16) //31:16
3091 +#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
3092 +#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
3093 +#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
3094 +#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
3097 +#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
3100 +#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
3103 +#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
3109 +#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
3110 +#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
3111 +#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
3112 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
3113 +#define RG_SSUSB_SIGDET_EN_OFST (15)
3114 +#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
3115 +#define RG_SSUSB_CLKRX_EN_OFST (13)
3116 +#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
3117 +#define RG_SSUSB_CLKTX_EN_OFST (11)
3118 +#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
3119 +#define RG_SSUSB_CLK_REQ_N_I_OFST (9)
3120 +#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
3121 +#define RG_SSUSB_RATE_OFST (6)
3122 +#define RG_SSUSB_FORCE_RATE_OFST (5)
3123 +#define RG_SSUSB_PCIE_MODE_SEL_OFST (4)
3124 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
3125 +#define RG_SSUSB_PHY_MODE_OFST (1)
3126 +#define RG_SSUSB_FORCE_PHY_MODE_OFST (0)
3129 +#define RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
3130 +#define RG_SSUSB_IDRV_6DB_OFST (24)
3131 +#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
3132 +#define RG_SSUSB_IDEM_3P5DB_OFST (16)
3133 +#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
3134 +#define RG_SSUSB_IDRV_3P5DB_OFST (8)
3135 +#define RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
3136 +#define RG_SSUSB_IDRV_0DB_OFST (0)
3139 +#define RG_SSUSB_TX_BIASI_OFST (25)
3140 +#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
3141 +#define RG_SSUSB_TX_BIASI_EN_OFST (16)
3142 +#define RG_SSUSB_FORCE_TX_BIASI_OFST (13)
3143 +#define RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
3144 +#define RG_SSUSB_IDEM_6DB_OFST (0)
3147 +#define RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
3148 +#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
3149 +#define RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
3150 +#define RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
3151 +#define RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
3154 +#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
3155 +#define RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
3156 +#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
3157 +#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
3160 +#define RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
3161 +#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
3162 +#define RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
3163 +#define RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
3164 +#define RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
3167 +#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
3168 +#define RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
3169 +#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
3170 +#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
3172 +//U3D_B2_PHYD_P_SIGDET1
3173 +#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
3174 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
3175 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
3176 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
3177 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
3179 +//U3D_B2_PHYD_P_SIGDET2
3180 +#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
3181 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
3182 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
3183 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
3184 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
3185 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
3186 +#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
3187 +#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
3188 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
3189 +#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
3190 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
3191 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
3192 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
3194 +//U3D_B2_PHYD_P_SIGDET_CAL1
3195 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
3196 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
3197 +#define RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
3198 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
3199 +#define RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
3200 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
3201 +#define RG_SSUSB_P_SIGDET_REK_OFST (0)
3203 +//U3D_B2_PHYD_RXDET1
3204 +#define RG_SSUSB_RXDET_PRB_SEL_OFST (31)
3205 +#define RG_SSUSB_FORCE_CMDET_OFST (30)
3206 +#define RG_SSUSB_RXDET_EN_OFST (29)
3207 +#define RG_SSUSB_FORCE_RXDET_EN_OFST (28)
3208 +#define RG_SSUSB_RXDET_K_TWICE_OFST (27)
3209 +#define RG_SSUSB_RXDET_STB3_SET_OFST (18)
3210 +#define RG_SSUSB_RXDET_STB2_SET_OFST (9)
3211 +#define RG_SSUSB_RXDET_STB1_SET_OFST (0)
3213 +//U3D_B2_PHYD_RXDET2
3214 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
3215 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
3216 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
3217 +#define RG_SSUSB_PDN_T_SEL_OFST (18)
3218 +#define RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
3219 +#define RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
3221 +//U3D_B2_PHYD_MISC0
3222 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
3223 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
3224 +#define RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
3225 +#define RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
3226 +#define RG_SSUSB_LFPS_PSEL_OFST (15)
3227 +#define RG_SSUSB_RX_SIGDET_EN_OFST (14)
3228 +#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
3229 +#define RG_SSUSB_RX_PI_CAL_EN_OFST (12)
3230 +#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
3231 +#define RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
3232 +#define RG_SSUSB_T2RLB_PSEL_OFST (8)
3233 +#define RG_SSUSB_PPCTL_PSEL_OFST (5)
3234 +#define RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
3235 +#define RG_SSUSB_BERTLB_PSEL_OFST (2)
3236 +#define RG_SSUSB_RETRACK_DIS_OFST (1)
3237 +#define RG_SSUSB_PPERRCNT_CLR_OFST (0)
3239 +//U3D_B2_PHYD_MISC2
3240 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
3241 +#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
3242 +#define RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
3243 +#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
3244 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
3245 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
3246 +#define RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
3247 +#define RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
3248 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
3249 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
3250 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
3252 +//U3D_B2_PHYD_MISC3
3253 +#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
3254 +#define RGS_SSUSB_PPERRCNT_OFST (0)
3257 +#define RG_SSUSB_RING_OSC_CNTEND_OFST (23)
3258 +#define RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
3259 +#define RG_SSUSB_RING_OSC_EN_OFST (3)
3260 +#define RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
3261 +#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
3262 +#define RG_SSUSB_RING_BYPASS_DET_OFST (0)
3265 +#define RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
3266 +#define RG_SSUSB_RING_OSC_P3_OFST (19)
3267 +#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
3268 +#define RG_SSUSB_RING_OSC_RECAL_OFST (16)
3269 +#define RG_SSUSB_RING_OSC_SEL_OFST (8)
3270 +#define RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
3273 +#define RG_SSUSB_RING_DET_STRCYC2_OFST (16)
3274 +#define RG_SSUSB_RING_DET_STRCYC1_OFST (0)
3277 +#define RG_SSUSB_RING_DET_DETWIN1_OFST (16)
3278 +#define RG_SSUSB_RING_DET_STRCYC3_OFST (0)
3281 +#define RG_SSUSB_RING_DET_DETWIN3_OFST (16)
3282 +#define RG_SSUSB_RING_DET_DETWIN2_OFST (0)
3285 +#define RG_SSUSB_RING_DET_LBOND1_OFST (16)
3286 +#define RG_SSUSB_RING_DET_UBOND1_OFST (0)
3289 +#define RG_SSUSB_RING_DET_LBOND2_OFST (16)
3290 +#define RG_SSUSB_RING_DET_UBOND2_OFST (0)
3293 +#define RG_SSUSB_RING_DET_LBOND3_OFST (16)
3294 +#define RG_SSUSB_RING_DET_UBOND3_OFST (0)
3297 +#define RG_SSUSB_RING_RESERVE_OFST (16)
3298 +#define RG_SSUSB_ROSC_PROB_SEL_OFST (2)
3299 +#define RG_SSUSB_RING_FREQMETER_EN_OFST (1)
3300 +#define RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
3303 +#define RGS_FM_RING_CNT_OFST (16)
3304 +#define RGS_SSUSB_RING_OSC_STATE_OFST (10)
3305 +#define RGS_SSUSB_RING_OSC_STABLE_OFST (9)
3306 +#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
3307 +#define RGS_SSUSB_RING_OSC_CAL_OFST (0)
3310 +#define RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
3313 +#define RGS_SSUSB_PHYD_VERSION_OFST (0)
3316 +#define RGS_SSUSB_PHYD_MODEL_OFST (0)
3319 +///////////////////////////////////////////////////////////////////////////////
3321 +struct sifslv_chip_reg {
3322 + PHY_LE32 xtalbias;
3324 + PHY_LE32 gpio_ctla;
3325 + PHY_LE32 gpio_ctlb;
3326 + PHY_LE32 gpio_ctlc;
3330 +#define RG_C60802_GPIO_CTLA (0xffffffff<<0) //31:0
3333 +#define RG_C60802_GPIO_CTLB (0xffffffff<<0) //31:0
3336 +#define RG_C60802_GPIO_CTLC (0xffffffff<<0) //31:0
3341 +#define RG_C60802_GPIO_CTLA_OFST (0)
3344 +#define RG_C60802_GPIO_CTLB_OFST (0)
3347 +#define RG_C60802_GPIO_CTLC_OFST (0)
3349 +///////////////////////////////////////////////////////////////////////////////
3351 +struct sifslv_fm_feg {
3362 +#define RG_LOCKTH (0xf<<28) //31:28
3363 +#define RG_MONCLK_SEL (0x3<<26) //27:26
3364 +#define RG_FM_MODE (0x1<<25) //25:25
3365 +#define RG_FREQDET_EN (0x1<<24) //24:24
3366 +#define RG_CYCLECNT (0xffffff<<0) //23:0
3369 +#define RG_TARGET (0xffffffff<<0) //31:0
3372 +#define RG_OFFSET (0xffffffff<<0) //31:0
3375 +#define USB_FM_OUT (0xffffffff<<0) //31:0
3378 +#define RG_MONCLK_SEL_3 (0x1<<9) //9:9
3379 +#define RG_FRCK_EN (0x1<<8) //8:8
3380 +#define USBPLL_LOCK (0x1<<1) //1:1
3381 +#define USB_FM_VLD (0x1<<0) //0:0
3387 +#define RG_LOCKTH_OFST (28)
3388 +#define RG_MONCLK_SEL_OFST (26)
3389 +#define RG_FM_MODE_OFST (25)
3390 +#define RG_FREQDET_EN_OFST (24)
3391 +#define RG_CYCLECNT_OFST (0)
3394 +#define RG_TARGET_OFST (0)
3397 +#define RG_OFFSET_OFST (0)
3400 +#define USB_FM_OUT_OFST (0)
3403 +#define RG_MONCLK_SEL_3_OFST (9)
3404 +#define RG_FRCK_EN_OFST (8)
3405 +#define USBPLL_LOCK_OFST (1)
3406 +#define USB_FM_VLD_OFST (0)
3409 +///////////////////////////////////////////////////////////////////////////////
3411 +PHY_INT32 phy_init(struct u3phy_info *info);
3412 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3413 +PHY_INT32 eyescan_init(struct u3phy_info *info);
3414 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
3415 + , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3416 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
3417 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
3418 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
3423 +++ b/drivers/usb/host/mtk-phy-ahb.c
3425 +#include "mtk-phy.h"
3426 +#ifdef CONFIG_U3D_HAL_SUPPORT
3427 +#include "mu3d_hal_osal.h"
3430 +#ifdef CONFIG_U3_PHY_AHB_SUPPORT
3431 +#include <linux/gfp.h>
3432 +#include <linux/kernel.h>
3433 +#include <linux/slab.h>
3435 +#ifndef CONFIG_U3D_HAL_SUPPORT
3436 +#define os_writel(addr,data) {\
3437 + (*((volatile PHY_UINT32*)(addr)) = data);\
3439 +#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
3440 +#define os_writelmsk(addr, data, msk) \
3441 + { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
3443 +#define os_setmsk(addr, msk) \
3444 + { os_writel(addr, os_readl(addr) | msk); \
3446 +#define os_clrmsk(addr, msk) \
3447 + { os_writel(addr, os_readl(addr) &~ msk); \
3449 +/*msk the data first, then umsk with the umsk.*/
3450 +#define os_writelmskumsk(addr, data, msk, umsk) \
3452 + os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
3457 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
3459 + os_writel(addr, data);
3464 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
3466 + return os_readl(addr);
3469 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
3471 + os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
3476 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
3478 + return ((os_readl(addr)>>((addr%4)*8))&0xff);
3484 +++ b/drivers/usb/host/mtk-phy.c
3486 +#include <linux/gfp.h>
3487 +#include <linux/kernel.h>
3488 +#include <linux/slab.h>
3490 +#include "mtk-phy.h"
3491 +#ifdef CONFIG_PROJECT_7621
3492 +#include "mtk-phy-7621.h"
3494 +#ifdef CONFIG_PROJECT_PHY
3495 +static struct u3phy_operator project_operators = {
3497 + .change_pipe_phase = phy_change_pipe_phase,
3498 + .eyescan_init = eyescan_init,
3499 + .eyescan = phy_eyescan,
3500 + .u2_slew_rate_calibration = u2_slew_rate_calibration,
3505 +PHY_INT32 u3phy_init(){
3506 +#ifndef CONFIG_PROJECT_PHY
3507 + PHY_INT32 u3phy_version;
3510 + if(u3phy != NULL){
3514 + u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3515 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3516 + u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3518 +#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
3519 + u3phy->phyd_version_addr = 0x2000e4;
3520 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3521 + u3phy_p1->phyd_version_addr = 0x2000e4;
3524 + u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
3525 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3526 + u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
3530 +#ifdef CONFIG_PROJECT_PHY
3532 + u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
3533 + u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
3534 + u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
3535 + u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
3536 + u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
3537 + u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3538 + u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3539 + u3phy_ops = &project_operators;
3541 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3542 + u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
3543 + u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
3544 + u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
3545 + u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
3546 + u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
3547 + u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3548 + u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3555 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3556 + PHY_INT8 cur_value;
3557 + PHY_INT8 new_value;
3559 + cur_value = U3PhyReadReg8(addr);
3560 + new_value = (cur_value & (~mask)) | (value << offset);
3561 + //udelay(i2cdelayus);
3562 + U3PhyWriteReg8(addr, new_value);
3566 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3567 + PHY_INT32 cur_value;
3568 + PHY_INT32 new_value;
3570 + cur_value = U3PhyReadReg32(addr);
3571 + new_value = (cur_value & (~mask)) | ((value << offset) & mask);
3572 + U3PhyWriteReg32(addr, new_value);
3573 + //DRV_MDELAY(100);
3578 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
3580 + return ((U3PhyReadReg8(addr) & mask) >> offset);
3583 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
3585 + return ((U3PhyReadReg32(addr) & mask) >> offset);
3589 +++ b/drivers/usb/host/mtk-phy.h
3591 +#ifndef __MTK_PHY_NEW_H
3592 +#define __MTK_PHY_NEW_H
3594 +//#define CONFIG_U3D_HAL_SUPPORT
3596 +/* include system library */
3597 +#include <linux/gfp.h>
3598 +#include <linux/kernel.h>
3599 +#include <linux/slab.h>
3600 +#include <linux/delay.h>
3602 +/* Choose PHY R/W implementation */
3603 +//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
3604 +#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
3606 +/* Choose PHY version */
3607 +//Select your project by defining one of the followings
3608 +#define CONFIG_PROJECT_7621 //7621
3609 +#define CONFIG_PROJECT_PHY
3611 +/* BASE ADDRESS DEFINE, should define this on ASIC */
3612 +#define PHY_BASE 0xBE1D0000
3613 +#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
3614 +#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
3615 +#define U2_PHY_BASE (PHY_BASE+0x800)
3616 +#define U3_PHYD_BASE (PHY_BASE+0x900)
3617 +#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
3618 +#define U3_PHYA_BASE (PHY_BASE+0xb00)
3619 +#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
3621 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3622 +#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
3623 +#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
3624 +#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
3625 +#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
3626 +#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
3627 +#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
3628 +#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
3633 +0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
3634 +0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
3635 +0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
3636 +0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
3637 +0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
3638 +0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
3639 +0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
3644 +typedef unsigned int PHY_UINT32;
3645 +typedef int PHY_INT32;
3646 +typedef unsigned short PHY_UINT16;
3647 +typedef short PHY_INT16;
3648 +typedef unsigned char PHY_UINT8;
3649 +typedef char PHY_INT8;
3651 +typedef PHY_UINT32 __bitwise PHY_LE32;
3653 +/* CONSTANT DEFINE */
3654 +#define PHY_FALSE 0
3658 +#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
3659 +#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
3661 +#define DRV_MDELAY mdelay
3662 +#define DRV_MSLEEP msleep
3663 +#define DRV_UDELAY udelay
3664 +#define DRV_USLEEP usleep
3666 +/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
3667 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
3668 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
3669 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
3670 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
3672 +/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
3673 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3674 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3675 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3676 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3678 +struct u3phy_info {
3679 + PHY_INT32 phy_version;
3680 + PHY_INT32 phyd_version_addr;
3682 +#ifdef CONFIG_PROJECT_PHY
3683 + struct u2phy_reg *u2phy_regs;
3684 + struct u3phya_reg *u3phya_regs;
3685 + struct u3phya_da_reg *u3phya_da_regs;
3686 + struct u3phyd_reg *u3phyd_regs;
3687 + struct u3phyd_bank2_reg *u3phyd_bank2_regs;
3688 + struct sifslv_chip_reg *sifslv_chip_regs;
3689 + struct sifslv_fm_feg *sifslv_fm_regs;
3693 +struct u3phy_operator {
3694 + PHY_INT32 (*init) (struct u3phy_info *info);
3695 + PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3696 + PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
3697 + PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3698 + PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
3699 + PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
3700 + PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
3706 +#define AUTOEXT extern
3709 +AUTOEXT struct u3phy_info *u3phy;
3710 +AUTOEXT struct u3phy_info *u3phy_p1;
3711 +AUTOEXT struct u3phy_operator *u3phy_ops;
3713 +/*********eye scan required*********/
3715 +#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
3716 +#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
3724 +struct strucScanRegion
3734 +struct strucTestCycle
3736 + PHY_UINT16 wEyeCnt;
3737 + PHY_INT8 bNumOfEyeCnt;
3738 + PHY_INT8 bPICalEn;
3739 + PHY_INT8 bNumOfIgnoreCnt;
3742 +#define ERRCNT_MAX 128
3743 +#define CYCLE_COUNT_MAX 15
3745 +/// the map resolution is 128 x 128 pts
3751 +PHY_INT32 u3phy_init(void);
3753 +AUTOEXT struct strucScanRegion _rEye1;
3754 +AUTOEXT struct strucScanRegion _rEye2;
3755 +AUTOEXT struct strucTestCycle _rTestCycle;
3756 +AUTOEXT PHY_UINT8 _bXcurr;
3757 +AUTOEXT PHY_UINT8 _bYcurr;
3758 +AUTOEXT enumScanDir _eScanDir;
3759 +AUTOEXT PHY_INT8 _fgXChged;
3760 +AUTOEXT PHY_INT8 _bPIResult;
3761 +/* use local variable instead to save memory use */
3763 +AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3764 +AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3767 +/***********************************/
3770 --- a/drivers/usb/host/pci-quirks.h
3771 +++ b/drivers/usb/host/pci-quirks.h
3773 #ifndef __LINUX_USB_PCI_QUIRKS_H
3774 #define __LINUX_USB_PCI_QUIRKS_H
3777 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3778 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
3779 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
3780 #endif /* CONFIG_PCI */
3781 --- a/drivers/usb/host/xhci-dbg.c
3782 +++ b/drivers/usb/host/xhci-dbg.c
3787 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3788 +#include "xhci-mtk.h"
3791 #define XHCI_INIT_VALUE 0x0
3793 --- a/drivers/usb/host/xhci-mem.c
3794 +++ b/drivers/usb/host/xhci-mem.c
3795 @@ -67,6 +67,9 @@ static struct xhci_segment *xhci_segment
3797 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
3803 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
3805 @@ -1475,9 +1478,17 @@ int xhci_endpoint_init(struct xhci_hcd *
3806 max_burst = (usb_endpoint_maxp(&ep->desc)
3809 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3810 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3814 case USB_SPEED_FULL:
3816 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3817 + if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3824 +++ b/drivers/usb/host/xhci-mtk-power.c
3826 +#include "xhci-mtk.h"
3827 +#include "xhci-mtk-power.h"
3829 +#include <linux/kernel.h> /* printk() */
3830 +#include <linux/slab.h>
3831 +#include <linux/delay.h>
3833 +static int g_num_u3_port;
3834 +static int g_num_u2_port;
3837 +void enableXhciAllPortPower(struct xhci_hcd *xhci){
3839 + u32 port_id, temp;
3840 + u32 __iomem *addr;
3842 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3843 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3845 + for(i=1; i<=g_num_u3_port; i++){
3847 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3848 + temp = readl(addr);
3849 + temp = xhci_port_state_to_neutral(temp);
3850 + temp |= PORT_POWER;
3851 + writel(temp, addr);
3853 + for(i=1; i<=g_num_u2_port; i++){
3854 + port_id=i+g_num_u3_port;
3855 + addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3856 + temp = readl(addr);
3857 + temp = xhci_port_state_to_neutral(temp);
3858 + temp |= PORT_POWER;
3859 + writel(temp, addr);
3863 +void enableAllClockPower(){
3868 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3869 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3872 + writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3873 + writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3874 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3876 + //1. Enable target ports
3877 + for(i=0; i<g_num_u3_port; i++){
3878 + temp = readl(SSUSB_U3_CTRL(i));
3879 + temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
3880 + writel(temp, SSUSB_U3_CTRL(i));
3882 + for(i=0; i<g_num_u2_port; i++){
3883 + temp = readl(SSUSB_U2_CTRL(i));
3884 + temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
3885 + writel(temp, SSUSB_U2_CTRL(i));
3891 +//(X)disable clock/power of a port
3892 +//(X)if all ports are disabled, disable IP ctrl power
3893 +//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
3894 +//and IP could be disable if suspended.
3895 +//If doesn't not disable all ports at first, the IP clock/power will never be disabled
3896 +//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
3897 +//port_index: port number
3898 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3899 +void disablePortClockPower(void){
3903 + g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3904 + g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3906 + for(i=0; i<g_num_u3_port; i++){
3907 + temp = readl(SSUSB_U3_CTRL(i));
3908 + temp = temp | (SSUSB_U3_PORT_PDN);
3909 + writel(temp, SSUSB_U3_CTRL(i));
3911 + for(i=0; i<g_num_u2_port; i++){
3912 + temp = readl(SSUSB_U2_CTRL(i));
3913 + temp = temp | (SSUSB_U2_PORT_PDN);
3914 + writel(temp, SSUSB_U2_CTRL(i));
3916 + writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3919 +//if IP ctrl power is disabled, enable it
3920 +//enable clock/power of a port
3921 +//port_index: port number
3922 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3923 +void enablePortClockPower(int port_index, int port_rev){
3927 + writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3929 + if(port_rev == 0x3){
3930 + temp = readl(SSUSB_U3_CTRL(port_index));
3931 + temp = temp & (~SSUSB_U3_PORT_PDN);
3932 + writel(temp, SSUSB_U3_CTRL(port_index));
3934 + else if(port_rev == 0x2){
3935 + temp = readl(SSUSB_U2_CTRL(port_index));
3936 + temp = temp & (~SSUSB_U2_PORT_PDN);
3937 + writel(temp, SSUSB_U2_CTRL(port_index));
3942 +++ b/drivers/usb/host/xhci-mtk-power.h
3944 +#ifndef _XHCI_MTK_POWER_H
3945 +#define _XHCI_MTK_POWER_H
3947 +#include <linux/usb.h>
3949 +#include "xhci-mtk.h"
3951 +void enableXhciAllPortPower(struct xhci_hcd *xhci);
3952 +void enableAllClockPower(void);
3953 +void disablePortClockPower(void);
3954 +void enablePortClockPower(int port_index, int port_rev);
3958 +++ b/drivers/usb/host/xhci-mtk-scheduler.c
3960 +#include "xhci-mtk-scheduler.h"
3961 +#include <linux/kernel.h> /* printk() */
3963 +static struct sch_ep **ss_out_eps[MAX_EP_NUM];
3964 +static struct sch_ep **ss_in_eps[MAX_EP_NUM];
3965 +static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
3966 +static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
3969 +int mtk_xhci_scheduler_init(void){
3972 + for(i=0; i<MAX_EP_NUM; i++){
3973 + ss_out_eps[i] = NULL;
3975 + for(i=0; i<MAX_EP_NUM; i++){
3976 + ss_in_eps[i] = NULL;
3978 + for(i=0; i<MAX_EP_NUM; i++){
3981 + for(i=0; i<MAX_EP_NUM; i++){
3982 + tt_intr_eps[i] = NULL;
3987 +int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
3988 + , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
3989 + , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
3991 + struct sch_ep **ep_array;
3994 + if(is_in && dev_speed == USB_SPEED_SUPER ){
3995 + ep_array = (struct sch_ep **)ss_in_eps;
3997 + else if(dev_speed == USB_SPEED_SUPER){
3998 + ep_array = (struct sch_ep **)ss_out_eps;
4000 + else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
4001 + ep_array = (struct sch_ep **)hs_eps;
4004 + ep_array = (struct sch_ep **)tt_intr_eps;
4006 + for(i=0; i<MAX_EP_NUM; i++){
4007 + if(ep_array[i] == NULL){
4008 + tmp_ep->dev_speed = dev_speed;
4009 + tmp_ep->isTT = isTT;
4010 + tmp_ep->is_in = is_in;
4011 + tmp_ep->ep_type = ep_type;
4012 + tmp_ep->maxp = maxp;
4013 + tmp_ep->interval = interval;
4014 + tmp_ep->burst = burst;
4015 + tmp_ep->mult = mult;
4016 + tmp_ep->offset = offset;
4017 + tmp_ep->repeat = repeat;
4018 + tmp_ep->pkts = pkts;
4019 + tmp_ep->cs_count = cs_count;
4020 + tmp_ep->burst_mode = burst_mode;
4021 + tmp_ep->bw_cost = bw_cost;
4023 + ep_array[i] = tmp_ep;
4024 + return SCH_SUCCESS;
4030 +int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
4033 + int bw_required[3];
4034 + int final_bw_required;
4035 + int bw_required_per_repeat;
4036 + int tmp_bw_required;
4037 + struct sch_ep *cur_sch_ep;
4038 + struct sch_ep **ep_array;
4040 + int cur_ep_offset;
4049 + ep_array = (struct sch_ep **)ss_in_eps;
4052 + ep_array = (struct sch_ep **)ss_out_eps;
4055 + bw_required[0] = 0;
4056 + bw_required[1] = 0;
4057 + bw_required[2] = 0;
4060 + final_bw_required = 0;
4061 + for(i=0; i<MAX_EP_NUM; i++){
4062 + cur_sch_ep = ep_array[i];
4063 + if(cur_sch_ep == NULL){
4066 + ep_interval = cur_sch_ep->interval;
4067 + ep_offset = cur_sch_ep->offset;
4068 + if(cur_sch_ep->repeat == 0){
4069 + if(ep_interval >= interval){
4070 + tmp_offset = ep_offset + ep_interval - offset;
4071 + tmp_interval = interval;
4074 + tmp_offset = offset + interval - ep_offset;
4075 + tmp_interval = ep_interval;
4077 + if(tmp_offset % tmp_interval == 0){
4078 + final_bw_required += cur_sch_ep->bw_cost;
4082 + ep_repeat = cur_sch_ep->repeat;
4083 + ep_mult = cur_sch_ep->mult;
4084 + for(k=0; k<=ep_mult; k++){
4085 + cur_ep_offset = ep_offset+(k*ep_mult);
4086 + if(ep_interval >= interval){
4087 + tmp_offset = cur_ep_offset + ep_interval - offset;
4088 + tmp_interval = interval;
4091 + tmp_offset = offset + interval - cur_ep_offset;
4092 + tmp_interval = ep_interval;
4094 + if(tmp_offset % tmp_interval == 0){
4095 + final_bw_required += cur_sch_ep->bw_cost;
4101 + final_bw_required += td_size;
4104 + bw_required_per_repeat = maxp * (burst+1);
4105 + for(j=0; j<=mult; j++){
4106 + tmp_bw_required = 0;
4107 + cur_offset = offset+(j*repeat);
4108 + for(i=0; i<MAX_EP_NUM; i++){
4109 + cur_sch_ep = ep_array[i];
4110 + if(cur_sch_ep == NULL){
4113 + ep_interval = cur_sch_ep->interval;
4114 + ep_offset = cur_sch_ep->offset;
4115 + if(cur_sch_ep->repeat == 0){
4116 + if(ep_interval >= interval){
4117 + tmp_offset = ep_offset + ep_interval - cur_offset;
4118 + tmp_interval = interval;
4121 + tmp_offset = cur_offset + interval - ep_offset;
4122 + tmp_interval = ep_interval;
4124 + if(tmp_offset % tmp_interval == 0){
4125 + tmp_bw_required += cur_sch_ep->bw_cost;
4129 + ep_repeat = cur_sch_ep->repeat;
4130 + ep_mult = cur_sch_ep->mult;
4131 + for(k=0; k<=ep_mult; k++){
4132 + cur_ep_offset = ep_offset+(k*ep_repeat);
4133 + if(ep_interval >= interval){
4134 + tmp_offset = cur_ep_offset + ep_interval - cur_offset;
4135 + tmp_interval = interval;
4138 + tmp_offset = cur_offset + interval - cur_ep_offset;
4139 + tmp_interval = ep_interval;
4141 + if(tmp_offset % tmp_interval == 0){
4142 + tmp_bw_required += cur_sch_ep->bw_cost;
4148 + bw_required[j] = tmp_bw_required;
4150 + final_bw_required = SS_BW_BOUND;
4151 + for(j=0; j<=mult; j++){
4152 + if(bw_required[j] < final_bw_required){
4153 + final_bw_required = bw_required[j];
4156 + final_bw_required += bw_required_per_repeat;
4158 + return final_bw_required;
4161 +int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
4164 + struct sch_ep *cur_sch_ep;
4169 + int cur_tt_isoc_interval; //for isoc tt check
4172 + for(i=0; i<MAX_EP_NUM; i++){
4174 + cur_sch_ep = (struct sch_ep *)hs_eps[i];
4175 + if(cur_sch_ep == NULL){
4178 + ep_offset = cur_sch_ep->offset;
4179 + ep_interval = cur_sch_ep->interval;
4181 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4182 + cur_tt_isoc_interval = ep_interval<<3;
4183 + if(ep_interval >= interval){
4184 + tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
4185 + tmp_interval = interval;
4188 + tmp_offset = offset + interval - ep_offset;
4189 + tmp_interval = cur_tt_isoc_interval;
4191 + if(cur_sch_ep->is_in){
4192 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4193 + bw_required += 188;
4197 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4198 + bw_required += 188;
4203 + if(ep_interval >= interval){
4204 + tmp_offset = ep_offset + ep_interval - offset;
4205 + tmp_interval = interval;
4208 + tmp_offset = offset + interval - ep_offset;
4209 + tmp_interval = ep_interval;
4211 + if(tmp_offset%tmp_interval == 0){
4212 + bw_required += cur_sch_ep->bw_cost;
4216 + bw_required += td_size;
4217 + return bw_required;
4220 +int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
4222 + int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
4223 + int bw_required, max_bw;
4228 + struct sch_ep *cur_sch_ep;
4232 + int tt_isoc_interval; //for isoc tt check
4233 + int cur_tt_isoc_interval; //for isoc tt check
4239 + tt_isoc_interval = interval<<3; //frame to mframe
4243 + s_frame = offset/8;
4244 + s_mframe = offset%8;
4245 + ss_cs_count = (maxp + (188 - 1))/188;
4247 + cs_mframe = offset%8 + 2 + ss_cs_count;
4248 + if (cs_mframe <= 6)
4250 + else if (cs_mframe == 7)
4252 + else if (cs_mframe > 8)
4259 + for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
4261 + for(j=0; j<MAX_EP_NUM; j++){
4262 + cur_sch_ep = (struct sch_ep *)hs_eps[j];
4263 + if(cur_sch_ep == NULL){
4266 + ep_offset = cur_sch_ep->offset;
4267 + ep_interval = cur_sch_ep->interval;
4268 + if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4270 + //check if mframe offset overlap
4271 + //if overlap, add 188 to the bw
4272 + cur_tt_isoc_interval = ep_interval<<3;
4273 + if(cur_tt_isoc_interval >= tt_isoc_interval){
4274 + tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
4275 + tmp_interval = tt_isoc_interval;
4278 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4279 + tmp_interval = cur_tt_isoc_interval;
4281 + if(cur_sch_ep->is_in){
4282 + if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4283 + bw_required += 188;
4287 + if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4288 + bw_required += 188;
4293 + else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
4295 + if(ep_interval >= tt_isoc_interval){
4296 + tmp_offset = (ep_offset+ep_interval) - cur_mframe;
4297 + tmp_interval = tt_isoc_interval;
4300 + tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4301 + tmp_interval = ep_interval;
4303 + if(tmp_offset%tmp_interval == 0){
4304 + bw_required += cur_sch_ep->bw_cost;
4308 + bw_required += 188;
4309 + if(bw_required > max_bw){
4310 + max_bw = bw_required;
4316 +int count_tt_intr_bw(int interval, int frame_offset){
4317 + //check all eps in tt_intr_eps
4324 + ret = SCH_SUCCESS;
4325 + struct sch_ep *cur_sch_ep;
4327 + for(i=0; i<MAX_EP_NUM; i++){
4328 + cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
4329 + if(cur_sch_ep == NULL){
4332 + ep_offset = cur_sch_ep->offset;
4333 + ep_interval = cur_sch_ep->interval;
4334 + if(ep_interval >= interval){
4335 + tmp_offset = ep_offset + ep_interval - frame_offset;
4336 + tmp_interval = interval;
4339 + tmp_offset = frame_offset + interval - ep_offset;
4340 + tmp_interval = ep_interval;
4343 + if(tmp_offset%tmp_interval==0){
4347 + return SCH_SUCCESS;
4350 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
4352 + struct sch_ep **ep_array;
4353 + struct sch_ep *cur_ep;
4355 + if (is_in && dev_speed == USB_SPEED_SUPER) {
4356 + ep_array = (struct sch_ep **)ss_in_eps;
4358 + else if (dev_speed == USB_SPEED_SUPER) {
4359 + ep_array = (struct sch_ep **)ss_out_eps;
4361 + else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
4362 + ep_array = (struct sch_ep **)hs_eps;
4365 + ep_array = (struct sch_ep **)tt_intr_eps;
4367 + for (i = 0; i < MAX_EP_NUM; i++) {
4368 + cur_ep = (struct sch_ep *)ep_array[i];
4369 + if(cur_ep != NULL && cur_ep->ep == ep){
4370 + ep_array[i] = NULL;
4377 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4378 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
4379 + mtk_u32 bPkts = 0;
4380 + mtk_u32 bCsCount = 0;
4382 + mtk_u32 bOffset = 0;
4383 + mtk_u32 bRepeat = 0;
4385 + struct mtk_xhci_ep_ctx *temp_ep_ctx;
4387 + int mframe_idx, frame_idx;
4389 + int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
4390 + int cur_offset, cs_mframe;
4392 + int frame_interval;
4394 + printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
4395 + , interval, burst, mult, ep, ep_ctx, sch_ep);
4396 + if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
4397 + frame_interval = interval >> 3;
4398 + for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
4399 + printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
4400 + if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
4401 + printk(KERN_ERR "check OK............\n");
4402 + bOffset = frame_idx<<3;
4407 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
4408 + , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
4411 + ret = SCH_SUCCESS;
4416 + else if(isTT && ep_type == USB_EP_ISOC){
4417 + best_bw = HS_BW_BOUND;
4422 + frame_interval = interval>>3;
4423 + for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
4424 + for(mframe_idx=0; mframe_idx<8; mframe_idx++){
4425 + cur_offset = (frame_idx*8) + mframe_idx;
4426 + cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
4427 + if(cur_bw > 0 && cur_bw < best_bw){
4428 + best_bw_idx = cur_offset;
4430 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4437 + if(best_bw_idx == -1){
4441 + bOffset = best_bw_idx;
4443 + bCsCount = (maxp + (188 - 1)) / 188;
4445 + cs_mframe = bOffset%8 + 2 + bCsCount;
4446 + if (cs_mframe <= 6)
4448 + else if (cs_mframe == 7)
4453 + if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4454 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4457 + ret = SCH_SUCCESS;
4460 + else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
4462 + ret = SCH_SUCCESS;
4464 + else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
4466 + ret = SCH_SUCCESS;
4468 + else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4469 + best_bw = HS_BW_BOUND;
4472 + td_size = maxp*(burst+1);
4473 + for(cur_offset = 0; cur_offset<interval; cur_offset++){
4474 + cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
4475 + if(cur_bw > 0 && cur_bw < best_bw){
4476 + best_bw_idx = cur_offset;
4478 + if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4483 + if(best_bw_idx == -1){
4487 + bOffset = best_bw_idx;
4488 + bPkts = burst + 1;
4490 + bw_cost = td_size;
4492 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4493 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4496 + ret = SCH_SUCCESS;
4499 + else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4500 + best_bw = SS_BW_BOUND;
4503 + td_size = maxp * (mult+1) * (burst+1);
4508 + max_repeat = (interval-1)/(mult+1);
4511 + for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
4512 + for(repeat = max_repeat; repeat >= 0; repeat--){
4513 + cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
4514 + , repeat, td_size);
4515 + printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
4516 + , frame_idx, repeat, td_size, cur_bw);
4517 + if(cur_bw > 0 && cur_bw < best_bw){
4518 + best_bw_idx = frame_idx;
4519 + best_bw_repeat = repeat;
4521 + if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
4528 + printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
4529 + if(best_bw_idx == -1){
4533 + bOffset = best_bw_idx;
4535 + bRepeat = best_bw_repeat;
4537 + bw_cost = (burst+1)*(mult+1)*maxp;
4538 + bPkts = (burst+1)*(mult+1);
4541 + bw_cost = (burst+1)*maxp;
4542 + bPkts = (burst+1);
4544 + if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4545 + , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4548 + ret = SCH_SUCCESS;
4553 + ret = SCH_SUCCESS;
4555 + if(ret == SCH_SUCCESS){
4556 + temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
4557 + temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
4558 + temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
4560 + printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
4561 + printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
4562 + return SCH_SUCCESS;
4569 +++ b/drivers/usb/host/xhci-mtk-scheduler.h
4571 +#ifndef _XHCI_MTK_SCHEDULER_H
4572 +#define _XHCI_MTK_SCHEDULER_H
4574 +#define MTK_SCH_NEW 1
4576 +#define SCH_SUCCESS 1
4579 +#define MAX_EP_NUM 64
4580 +#define SS_BW_BOUND 51000
4581 +#define HS_BW_BOUND 6144
4583 +#define USB_EP_CONTROL 0
4584 +#define USB_EP_ISOC 1
4585 +#define USB_EP_BULK 2
4586 +#define USB_EP_INT 3
4588 +#define USB_SPEED_LOW 1
4589 +#define USB_SPEED_FULL 2
4590 +#define USB_SPEED_HIGH 3
4591 +#define USB_SPEED_SUPER 5
4593 +/* mtk scheduler bitmasks */
4594 +#define BPKTS(p) ((p) & 0x3f)
4595 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
4596 +#define BBM(p) ((p) << 11)
4597 +#define BOFFSET(p) ((p) & 0x3fff)
4598 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
4602 +typedef unsigned int mtk_u32;
4603 +typedef unsigned long long mtk_u64;
4606 +#define NULL ((void *)0)
4608 +struct mtk_xhci_ep_ctx {
4613 + /* offset 0x14 - 0x1f reserved for HC internal use */
4614 + mtk_u32 reserved[3];
4637 + int bw_cost; //bandwidth cost in each repeat; including overhead
4638 + mtk_u32 *ep; //address of usb_endpoint pointer
4641 +int mtk_xhci_scheduler_init(void);
4642 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4643 + , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
4644 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
4649 +++ b/drivers/usb/host/xhci-mtk.c
4651 +#include "xhci-mtk.h"
4652 +#include "xhci-mtk-power.h"
4654 +#include "mtk-phy.h"
4655 +#ifdef CONFIG_C60802_SUPPORT
4656 +#include "mtk-phy-c60802.h"
4658 +#include "xhci-mtk-scheduler.h"
4659 +#include <linux/kernel.h> /* printk() */
4660 +#include <linux/slab.h>
4661 +#include <linux/delay.h>
4662 +#include <asm/uaccess.h>
4663 +#include <linux/dma-mapping.h>
4664 +#include <linux/platform_device.h>
4666 +void setInitialReg(void )
4668 + __u32 __iomem *addr;
4671 + /* set SSUSB DMA burst size to 128B */
4672 + addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
4673 + temp = SSUSB_HDMA_CFG_MT7621_VALUE;
4674 + writel(temp, addr);
4676 + /* extend U3 LTSSM Polling.LFPS timeout value */
4677 + addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
4678 + temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
4679 + writel(temp, addr);
4682 + addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
4683 + temp = SYNC_HS_EOF_VALUE;
4684 + writel(temp, addr);
4686 +#if defined (CONFIG_PERIODIC_ENP)
4687 + /* HSCH_CFG1: SCH2_FIFO_DEPTH */
4688 + addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
4689 + temp = readl(addr);
4690 + temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
4691 + writel(temp, addr);
4694 + /* Doorbell handling */
4695 + addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
4697 + writel(temp, addr);
4699 + /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
4701 + addr = U2_PHY_BASE + U2_PHYD_CR1;
4702 + temp = readl(addr);
4703 + temp &= ~(0x3 << 18);
4704 + temp |= (1 << 18);
4705 + writel(temp, addr);
4708 + addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
4709 + temp = readl(addr);
4710 + temp &= ~(0x3 << 18);
4711 + temp |= (1 << 18);
4712 + writel(temp, addr);
4716 +void setLatchSel(void){
4717 + __u32 __iomem *latch_sel_addr;
4718 + u32 latch_sel_value;
4719 + latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
4720 + latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
4721 + writel(latch_sel_value, latch_sel_addr);
4724 +void reinitIP(void){
4725 + __u32 __iomem *ip_reset_addr;
4726 + u32 ip_reset_value;
4728 + enableAllClockPower();
4729 + mtk_xhci_scheduler_init();
4732 +void dbg_prb_out(void){
4733 + mtk_probe_init(0x0f0f0f0f);
4734 + mtk_probe_out(0xffffffff);
4735 + mtk_probe_out(0x01010101);
4736 + mtk_probe_out(0x02020202);
4737 + mtk_probe_out(0x04040404);
4738 + mtk_probe_out(0x08080808);
4739 + mtk_probe_out(0x10101010);
4740 + mtk_probe_out(0x20202020);
4741 + mtk_probe_out(0x40404040);
4742 + mtk_probe_out(0x80808080);
4743 + mtk_probe_out(0x55555555);
4744 + mtk_probe_out(0xaaaaaaaa);
4749 +///////////////////////////////////////////////////////////////////////////////
4751 +#define RET_SUCCESS 0
4754 +static int dbg_u3w(int argc, char**argv)
4756 + int u4TimingValue;
4757 + char u1TimingValue;
4758 + int u4TimingAddress;
4762 + printk(KERN_ERR "Arg: address value\n");
4767 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4768 + u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
4769 + u1TimingValue = u4TimingValue & 0xff;
4770 + /* access MMIO directly */
4771 + writel(u1TimingValue, u4TimingAddress);
4772 + printk(KERN_ERR "Write done\n");
4773 + return RET_SUCCESS;
4777 +static int dbg_u3r(int argc, char**argv)
4779 + char u1ReadTimingValue;
4780 + int u4TimingAddress;
4783 + printk(KERN_ERR "Arg: address\n");
4788 + u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4789 + /* access MMIO directly */
4790 + u1ReadTimingValue = readl(u4TimingAddress);
4791 + printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
4795 +static int dbg_u3init(int argc, char**argv)
4798 + ret = u3phy_init();
4799 + printk(KERN_ERR "phy registers and operations initial done\n");
4800 + if(u3phy_ops->u2_slew_rate_calibration){
4801 + u3phy_ops->u2_slew_rate_calibration(u3phy);
4804 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
4806 + if(u3phy_ops->init(u3phy) == PHY_TRUE)
4807 + return RET_SUCCESS;
4811 +void dbg_setU1U2(int argc, char**argv){
4812 + struct xhci_hcd *xhci;
4815 + u32 port_id, temp;
4816 + u32 __iomem *addr;
4820 + printk(KERN_ERR "Arg: u1value u2value\n");
4824 + u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
4825 + u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
4826 + addr = (SSUSB_U3_XHCI_BASE + 0x424);
4827 + temp = readl(addr);
4828 + temp = temp & (~(0x0000ffff));
4829 + temp = temp | u1_value | (u2_value<<8);
4830 + writel(temp, addr);
4832 +///////////////////////////////////////////////////////////////////////////////
4834 +int call_function(char *buf)
4843 + argv[argc] = strsep(&buf, " ");
4844 + printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
4847 + if (!strcmp("dbg.r", argv[0]))
4849 + else if (!strcmp("dbg.u3w", argv[0]))
4850 + dbg_u3w(argc, argv);
4851 + else if (!strcmp("dbg.u3r", argv[0]))
4852 + dbg_u3r(argc, argv);
4853 + else if (!strcmp("dbg.u3i", argv[0]))
4854 + dbg_u3init(argc, argv);
4855 + else if (!strcmp("pw.u1u2", argv[0]))
4856 + dbg_setU1U2(argc, argv);
4860 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
4863 + char r_buf[200] = "this is a test";
4868 + copy_to_user((char *) arg, r_buf, len);
4869 + printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
4872 + copy_from_user(w_buf, (char *) arg, len);
4873 + printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
4876 + return call_function(w_buf);
4885 +int xhci_mtk_test_open(struct inode *inode, struct file *file)
4888 + printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
4892 +int xhci_mtk_test_release(struct inode *inode, struct file *file)
4895 + printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
4899 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
4902 + printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
4906 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
4909 + printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
4917 +++ b/drivers/usb/host/xhci-mtk.h
4919 +#ifndef _XHCI_MTK_H
4920 +#define _XHCI_MTK_H
4922 +#include <linux/usb.h>
4925 +#define SSUSB_U3_XHCI_BASE 0xBE1C0000
4926 +#define SSUSB_U3_MAC_BASE 0xBE1C2400
4927 +#define SSUSB_U3_SYS_BASE 0xBE1C2600
4928 +#define SSUSB_U2_SYS_BASE 0xBE1C3400
4929 +#define SSUB_SIF_SLV_TOP 0xBE1D0000
4930 +#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
4932 +#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
4933 +#define U3_PIPE_LATCH_TX 0
4934 +#define U3_PIPE_LATCH_RX 0
4936 +#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
4937 +#define U3_REF_CK_PAR 0xb0
4938 +#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
4939 +#define U3_RX_UX_EXIT_LFPS_REF 3
4940 +#define U3_REF_CK_VAL 10
4942 +#define U3_TIMING_PULSE_CTRL 0xb4
4943 +#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
4945 +#define USB20_TIMING_PARAMETER 0x40
4946 +#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
4948 +#define LINK_PM_TIMER 0x8
4949 +#define PM_LC_TIMEOUT_VALUE 3
4951 +#define XHCI_IMOD 0x624
4952 +#define XHCI_IMOD_MT7621_VALUE 0x10
4954 +#define SSUSB_HDMA_CFG 0x950
4955 +#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
4957 +#define U3_LTSSM_TIMING_PARAMETER3 0x2514
4958 +#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
4960 +#define U2_PHYD_CR1 0x64
4962 +#define SSUSB_IP_SPAR0 0xC8
4964 +#define SYNC_HS_EOF 0x938
4965 +#define SYNC_HS_EOF_VALUE 0x201F3
4967 +#define HSCH_CFG1 0x960
4968 +#define SCH2_FIFO_DEPTH_OFFSET 16
4971 +#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
4972 +#define SSUSB_IP_SW_RST (1<<0)
4973 +#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
4974 +#define SSUSB_IP_PDN (1<<0)
4975 +#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
4976 +#define SSUSB_U3_PORT_DIS (1<<0)
4977 +#define SSUSB_U3_PORT_PDN (1<<1)
4978 +#define SSUSB_U3_PORT_HOST_SEL (1<<2)
4979 +#define SSUSB_U3_PORT_CKBG_EN (1<<3)
4980 +#define SSUSB_U3_PORT_MAC_RST (1<<4)
4981 +#define SSUSB_U3_PORT_PHYD_RST (1<<5)
4982 +#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
4983 +#define SSUSB_U2_PORT_DIS (1<<0)
4984 +#define SSUSB_U2_PORT_PDN (1<<1)
4985 +#define SSUSB_U2_PORT_HOST_SEL (1<<2)
4986 +#define SSUSB_U2_PORT_CKBG_EN (1<<3)
4987 +#define SSUSB_U2_PORT_MAC_RST (1<<4)
4988 +#define SSUSB_U2_PORT_PHYD_RST (1<<5)
4989 +#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
4991 +#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
4992 +#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
4995 +#define XHCI_MTK_TEST_MAJOR 234
4996 +#define DEVICE_NAME "xhci_mtk_test"
4998 +#define CLI_MAGIC 'CLI'
4999 +#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
5000 +#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
5002 +void reinitIP(void);
5003 +void setInitialReg(void);
5004 +void dbg_prb_out(void);
5005 +int call_function(char *buf);
5007 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5008 +int xhci_mtk_test_open(struct inode *inode, struct file *file);
5009 +int xhci_mtk_test_release(struct inode *inode, struct file *file);
5010 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
5011 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
5014 + mediatek probe out
5016 +/************************************************************************************/
5018 +#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
5019 +#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
5021 +static inline void mtk_probe_init(const u32 byte){
5022 + __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
5023 + writel(byte, ptr);
5026 +static inline void mtk_probe_out(const u32 value){
5027 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5028 + writel(value, ptr);
5031 +static inline u32 mtk_probe_value(void){
5032 + __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5034 + return readl(ptr);
5039 --- a/drivers/usb/host/xhci-plat.c
5040 +++ b/drivers/usb/host/xhci-plat.c
5041 @@ -33,6 +33,13 @@ static void xhci_plat_quirks(struct devi
5042 * dev struct in order to setup MSI
5044 xhci->quirks |= XHCI_PLAT;
5045 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5046 + /* MTK host controller gives a spurious successful event after a
5047 + * short transfer. Ignore it.
5049 + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5050 + xhci->quirks |= XHCI_LPM_SUPPORT;
5054 /* called during probe() after chip reset completes */
5055 @@ -79,7 +86,11 @@ static int xhci_plat_probe(struct platfo
5057 driver = &xhci_plat_hc_driver;
5059 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5062 irq = platform_get_irq(pdev, 0);
5067 --- a/drivers/usb/host/xhci-ring.c
5068 +++ b/drivers/usb/host/xhci-ring.c
5069 @@ -254,16 +254,20 @@ static void inc_enq(struct xhci_hcd *xhc
5070 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
5071 unsigned int num_trbs)
5073 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5074 int num_trbs_in_deq_seg;
5077 if (ring->num_trbs_free < num_trbs)
5080 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5081 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
5082 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
5083 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
5090 @@ -2820,6 +2824,7 @@ static int prepare_ring(struct xhci_hcd
5091 next = ring->enqueue;
5093 while (last_trb(xhci, ring, ring->enq_seg, next)) {
5094 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5095 /* If we're not dealing with 0.95 hardware or isoc rings
5096 * on AMD 0.96 host, clear the chain bit.
5098 @@ -2829,6 +2834,9 @@ static int prepare_ring(struct xhci_hcd
5099 next->link.control &= cpu_to_le32(~TRB_CHAIN);
5101 next->link.control |= cpu_to_le32(TRB_CHAIN);
5103 + next->link.control &= cpu_to_le32(~TRB_CHAIN);
5107 next->link.control ^= cpu_to_le32(TRB_CYCLE);
5108 @@ -2959,6 +2967,9 @@ static void giveback_first_trb(struct xh
5109 start_trb->field[3] |= cpu_to_le32(start_cycle);
5111 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
5112 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5115 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
5118 @@ -3014,6 +3025,29 @@ static u32 xhci_td_remainder(unsigned in
5119 return (remainder >> 10) << 17;
5122 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5123 +static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
5126 + int remainder, td_packet_count, packet_transferred;
5128 + //0 for the last TRB
5129 + //FIXME: need to workaround if there is ZLP in this TD
5130 + if (td_running_total + trb_buffer_length == td_transfer_size)
5133 + //FIXME: need to take care of high-bandwidth (MAX_ESIT)
5134 + packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
5135 + td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
5136 + remainder = td_packet_count - packet_transferred;
5138 + if (remainder > max)
5141 + return remainder << 17;
5146 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
5147 * packets remaining in the TD (*not* including this TRB).
5148 @@ -3171,6 +3205,7 @@ static int queue_bulk_sg_tx(struct xhci_
5151 /* Set the TRB length, TD size, and interrupter fields. */
5152 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5153 if (xhci->hci_version < 0x100) {
5154 remainder = xhci_td_remainder(
5155 urb->transfer_buffer_length -
5156 @@ -3180,6 +3215,12 @@ static int queue_bulk_sg_tx(struct xhci_
5157 trb_buff_len, total_packet_count, urb,
5162 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
5163 + running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
5166 length_field = TRB_LEN(trb_buff_len) |
5169 @@ -3244,6 +3285,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5170 int running_total, trb_buff_len, ret;
5171 unsigned int total_packet_count;
5173 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5178 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
5179 @@ -3268,6 +3312,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5181 running_total += TRB_MAX_BUFF_SIZE;
5183 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5184 + switch(urb->dev->speed){
5185 + case USB_SPEED_SUPER:
5186 + max_packet = urb->ep->desc.wMaxPacketSize;
5188 + case USB_SPEED_HIGH:
5189 + case USB_SPEED_FULL:
5190 + case USB_SPEED_LOW:
5191 + case USB_SPEED_WIRELESS:
5192 + case USB_SPEED_UNKNOWN:
5194 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5197 + if((urb->transfer_flags & URB_ZERO_PACKET)
5198 + && ((urb->transfer_buffer_length % max_packet) == 0)){
5203 ret = prepare_transfer(xhci, xhci->devs[slot_id],
5204 ep_index, urb->stream_id,
5205 @@ -3344,6 +3407,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5208 /* Set the TRB length, TD size, and interrupter fields. */
5209 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5210 if (xhci->hci_version < 0x100) {
5211 remainder = xhci_td_remainder(
5212 urb->transfer_buffer_length -
5213 @@ -3353,6 +3417,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5214 trb_buff_len, total_packet_count, urb,
5218 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5221 length_field = TRB_LEN(trb_buff_len) |
5224 @@ -3442,7 +3510,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5227 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
5228 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5231 if (xhci->hci_version >= 0x100) {
5233 if (urb->transfer_buffer_length > 0) {
5234 if (setup->bRequestType & USB_DIR_IN)
5235 field |= TRB_TX_TYPE(TRB_DATA_IN);
5236 @@ -3466,7 +3538,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5237 field = TRB_TYPE(TRB_DATA);
5239 length_field = TRB_LEN(urb->transfer_buffer_length) |
5240 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5241 xhci_td_remainder(urb->transfer_buffer_length) |
5243 + //CC: MTK style, no scatter-gather for control transfer
5247 if (urb->transfer_buffer_length > 0) {
5248 if (setup->bRequestType & USB_DIR_IN)
5249 @@ -3589,6 +3666,9 @@ static int xhci_queue_isoc_tx(struct xhc
5250 u64 start_addr, addr;
5252 bool more_trbs_coming;
5253 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5257 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
5259 @@ -3602,6 +3682,21 @@ static int xhci_queue_isoc_tx(struct xhc
5260 start_trb = &ep_ring->enqueue->generic;
5261 start_cycle = ep_ring->cycle_state;
5263 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5264 + switch(urb->dev->speed){
5265 + case USB_SPEED_SUPER:
5266 + max_packet = urb->ep->desc.wMaxPacketSize;
5268 + case USB_SPEED_HIGH:
5269 + case USB_SPEED_FULL:
5270 + case USB_SPEED_LOW:
5271 + case USB_SPEED_WIRELESS:
5272 + case USB_SPEED_UNKNOWN:
5273 + max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5278 urb_priv = urb->hcpriv;
5279 /* Queue the first TRB, even if it's zero-length */
5280 for (i = 0; i < num_tds; i++) {
5281 @@ -3673,9 +3768,13 @@ static int xhci_queue_isoc_tx(struct xhc
5283 td->last_trb = ep_ring->enqueue;
5285 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5286 + if (!(xhci->quirks & XHCI_AVOID_BEI)) {
5288 if (xhci->hci_version == 0x100 &&
5292 /* Set BEI bit except for the last td */
5293 if (i < num_tds - 1)
5295 @@ -3690,6 +3789,7 @@ static int xhci_queue_isoc_tx(struct xhc
5296 trb_buff_len = td_remain_len;
5298 /* Set the TRB length, TD size, & interrupter fields. */
5299 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5300 if (xhci->hci_version < 0x100) {
5301 remainder = xhci_td_remainder(
5302 td_len - running_total);
5303 @@ -3699,6 +3799,10 @@ static int xhci_queue_isoc_tx(struct xhc
5304 total_packet_count, urb,
5305 (trbs_per_td - j - 1));
5308 + remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5311 length_field = TRB_LEN(trb_buff_len) |
5314 --- a/drivers/usb/host/xhci.c
5315 +++ b/drivers/usb/host/xhci.c
5318 #include "xhci-trace.h"
5320 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5321 +#include <asm/uaccess.h>
5322 +#include <linux/dma-mapping.h>
5323 +#include <linux/platform_device.h>
5324 +#include "mtk-phy.h"
5325 +#include "xhci-mtk-scheduler.h"
5326 +#include "xhci-mtk-power.h"
5327 +#include "xhci-mtk.h"
5330 #define DRIVER_AUTHOR "Sarah Sharp"
5331 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
5333 @@ -46,6 +56,18 @@ static unsigned int quirks;
5334 module_param(quirks, uint, S_IRUGO);
5335 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
5337 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5338 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5339 +static struct file_operations xhci_mtk_test_fops = {
5340 + .owner = THIS_MODULE,
5341 + .read = xhci_mtk_test_read,
5342 + .write = xhci_mtk_test_write,
5343 + .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
5344 + .open = xhci_mtk_test_open,
5345 + .release = xhci_mtk_test_release,
5349 /* TODO: copied from ehci-hcd.c - can this be refactored? */
5351 * xhci_handshake - spin reading hc until handshake completes or fails
5352 @@ -200,7 +222,7 @@ int xhci_reset(struct xhci_hcd *xhci)
5357 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5358 static int xhci_free_msi(struct xhci_hcd *xhci)
5361 @@ -450,6 +472,11 @@ static void compliance_mode_recovery(uns
5362 "Attempting compliance mode recovery");
5363 hcd = xhci->shared_hcd;
5365 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5366 + temp |= (1 << 31);
5367 + writel(temp, xhci->usb3_ports[i]);
5370 if (hcd->state == HC_STATE_SUSPENDED)
5371 usb_hcd_resume_root_hub(hcd);
5373 @@ -499,6 +526,9 @@ static bool xhci_compliance_mode_recover
5375 const char *dmi_product_name, *dmi_sys_vendor;
5377 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5380 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
5381 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
5382 if (!dmi_product_name || !dmi_sys_vendor)
5383 @@ -544,6 +574,10 @@ int xhci_init(struct usb_hcd *hcd)
5384 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5385 "xHCI doesn't need link TRB QUIRK");
5388 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5389 + mtk_xhci_scheduler_init();
5391 retval = xhci_mem_init(xhci, GFP_KERNEL);
5392 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
5394 @@ -628,7 +662,11 @@ int xhci_run(struct usb_hcd *hcd)
5395 "// Set the interrupt modulation register");
5396 temp = readl(&xhci->ir_set->irq_control);
5397 temp &= ~ER_IRQ_INTERVAL_MASK;
5398 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5403 writel(temp, &xhci->ir_set->irq_control);
5405 /* Set the HCD state before we enable the irqs */
5406 @@ -653,6 +691,9 @@ int xhci_run(struct usb_hcd *hcd)
5407 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
5408 TRB_TYPE(TRB_NEC_GET_FW));
5410 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5411 + enableXhciAllPortPower(xhci);
5413 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5414 "Finished xhci_run for USB2 roothub");
5416 @@ -1651,6 +1692,14 @@ int xhci_drop_endpoint(struct usb_hcd *h
5418 u32 new_add_flags, new_drop_flags;
5420 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5422 + struct xhci_slot_ctx *slot_ctx;
5423 + struct sch_ep *sch_ep = NULL;
5429 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5431 @@ -1698,6 +1747,40 @@ int xhci_drop_endpoint(struct usb_hcd *h
5433 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
5435 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5437 + slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
5438 + if ((slot_ctx->tt_info & 0xff) > 0) {
5444 + if (usb_endpoint_xfer_int(&ep->desc)) {
5445 + ep_type = USB_EP_INT;
5447 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5448 + ep_type = USB_EP_ISOC;
5450 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5451 + ep_type = USB_EP_BULK;
5454 + ep_type = USB_EP_CONTROL;
5456 + sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
5457 + , isTT, ep_type, (mtk_u32 *)ep);
5458 + if (sch_ep != NULL) {
5462 + xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
5465 + mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
5469 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
5470 (unsigned int) ep->desc.bEndpointAddress,
5472 @@ -1730,6 +1813,19 @@ int xhci_add_endpoint(struct usb_hcd *hc
5473 u32 new_add_flags, new_drop_flags;
5474 struct xhci_virt_device *virt_dev;
5476 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5477 + struct xhci_ep_ctx *in_ep_ctx;
5479 + struct xhci_slot_ctx *slot_ctx;
5480 + struct sch_ep *sch_ep;
5490 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5492 @@ -1796,6 +1892,56 @@ int xhci_add_endpoint(struct usb_hcd *hc
5496 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5497 + in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
5499 + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
5500 + if ((slot_ctx->tt_info & 0xff) > 0) {
5506 + if (usb_endpoint_xfer_int(&ep->desc)) {
5507 + ep_type = USB_EP_INT;
5509 + else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5510 + ep_type = USB_EP_ISOC;
5512 + else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5513 + ep_type = USB_EP_BULK;
5516 + ep_type = USB_EP_CONTROL;
5518 + if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
5519 + || udev->speed == USB_SPEED_LOW) {
5520 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5521 + burst = ep->desc.wMaxPacketSize >> 11;
5524 + else if (udev->speed == USB_SPEED_SUPER) {
5525 + maxp = ep->desc.wMaxPacketSize & 0x7FF;
5526 + burst = ep->ss_ep_comp.bMaxBurst;
5527 + mult = ep->ss_ep_comp.bmAttributes & 0x3;
5529 + interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
5530 + sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
5531 + if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
5532 + isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
5533 + , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
5534 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5539 + if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
5540 + xhci_err(xhci, "[MTK] not enough bandwidth\n");
5546 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
5547 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
5549 @@ -4467,8 +4613,14 @@ static u16 xhci_call_host_update_timeout
5552 if (state == USB3_LPM_U1)
5553 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5554 + if (xhci->quirks & XHCI_INTEL_HOST)
5556 return xhci_calculate_u1_timeout(xhci, udev, desc);
5557 else if (state == USB3_LPM_U2)
5558 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5559 + if (xhci->quirks & XHCI_INTEL_HOST)
5561 return xhci_calculate_u2_timeout(xhci, udev, desc);
5563 return USB3_LPM_DISABLED;
5564 @@ -4853,7 +5005,9 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5565 hcd->self.no_sg_constraint = 1;
5567 /* XHCI controllers don't stop the ep queue on short packets :| */
5568 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5569 hcd->self.no_stop_on_short = 1;
5572 if (usb_hcd_is_primary_hcd(hcd)) {
5573 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
5574 @@ -4926,6 +5080,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5575 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5576 xhci->hcc_params &= ~BIT(0);
5578 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5582 /* Set dma_mask and coherent_dma_mask to 64-bits,
5583 * if xHC supports 64-bit addressing */
5584 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5585 @@ -5020,8 +5178,57 @@ MODULE_DESCRIPTION(DRIVER_DESC);
5586 MODULE_AUTHOR(DRIVER_AUTHOR);
5587 MODULE_LICENSE("GPL");
5589 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5590 +static struct resource xhci_resouce[] = {
5592 + .name = "xhci-hcd",
5593 + .start = XHC_IO_START,
5594 + .end = XHC_IO_START + XHC_IO_LENGTH -1,
5595 + .flags = IORESOURCE_MEM,
5599 +static struct platform_device xhci_platform_dev = {
5600 + .name = "xhci-hcd",
5603 + .coherent_dma_mask = 0xffffffff,
5605 + .resource = xhci_resouce,
5609 static int __init xhci_hcd_init(void)
5611 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5612 + struct platform_device *pPlatformDev;
5614 + register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
5617 + if (u3phy_ops->u2_slew_rate_calibration) {
5618 + u3phy_ops->u2_slew_rate_calibration(u3phy);
5619 + u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
5622 + printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
5624 + u3phy_ops->init(u3phy);
5627 + pPlatformDev = &xhci_platform_dev;
5628 + memset(pPlatformDev, 0, sizeof(struct platform_device));
5629 + pPlatformDev->name = "xhci-hcd";
5630 + pPlatformDev->id = -1;
5631 + pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
5632 + pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
5633 + pPlatformDev->resource = xhci_resouce;
5634 + pPlatformDev->num_resources = ARRAY_SIZE(xhci_resouce);
5636 + platform_device_register(&xhci_platform_dev);
5641 * Check the compiler generated sizes of structures that must be laid
5642 * out in specific ways for hardware access.
5643 --- a/drivers/usb/host/xhci.h
5644 +++ b/drivers/usb/host/xhci.h
5646 #include "xhci-ext-caps.h"
5647 #include "pci-quirks.h"
5649 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5650 +#define XHC_IRQ (22 + 8)
5651 +#define XHC_IO_START 0x1E1C0000
5652 +#define XHC_IO_LENGTH 0x10000
5653 +/* mtk scheduler bitmasks */
5654 +#define BPKTS(p) ((p) & 0x3f)
5655 +#define BCSCOUNT(p) (((p) & 0x7) << 8)
5656 +#define BBM(p) ((p) << 11)
5657 +#define BOFFSET(p) ((p) & 0x3fff)
5658 +#define BREPEAT(p) (((p) & 0x7fff) << 16)
5664 /* xHCI PCI Configuration Registers */
5665 #define XHCI_SBRN_OFFSET (0x60)
5667 @@ -1590,8 +1605,12 @@ struct xhci_hcd {
5668 /* Compliance Mode Recovery Data */
5669 struct timer_list comp_mode_recovery_timer;
5671 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
5672 +#define COMP_MODE_RCVRY_MSECS 5000
5674 /* Compliance Mode Timer Triggered every 2 seconds */
5675 #define COMP_MODE_RCVRY_MSECS 2000
5679 /* convert between an HCD pointer and the corresponding EHCI_HCD */
5680 @@ -1739,6 +1758,26 @@ void xhci_urb_free_priv(struct xhci_hcd
5681 void xhci_free_command(struct xhci_hcd *xhci,
5682 struct xhci_command *command);
5684 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5685 +/* xHCI PCI glue */
5686 +int xhci_register_pci(void);
5687 +void xhci_unregister_pci(void);
5689 +static inline int xhci_register_pci(void) { return 0; }
5690 +static inline void xhci_unregister_pci(void) {}
5693 +#if defined(CONFIG_USB_XHCI_PLATFORM) \
5694 + || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
5695 +int xhci_register_plat(void);
5696 +void xhci_unregister_plat(void);
5698 +static inline int xhci_register_plat(void)
5700 +static inline void xhci_unregister_plat(void)
5704 /* xHCI host controller glue */
5705 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
5706 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,