1 From 2028cb37c941014f6a817d27a867ee1d37ccf2b6 Mon Sep 17 00:00:00 2001
2 From: "pi-cheng.chen" <pi-cheng.chen@linaro.org>
3 Date: Mon, 8 Jun 2015 20:29:21 +0800
4 Subject: [PATCH 33/76] cpufreq: mediatek: Add MT8173 cpufreq driver
6 This patch implements MT8173 cpufreq driver.
8 Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
10 drivers/cpufreq/Kconfig.arm | 7 +
11 drivers/cpufreq/Makefile | 1 +
12 drivers/cpufreq/mt8173-cpufreq.c | 550 ++++++++++++++++++++++++++++++++++++++
13 3 files changed, 558 insertions(+)
14 create mode 100644 drivers/cpufreq/mt8173-cpufreq.c
16 --- a/drivers/cpufreq/Kconfig.arm
17 +++ b/drivers/cpufreq/Kconfig.arm
18 @@ -141,6 +141,13 @@ config ARM_KIRKWOOD_CPUFREQ
19 This adds the CPUFreq driver for Marvell Kirkwood
22 +config ARM_MT8173_CPUFREQ
23 + bool "Mediatek MT8173 CPUFreq support"
24 + depends on ARCH_MEDIATEK && REGULATOR
27 + This adds the CPUFreq driver support for Mediatek MT8173 SoC.
29 config ARM_OMAP2PLUS_CPUFREQ
31 depends on ARCH_OMAP2PLUS
32 --- a/drivers/cpufreq/Makefile
33 +++ b/drivers/cpufreq/Makefile
34 @@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ) += h
35 obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
36 obj-$(CONFIG_ARM_INTEGRATOR) += integrator-cpufreq.o
37 obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
38 +obj-$(CONFIG_ARM_MT8173_CPUFREQ) += mt8173-cpufreq.o
39 obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
40 obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
41 obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
43 +++ b/drivers/cpufreq/mt8173-cpufreq.c
46 + * Copyright (c) 2015 Linaro Ltd.
47 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
49 + * This program is free software; you can redistribute it and/or modify
50 + * it under the terms of the GNU General Public License version 2 as
51 + * published by the Free Software Foundation.
53 + * This program is distributed in the hope that it will be useful,
54 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
55 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56 + * GNU General Public License for more details.
59 +#include <linux/clk.h>
60 +#include <linux/cpu.h>
61 +#include <linux/cpufreq.h>
62 +#include <linux/cpumask.h>
63 +#include <linux/module.h>
64 +#include <linux/of.h>
65 +#include <linux/platform_device.h>
66 +#include <linux/pm_opp.h>
67 +#include <linux/regulator/consumer.h>
68 +#include <linux/slab.h>
70 +#define MIN_VOLT_SHIFT (100000)
71 +#define MAX_VOLT_SHIFT (200000)
72 +#define MAX_VOLT_LIMIT (1150000)
73 +#define VOLT_TOL (10000)
76 + * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
77 + * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
78 + * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
79 + * voltage inputs need to be controlled under a hardware limitation:
80 + * 100mV < Vsram - Vproc < 200mV
82 + * When scaling the clock frequency of a CPU clock domain, the clock source
83 + * needs to be switched to another stable PLL clock temporarily until
84 + * the original PLL becomes stable at target frequency.
86 +struct mtk_cpu_dvfs_info {
87 + struct list_head node;
89 + struct cpufreq_frequency_table *freq_table;
90 + struct device *cpu_dev;
91 + struct regulator *proc_reg;
92 + struct regulator *sram_reg;
93 + struct clk *cpu_clk;
94 + struct clk *inter_clk;
95 + int intermediate_voltage;
96 + bool need_voltage_trace;
99 +static LIST_HEAD(cpu_dvfs_info_list);
101 +static inline struct mtk_cpu_dvfs_info *to_mtk_cpu_dvfs_info(
102 + struct list_head *list)
104 + return list_entry(list, struct mtk_cpu_dvfs_info, node);
107 +static inline void mtk_cpu_dvfs_info_add(struct mtk_cpu_dvfs_info *info)
109 + list_add(&info->node, &cpu_dvfs_info_list);
112 +static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_get(int cpu)
114 + struct mtk_cpu_dvfs_info *info;
115 + struct list_head *list;
117 + list_for_each(list, &cpu_dvfs_info_list) {
118 + info = to_mtk_cpu_dvfs_info(list);
120 + if (cpumask_test_cpu(cpu, info->cpus))
127 +static void mtk_cpu_dvfs_info_release(void)
129 + struct list_head *list, *tmp;
130 + struct mtk_cpu_dvfs_info *info;
132 + list_for_each_safe(list, tmp, &cpu_dvfs_info_list) {
133 + info = to_mtk_cpu_dvfs_info(list);
135 + dev_pm_opp_free_cpufreq_table(info->cpu_dev,
136 + &info->freq_table);
138 + if (!IS_ERR(info->proc_reg))
139 + regulator_put(info->proc_reg);
140 + if (!IS_ERR(info->sram_reg))
141 + regulator_put(info->sram_reg);
142 + if (!IS_ERR(info->cpu_clk))
143 + clk_put(info->cpu_clk);
144 + if (!IS_ERR(info->inter_clk))
145 + clk_put(info->inter_clk);
147 + of_free_opp_table(info->cpu_dev);
154 +#define MIN(a, b) ((a) < (b) ? (a) : (b))
155 +#define MAX(a, b) ((a) > (b) ? (a) : (b))
157 +static int mtk_cpufreq_voltage_trace(struct mtk_cpu_dvfs_info *info,
160 + struct regulator *proc_reg = info->proc_reg;
161 + struct regulator *sram_reg = info->sram_reg;
162 + int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
164 + old_vproc = regulator_get_voltage(proc_reg);
165 + old_vsram = regulator_get_voltage(sram_reg);
166 + /* Vsram should not exceed the maximum allowed voltage of SoC. */
167 + new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
169 + if (old_vproc < new_vproc) {
171 + * When scaling up voltages, Vsram and Vproc scale up step
172 + * by step. At each step, set Vsram to (Vproc + 200mV) first,
173 + * then set Vproc to (Vsram - 100mV).
174 + * Keep doing it until Vsram and Vproc hit target voltages.
177 + old_vsram = regulator_get_voltage(sram_reg);
178 + old_vproc = regulator_get_voltage(proc_reg);
180 + vsram = MIN(new_vsram, old_vproc + MAX_VOLT_SHIFT);
182 + if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
183 + vsram = MAX_VOLT_LIMIT;
186 + * If the target Vsram hits the maximum voltage,
187 + * try to set the exact voltage value first.
189 + ret = regulator_set_voltage(sram_reg, vsram,
192 + ret = regulator_set_voltage(sram_reg,
198 + ret = regulator_set_voltage(sram_reg, vsram,
201 + vproc = vsram - MIN_VOLT_SHIFT;
206 + ret = regulator_set_voltage(proc_reg, vproc,
209 + regulator_set_voltage(sram_reg, old_vsram,
213 + } while (vproc < new_vproc || vsram < new_vsram);
214 + } else if (old_vproc > new_vproc) {
216 + * When scaling down voltages, Vsram and Vproc scale down step
217 + * by step. At each step, set Vproc to (Vsram - 200mV) first,
218 + * then set Vproc to (Vproc + 100mV).
219 + * Keep doing it until Vsram and Vproc hit target voltages.
222 + old_vproc = regulator_get_voltage(proc_reg);
223 + old_vsram = regulator_get_voltage(sram_reg);
225 + vproc = MAX(new_vproc, old_vsram - MAX_VOLT_SHIFT);
226 + ret = regulator_set_voltage(proc_reg, vproc,
231 + if (vproc == new_vproc)
234 + vsram = MAX(new_vsram, vproc + MIN_VOLT_SHIFT);
236 + if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
237 + vsram = MAX_VOLT_LIMIT;
240 + * If the target Vsram hits the maximum voltage,
241 + * try to set the exact voltage value first.
243 + ret = regulator_set_voltage(sram_reg, vsram,
246 + ret = regulator_set_voltage(sram_reg,
250 + ret = regulator_set_voltage(sram_reg, vsram,
255 + regulator_set_voltage(proc_reg, old_vproc,
259 + } while (vproc > new_vproc + VOLT_TOL ||
260 + vsram > new_vsram + VOLT_TOL);
266 +static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
268 + if (info->need_voltage_trace)
269 + return mtk_cpufreq_voltage_trace(info, vproc);
271 + return regulator_set_voltage(info->proc_reg, vproc,
275 +static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
276 + unsigned int index)
278 + struct cpufreq_frequency_table *freq_table = policy->freq_table;
279 + struct clk *cpu_clk = policy->clk;
280 + struct clk *armpll = clk_get_parent(cpu_clk);
281 + struct mtk_cpu_dvfs_info *info = policy->driver_data;
282 + struct device *cpu_dev = info->cpu_dev;
283 + struct dev_pm_opp *opp;
284 + long freq_hz, old_freq_hz;
285 + int vproc, old_vproc, inter_vproc, target_vproc, ret;
287 + inter_vproc = info->intermediate_voltage;
289 + old_freq_hz = clk_get_rate(cpu_clk);
290 + old_vproc = regulator_get_voltage(info->proc_reg);
292 + freq_hz = freq_table[index].frequency * 1000;
294 + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
297 + pr_err("cpu%d: failed to find OPP for %ld\n",
298 + policy->cpu, freq_hz);
299 + return PTR_ERR(opp);
301 + vproc = dev_pm_opp_get_voltage(opp);
305 + * If the new voltage or the intermediate voltage is higher than the
306 + * current voltage, scale up voltage first.
308 + target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
309 + if (old_vproc < target_vproc) {
310 + ret = mtk_cpufreq_set_voltage(info, target_vproc);
312 + pr_err("cpu%d: failed to scale up voltage!\n",
314 + mtk_cpufreq_set_voltage(info, old_vproc);
319 + /* Reparent the CPU clock to intermediate clock. */
320 + ret = clk_set_parent(cpu_clk, info->inter_clk);
322 + pr_err("cpu%d: failed to re-parent cpu clock!\n",
324 + mtk_cpufreq_set_voltage(info, old_vproc);
329 + /* Set the original PLL to target rate. */
330 + ret = clk_set_rate(armpll, freq_hz);
332 + pr_err("cpu%d: failed to scale cpu clock rate!\n",
334 + clk_set_parent(cpu_clk, armpll);
335 + mtk_cpufreq_set_voltage(info, old_vproc);
339 + /* Set parent of CPU clock back to the original PLL. */
340 + ret = clk_set_parent(cpu_clk, armpll);
342 + pr_err("cpu%d: failed to re-parent cpu clock!\n",
344 + mtk_cpufreq_set_voltage(info, inter_vproc);
350 + * If the new voltage is lower than the intermediate voltage or the
351 + * original voltage, scale down to the new voltage.
353 + if (vproc < inter_vproc || vproc < old_vproc) {
354 + ret = mtk_cpufreq_set_voltage(info, vproc);
356 + pr_err("cpu%d: failed to scale down voltage!\n",
358 + clk_set_parent(cpu_clk, info->inter_clk);
359 + clk_set_rate(armpll, old_freq_hz);
360 + clk_set_parent(cpu_clk, armpll);
368 +static int mtk_cpufreq_init(struct cpufreq_policy *policy)
370 + struct mtk_cpu_dvfs_info *info;
373 + info = mtk_cpu_dvfs_info_get(policy->cpu);
375 + pr_err("%s: mtk cpu dvfs info for cpu%d is not initialized\n",
376 + __func__, policy->cpu);
380 + ret = cpufreq_table_validate_and_show(policy, info->freq_table);
382 + pr_err("%s: invalid frequency table: %d\n", __func__, ret);
386 + cpumask_copy(policy->cpus, info->cpus);
387 + policy->driver_data = info;
388 + policy->clk = info->cpu_clk;
393 +static struct cpufreq_driver mt8173_cpufreq_driver = {
394 + .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
395 + .verify = cpufreq_generic_frequency_table_verify,
396 + .target_index = mtk_cpufreq_set_target,
397 + .get = cpufreq_generic_get,
398 + .init = mtk_cpufreq_init,
399 + .name = "mtk-cpufreq",
400 + .attr = cpufreq_generic_attr,
403 +static int mtk_cpu_dvfs_info_init(int cpu)
405 + struct device *cpu_dev;
406 + struct regulator *proc_reg = ERR_PTR(-ENODEV);
407 + struct regulator *sram_reg = ERR_PTR(-ENODEV);
408 + struct clk *cpu_clk = ERR_PTR(-ENODEV);
409 + struct clk *inter_clk = ERR_PTR(-ENODEV);
410 + struct mtk_cpu_dvfs_info *info;
411 + struct cpufreq_frequency_table *freq_table;
412 + struct dev_pm_opp *opp;
413 + unsigned long rate;
416 + cpu_dev = get_cpu_device(cpu);
418 + pr_err("failed to get cpu%d device\n", cpu);
422 + ret = of_init_opp_table(cpu_dev);
424 + pr_warn("no OPP table for cpu%d\n", cpu);
428 + cpu_clk = clk_get(cpu_dev, "cpu");
429 + if (IS_ERR(cpu_clk)) {
430 + if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
431 + pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
433 + pr_err("failed to get cpu clk for cpu%d\n", cpu);
435 + ret = PTR_ERR(cpu_clk);
436 + goto out_free_opp_table;
439 + inter_clk = clk_get(cpu_dev, "intermediate");
440 + if (IS_ERR(inter_clk)) {
441 + if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
442 + pr_warn("intermediate clk for cpu%d not ready, retry.\n",
445 + pr_err("failed to get intermediate clk for cpu%d\n",
448 + ret = PTR_ERR(cpu_clk);
449 + goto out_free_resources;
452 + proc_reg = regulator_get_exclusive(cpu_dev, "proc");
453 + if (IS_ERR(proc_reg)) {
454 + if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
455 + pr_warn("proc regulator for cpu%d not ready, retry.\n",
458 + pr_err("failed to get proc regulator for cpu%d\n",
461 + ret = PTR_ERR(proc_reg);
462 + goto out_free_resources;
465 + /* Both presence and absence of sram regulator are valid cases. */
466 + sram_reg = regulator_get_exclusive(cpu_dev, "sram");
468 + info = kzalloc(sizeof(*info), GFP_KERNEL);
471 + goto out_free_resources;
474 + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
476 + pr_err("failed to init cpufreq table for cpu%d: %d\n",
478 + goto out_free_mtk_cpu_dvfs_info;
481 + if (!alloc_cpumask_var(&info->cpus, GFP_KERNEL))
482 + goto out_free_cpufreq_table;
484 + /* Search a safe voltage for intermediate frequency. */
485 + rate = clk_get_rate(inter_clk);
487 + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
489 + pr_err("failed to get intermediate opp for cpu%d\n", cpu);
490 + ret = PTR_ERR(opp);
491 + goto out_free_cpumask;
493 + info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
496 + /* CPUs in the same cluster share a clock and power domain. */
497 + cpumask_copy(info->cpus, &cpu_topology[cpu].core_sibling);
499 + info->cpu_dev = cpu_dev;
500 + info->proc_reg = proc_reg;
501 + info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
502 + info->cpu_clk = cpu_clk;
503 + info->inter_clk = inter_clk;
504 + info->freq_table = freq_table;
507 + * If SRAM regulator is present, software "voltage trace" is needed
508 + * for this CPU power domain.
510 + info->need_voltage_trace = !IS_ERR(sram_reg);
512 + mtk_cpu_dvfs_info_add(info);
517 + free_cpumask_var(info->cpus);
519 +out_free_cpufreq_table:
520 + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
522 +out_free_mtk_cpu_dvfs_info:
526 + if (!IS_ERR(proc_reg))
527 + regulator_put(proc_reg);
528 + if (!IS_ERR(sram_reg))
529 + regulator_put(sram_reg);
530 + if (!IS_ERR(cpu_clk))
532 + if (!IS_ERR(inter_clk))
533 + clk_put(inter_clk);
536 + of_free_opp_table(cpu_dev);
541 +static int mt8173_cpufreq_probe(struct platform_device *pdev)
545 + for_each_possible_cpu(cpu) {
547 + * If the struct mtk_cpu_dvfs_info for the cpu power domain
548 + * is already initialized, skip this CPU.
550 + if (!mtk_cpu_dvfs_info_get(cpu)) {
551 + ret = mtk_cpu_dvfs_info_init(cpu);
553 + if (ret != -EPROBE_DEFER)
554 + pr_err("%s probe fail\n", __func__);
556 + mtk_cpu_dvfs_info_release();
562 + ret = cpufreq_register_driver(&mt8173_cpufreq_driver);
564 + pr_err("failed to register mtk cpufreq driver\n");
565 + mtk_cpu_dvfs_info_release();
571 +static struct platform_driver mt8173_cpufreq_platdrv = {
573 + .name = "mt8173-cpufreq",
575 + .probe = mt8173_cpufreq_probe,
577 +module_platform_driver(mt8173_cpufreq_platdrv);
579 +static int mt8173_cpufreq_driver_init(void)
581 + struct platform_device *pdev;
583 + if (!of_machine_is_compatible("mediatek,mt8173"))
586 + pdev = platform_device_register_simple("mt8173-cpufreq", -1, NULL, 0);
587 + if (IS_ERR(pdev)) {
588 + pr_err("failed to register mtk-cpufreq platform device\n");
589 + return PTR_ERR(pdev);
594 +module_init(mt8173_cpufreq_driver_init);