1 From 8a0a335ed5d4f6c8455090f77ac57c0c25800070 Mon Sep 17 00:00:00 2001
2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 Date: Thu, 16 May 2013 17:55:22 +0200
4 Subject: [PATCH 06/29] pci: PCIe driver for Marvell Armada 370/XP systems
6 This driver implements the support for the PCIe interfaces on the
7 Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
8 cover earlier families of Marvell SoCs, such as Dove, Orion and
11 The driver implements the hw_pci operations needed by the core ARM PCI
12 code to setup PCI devices and get their corresponding IRQs, and the
13 pci_ops operations that are used by the PCI core to read/write the
14 configuration space of PCI devices.
16 Since the PCIe interfaces of Marvell SoCs are completely separate and
17 not linked together in a bus, this driver sets up an emulated PCI host
18 bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
21 In addition, this driver enumerates the different PCIe slots, and for
22 those having a device plugged in, it sets up the necessary address
23 decoding windows, using the mvebu-mbus driver.
25 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
26 Acked-by: Bjorn Helgaas <bhelgaas@google.com>
27 Signed-off-by: Jason Cooper <jason@lakedaemon.net>
29 .../devicetree/bindings/pci/mvebu-pci.txt | 220 ++++++
30 drivers/pci/Kconfig | 2 +
31 drivers/pci/Makefile | 3 +
32 drivers/pci/host/Kconfig | 8 +
33 drivers/pci/host/Makefile | 1 +
34 drivers/pci/host/pci-mvebu.c | 880 +++++++++++++++++++++
35 6 files changed, 1114 insertions(+)
36 create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
37 create mode 100644 drivers/pci/host/Kconfig
38 create mode 100644 drivers/pci/host/Makefile
39 create mode 100644 drivers/pci/host/pci-mvebu.c
42 +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
44 +* Marvell EBU PCIe interfaces
46 +Mandatory properties:
47 +- compatible: one of the following values:
48 + marvell,armada-370-pcie
49 + marvell,armada-xp-pcie
50 +- #address-cells, set to <3>
51 +- #size-cells, set to <2>
52 +- #interrupt-cells, set to <1>
53 +- bus-range: PCI bus numbers covered
54 +- device_type, set to "pci"
55 +- ranges: ranges for the PCI memory and I/O regions, as well as the
56 + MMIO registers to control the PCIe interfaces.
58 +In addition, the Device Tree node must have sub-nodes describing each
59 +PCIe interface, having the following mandatory properties:
60 +- reg: used only for interrupt mapping, so only the first four bytes
61 + are used to refer to the correct bus number and device number.
62 +- assigned-addresses: reference to the MMIO registers used to control
63 + this PCIe interface.
64 +- clocks: the clock associated to this PCIe interface
65 +- marvell,pcie-port: the physical PCIe port number
66 +- status: either "disabled" or "okay"
67 +- device_type, set to "pci"
68 +- #address-cells, set to <3>
69 +- #size-cells, set to <2>
70 +- #interrupt-cells, set to <1>
71 +- ranges, empty property.
72 +- interrupt-map-mask and interrupt-map, standard PCI properties to
73 + define the mapping of the PCIe interface to interrupt numbers.
75 +and the following optional properties:
76 +- marvell,pcie-lane: the physical PCIe lane number, for ports having
77 + multiple lanes. If this property is not found, we assume that the
83 + compatible = "marvell,armada-xp-pcie";
84 + status = "disabled";
85 + device_type = "pci";
87 + #address-cells = <3>;
90 + bus-range = <0x00 0xff>;
92 + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
93 + 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
94 + 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
95 + 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
96 + 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
97 + 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
98 + 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
99 + 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
100 + 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
101 + 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
102 + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
103 + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
106 + device_type = "pci";
107 + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
108 + reg = <0x0800 0 0 0 0>;
109 + #address-cells = <3>;
111 + #interrupt-cells = <1>;
113 + interrupt-map-mask = <0 0 0 0>;
114 + interrupt-map = <0 0 0 0 &mpic 58>;
115 + marvell,pcie-port = <0>;
116 + marvell,pcie-lane = <0>;
117 + clocks = <&gateclk 5>;
118 + status = "disabled";
122 + device_type = "pci";
123 + assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
124 + reg = <0x1000 0 0 0 0>;
125 + #address-cells = <3>;
127 + #interrupt-cells = <1>;
129 + interrupt-map-mask = <0 0 0 0>;
130 + interrupt-map = <0 0 0 0 &mpic 59>;
131 + marvell,pcie-port = <0>;
132 + marvell,pcie-lane = <1>;
133 + clocks = <&gateclk 6>;
134 + status = "disabled";
138 + device_type = "pci";
139 + assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
140 + reg = <0x1800 0 0 0 0>;
141 + #address-cells = <3>;
143 + #interrupt-cells = <1>;
145 + interrupt-map-mask = <0 0 0 0>;
146 + interrupt-map = <0 0 0 0 &mpic 60>;
147 + marvell,pcie-port = <0>;
148 + marvell,pcie-lane = <2>;
149 + clocks = <&gateclk 7>;
150 + status = "disabled";
154 + device_type = "pci";
155 + assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
156 + reg = <0x2000 0 0 0 0>;
157 + #address-cells = <3>;
159 + #interrupt-cells = <1>;
161 + interrupt-map-mask = <0 0 0 0>;
162 + interrupt-map = <0 0 0 0 &mpic 61>;
163 + marvell,pcie-port = <0>;
164 + marvell,pcie-lane = <3>;
165 + clocks = <&gateclk 8>;
166 + status = "disabled";
170 + device_type = "pci";
171 + assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
172 + reg = <0x2800 0 0 0 0>;
173 + #address-cells = <3>;
175 + #interrupt-cells = <1>;
177 + interrupt-map-mask = <0 0 0 0>;
178 + interrupt-map = <0 0 0 0 &mpic 62>;
179 + marvell,pcie-port = <1>;
180 + marvell,pcie-lane = <0>;
181 + clocks = <&gateclk 9>;
182 + status = "disabled";
186 + device_type = "pci";
187 + assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
188 + reg = <0x3000 0 0 0 0>;
189 + #address-cells = <3>;
191 + #interrupt-cells = <1>;
193 + interrupt-map-mask = <0 0 0 0>;
194 + interrupt-map = <0 0 0 0 &mpic 63>;
195 + marvell,pcie-port = <1>;
196 + marvell,pcie-lane = <1>;
197 + clocks = <&gateclk 10>;
198 + status = "disabled";
202 + device_type = "pci";
203 + assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
204 + reg = <0x3800 0 0 0 0>;
205 + #address-cells = <3>;
207 + #interrupt-cells = <1>;
209 + interrupt-map-mask = <0 0 0 0>;
210 + interrupt-map = <0 0 0 0 &mpic 64>;
211 + marvell,pcie-port = <1>;
212 + marvell,pcie-lane = <2>;
213 + clocks = <&gateclk 11>;
214 + status = "disabled";
218 + device_type = "pci";
219 + assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
220 + reg = <0x4000 0 0 0 0>;
221 + #address-cells = <3>;
223 + #interrupt-cells = <1>;
225 + interrupt-map-mask = <0 0 0 0>;
226 + interrupt-map = <0 0 0 0 &mpic 65>;
227 + marvell,pcie-port = <1>;
228 + marvell,pcie-lane = <3>;
229 + clocks = <&gateclk 12>;
230 + status = "disabled";
233 + device_type = "pci";
234 + assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
235 + reg = <0x4800 0 0 0 0>;
236 + #address-cells = <3>;
238 + #interrupt-cells = <1>;
240 + interrupt-map-mask = <0 0 0 0>;
241 + interrupt-map = <0 0 0 0 &mpic 99>;
242 + marvell,pcie-port = <2>;
243 + marvell,pcie-lane = <0>;
244 + clocks = <&gateclk 26>;
245 + status = "disabled";
249 + device_type = "pci";
250 + assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
251 + reg = <0x5000 0 0 0 0>;
252 + #address-cells = <3>;
254 + #interrupt-cells = <1>;
256 + interrupt-map-mask = <0 0 0 0>;
257 + interrupt-map = <0 0 0 0 &mpic 103>;
258 + marvell,pcie-port = <3>;
259 + marvell,pcie-lane = <0>;
260 + clocks = <&gateclk 27>;
261 + status = "disabled";
264 --- a/drivers/pci/Kconfig
265 +++ b/drivers/pci/Kconfig
266 @@ -125,3 +125,5 @@ config PCI_IOAPIC
268 def_bool y if (DMI || ACPI)
271 +source "drivers/pci/host/Kconfig"
272 --- a/drivers/pci/Makefile
273 +++ b/drivers/pci/Makefile
274 @@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen
275 obj-$(CONFIG_OF) += of.o
277 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
279 +# PCI host controller drivers
282 +++ b/drivers/pci/host/Kconfig
284 +menu "PCI host controller drivers"
288 + bool "Marvell EBU PCIe controller"
289 + depends on ARCH_MVEBU
293 +++ b/drivers/pci/host/Makefile
295 +obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
297 +++ b/drivers/pci/host/pci-mvebu.c
300 + * PCIe driver for Marvell Armada 370 and Armada XP SoCs
302 + * This file is licensed under the terms of the GNU General Public
303 + * License version 2. This program is licensed "as is" without any
304 + * warranty of any kind, whether express or implied.
307 +#include <linux/kernel.h>
308 +#include <linux/pci.h>
309 +#include <linux/clk.h>
310 +#include <linux/module.h>
311 +#include <linux/mbus.h>
312 +#include <linux/slab.h>
313 +#include <linux/platform_device.h>
314 +#include <linux/of_address.h>
315 +#include <linux/of_pci.h>
316 +#include <linux/of_irq.h>
317 +#include <linux/of_platform.h>
320 + * PCIe unit register offsets.
322 +#define PCIE_DEV_ID_OFF 0x0000
323 +#define PCIE_CMD_OFF 0x0004
324 +#define PCIE_DEV_REV_OFF 0x0008
325 +#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
326 +#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
327 +#define PCIE_HEADER_LOG_4_OFF 0x0128
328 +#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
329 +#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
330 +#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
331 +#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
332 +#define PCIE_WIN5_CTRL_OFF 0x1880
333 +#define PCIE_WIN5_BASE_OFF 0x1884
334 +#define PCIE_WIN5_REMAP_OFF 0x188c
335 +#define PCIE_CONF_ADDR_OFF 0x18f8
336 +#define PCIE_CONF_ADDR_EN 0x80000000
337 +#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
338 +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
339 +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
340 +#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
341 +#define PCIE_CONF_ADDR(bus, devfn, where) \
342 + (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
343 + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
345 +#define PCIE_CONF_DATA_OFF 0x18fc
346 +#define PCIE_MASK_OFF 0x1910
347 +#define PCIE_MASK_ENABLE_INTS 0x0f000000
348 +#define PCIE_CTRL_OFF 0x1a00
349 +#define PCIE_CTRL_X1_MODE 0x0001
350 +#define PCIE_STAT_OFF 0x1a04
351 +#define PCIE_STAT_BUS 0xff00
352 +#define PCIE_STAT_LINK_DOWN BIT(0)
353 +#define PCIE_DEBUG_CTRL 0x1a60
354 +#define PCIE_DEBUG_SOFT_RESET BIT(20)
357 + * This product ID is registered by Marvell, and used when the Marvell
358 + * SoC is not the root complex, but an endpoint on the PCIe bus. It is
359 + * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
362 +#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
364 +/* PCI configuration space of a PCI-to-PCI bridge */
365 +struct mvebu_sw_pci_bridge {
376 + u8 cache_line_size;
380 + u8 subordinate_bus;
381 + u8 secondary_latency_timer;
384 + u16 secondary_status;
390 + u32 preflimitupper;
402 +struct mvebu_pcie_port;
404 +/* Structure representing all PCIe interfaces */
406 + struct platform_device *pdev;
407 + struct mvebu_pcie_port *ports;
408 + struct resource io;
409 + struct resource realio;
410 + struct resource mem;
411 + struct resource busn;
415 +/* Structure representing one PCIe interface */
416 +struct mvebu_pcie_port {
418 + void __iomem *base;
419 + spinlock_t conf_lock;
425 + struct mvebu_sw_pci_bridge bridge;
426 + struct device_node *dn;
427 + struct mvebu_pcie *pcie;
428 + phys_addr_t memwin_base;
429 + size_t memwin_size;
430 + phys_addr_t iowin_base;
434 +static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
436 + return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
439 +static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
443 + stat = readl(port->base + PCIE_STAT_OFF);
444 + stat &= ~PCIE_STAT_BUS;
446 + writel(stat, port->base + PCIE_STAT_OFF);
450 + * Setup PCIE BARs and Address Decode Wins:
451 + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
452 + * WIN[0-3] -> DRAM bank[0-3]
454 +static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
456 + const struct mbus_dram_target_info *dram;
460 + dram = mv_mbus_dram_info();
462 + /* First, disable and clear BARs and windows. */
463 + for (i = 1; i < 3; i++) {
464 + writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
465 + writel(0, port->base + PCIE_BAR_LO_OFF(i));
466 + writel(0, port->base + PCIE_BAR_HI_OFF(i));
469 + for (i = 0; i < 5; i++) {
470 + writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
471 + writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
472 + writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
475 + writel(0, port->base + PCIE_WIN5_CTRL_OFF);
476 + writel(0, port->base + PCIE_WIN5_BASE_OFF);
477 + writel(0, port->base + PCIE_WIN5_REMAP_OFF);
479 + /* Setup windows for DDR banks. Count total DDR size on the fly. */
481 + for (i = 0; i < dram->num_cs; i++) {
482 + const struct mbus_dram_window *cs = dram->cs + i;
484 + writel(cs->base & 0xffff0000,
485 + port->base + PCIE_WIN04_BASE_OFF(i));
486 + writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
487 + writel(((cs->size - 1) & 0xffff0000) |
488 + (cs->mbus_attr << 8) |
489 + (dram->mbus_dram_target_id << 4) | 1,
490 + port->base + PCIE_WIN04_CTRL_OFF(i));
495 + /* Round up 'size' to the nearest power of two. */
496 + if ((size & (size - 1)) != 0)
497 + size = 1 << fls(size);
499 + /* Setup BAR[1] to all DRAM banks. */
500 + writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
501 + writel(0, port->base + PCIE_BAR_HI_OFF(1));
502 + writel(((size - 1) & 0xffff0000) | 1,
503 + port->base + PCIE_BAR_CTRL_OFF(1));
506 +static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
511 + /* Point PCIe unit MBUS decode windows to DRAM space. */
512 + mvebu_pcie_setup_wins(port);
514 + /* Master + slave enable. */
515 + cmd = readw(port->base + PCIE_CMD_OFF);
516 + cmd |= PCI_COMMAND_IO;
517 + cmd |= PCI_COMMAND_MEMORY;
518 + cmd |= PCI_COMMAND_MASTER;
519 + writew(cmd, port->base + PCIE_CMD_OFF);
521 + /* Enable interrupt lines A-D. */
522 + mask = readl(port->base + PCIE_MASK_OFF);
523 + mask |= PCIE_MASK_ENABLE_INTS;
524 + writel(mask, port->base + PCIE_MASK_OFF);
527 +static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
528 + struct pci_bus *bus,
529 + u32 devfn, int where, int size, u32 *val)
531 + writel(PCIE_CONF_ADDR(bus->number, devfn, where),
532 + port->base + PCIE_CONF_ADDR_OFF);
534 + *val = readl(port->base + PCIE_CONF_DATA_OFF);
537 + *val = (*val >> (8 * (where & 3))) & 0xff;
538 + else if (size == 2)
539 + *val = (*val >> (8 * (where & 3))) & 0xffff;
541 + return PCIBIOS_SUCCESSFUL;
544 +static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
545 + struct pci_bus *bus,
546 + u32 devfn, int where, int size, u32 val)
548 + int ret = PCIBIOS_SUCCESSFUL;
550 + writel(PCIE_CONF_ADDR(bus->number, devfn, where),
551 + port->base + PCIE_CONF_ADDR_OFF);
554 + writel(val, port->base + PCIE_CONF_DATA_OFF);
555 + else if (size == 2)
556 + writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
557 + else if (size == 1)
558 + writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
560 + ret = PCIBIOS_BAD_REGISTER_NUMBER;
565 +static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
567 + phys_addr_t iobase;
569 + /* Are the new iobase/iolimit values invalid? */
570 + if (port->bridge.iolimit < port->bridge.iobase ||
571 + port->bridge.iolimitupper < port->bridge.iobaseupper) {
573 + /* If a window was configured, remove it */
574 + if (port->iowin_base) {
575 + mvebu_mbus_del_window(port->iowin_base,
577 + port->iowin_base = 0;
578 + port->iowin_size = 0;
585 + * We read the PCI-to-PCI bridge emulated registers, and
586 + * calculate the base address and size of the address decoding
587 + * window to setup, according to the PCI-to-PCI bridge
588 + * specifications. iobase is the bus address, port->iowin_base
589 + * is the CPU address.
591 + iobase = ((port->bridge.iobase & 0xF0) << 8) |
592 + (port->bridge.iobaseupper << 16);
593 + port->iowin_base = port->pcie->io.start + iobase;
594 + port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
595 + (port->bridge.iolimitupper << 16)) -
598 + mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
601 + MVEBU_MBUS_PCI_IO);
603 + pci_ioremap_io(iobase, port->iowin_base);
606 +static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
608 + /* Are the new membase/memlimit values invalid? */
609 + if (port->bridge.memlimit < port->bridge.membase) {
611 + /* If a window was configured, remove it */
612 + if (port->memwin_base) {
613 + mvebu_mbus_del_window(port->memwin_base,
614 + port->memwin_size);
615 + port->memwin_base = 0;
616 + port->memwin_size = 0;
623 + * We read the PCI-to-PCI bridge emulated registers, and
624 + * calculate the base address and size of the address decoding
625 + * window to setup, according to the PCI-to-PCI bridge
628 + port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
629 + port->memwin_size =
630 + (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
633 + mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
635 + MVEBU_MBUS_NO_REMAP,
636 + MVEBU_MBUS_PCI_MEM);
640 + * Initialize the configuration space of the PCI-to-PCI bridge
641 + * associated with the given PCIe interface.
643 +static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
645 + struct mvebu_sw_pci_bridge *bridge = &port->bridge;
647 + memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
649 + bridge->status = PCI_STATUS_CAP_LIST;
650 + bridge->class = PCI_CLASS_BRIDGE_PCI;
651 + bridge->vendor = PCI_VENDOR_ID_MARVELL;
652 + bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
653 + bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
654 + bridge->cache_line_size = 0x10;
656 + /* We support 32 bits I/O addressing */
657 + bridge->iobase = PCI_IO_RANGE_TYPE_32;
658 + bridge->iolimit = PCI_IO_RANGE_TYPE_32;
662 + * Read the configuration space of the PCI-to-PCI bridge associated to
663 + * the given PCIe interface.
665 +static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
666 + unsigned int where, int size, u32 *value)
668 + struct mvebu_sw_pci_bridge *bridge = &port->bridge;
670 + switch (where & ~3) {
671 + case PCI_VENDOR_ID:
672 + *value = bridge->device << 16 | bridge->vendor;
676 + *value = bridge->status << 16 | bridge->command;
679 + case PCI_CLASS_REVISION:
680 + *value = bridge->class << 16 | bridge->interface << 8 |
684 + case PCI_CACHE_LINE_SIZE:
685 + *value = bridge->bist << 24 | bridge->header_type << 16 |
686 + bridge->latency_timer << 8 | bridge->cache_line_size;
689 + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
690 + *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
693 + case PCI_PRIMARY_BUS:
694 + *value = (bridge->secondary_latency_timer << 24 |
695 + bridge->subordinate_bus << 16 |
696 + bridge->secondary_bus << 8 |
697 + bridge->primary_bus);
701 + *value = (bridge->secondary_status << 16 |
702 + bridge->iolimit << 8 |
706 + case PCI_MEMORY_BASE:
707 + *value = (bridge->memlimit << 16 | bridge->membase);
710 + case PCI_PREF_MEMORY_BASE:
711 + *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
714 + case PCI_PREF_BASE_UPPER32:
715 + *value = bridge->prefbaseupper;
718 + case PCI_PREF_LIMIT_UPPER32:
719 + *value = bridge->preflimitupper;
722 + case PCI_IO_BASE_UPPER16:
723 + *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
726 + case PCI_ROM_ADDRESS1:
731 + *value = 0xffffffff;
732 + return PCIBIOS_BAD_REGISTER_NUMBER;
736 + *value = (*value >> (8 * (where & 3))) & 0xffff;
737 + else if (size == 1)
738 + *value = (*value >> (8 * (where & 3))) & 0xff;
740 + return PCIBIOS_SUCCESSFUL;
743 +/* Write to the PCI-to-PCI bridge configuration space */
744 +static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
745 + unsigned int where, int size, u32 value)
747 + struct mvebu_sw_pci_bridge *bridge = &port->bridge;
753 + else if (size == 2)
754 + mask = ~(0xffff << ((where & 3) * 8));
755 + else if (size == 1)
756 + mask = ~(0xff << ((where & 3) * 8));
758 + return PCIBIOS_BAD_REGISTER_NUMBER;
760 + err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
764 + value = (reg & mask) | value << ((where & 3) * 8);
766 + switch (where & ~3) {
768 + bridge->command = value & 0xffff;
769 + bridge->status = value >> 16;
772 + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
773 + bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
778 + * We also keep bit 1 set, it is a read-only bit that
779 + * indicates we support 32 bits addressing for the
782 + bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
783 + bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
784 + bridge->secondary_status = value >> 16;
785 + mvebu_pcie_handle_iobase_change(port);
788 + case PCI_MEMORY_BASE:
789 + bridge->membase = value & 0xffff;
790 + bridge->memlimit = value >> 16;
791 + mvebu_pcie_handle_membase_change(port);
794 + case PCI_PREF_MEMORY_BASE:
795 + bridge->prefmembase = value & 0xffff;
796 + bridge->prefmemlimit = value >> 16;
799 + case PCI_PREF_BASE_UPPER32:
800 + bridge->prefbaseupper = value;
803 + case PCI_PREF_LIMIT_UPPER32:
804 + bridge->preflimitupper = value;
807 + case PCI_IO_BASE_UPPER16:
808 + bridge->iobaseupper = value & 0xffff;
809 + bridge->iolimitupper = value >> 16;
810 + mvebu_pcie_handle_iobase_change(port);
813 + case PCI_PRIMARY_BUS:
814 + bridge->primary_bus = value & 0xff;
815 + bridge->secondary_bus = (value >> 8) & 0xff;
816 + bridge->subordinate_bus = (value >> 16) & 0xff;
817 + bridge->secondary_latency_timer = (value >> 24) & 0xff;
818 + mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
825 + return PCIBIOS_SUCCESSFUL;
828 +static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
830 + return sys->private_data;
833 +static struct mvebu_pcie_port *
834 +mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
839 + for (i = 0; i < pcie->nports; i++) {
840 + struct mvebu_pcie_port *port = &pcie->ports[i];
841 + if (bus->number == 0 && port->devfn == devfn)
843 + if (bus->number != 0 &&
844 + port->bridge.secondary_bus == bus->number)
851 +/* PCI configuration space write function */
852 +static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
853 + int where, int size, u32 val)
855 + struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
856 + struct mvebu_pcie_port *port;
857 + unsigned long flags;
860 + port = mvebu_pcie_find_port(pcie, bus, devfn);
862 + return PCIBIOS_DEVICE_NOT_FOUND;
864 + /* Access the emulated PCI-to-PCI bridge */
865 + if (bus->number == 0)
866 + return mvebu_sw_pci_bridge_write(port, where, size, val);
868 + if (!port->haslink || PCI_SLOT(devfn) != 0)
869 + return PCIBIOS_DEVICE_NOT_FOUND;
871 + /* Access the real PCIe interface */
872 + spin_lock_irqsave(&port->conf_lock, flags);
873 + ret = mvebu_pcie_hw_wr_conf(port, bus,
874 + PCI_DEVFN(1, PCI_FUNC(devfn)),
876 + spin_unlock_irqrestore(&port->conf_lock, flags);
881 +/* PCI configuration space read function */
882 +static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
883 + int size, u32 *val)
885 + struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
886 + struct mvebu_pcie_port *port;
887 + unsigned long flags;
890 + port = mvebu_pcie_find_port(pcie, bus, devfn);
893 + return PCIBIOS_DEVICE_NOT_FOUND;
896 + /* Access the emulated PCI-to-PCI bridge */
897 + if (bus->number == 0)
898 + return mvebu_sw_pci_bridge_read(port, where, size, val);
900 + if (!port->haslink || PCI_SLOT(devfn) != 0) {
902 + return PCIBIOS_DEVICE_NOT_FOUND;
905 + /* Access the real PCIe interface */
906 + spin_lock_irqsave(&port->conf_lock, flags);
907 + ret = mvebu_pcie_hw_rd_conf(port, bus,
908 + PCI_DEVFN(1, PCI_FUNC(devfn)),
910 + spin_unlock_irqrestore(&port->conf_lock, flags);
915 +static struct pci_ops mvebu_pcie_ops = {
916 + .read = mvebu_pcie_rd_conf,
917 + .write = mvebu_pcie_wr_conf,
920 +static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
922 + struct mvebu_pcie *pcie = sys_to_pcie(sys);
925 + pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
926 + pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
927 + pci_add_resource(&sys->resources, &pcie->busn);
929 + for (i = 0; i < pcie->nports; i++) {
930 + struct mvebu_pcie_port *port = &pcie->ports[i];
931 + mvebu_pcie_setup_hw(port);
937 +static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
939 + struct of_irq oirq;
942 + ret = of_irq_map_pci(dev, &oirq);
946 + return irq_create_of_mapping(oirq.controller, oirq.specifier,
950 +static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
952 + struct mvebu_pcie *pcie = sys_to_pcie(sys);
953 + struct pci_bus *bus;
955 + bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
956 + &mvebu_pcie_ops, sys, &sys->resources);
960 + pci_scan_child_bus(bus);
965 +resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
966 + const struct resource *res,
967 + resource_size_t start,
968 + resource_size_t size,
969 + resource_size_t align)
971 + if (dev->bus->number != 0)
975 + * On the PCI-to-PCI bridge side, the I/O windows must have at
976 + * least a 64 KB size and be aligned on their size, and the
977 + * memory windows must have at least a 1 MB size and be
978 + * aligned on their size
980 + if (res->flags & IORESOURCE_IO)
981 + return round_up(start, max((resource_size_t)SZ_64K, size));
982 + else if (res->flags & IORESOURCE_MEM)
983 + return round_up(start, max((resource_size_t)SZ_1M, size));
988 +static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
992 + memset(&hw, 0, sizeof(hw));
994 + hw.nr_controllers = 1;
995 + hw.private_data = (void **)&pcie;
996 + hw.setup = mvebu_pcie_setup;
997 + hw.scan = mvebu_pcie_scan_bus;
998 + hw.map_irq = mvebu_pcie_map_irq;
999 + hw.ops = &mvebu_pcie_ops;
1000 + hw.align_resource = mvebu_pcie_align_resource;
1002 + pci_common_init(&hw);
1006 + * Looks up the list of register addresses encoded into the reg =
1007 + * <...> property for one that matches the given port/lane. Once
1010 +static void __iomem * __init
1011 +mvebu_pcie_map_registers(struct platform_device *pdev,
1012 + struct device_node *np,
1013 + struct mvebu_pcie_port *port)
1015 + struct resource regs;
1018 + ret = of_address_to_resource(np, 0, ®s);
1022 + return devm_request_and_ioremap(&pdev->dev, ®s);
1025 +static int __init mvebu_pcie_probe(struct platform_device *pdev)
1027 + struct mvebu_pcie *pcie;
1028 + struct device_node *np = pdev->dev.of_node;
1029 + struct of_pci_range range;
1030 + struct of_pci_range_parser parser;
1031 + struct device_node *child;
1034 + pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
1039 + pcie->pdev = pdev;
1041 + if (of_pci_range_parser_init(&parser, np))
1044 + /* Get the I/O and memory ranges from DT */
1045 + for_each_of_pci_range(&parser, &range) {
1046 + unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
1047 + if (restype == IORESOURCE_IO) {
1048 + of_pci_range_to_resource(&range, np, &pcie->io);
1049 + of_pci_range_to_resource(&range, np, &pcie->realio);
1050 + pcie->io.name = "I/O";
1051 + pcie->realio.start = max_t(resource_size_t,
1054 + pcie->realio.end = min_t(resource_size_t,
1056 + range.pci_addr + range.size);
1058 + if (restype == IORESOURCE_MEM) {
1059 + of_pci_range_to_resource(&range, np, &pcie->mem);
1060 + pcie->mem.name = "MEM";
1064 + /* Get the bus range */
1065 + ret = of_pci_parse_bus_range(np, &pcie->busn);
1067 + dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
1072 + for_each_child_of_node(pdev->dev.of_node, child) {
1073 + if (!of_device_is_available(child))
1078 + pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
1079 + sizeof(struct mvebu_pcie_port),
1085 + for_each_child_of_node(pdev->dev.of_node, child) {
1086 + struct mvebu_pcie_port *port = &pcie->ports[i];
1088 + if (!of_device_is_available(child))
1091 + port->pcie = pcie;
1093 + if (of_property_read_u32(child, "marvell,pcie-port",
1095 + dev_warn(&pdev->dev,
1096 + "ignoring PCIe DT node, missing pcie-port property\n");
1100 + if (of_property_read_u32(child, "marvell,pcie-lane",
1104 + port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
1105 + port->port, port->lane);
1107 + port->devfn = of_pci_get_devfn(child);
1108 + if (port->devfn < 0)
1111 + port->base = mvebu_pcie_map_registers(pdev, child, port);
1112 + if (!port->base) {
1113 + dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
1114 + port->port, port->lane);
1118 + if (mvebu_pcie_link_up(port)) {
1119 + port->haslink = 1;
1120 + dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
1121 + port->port, port->lane);
1123 + port->haslink = 0;
1124 + dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
1125 + port->port, port->lane);
1128 + port->clk = of_clk_get_by_name(child, NULL);
1130 + dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
1131 + port->port, port->lane);
1132 + iounmap(port->base);
1133 + port->haslink = 0;
1139 + clk_prepare_enable(port->clk);
1140 + spin_lock_init(&port->conf_lock);
1142 + mvebu_sw_pci_bridge_init(port);
1147 + mvebu_pcie_enable(pcie);
1152 +static const struct of_device_id mvebu_pcie_of_match_table[] = {
1153 + { .compatible = "marvell,armada-xp-pcie", },
1154 + { .compatible = "marvell,armada-370-pcie", },
1157 +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1159 +static struct platform_driver mvebu_pcie_driver = {
1161 + .owner = THIS_MODULE,
1162 + .name = "mvebu-pcie",
1164 + of_match_ptr(mvebu_pcie_of_match_table),
1168 +static int __init mvebu_pcie_init(void)
1170 + return platform_driver_probe(&mvebu_pcie_driver,
1171 + mvebu_pcie_probe);
1174 +subsys_initcall(mvebu_pcie_init);
1176 +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1177 +MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1178 +MODULE_LICENSE("GPLv2");