1 From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Mon, 11 May 2015 12:29:18 -0700
4 Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms
6 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++
10 arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++
11 3 files changed, 160 insertions(+)
13 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
14 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
20 + rgmii2_pins: rgmii2_pins {
22 + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
23 + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
24 + function = "rgmii2";
25 + drive-strength = <8>;
37 + gmac1: ethernet@37200000 {
40 + phy-handle = <&phy4>;
43 + pinctrl-0 = <&rgmii2_pins>;
44 + pinctrl-names = "default";
47 + gmac2: ethernet@37400000 {
60 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
61 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
67 + rgmii0_pins: rgmii0_pins {
69 + pins = "gpio2", "gpio66";
70 + drive-strength = <8>;
76 gsbi2: gsbi@12480000 {
82 + gmac0: ethernet@37000000 {
86 + phy-handle = <&phy4>;
88 + pinctrl-0 = <&rgmii0_pins>;
89 + pinctrl-names = "default";
92 + gmac1: ethernet@37200000 {
103 + gmac2: ethernet@37400000 {
105 + phy-mode = "sgmii";
107 + phy-handle = <&phy6>;
110 + gmac3: ethernet@37600000 {
112 + phy-mode = "sgmii";
114 + phy-handle = <&phy7>;
118 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
119 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
124 + nss_common: syscon@03000000 {
125 + compatible = "syscon";
126 + reg = <0x03000000 0x0000FFFF>;
129 + qsgmii_csr: syscon@1bb00000 {
130 + compatible = "syscon";
131 + reg = <0x1bb00000 0x000001FF>;
134 + gmac0: ethernet@37000000 {
135 + device_type = "network";
136 + compatible = "qcom,ipq806x-gmac";
137 + reg = <0x37000000 0x200000>;
138 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
139 + interrupt-names = "macirq";
141 + qcom,nss-common = <&nss_common>;
142 + qcom,qsgmii-csr = <&qsgmii_csr>;
144 + clocks = <&gcc GMAC_CORE1_CLK>;
145 + clock-names = "stmmaceth";
147 + resets = <&gcc GMAC_CORE1_RESET>;
148 + reset-names = "stmmaceth";
150 + status = "disabled";
153 + gmac1: ethernet@37200000 {
154 + device_type = "network";
155 + compatible = "qcom,ipq806x-gmac";
156 + reg = <0x37200000 0x200000>;
157 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
158 + interrupt-names = "macirq";
160 + qcom,nss-common = <&nss_common>;
161 + qcom,qsgmii-csr = <&qsgmii_csr>;
163 + clocks = <&gcc GMAC_CORE2_CLK>;
164 + clock-names = "stmmaceth";
166 + resets = <&gcc GMAC_CORE2_RESET>;
167 + reset-names = "stmmaceth";
169 + status = "disabled";
172 + gmac2: ethernet@37400000 {
173 + device_type = "network";
174 + compatible = "qcom,ipq806x-gmac";
175 + reg = <0x37400000 0x200000>;
176 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
177 + interrupt-names = "macirq";
179 + qcom,nss-common = <&nss_common>;
180 + qcom,qsgmii-csr = <&qsgmii_csr>;
182 + clocks = <&gcc GMAC_CORE3_CLK>;
183 + clock-names = "stmmaceth";
185 + resets = <&gcc GMAC_CORE3_RESET>;
186 + reset-names = "stmmaceth";
188 + status = "disabled";
191 + gmac3: ethernet@37600000 {
192 + device_type = "network";
193 + compatible = "qcom,ipq806x-gmac";
194 + reg = <0x37600000 0x200000>;
195 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
196 + interrupt-names = "macirq";
198 + qcom,nss-common = <&nss_common>;
199 + qcom,qsgmii-csr = <&qsgmii_csr>;
201 + clocks = <&gcc GMAC_CORE4_CLK>;
202 + clock-names = "stmmaceth";
204 + resets = <&gcc GMAC_CORE4_RESET>;
205 + reset-names = "stmmaceth";
207 + status = "disabled";
212 sfpb_mutex: sfpb-mutex {