1 From 355bf7c6410f5b6e37b5c2b28ebe59bb701c42d6 Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Wed, 28 May 2014 12:12:40 -0500
4 Subject: [PATCH 093/182] ARM: dts: qcom: Update msm8660 device trees
6 * Move SoC peripherals into an SoC container node
7 * Move serial enabling into board file (qcom-msm8660-surf.dts)
8 * Cleanup cpu node to match binding spec, enable-method and compatible
9 should be per cpu, not part of the container
10 * Add GSBI node and configuration of GSBI controller
12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
14 arch/arm/boot/dts/qcom-msm8660-surf.dts | 10 +++
15 arch/arm/boot/dts/qcom-msm8660.dtsi | 115 ++++++++++++++++++-------------
16 2 files changed, 78 insertions(+), 47 deletions(-)
18 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
19 +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
22 model = "Qualcomm MSM8660 SURF";
23 compatible = "qcom,msm8660-surf", "qcom,msm8660";
28 + qcom,mode = <GSBI_PROT_I2C_UART>;
35 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi
36 +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
38 /include/ "skeleton.dtsi"
40 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
41 +#include <dt-bindings/soc/qcom,gsbi.h>
44 model = "Qualcomm MSM8660";
49 - compatible = "qcom,scorpion";
50 - enable-method = "qcom,gcc-msm8660";
53 + compatible = "qcom,scorpion";
54 + enable-method = "qcom,gcc-msm8660";
57 next-level-cache = <&L2>;
61 + compatible = "qcom,scorpion";
62 + enable-method = "qcom,gcc-msm8660";
65 next-level-cache = <&L2>;
70 - intc: interrupt-controller@2080000 {
71 - compatible = "qcom,msm-8660-qgic";
72 - interrupt-controller;
73 - #interrupt-cells = <3>;
74 - reg = < 0x02080000 0x1000 >,
75 - < 0x02081000 0x1000 >;
78 + #address-cells = <1>;
81 + compatible = "simple-bus";
83 + intc: interrupt-controller@2080000 {
84 + compatible = "qcom,msm-8660-qgic";
85 + interrupt-controller;
86 + #interrupt-cells = <3>;
87 + reg = < 0x02080000 0x1000 >,
88 + < 0x02081000 0x1000 >;
92 - compatible = "qcom,scss-timer", "qcom,msm-timer";
93 - interrupts = <1 0 0x301>,
96 - reg = <0x02000000 0x100>;
97 - clock-frequency = <27000000>,
99 - cpu-offset = <0x40000>;
102 + compatible = "qcom,scss-timer", "qcom,msm-timer";
103 + interrupts = <1 0 0x301>,
106 + reg = <0x02000000 0x100>;
107 + clock-frequency = <27000000>,
109 + cpu-offset = <0x40000>;
112 - msmgpio: gpio@800000 {
113 - compatible = "qcom,msm-gpio";
114 - reg = <0x00800000 0x4000>;
118 - interrupts = <0 16 0x4>;
119 - interrupt-controller;
120 - #interrupt-cells = <2>;
122 + msmgpio: gpio@800000 {
123 + compatible = "qcom,msm-gpio";
124 + reg = <0x00800000 0x4000>;
128 + interrupts = <0 16 0x4>;
129 + interrupt-controller;
130 + #interrupt-cells = <2>;
133 - gcc: clock-controller@900000 {
134 - compatible = "qcom,gcc-msm8660";
135 - #clock-cells = <1>;
136 - #reset-cells = <1>;
137 - reg = <0x900000 0x4000>;
139 + gcc: clock-controller@900000 {
140 + compatible = "qcom,gcc-msm8660";
141 + #clock-cells = <1>;
142 + #reset-cells = <1>;
143 + reg = <0x900000 0x4000>;
147 - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
148 - reg = <0x19c40000 0x1000>,
149 - <0x19c00000 0x1000>;
150 - interrupts = <0 195 0x0>;
151 - clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
152 - clock-names = "core", "iface";
154 + gsbi12: gsbi@19c00000 {
155 + compatible = "qcom,gsbi-v1.0.0";
156 + reg = <0x19c00000 0x100>;
157 + clocks = <&gcc GSBI12_H_CLK>;
158 + clock-names = "iface";
159 + #address-cells = <1>;
164 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
165 + reg = <0x19c40000 0x1000>,
166 + <0x19c00000 0x1000>;
167 + interrupts = <0 195 0x0>;
168 + clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
169 + clock-names = "core", "iface";
170 + status = "disabled";
175 - compatible = "qcom,ssbi";
176 - reg = <0x500000 0x1000>;
177 - qcom,controller-type = "pmic-arbiter";
179 + compatible = "qcom,ssbi";
180 + reg = <0x500000 0x1000>;
181 + qcom,controller-type = "pmic-arbiter";