target/linux/ipq806x/patches/0013-ARM-qcom-Add-SMP-support-for-KPSSv1.patch

   1 From 8e843640b3c4a43b963332fdc7b233948ad25a5b Mon Sep 17 00:00:00 2001
   2 From: Rohit Vaswani <rvaswani@codeaurora.org>
   3 Date: Tue, 21 May 2013 19:13:50 -0700
   4 Subject: [PATCH 013/182] ARM: qcom: Add SMP support for KPSSv1
   5
   6 Implement support for the Krait CPU release sequence when the
   7 CPUs are part of the first version of the krait processor
   8 subsystem.
   9
  10 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
  11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  13 ---
  14  arch/arm/mach-qcom/platsmp.c  |  106 +++++++++++++++++++++++++++++++++++++++++
  15  arch/arm/mach-qcom/scm-boot.h |    8 ++--
  16  2 files changed, 111 insertions(+), 3 deletions(-)
  17
  18 --- a/arch/arm/mach-qcom/platsmp.c
  19 +++ b/arch/arm/mach-qcom/platsmp.c
  20 @@ -26,6 +26,16 @@
  21  #define SCSS_CPU1CORE_RESET            0x2d80
  22  #define SCSS_DBG_STATUS_CORE_PWRDUP    0x2e64
  23
  24 +#define APCS_CPU_PWR_CTL       0x04
  25 +#define PLL_CLAMP              BIT(8)
  26 +#define CORE_PWRD_UP           BIT(7)
  27 +#define COREPOR_RST            BIT(5)
  28 +#define CORE_RST               BIT(4)
  29 +#define L2DT_SLP               BIT(3)
  30 +#define CLAMP                  BIT(0)
  31 +
  32 +#define APCS_SAW2_VCTL         0x14
  33 +
  34  extern void secondary_startup(void);
  35
  36  static DEFINE_SPINLOCK(boot_lock);
  37 @@ -71,6 +81,85 @@ static int scss_release_secondary(unsign
  38         return 0;
  39  }
  40
  41 +static int kpssv1_release_secondary(unsigned int cpu)
  42 +{
  43 +       int ret = 0;
  44 +       void __iomem *reg, *saw_reg;
  45 +       struct device_node *cpu_node, *acc_node, *saw_node;
  46 +       u32 val;
  47 +
  48 +       cpu_node = of_get_cpu_node(cpu, NULL);
  49 +       if (!cpu_node)
  50 +               return -ENODEV;
  51 +
  52 +       acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
  53 +       if (!acc_node) {
  54 +               ret = -ENODEV;
  55 +               goto out_acc;
  56 +       }
  57 +
  58 +       saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
  59 +       if (!saw_node) {
  60 +               ret = -ENODEV;
  61 +               goto out_saw;
  62 +       }
  63 +
  64 +       reg = of_iomap(acc_node, 0);
  65 +       if (!reg) {
  66 +               ret = -ENOMEM;
  67 +               goto out_acc_map;
  68 +       }
  69 +
  70 +       saw_reg = of_iomap(saw_node, 0);
  71 +       if (!saw_reg) {
  72 +               ret = -ENOMEM;
  73 +               goto out_saw_map;
  74 +       }
  75 +
  76 +       /* Turn on CPU rail */
  77 +       writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
  78 +       mb();
  79 +       udelay(512);
  80 +
  81 +       /* Krait bring-up sequence */
  82 +       val = PLL_CLAMP | L2DT_SLP | CLAMP;
  83 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
  84 +       val &= ~L2DT_SLP;
  85 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
  86 +       mb();
  87 +       ndelay(300);
  88 +
  89 +       val |= COREPOR_RST;
  90 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
  91 +       mb();
  92 +       udelay(2);
  93 +
  94 +       val &= ~CLAMP;
  95 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
  96 +       mb();
  97 +       udelay(2);
  98 +
  99 +       val &= ~COREPOR_RST;
 100 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
 101 +       mb();
 102 +       udelay(100);
 103 +
 104 +       val |= CORE_PWRD_UP;
 105 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
 106 +       mb();
 107 +
 108 +       iounmap(saw_reg);
 109 +out_saw_map:
 110 +       iounmap(reg);
 111 +out_acc_map:
 112 +       of_node_put(saw_node);
 113 +out_saw:
 114 +       of_node_put(acc_node);
 115 +out_acc:
 116 +       of_node_put(cpu_node);
 117 +       return ret;
 118 +}
 119 +
 120  static DEFINE_PER_CPU(int, cold_boot_done);
 121
 122  static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
 123 @@ -110,6 +199,11 @@ static int msm8660_boot_secondary(unsign
 124         return qcom_boot_secondary(cpu, scss_release_secondary);
 125  }
 126
 127 +static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
 128 +{
 129 +       return qcom_boot_secondary(cpu, kpssv1_release_secondary);
 130 +}
 131 +
 132  static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
 133  {
 134         int cpu, map;
 135 @@ -117,6 +211,8 @@ static void __init qcom_smp_prepare_cpus
 136         static const int cold_boot_flags[] = {
 137                 0,
 138                 SCM_FLAG_COLDBOOT_CPU1,
 139 +               SCM_FLAG_COLDBOOT_CPU2,
 140 +               SCM_FLAG_COLDBOOT_CPU3,
 141         };
 142
 143         for_each_present_cpu(cpu) {
 144 @@ -147,3 +243,13 @@ static struct smp_operations smp_msm8660
 145  #endif
 146  };
 147  CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
 148 +
 149 +static struct smp_operations qcom_smp_kpssv1_ops __initdata = {
 150 +       .smp_prepare_cpus       = qcom_smp_prepare_cpus,
 151 +       .smp_secondary_init     = qcom_secondary_init,
 152 +       .smp_boot_secondary     = kpssv1_boot_secondary,
 153 +#ifdef CONFIG_HOTPLUG_CPU
 154 +       .cpu_die                = qcom_cpu_die,
 155 +#endif
 156 +};
 157 +CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
 158 --- a/arch/arm/mach-qcom/scm-boot.h
 159 +++ b/arch/arm/mach-qcom/scm-boot.h
 160 @@ -13,9 +13,11 @@
 161  #define __MACH_SCM_BOOT_H
 162
 163  #define SCM_BOOT_ADDR                  0x1
 164 -#define SCM_FLAG_COLDBOOT_CPU1         0x1
 165 -#define SCM_FLAG_WARMBOOT_CPU1         0x2
 166 -#define SCM_FLAG_WARMBOOT_CPU0         0x4
 167 +#define SCM_FLAG_COLDBOOT_CPU1         0x01
 168 +#define SCM_FLAG_COLDBOOT_CPU2         0x08
 169 +#define SCM_FLAG_COLDBOOT_CPU3         0x20
 170 +#define SCM_FLAG_WARMBOOT_CPU0         0x04
 171 +#define SCM_FLAG_WARMBOOT_CPU1         0x02
 172
 173  int scm_set_boot_addr(phys_addr_t addr, int flags);
 174