1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -75,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
4 config BCMA_DRIVER_GPIO
5 bool "BCMA GPIO driver"
6 depends on BCMA && GPIOLIB
7 + select IRQ_DOMAIN if BCMA_HOST_SOC
9 Driver to provide access to the GPIO pins of the bcma bus.
11 --- a/drivers/bcma/Makefile
12 +++ b/drivers/bcma/Makefile
13 @@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver
14 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
15 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
16 bcma-y += driver_pci.o
17 +bcma-y += driver_pcie2.o
18 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
19 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
20 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
21 --- a/drivers/bcma/bcma_private.h
22 +++ b/drivers/bcma/bcma_private.h
23 @@ -33,8 +33,6 @@ int __init bcma_bus_early_register(struc
24 int bcma_bus_suspend(struct bcma_bus *bus);
25 int bcma_bus_resume(struct bcma_bus *bus);
27 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
31 int bcma_bus_scan(struct bcma_bus *bus);
32 --- a/drivers/bcma/driver_chipcommon_pmu.c
33 +++ b/drivers/bcma/driver_chipcommon_pmu.c
34 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
35 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
38 + case BCMA_CHIP_ID_BCM43131:
39 + case BCMA_CHIP_ID_BCM43217:
40 case BCMA_CHIP_ID_BCM43227:
41 case BCMA_CHIP_ID_BCM43228:
42 case BCMA_CHIP_ID_BCM43428:
43 --- a/drivers/bcma/driver_chipcommon_sflash.c
44 +++ b/drivers/bcma/driver_chipcommon_sflash.c
45 @@ -38,7 +38,7 @@ static const struct bcma_sflash_tbl_e bc
46 { "M25P32", 0x15, 0x10000, 64, },
47 { "M25P64", 0x16, 0x10000, 128, },
48 { "M25FL128", 0x17, 0x10000, 256, },
53 static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
54 @@ -56,7 +56,7 @@ static const struct bcma_sflash_tbl_e bc
55 { "SST25VF016", 0x41, 0x1000, 512, },
56 { "SST25VF032", 0x4a, 0x1000, 1024, },
57 { "SST25VF064", 0x4b, 0x1000, 2048, },
62 static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
63 @@ -67,7 +67,7 @@ static const struct bcma_sflash_tbl_e bc
64 { "AT45DB161", 0x2c, 512, 4096, },
65 { "AT45DB321", 0x34, 512, 8192, },
66 { "AT45DB642", 0x3c, 1024, 8192, },
71 static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
72 --- a/drivers/bcma/driver_gpio.c
73 +++ b/drivers/bcma/driver_gpio.c
77 #include <linux/gpio.h>
78 +#include <linux/irq.h>
79 +#include <linux/interrupt.h>
80 +#include <linux/irqdomain.h>
81 #include <linux/export.h>
82 #include <linux/bcma/bcma.h>
84 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
85 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
88 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
89 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
91 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
93 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
94 - return bcma_core_irq(cc->core);
95 + return irq_find_mapping(cc->irq_domain, gpio);
100 +static void bcma_gpio_irq_unmask(struct irq_data *d)
102 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
103 + int gpio = irqd_to_hwirq(d);
104 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
106 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
107 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
110 +static void bcma_gpio_irq_mask(struct irq_data *d)
112 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
113 + int gpio = irqd_to_hwirq(d);
115 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
118 +static struct irq_chip bcma_gpio_irq_chip = {
119 + .name = "BCMA-GPIO",
120 + .irq_mask = bcma_gpio_irq_mask,
121 + .irq_unmask = bcma_gpio_irq_unmask,
124 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
126 + struct bcma_drv_cc *cc = dev_id;
127 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
128 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
129 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
130 + unsigned long irqs = (val ^ pol) & mask;
136 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
137 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
138 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
140 + return IRQ_HANDLED;
143 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
145 + struct gpio_chip *chip = &cc->gpio;
146 + int gpio, hwirq, err;
148 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
151 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
152 + &irq_domain_simple_ops, cc);
153 + if (!cc->irq_domain) {
155 + goto err_irq_domain;
157 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
158 + int irq = irq_create_mapping(cc->irq_domain, gpio);
160 + irq_set_chip_data(irq, cc);
161 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
162 + handle_simple_irq);
165 + hwirq = bcma_core_irq(cc->core);
166 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
171 + bcma_chipco_gpio_intmask(cc, ~0, 0);
172 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
177 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
178 + int irq = irq_find_mapping(cc->irq_domain, gpio);
180 + irq_dispose_mapping(irq);
182 + irq_domain_remove(cc->irq_domain);
187 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
189 + struct gpio_chip *chip = &cc->gpio;
192 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
195 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
196 + free_irq(bcma_core_irq(cc->core), cc);
197 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
198 + int irq = irq_find_mapping(cc->irq_domain, gpio);
200 + irq_dispose_mapping(irq);
202 + irq_domain_remove(cc->irq_domain);
205 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
210 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
215 int bcma_gpio_init(struct bcma_drv_cc *cc)
217 struct gpio_chip *chip = &cc->gpio;
220 chip->label = "bcma_gpio";
221 chip->owner = THIS_MODULE;
222 @@ -95,8 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c
223 chip->set = bcma_gpio_set_value;
224 chip->direction_input = bcma_gpio_direction_input;
225 chip->direction_output = bcma_gpio_direction_output;
226 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
227 chip->to_irq = bcma_gpio_to_irq;
230 + switch (cc->core->bus->chipinfo.id) {
231 + case BCMA_CHIP_ID_BCM5357:
232 + case BCMA_CHIP_ID_BCM53572:
239 /* There is just one SoC in one device and its GPIO addresses should be
240 * deterministic to address them more easily. The other buses could get
241 * a random base number. */
242 @@ -105,10 +235,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
246 - return gpiochip_add(chip);
247 + err = bcma_gpio_irq_domain_init(cc);
251 + err = gpiochip_add(chip);
253 + bcma_gpio_irq_domain_exit(cc);
260 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
262 + bcma_gpio_irq_domain_exit(cc);
263 return gpiochip_remove(&cc->gpio);
266 +++ b/drivers/bcma/driver_pcie2.c
269 + * Broadcom specific AMBA
272 + * Copyright 2014, Broadcom Corporation
273 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
275 + * Licensed under the GNU/GPL. See COPYING for details.
278 +#include "bcma_private.h"
279 +#include <linux/bcma/bcma.h>
281 +/**************************************************
283 + **************************************************/
286 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
288 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
289 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
290 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
294 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
297 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
298 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
301 +/**************************************************
303 + **************************************************/
305 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
310 + /* restore back to default */
311 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
312 + val |= PCIE2_CLKC_DLYPERST;
313 + val &= ~PCIE2_CLKC_DISSPROMLD;
315 + val &= ~PCIE2_CLKC_DLYPERST;
316 + val |= PCIE2_CLKC_DISSPROMLD;
318 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
320 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
323 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
326 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
327 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
329 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
330 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
332 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
333 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
336 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
338 + u8 core_rev = pcie2->core->id.rev;
341 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
344 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
345 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
346 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
347 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
348 + /* force the right LTR values */
349 + bcma_core_pcie2_set_ltr_vals(pcie2);
352 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
354 + /* enable the LTR */
355 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
356 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
357 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
358 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
360 + /* set the LTR state to be active */
361 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
363 + usleep_range(1000, 2000);
365 + /* set the LTR state to be sleep */
366 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
368 + usleep_range(1000, 2000);
372 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
374 + u8 core_rev = pcie2->core->id.rev;
375 + bool pciewar160, pciewar162;
377 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
378 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
379 + core_rev == 9 || core_rev == 11;
381 + if (!pciewar160 && !pciewar162)
386 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
387 + PCIE_DISABLE_L1CLK_GATING);
389 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
390 + PCIEGEN2_COE_PVT_TL_CTRL_0);
391 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
392 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
397 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
399 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
400 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
403 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
405 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
406 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
409 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
411 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
412 + u8 core_rev = pcie2->core->id.rev;
413 + u32 alp_khz, pm_value;
415 + if (core_rev <= 13) {
416 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
417 + pm_value = (1000000 * 2) / alp_khz;
418 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
419 + PCIE2_PVT_REG_PM_CLK_PERIOD);
420 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
424 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
426 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
429 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
430 + if ((tmp & 0xe) >> 1 == 2)
431 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
433 + /* TODO: Do we need pcie_reqsize? */
435 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
436 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
437 + bcma_core_pcie2_hw_ltr_war(pcie2);
438 + pciedev_crwlpciegen2(pcie2);
439 + pciedev_reg_pm_clk_period(pcie2);
440 + pciedev_crwlpciegen2_180(pcie2);
441 + pciedev_crwlpciegen2_182(pcie2);
443 --- a/drivers/bcma/host_pci.c
444 +++ b/drivers/bcma/host_pci.c
445 @@ -238,7 +238,6 @@ static void bcma_host_pci_remove(struct
446 pci_release_regions(dev);
447 pci_disable_device(dev);
449 - pci_set_drvdata(dev, NULL);
452 #ifdef CONFIG_PM_SLEEP
453 @@ -270,7 +269,7 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
455 #endif /* CONFIG_PM_SLEEP */
457 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
458 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
459 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
460 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
461 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
462 @@ -280,6 +279,8 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
463 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
464 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
465 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
466 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
467 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
468 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
471 --- a/drivers/bcma/main.c
472 +++ b/drivers/bcma/main.c
473 @@ -78,18 +78,6 @@ static u16 bcma_cc_core_id(struct bcma_b
474 return BCMA_CORE_CHIPCOMMON;
477 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
479 - struct bcma_device *core;
481 - list_for_each_entry(core, &bus->cores, list) {
482 - if (core->id.id == coreid)
487 -EXPORT_SYMBOL_GPL(bcma_find_core);
489 struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
492 @@ -101,6 +89,7 @@ struct bcma_device *bcma_find_core_unit(
496 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
498 bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
500 @@ -143,6 +132,7 @@ static int bcma_register_cores(struct bc
501 case BCMA_CORE_CHIPCOMMON:
504 + case BCMA_CORE_PCIE2:
505 case BCMA_CORE_MIPS_74K:
506 case BCMA_CORE_4706_MAC_GBIT_COMMON:
508 @@ -176,6 +166,7 @@ static int bcma_register_cores(struct bc
510 "Could not register dev for core 0x%03X\n",
512 + put_device(&core->dev);
515 core->dev_registered = true;
516 @@ -291,6 +282,13 @@ int bcma_bus_register(struct bcma_bus *b
517 bcma_core_pci_init(&bus->drv_pci[1]);
520 + /* Init PCIe Gen 2 core */
521 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
523 + bus->drv_pcie2.core = core;
524 + bcma_core_pcie2_init(&bus->drv_pcie2);
527 /* Init GBIT MAC COMMON core */
528 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
530 --- a/drivers/bcma/sprom.c
531 +++ b/drivers/bcma/sprom.c
532 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
533 SPEX(_field[7], _offset + 14, _mask, _shift); \
536 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
541 + v = in[SPOFF(offset)];
542 + gain = (v & mask) >> shift;
543 + if (gain == 0xFF) {
544 + gain = 8; /* If unset use 2dBm */
546 + /* Q5.2 Fractional part is stored in 0xC0 */
547 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
553 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
556 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
557 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
559 /* Extract the antenna gain values. */
560 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
561 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
562 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
563 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
564 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
565 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
566 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
567 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
568 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
569 + SSB_SPROM8_AGAIN01,
571 + SSB_SPROM8_AGAIN0_SHIFT);
572 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
573 + SSB_SPROM8_AGAIN01,
575 + SSB_SPROM8_AGAIN1_SHIFT);
576 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
577 + SSB_SPROM8_AGAIN23,
579 + SSB_SPROM8_AGAIN2_SHIFT);
580 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
581 + SSB_SPROM8_AGAIN23,
583 + SSB_SPROM8_AGAIN3_SHIFT);
585 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
586 SSB_SPROM8_LEDDC_ON_SHIFT);
587 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
588 /* for these chips OTP is always available */
591 + case BCMA_CHIP_ID_BCM43131:
592 + case BCMA_CHIP_ID_BCM43217:
593 case BCMA_CHIP_ID_BCM43227:
594 case BCMA_CHIP_ID_BCM43228:
595 case BCMA_CHIP_ID_BCM43428:
596 --- a/include/linux/bcma/bcma.h
597 +++ b/include/linux/bcma/bcma.h
600 #include <linux/bcma/bcma_driver_chipcommon.h>
601 #include <linux/bcma/bcma_driver_pci.h>
602 +#include <linux/bcma/bcma_driver_pcie2.h>
603 #include <linux/bcma/bcma_driver_mips.h>
604 #include <linux/bcma/bcma_driver_gmac_cmn.h>
605 #include <linux/ssb/ssb.h> /* SPROM sharing */
606 @@ -72,17 +73,17 @@ struct bcma_host_ops {
607 /* Core-ID values. */
608 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
609 #define BCMA_CORE_4706_CHIPCOMMON 0x500
610 -#define BCMA_CORE_PCIEG2 0x501
611 -#define BCMA_CORE_DMA 0x502
612 -#define BCMA_CORE_SDIO3 0x503
613 -#define BCMA_CORE_USB20 0x504
614 -#define BCMA_CORE_USB30 0x505
615 -#define BCMA_CORE_A9JTAG 0x506
616 -#define BCMA_CORE_DDR23 0x507
617 -#define BCMA_CORE_ROM 0x508
618 -#define BCMA_CORE_NAND 0x509
619 -#define BCMA_CORE_QSPI 0x50A
620 -#define BCMA_CORE_CHIPCOMMON_B 0x50B
621 +#define BCMA_CORE_NS_PCIEG2 0x501
622 +#define BCMA_CORE_NS_DMA 0x502
623 +#define BCMA_CORE_NS_SDIO3 0x503
624 +#define BCMA_CORE_NS_USB20 0x504
625 +#define BCMA_CORE_NS_USB30 0x505
626 +#define BCMA_CORE_NS_A9JTAG 0x506
627 +#define BCMA_CORE_NS_DDR23 0x507
628 +#define BCMA_CORE_NS_ROM 0x508
629 +#define BCMA_CORE_NS_NAND 0x509
630 +#define BCMA_CORE_NS_QSPI 0x50A
631 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
632 #define BCMA_CORE_4706_SOC_RAM 0x50E
633 #define BCMA_CORE_ARMCA9 0x510
634 #define BCMA_CORE_4706_MAC_GBIT 0x52D
635 @@ -157,6 +158,9 @@ struct bcma_host_ops {
636 /* Chip IDs of PCIe devices */
637 #define BCMA_CHIP_ID_BCM4313 0x4313
638 #define BCMA_CHIP_ID_BCM43142 43142
639 +#define BCMA_CHIP_ID_BCM43131 43131
640 +#define BCMA_CHIP_ID_BCM43217 43217
641 +#define BCMA_CHIP_ID_BCM43222 43222
642 #define BCMA_CHIP_ID_BCM43224 43224
643 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
644 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
645 @@ -333,6 +337,7 @@ struct bcma_bus {
647 struct bcma_drv_cc drv_cc;
648 struct bcma_drv_pci drv_pci[2];
649 + struct bcma_drv_pcie2 drv_pcie2;
650 struct bcma_drv_mips drv_mips;
651 struct bcma_drv_gmac_cmn drv_gmac_cmn;
653 @@ -418,7 +423,14 @@ static inline void bcma_maskset16(struct
654 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
657 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
658 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
660 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
663 + return bcma_find_core_unit(bus, coreid, 0);
666 extern bool bcma_core_is_enabled(struct bcma_device *core);
667 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
668 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
669 --- a/include/linux/bcma/bcma_driver_chipcommon.h
670 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
671 @@ -640,6 +640,7 @@ struct bcma_drv_cc {
672 spinlock_t gpio_lock;
673 #ifdef CONFIG_BCMA_DRIVER_GPIO
674 struct gpio_chip gpio;
675 + struct irq_domain *irq_domain;
680 +++ b/include/linux/bcma/bcma_driver_pcie2.h
682 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
683 +#define LINUX_BCMA_DRIVER_PCIE2_H_
685 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
686 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
687 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
688 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
689 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
690 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
691 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
692 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
693 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
694 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
695 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
696 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
697 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
698 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
699 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
700 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
701 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
702 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
703 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
704 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
705 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
706 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
707 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
708 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
709 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
710 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
711 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
712 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
713 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
714 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
715 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
716 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
717 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
718 +#define PCIE2_LTR_ACTIVE 2
719 +#define PCIE2_LTR_ACTIVE_IDLE 1
720 +#define PCIE2_LTR_SLEEP 0
721 +#define PCIE2_LTR_FINAL_MASK 0x300
722 +#define PCIE2_LTR_FINAL_SHIFT 8
723 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
724 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
725 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
726 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
727 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
728 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
729 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
730 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
731 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
732 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
733 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
734 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
735 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
736 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
737 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
738 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
739 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
740 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
741 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
742 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
743 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
744 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
745 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
746 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
747 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
748 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
749 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
750 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
751 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
752 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
753 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
754 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
755 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
756 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
757 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
758 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
759 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
760 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
761 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
762 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
763 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
764 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
765 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
766 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
767 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
768 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
769 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
770 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
771 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
772 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
773 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
774 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
775 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
776 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
777 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
778 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
779 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
780 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
781 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
782 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
783 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
784 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
785 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
786 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
787 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
788 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
789 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
790 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
791 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
792 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
793 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
794 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
795 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
796 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
797 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
798 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
799 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
800 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
801 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
802 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
803 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
804 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
805 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
806 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
807 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
808 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
809 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
810 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
811 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
812 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
814 +/* PCIE gen2 config regs */
815 +#define PCIE2_INTSTATUS 0x090
816 +#define PCIE2_INTMASK 0x094
817 +#define PCIE2_SBMBX 0x098
819 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
821 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
822 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
823 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
825 +struct bcma_drv_pcie2 {
826 + struct bcma_device *core;
829 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
830 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
831 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
832 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
834 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
835 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
837 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
839 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
840 --- a/drivers/bcma/scan.c
841 +++ b/drivers/bcma/scan.c
842 @@ -32,17 +32,17 @@ static const struct bcma_device_id_name
843 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
844 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
845 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
846 - { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
847 - { BCMA_CORE_DMA, "DMA" },
848 - { BCMA_CORE_SDIO3, "SDIO3" },
849 - { BCMA_CORE_USB20, "USB 2.0" },
850 - { BCMA_CORE_USB30, "USB 3.0" },
851 - { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
852 - { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
853 - { BCMA_CORE_ROM, "ROM" },
854 - { BCMA_CORE_NAND, "NAND flash controller" },
855 - { BCMA_CORE_QSPI, "SPI flash controller" },
856 - { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
857 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
858 + { BCMA_CORE_NS_DMA, "DMA" },
859 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
860 + { BCMA_CORE_NS_USB20, "USB 2.0" },
861 + { BCMA_CORE_NS_USB30, "USB 3.0" },
862 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
863 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
864 + { BCMA_CORE_NS_ROM, "ROM" },
865 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
866 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
867 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
868 { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
869 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
870 { BCMA_CORE_ALTA, "ALTA (I2S)" },