1 From 6891d3c1014cf56dc76ec583b69d341ea47984d6 Mon Sep 17 00:00:00 2001
2 From: Maxime Bizon <mbizon@freebox.fr>
3 Date: Fri, 18 Jul 2008 20:34:35 +0200
4 Subject: [PATCH] [MIPS] BCM63XX: Change PCI code to emulate a fake cardbus bridge.
6 Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
8 arch/mips/pci/ops-bcm63xx.c | 288 +++++++++++++++++++++++++++++++++++++++++++
9 arch/mips/pci/pci-bcm63xx.c | 44 +++++++
10 2 files changed, 332 insertions(+), 0 deletions(-)
12 --- a/arch/mips/pci/ops-bcm63xx.c
13 +++ b/arch/mips/pci/ops-bcm63xx.c
14 @@ -177,3 +177,291 @@ struct pci_ops bcm63xx_pci_ops = {
15 .read = bcm63xx_pci_read,
16 .write = bcm63xx_pci_write
19 +#ifdef CONFIG_CARDBUS
21 + * emulate configuration read access on a cardbus bridge
23 +#define FAKE_CB_BRIDGE_SLOT 0x1e
25 +static int fake_cb_bridge_bus_number = -1;
30 + u8 subordinate_busn;
45 +} fake_cb_bridge_regs;
47 +static int fake_cb_bridge_read(int where, int size, u32 *val)
55 + case (PCI_VENDOR_ID >> 2):
56 + case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
57 + /* create dummy vendor/device id from our cpu id */
58 + data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
61 + case (PCI_COMMAND >> 2):
62 + data = (PCI_STATUS_DEVSEL_SLOW << 16);
63 + data |= fake_cb_bridge_regs.pci_command;
66 + case (PCI_CLASS_REVISION >> 2):
67 + data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
70 + case (PCI_CACHE_LINE_SIZE >> 2):
71 + data = (PCI_HEADER_TYPE_CARDBUS << 16);
74 + case (PCI_INTERRUPT_LINE >> 2):
75 + /* bridge control */
76 + data = (fake_cb_bridge_regs.bridge_control << 16);
77 + /* pin:intA line:0xff */
78 + data |= (0x1 << 8) | 0xff;
81 + case (PCI_CB_PRIMARY_BUS >> 2):
82 + data = (fake_cb_bridge_regs.cb_latency << 24);
83 + data |= (fake_cb_bridge_regs.subordinate_busn << 16);
84 + data |= (fake_cb_bridge_regs.cardbus_busn << 8);
85 + data |= fake_cb_bridge_regs.pci_busn;
88 + case (PCI_CB_MEMORY_BASE_0 >> 2):
89 + data = fake_cb_bridge_regs.mem_base0;
92 + case (PCI_CB_MEMORY_LIMIT_0 >> 2):
93 + data = fake_cb_bridge_regs.mem_limit0;
96 + case (PCI_CB_MEMORY_BASE_1 >> 2):
97 + data = fake_cb_bridge_regs.mem_base1;
100 + case (PCI_CB_MEMORY_LIMIT_1 >> 2):
101 + data = fake_cb_bridge_regs.mem_limit1;
104 + case (PCI_CB_IO_BASE_0 >> 2):
105 + /* | 1 for 32bits io support */
106 + data = fake_cb_bridge_regs.io_base0 | 0x1;
109 + case (PCI_CB_IO_LIMIT_0 >> 2):
110 + data = fake_cb_bridge_regs.io_limit0;
113 + case (PCI_CB_IO_BASE_1 >> 2):
114 + /* | 1 for 32bits io support */
115 + data = fake_cb_bridge_regs.io_base1 | 0x1;
118 + case (PCI_CB_IO_LIMIT_1 >> 2):
119 + data = fake_cb_bridge_regs.io_limit1;
123 + *val = postprocess_read(data, where, size);
124 + return PCIBIOS_SUCCESSFUL;
128 + * emulate configuration write access on a cardbus bridge
130 +static int fake_cb_bridge_write(int where, int size, u32 val)
136 + ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
137 + if (ret != PCIBIOS_SUCCESSFUL)
140 + data = preprocess_write(data, val, where, size);
144 + case (PCI_COMMAND >> 2):
145 + fake_cb_bridge_regs.pci_command = (data & 0xffff);
148 + case (PCI_CB_PRIMARY_BUS >> 2):
149 + fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
150 + fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
151 + fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
152 + fake_cb_bridge_regs.pci_busn = data & 0xff;
153 + if (fake_cb_bridge_regs.cardbus_busn)
154 + fake_cb_bridge_regs.bus_assigned = 1;
157 + case (PCI_INTERRUPT_LINE >> 2):
158 + tmp = (data >> 16) & 0xffff;
159 + /* disable memory prefetch support */
160 + tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
161 + tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
162 + fake_cb_bridge_regs.bridge_control = tmp;
165 + case (PCI_CB_MEMORY_BASE_0 >> 2):
166 + fake_cb_bridge_regs.mem_base0 = data;
169 + case (PCI_CB_MEMORY_LIMIT_0 >> 2):
170 + fake_cb_bridge_regs.mem_limit0 = data;
173 + case (PCI_CB_MEMORY_BASE_1 >> 2):
174 + fake_cb_bridge_regs.mem_base1 = data;
177 + case (PCI_CB_MEMORY_LIMIT_1 >> 2):
178 + fake_cb_bridge_regs.mem_limit1 = data;
181 + case (PCI_CB_IO_BASE_0 >> 2):
182 + fake_cb_bridge_regs.io_base0 = data;
185 + case (PCI_CB_IO_LIMIT_0 >> 2):
186 + fake_cb_bridge_regs.io_limit0 = data;
189 + case (PCI_CB_IO_BASE_1 >> 2):
190 + fake_cb_bridge_regs.io_base1 = data;
193 + case (PCI_CB_IO_LIMIT_1 >> 2):
194 + fake_cb_bridge_regs.io_limit1 = data;
198 + return PCIBIOS_SUCCESSFUL;
201 +static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
202 + int where, int size, u32 *val)
204 + /* snoop access to slot 0x1e on root bus, we fake a cardbus
205 + * bridge at this location */
206 + if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
207 + fake_cb_bridge_bus_number = bus->number;
208 + return fake_cb_bridge_read(where, size, val);
211 + /* a configuration cycle for the device behind the cardbus
212 + * bridge is actually done as a type 0 cycle on the primary
213 + * bus. This means that only one device can be on the cardbus
215 + if (fake_cb_bridge_regs.bus_assigned &&
216 + bus->number == fake_cb_bridge_regs.cardbus_busn &&
217 + PCI_SLOT(devfn) == 0)
218 + return bcm63xx_do_cfg_read(0, 0,
219 + PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
222 + return PCIBIOS_DEVICE_NOT_FOUND;
225 +static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
226 + int where, int size, u32 val)
228 + if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
229 + fake_cb_bridge_bus_number = bus->number;
230 + return fake_cb_bridge_write(where, size, val);
233 + if (fake_cb_bridge_regs.bus_assigned &&
234 + bus->number == fake_cb_bridge_regs.cardbus_busn &&
235 + PCI_SLOT(devfn) == 0)
236 + return bcm63xx_do_cfg_write(0, 0,
237 + PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
240 + return PCIBIOS_DEVICE_NOT_FOUND;
243 +struct pci_ops bcm63xx_cb_ops = {
244 + .read = bcm63xx_cb_read,
245 + .write = bcm63xx_cb_write,
249 + * only one IO window, so it cannot be shared by PCI and cardbus, use
250 + * fixup to choose and detect unhandled configuration
252 +static void bcm63xx_fixup(struct pci_dev *dev)
254 + static int io_window = -1;
255 + int i, found, new_io_window;
258 + /* look for any io resource */
260 + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
261 + if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
270 + /* skip our fake bus with only cardbus bridge on it */
271 + if (dev->bus->number == fake_cb_bridge_bus_number)
274 + /* find on which bus the device is */
275 + if (fake_cb_bridge_regs.bus_assigned &&
276 + dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
277 + PCI_SLOT(dev->devfn) == 0)
282 + if (new_io_window == io_window)
285 + if (io_window != -1) {
286 + printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
287 + "need IO, which hardware cannot do\n");
291 + printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
292 + (new_io_window == 0) ? "PCI" : "cardbus");
294 + val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
296 + val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
298 + val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
299 + bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
301 + io_window = new_io_window;
304 +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
306 --- a/arch/mips/pci/pci-bcm63xx.c
307 +++ b/arch/mips/pci/pci-bcm63xx.c
308 @@ -28,7 +28,11 @@ static struct resource bcm_pci_mem_resou
309 static struct resource bcm_pci_io_resource = {
310 .name = "bcm63xx PCI IO space",
311 .start = BCM_PCI_IO_BASE_PA,
312 +#ifdef CONFIG_CARDBUS
313 + .end = BCM_PCI_IO_HALF_PA,
315 .end = BCM_PCI_IO_END_PA,
317 .flags = IORESOURCE_IO
320 @@ -38,6 +42,33 @@ struct pci_controller bcm63xx_controller
321 .mem_resource = &bcm_pci_mem_resource,
325 + * We handle cardbus via a fake Cardbus bridge, memory and io spaces
326 + * have to be clearly separated from PCI one since we have different
329 +#ifdef CONFIG_CARDBUS
330 +static struct resource bcm_cb_mem_resource = {
331 + .name = "bcm63xx Cardbus memory space",
332 + .start = BCM_CB_MEM_BASE_PA,
333 + .end = BCM_CB_MEM_END_PA,
334 + .flags = IORESOURCE_MEM
337 +static struct resource bcm_cb_io_resource = {
338 + .name = "bcm63xx Cardbus IO space",
339 + .start = BCM_PCI_IO_HALF_PA + 1,
340 + .end = BCM_PCI_IO_END_PA,
341 + .flags = IORESOURCE_IO
344 +struct pci_controller bcm63xx_cb_controller = {
345 + .pci_ops = &bcm63xx_cb_ops,
346 + .io_resource = &bcm_cb_io_resource,
347 + .mem_resource = &bcm_cb_mem_resource,
351 static u32 bcm63xx_int_cfg_readl(u32 reg)
354 @@ -98,8 +129,17 @@ static int __init bcm63xx_pci_init(void)
355 val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
356 bcm_pcmcia_writel(val, PCMCIA_C1_REG);
358 +#ifdef CONFIG_CARDBUS
359 + /* setup local bus to PCI access (Cardbus memory) */
360 + val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
361 + bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
362 + bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
363 + val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
364 + bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
366 /* disable second access windows */
367 bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
370 /* setup local bus to PCI access (IO memory), we have only 1
371 * IO window for both PCI and cardbus, but it cannot handle
372 @@ -169,6 +209,10 @@ static int __init bcm63xx_pci_init(void)
374 register_pci_controller(&bcm63xx_controller);
376 +#ifdef CONFIG_CARDBUS
377 + register_pci_controller(&bcm63xx_cb_controller);
380 /* mark memory space used for IO mapping as reserved */
381 request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
382 "bcm63xx PCI IO space");