2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/platform_device.h>
23 #include <linux/kernel.h>
24 #include <linux/reboot.h>
25 #include <asm/bootinfo.h>
26 #include <asm/reboot.h>
30 #include "../ar531x.h"
34 static int is_5312 = 0;
35 static struct platform_device *ar5312_devs[5];
37 static struct resource ar5312_eth0_res[] = {
39 .name = "eth0_membase",
40 .flags = IORESOURCE_MEM,
41 .start = KSEG1ADDR(AR531X_ENET0),
42 .end = KSEG1ADDR(AR531X_ENET0 + 0x2000),
46 .flags = IORESOURCE_IRQ,
47 .start = AR5312_IRQ_ENET0_INTRS,
48 .end = AR5312_IRQ_ENET0_INTRS,
51 static struct ar531x_eth ar5312_eth0_data = {
54 .reset_base = AR531X_RESET,
55 .reset_mac = AR531X_RESET_ENET0,
56 .reset_phy = AR531X_RESET_EPHY0,
57 .phy_base = KSEG1ADDR(AR531X_ENET0),
60 static struct resource ar5312_eth1_res[] = {
62 .name = "eth1_membase",
63 .flags = IORESOURCE_MEM,
64 .start = KSEG1ADDR(AR531X_ENET1),
65 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
69 .flags = IORESOURCE_IRQ,
70 .start = AR5312_IRQ_ENET1_INTRS,
71 .end = AR5312_IRQ_ENET1_INTRS,
74 static struct ar531x_eth ar5312_eth1_data = {
77 .reset_base = AR531X_RESET,
78 .reset_mac = AR531X_RESET_ENET1,
79 .reset_phy = AR531X_RESET_EPHY1,
80 .phy_base = KSEG1ADDR(AR531X_ENET1),
83 static struct platform_device ar5312_eth[] = {
87 .dev.platform_data = &ar5312_eth0_data,
88 .resource = ar5312_eth0_res,
89 .num_resources = ARRAY_SIZE(ar5312_eth0_res)
94 .dev.platform_data = &ar5312_eth1_data,
95 .resource = ar5312_eth1_res,
96 .num_resources = ARRAY_SIZE(ar5312_eth1_res)
102 * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
103 * of ENET1. Atheros calls it 'twisted' for a reason :)
105 static struct resource ar231x_eth0_res[] = {
107 .name = "eth0_membase",
108 .flags = IORESOURCE_MEM,
109 .start = KSEG1ADDR(AR531X_ENET1),
110 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
114 .flags = IORESOURCE_IRQ,
115 .start = AR5312_IRQ_ENET1_INTRS,
116 .end = AR5312_IRQ_ENET1_INTRS,
119 static struct ar531x_eth ar231x_eth0_data = {
122 .reset_base = AR531X_RESET,
123 .reset_mac = AR531X_RESET_ENET1,
124 .reset_phy = AR531X_RESET_EPHY1,
125 .phy_base = KSEG1ADDR(AR531X_ENET0),
127 static struct platform_device ar231x_eth0 = {
129 .name = "ar531x-eth",
130 .dev.platform_data = &ar231x_eth0_data,
131 .resource = ar231x_eth0_res,
132 .num_resources = ARRAY_SIZE(ar231x_eth0_res)
136 static struct platform_device ar5312_wmac[] = {
139 .name = "ar531x-wmac",
143 .name = "ar531x-wmac",
147 static struct physmap_flash_data ar5312_flash_data = {
151 static struct resource ar5312_flash_resource = {
152 .start = AR531X_FLASH,
153 .end = AR531X_FLASH + 0x800000 - 1,
154 .flags = IORESOURCE_MEM,
157 static struct platform_device ar5312_physmap_flash = {
158 .name = "physmap-flash",
161 .platform_data = &ar5312_flash_data,
164 .resource = &ar5312_flash_resource,
169 * NB: This mapping size is larger than the actual flash size,
170 * but this shouldn't be a problem here, because the flash
171 * will simply be mapped multiple times.
173 static char __init *ar5312_flash_limit(void)
177 * Configure flash bank 0.
178 * Assume 8M window size. Flash will be aliased if it's smaller
183 (0x01 << FLASHCTL_IDCY_S) |
184 (0x07 << FLASHCTL_WST1_S) |
185 (0x07 << FLASHCTL_WST2_S) |
186 (sysRegRead(AR531X_FLASHCTL0) & FLASHCTL_MW);
188 sysRegWrite(AR531X_FLASHCTL0, ctl);
190 /* Disable other flash banks */
191 sysRegWrite(AR531X_FLASHCTL1,
192 sysRegRead(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
194 sysRegWrite(AR531X_FLASHCTL2,
195 sysRegRead(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
197 return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
200 static struct ar531x_config __init *init_wmac(int unit)
202 struct ar531x_config *config;
204 config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
205 config->board = board_config;
206 config->radio = radio_config;
208 config->tag = (u_int16_t) ((sysRegRead(AR531X_REV) >> AR531X_REV_WMAC_MIN_S) & AR531X_REV_CHIP);
213 int __init ar5312_init_devices(void)
215 struct ar531x_boarddata *bcfg;
223 /* Locate board/radio config data */
224 ar531x_find_config(ar5312_flash_limit());
225 bcfg = (struct ar531x_boarddata *) board_config;
229 * Chip IDs and hardware detection for some Atheros
230 * models are really broken!
232 * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
233 * as indication for AR2312, which is otherwise
234 * indistinguishable from the real AR5312.
237 radio = radio_config + AR531X_RADIO_MASK_OFF;
238 if ((*((u32 *) radio) & AR531X_RADIO0_MASK) == 0)
239 bcfg->config |= BD_ISCASPER;
243 /* AR2313 has CPU minor rev. 10 */
244 if ((current_cpu_data.processor_id & 0xff) == 0x0a)
245 mips_machtype = MACH_ATHEROS_AR2313;
247 /* AR2312 shares the same Silicon ID as AR5312 */
248 else if (bcfg->config & BD_ISCASPER)
249 mips_machtype = MACH_ATHEROS_AR2312;
251 /* Everything else is probably AR5312 or compatible */
253 mips_machtype = MACH_ATHEROS_AR5312;
255 ar5312_eth0_data.board_config = board_config;
256 ar5312_eth1_data.board_config = board_config;
258 /* fixup flash width */
259 fctl = sysRegRead(AR531X_FLASHCTL) & FLASHCTL_MW;
262 ar5312_flash_data.width = 2;
266 ar5312_flash_data.width = 1;
270 ar5312_devs[dev++] = &ar5312_physmap_flash;
272 if (!memcmp(bcfg->enet0Mac, "\xff\xff\xff\xff\xff\xff", 6))
273 memcpy(bcfg->enet0Mac, bcfg->enet1Mac, 6);
275 if (memcmp(bcfg->enet0Mac, bcfg->enet1Mac, 6) == 0) {
276 /* ENET0 and ENET1 have the same mac.
277 * Increment the one from ENET1 */
278 c = bcfg->enet1Mac + 5;
279 while ((c >= (char *) bcfg->enet1Mac) && !(++(*c)))
283 switch(mips_machtype) {
284 case MACH_ATHEROS_AR5312:
285 ar5312_eth0_data.macaddr = bcfg->enet0Mac;
286 ar5312_eth1_data.macaddr = bcfg->enet1Mac;
287 ar5312_devs[dev++] = &ar5312_eth[0];
288 ar5312_devs[dev++] = &ar5312_eth[1];
290 case MACH_ATHEROS_AR2312:
291 case MACH_ATHEROS_AR2313:
292 ar231x_eth0_data.macaddr = bcfg->enet0Mac;
293 ar5312_devs[dev++] = &ar231x_eth0;
294 ar5312_flash_data.width = 1;
299 if (mips_machtype == MACH_ATHEROS_AR5312) {
300 if (*((u32 *) radio) & AR531X_RADIO0_MASK) {
301 ar5312_wmac[0].dev.platform_data = init_wmac(0);
302 ar5312_devs[dev++] = &ar5312_wmac[0];
305 if (*((u32 *) radio) & AR531X_RADIO1_MASK) {
306 ar5312_wmac[1].dev.platform_data = init_wmac(1);
307 ar5312_devs[dev++] = &ar5312_wmac[1];
311 return platform_add_devices(ar5312_devs, dev);
315 static void ar5312_halt(void)
320 static void ar5312_power_off(void)
326 static void ar5312_restart(char *command)
328 /* reset the system */
329 for(;;) sysRegWrite(AR531X_RESET, AR531X_RESET_SYSTEM);
334 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
335 * to determine the predevisor value.
337 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
345 static unsigned int __init ar5312_cpu_frequency(void)
348 unsigned int predivide_mask, predivide_shift;
349 unsigned int multiplier_mask, multiplier_shift;
350 unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
351 unsigned int doubler_mask;
352 unsigned int wisoc_revision;
354 /* Trust the bootrom's idea of cpu frequency. */
355 if ((result = sysRegRead(AR5312_SCRATCH)))
358 wisoc_revision = (sysRegRead(AR531X_REV) & AR531X_REV_MAJ) >> AR531X_REV_MAJ_S;
359 if (wisoc_revision == AR531X_REV_MAJ_AR2313) {
360 predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
361 predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
362 multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
363 multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
364 doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
365 } else { /* AR5312 and AR2312 */
366 predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
367 predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
368 multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
369 multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
370 doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
374 * Clocking is derived from a fixed 40MHz input clock.
376 * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
377 * sysFreq = cpuFreq / 4 (used for APB clock, serial,
378 * flash, Timer, Watchdog Timer)
380 * cntFreq = cpuFreq / 2 (use for CPU count/compare)
382 * So, for example, with a PLL multiplier of 5, we have
388 * We compute the CPU frequency, based on PLL settings.
391 clockCtl1 = sysRegRead(AR5312_CLOCKCTL1);
392 preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
393 preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
394 multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
396 if (clockCtl1 & doubler_mask) {
397 multiplier = multiplier << 1;
399 return (40000000 / preDivisor) * multiplier;
402 static inline int ar5312_sys_frequency(void)
404 return ar5312_cpu_frequency() / 4;
407 static void __init ar5312_time_init(void)
409 mips_hpt_frequency = ar5312_cpu_frequency() / 2;
413 void __init ar5312_prom_init(void)
415 u32 memsize, memcfg, bank0AC, bank1AC;
419 /* Detect memory size */
420 memcfg = sysRegRead(AR531X_MEM_CFG1);
421 bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
422 bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
423 memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
424 + (bank1AC ? (1 << (bank1AC+1)) : 0);
426 add_memory_region(0, memsize, BOOT_MEM_RAM);
428 /* Initialize it to AR5312 for now. Real detection will be done
429 * in ar5312_init_devices() */
430 mips_machtype = MACH_ATHEROS_AR5312;
433 void __init ar5312_plat_setup(void)
435 /* Clear any lingering AHB errors */
436 sysRegRead(AR531X_PROCADDR);
437 sysRegRead(AR531X_DMAADDR);
438 sysRegWrite(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
440 board_time_init = ar5312_time_init;
442 _machine_restart = ar5312_restart;
443 _machine_halt = ar5312_halt;
444 pm_power_off = ar5312_power_off;
446 serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
449 arch_initcall(ar5312_init_devices);