From 753d1f73c1f250ddc13a2d8e24a267abb2e5e9bc Mon Sep 17 00:00:00 2001 From: nbd Date: Sat, 21 Nov 2015 10:55:05 +0000 Subject: [PATCH] ipq806x: reduce PCIe buffer size setting to fix potential data corruption issues Signed-off-by: Felix Fietkau git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47545 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch | 4 ++-- target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch index 11c9810fe2..c0b65c712b 100644 --- a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch +++ b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch @@ -229,8 +229,8 @@ + writel(upper_32_bits(pp->mem_bus_addr), + pcie->dbi + PCIE20_PLR_IATU_UTAR); + -+ /* 1K PCIE buffer setting */ -+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); ++ /* 256B PCIE buffer setting */ ++ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); +} + diff --git a/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch index 11c9810fe2..c0b65c712b 100644 --- a/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch +++ b/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch @@ -229,8 +229,8 @@ + writel(upper_32_bits(pp->mem_bus_addr), + pcie->dbi + PCIE20_PLR_IATU_UTAR); + -+ /* 1K PCIE buffer setting */ -+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); ++ /* 256B PCIE buffer setting */ ++ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); +} + -- 2.11.0