ar71xx: add mask and shift for RXD/RDV bits in AR934X register file

The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X
register file") introduced definitions for some bits in the RDV/RXD part of the
ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is
specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit
only specified the lower bits. The upper bits also have to be unset when the
lower bits should only be set.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45522 3c298f89-4303-0410-b956-a3cf2f4a3e73

diff --git a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
index 2dec020..8bf7658 100644 (file)
--- a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
@@ -207,7 +207,7 @@
  #define AR934X_GPIO_REG_FUNC          0x6c
  
  #define AR71XX_GPIO_COUNT             16
  #define AR934X_GPIO_REG_FUNC          0x6c
  
  #define AR71XX_GPIO_COUNT             16

-@@ -560,4 +663,149 @@
+@@ -560,4 +663,153 @@

  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  


@@ -345,7 +345,11 @@
 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST       BIT(13)
 +#define AR934X_ETH_CFG_RXD_DELAY        BIT(14)
 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST       BIT(13)
 +#define AR934X_ETH_CFG_RXD_DELAY        BIT(14)

++#define AR934X_ETH_CFG_RXD_DELAY_MASK   0x3
++#define AR934X_ETH_CFG_RXD_DELAY_SHIFT  14

 +#define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
 +#define AR934X_ETH_CFG_RDV_DELAY        BIT(16)

++#define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3
++#define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16

 +
 +/*
 + * QCA955X GMAC Interface
 +
 +/*
 + * QCA955X GMAC Interface