ramips: Fix comment in rt3050 ethernet switch driver.
authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 2 May 2016 18:51:01 +0000 (18:51 +0000)
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 2 May 2016 18:51:01 +0000 (18:51 +0000)
Line 444 is actually enabling all switch ports by setting the disable bits
to 0. This needs to be done because the bootloader sets all ports to disabled
by default (which is the case for at least one router based on RT5350).

So, this patch fixes the comment in line 443.

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49289 3c298f89-4303-0410-b956-a3cf2f4a3e73

target/linux/ramips/patches-4.4/0517-net-mediatek-fix-comment-in-rt3050-ethernet-switch-d.patch [new file with mode: 0644]

diff --git a/target/linux/ramips/patches-4.4/0517-net-mediatek-fix-comment-in-rt3050-ethernet-switch-d.patch b/target/linux/ramips/patches-4.4/0517-net-mediatek-fix-comment-in-rt3050-ethernet-switch-d.patch
new file mode 100644 (file)
index 0000000..aefb6a5
--- /dev/null
@@ -0,0 +1,24 @@
+From: Vittorio Gambaletta <openwrt@vittgam.net>
+Date: Fri, 01 Jan 2016 00:00:01 +0100
+Subject: [PATCH 2/3] net: mediatek: Fix comment in rt3050 ethernet switch driver.
+
+Line 444 is actually enabling all switch ports by setting the disable bits
+to 0. This needs to be done because the bootloader sets all ports to disabled
+by default (which is the case for at least one router based on RT5350).
+
+So, this patch fixes the comment in line 443.
+
+Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>
+---
+
+--- a/drivers/net/ethernet/mediatek/esw_rt3050.c
++++ b/drivers/net/ethernet/mediatek/esw_rt3050.c
+@@ -440,7 +440,7 @@ static void esw_hw_init(struct rt305x_es
+                    (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
+               RT305X_ESW_REG_PFC1);
+-      /* Enable Back Pressure, and Flow Control */
++      /* Enable all ports, Back Pressure and Flow Control */
+       esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
+                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
+               RT305X_ESW_REG_POC0);