cns3xxx: Fix laguna arm11mpcore watchdog

The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where
all mpcore-wdt boards point the driver base too.  I believe this is wrong
because 0x600 is aliased to the timer/watchdog of the 'current CPU' where
0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog.  Thus
if your timer/watchdog application is switching between CPU's it can end up
writing to the wrong CPU's registers which results in random board resets
from watchdog timeouts etc.

This patch forces the timer/watchdog driver to use CPU0's registers always.
Its my opinion that other mpcore-wdt boards should be doing the same thing.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33683 3c298f89-4303-0410-b956-a3cf2f4a3e73

diff --git a/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch b/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
index 7fe970a..a4602f9 100644 (file)
--- a/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
+++ b/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch
@@ -563,7 +563,7 @@
 +
 +static struct resource laguna_watchdog_resources[] = {
 +      [0] = {
 +
 +static struct resource laguna_watchdog_resources[] = {
 +      [0] = {

-+              .start  = CNS3XXX_TC11MP_TWD_BASE,
++              .start  = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog

 +              .end    = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
 +              .flags  = IORESOURCE_MEM,
 +      },
 +              .end    = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
 +              .flags  = IORESOURCE_MEM,
 +      },