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ralink: fix mt7620a pinmux
authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 7 Oct 2013 15:02:18 +0000 (15:02 +0000)
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 7 Oct 2013 15:02:18 +0000 (15:02 +0000)
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38318 3c298f89-4303-0410-b956-a3cf2f4a3e73

target/linux/ramips/patches-3.10/0122-pinmux.patch patch | blob | history

diff --git a/target/linux/ramips/patches-3.10/0122-pinmux.patch b/target/linux/ramips/patches-3.10/0122-pinmux.patch
index f31e476..6923355 100644 (file)
--- a/target/linux/ramips/patches-3.10/0122-pinmux.patch
+++ b/target/linux/ramips/patches-3.10/0122-pinmux.patch
@@ -14,9 +14,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  6 files changed, 385 insertions(+), 19 deletions(-)
  create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
 
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -446,6 +446,8 @@ config RALINK
+Index: linux-3.10.13/arch/mips/Kconfig
+===================================================================
+--- linux-3.10.13.orig/arch/mips/Kconfig       2013-10-02 16:59:28.532051276 +0200
++++ linux-3.10.13/arch/mips/Kconfig    2013-10-02 16:59:29.440051316 +0200
+@@ -446,6 +446,8 @@
        select HAVE_MACH_CLKDEV
        select CLKDEV_LOOKUP
        select ARCH_REQUIRE_GPIOLIB
@@ -25,9 +27,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  config SGI_IP22
        bool "SGI IP22 (Indy/Indigo2)"
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -114,6 +114,11 @@ config PINCTRL_LANTIQ
+Index: linux-3.10.13/drivers/pinctrl/Kconfig
+===================================================================
+--- linux-3.10.13.orig/drivers/pinctrl/Kconfig 2013-09-27 02:18:49.000000000 +0200
++++ linux-3.10.13/drivers/pinctrl/Kconfig      2013-10-02 16:59:29.440051316 +0200
+@@ -114,6 +114,11 @@
        select PINMUX
        select PINCONF
  
@@ -39,9 +43,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  config PINCTRL_FALCON
        bool
        depends on SOC_FALCON
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440)     += pinc
+Index: linux-3.10.13/drivers/pinctrl/Makefile
+===================================================================
+--- linux-3.10.13.orig/drivers/pinctrl/Makefile        2013-09-27 02:18:49.000000000 +0200
++++ linux-3.10.13/drivers/pinctrl/Makefile     2013-10-02 16:59:29.440051316 +0200
+@@ -45,6 +45,7 @@
  obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
  obj-$(CONFIG_PINCTRL_XWAY)    += pinctrl-xway.o
  obj-$(CONFIG_PINCTRL_LANTIQ)  += pinctrl-lantiq.o
@@ -49,8 +55,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  obj-$(CONFIG_PLAT_ORION)        += mvebu/
  obj-$(CONFIG_ARCH_SHMOBILE)   += sh-pfc/
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-rt2880.c
+Index: linux-3.10.13/drivers/pinctrl/pinctrl-rt2880.c
+===================================================================
+--- /dev/null  1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.13/drivers/pinctrl/pinctrl-rt2880.c     2013-10-02 18:24:18.556268869 +0200
 @@ -0,0 +1,456 @@
 +/*
 + *  linux/drivers/pinctrl/pinctrl-rt2880.c
@@ -508,8 +516,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 +
 +core_initcall_sync(rt2880_pinmux_init);
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/pinmux.h
+Index: linux-3.10.13/arch/mips/include/asm/mach-ralink/pinmux.h
+===================================================================
+--- /dev/null  1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.13/arch/mips/include/asm/mach-ralink/pinmux.h   2013-10-02 16:59:29.444051317 +0200
 @@ -0,0 +1,47 @@
 +/*
 + *  This program is free software; you can redistribute it and/or modify
@@ -558,8 +568,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
 +
 +#endif
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
+Index: linux-3.10.13/arch/mips/ralink/mt7620.c
+===================================================================
+--- linux-3.10.13.orig/arch/mips/ralink/mt7620.c       2013-10-02 16:59:28.912051293 +0200
++++ linux-3.10.13/arch/mips/ralink/mt7620.c    2013-10-02 18:23:35.940267055 +0200
 @@ -17,6 +17,7 @@
  #include <asm/mipsregs.h>
  #include <asm/mach-ralink/ralink_regs.h>
@@ -568,7 +580,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  #include "common.h"
  
-@@ -48,118 +49,40 @@ static int dram_type;
+@@ -48,118 +49,40 @@
  /* the pll dividers */
  static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
  
@@ -635,8 +647,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 -              .gpio_first = 72,
 -              .gpio_last = 72,
 -      }, {0}
-+static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 1, 1, 2) };
-+static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 1, 3, 4) };
++static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
 +static struct rt2880_pmx_func uartf_grp[] = {
 +      FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
 +      FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
@@ -694,14 +706,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 -      .uart = uart_mux,
 -      .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
 -      .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
-+static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 1, 15, 2) };
-+static struct rt2880_pmx_func wdt_grp[] = { FUNC("wdt", 1, 17, 1) };
-+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 1, 22, 2) };
-+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 1, 24, 12) };
-+static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 1, 37, 3) };
-+static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 1, 40, 5) };
-+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 1, 60, 12) };
-+static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 1, 72, 1) };
++static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
++static struct rt2880_pmx_func wdt_grp[] = { FUNC("wdt", 0, 17, 1) };
++static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
++static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
++static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
++static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
++static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
 +
 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
 +      GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
@@ -720,15 +732,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  void __init ralink_clk_init(void)
-@@ -281,4 +204,6 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -281,4 +204,6 @@
                (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
        pr_info("Digital PMU set to %s control\n",
                (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 +
 +      rt2880_pinmux_data = mt7620a_pinmux_data;
  }
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
+Index: linux-3.10.13/arch/mips/ralink/rt305x.c
+===================================================================
+--- linux-3.10.13.orig/arch/mips/ralink/rt305x.c       2013-10-02 16:59:29.140051302 +0200
++++ linux-3.10.13/arch/mips/ralink/rt305x.c    2013-10-02 16:59:29.444051317 +0200
 @@ -17,90 +17,71 @@
  #include <asm/mipsregs.h>
  #include <asm/mach-ralink/ralink_regs.h>
@@ -878,7 +892,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  static void rt305x_wdt_reset(void)
-@@ -114,14 +95,6 @@ static void rt305x_wdt_reset(void)
+@@ -114,14 +95,6 @@
        rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
  }
  
@@ -893,7 +907,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static unsigned long rt5350_get_mem_size(void)
  {
        void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
-@@ -291,11 +264,14 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -291,11 +264,14 @@
        soc_info->mem_base = RT305X_SDRAM_BASE;
        if (soc_is_rt5350()) {
                soc_info->mem_size = rt5350_get_mem_size();
@@ -908,9 +922,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +              rt2880_pinmux_data = rt3352_pinmux_data;
        }
  }
---- a/arch/mips/include/asm/mach-ralink/rt305x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
-@@ -125,24 +125,28 @@ static inline int soc_is_rt5350(void)
+Index: linux-3.10.13/arch/mips/include/asm/mach-ralink/rt305x.h
+===================================================================
+--- linux-3.10.13.orig/arch/mips/include/asm/mach-ralink/rt305x.h      2013-09-27 02:18:49.000000000 +0200
++++ linux-3.10.13/arch/mips/include/asm/mach-ralink/rt305x.h   2013-10-02 16:59:29.444051317 +0200
+@@ -125,24 +125,28 @@
  #define RT305X_GPIO_GE0_TXD0          40
  #define RT305X_GPIO_GE0_RXCLK         51
  
@@ -954,8 +970,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  #define RT3352_SYSC_REG_SYSCFG0               0x010
  #define RT3352_SYSC_REG_SYSCFG1         0x014
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+Index: linux-3.10.13/arch/mips/include/asm/mach-ralink/mt7620.h
+===================================================================
+--- linux-3.10.13.orig/arch/mips/include/asm/mach-ralink/mt7620.h      2013-10-02 16:59:28.708051287 +0200
++++ linux-3.10.13/arch/mips/include/asm/mach-ralink/mt7620.h   2013-10-02 16:59:29.444051317 +0200
 @@ -59,7 +59,6 @@
  #define MT7620_DDR2_SIZE_MIN          32
  #define MT7620_DDR2_SIZE_MAX          256
@@ -992,8 +1010,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define MT7620_GPIO_MODE_WDT          22
  
  #endif
---- a/arch/mips/include/asm/mach-ralink/rt3883.h
-+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
+Index: linux-3.10.13/arch/mips/include/asm/mach-ralink/rt3883.h
+===================================================================
+--- linux-3.10.13.orig/arch/mips/include/asm/mach-ralink/rt3883.h      2013-09-27 02:18:49.000000000 +0200
++++ linux-3.10.13/arch/mips/include/asm/mach-ralink/rt3883.h   2013-10-02 16:59:29.444051317 +0200
 @@ -112,8 +112,6 @@
  #define RT3883_CLKCFG1_PCI_CLK_EN     BIT(19)
  #define RT3883_CLKCFG1_UPHY0_CLK_EN   BIT(18)
@@ -1024,8 +1044,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  #define RT3883_GPIO_MODE_PCI_SHIFT    11
  #define RT3883_GPIO_MODE_PCI_MASK     0x7
  #define RT3883_GPIO_MODE_PCI          (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
+Index: linux-3.10.13/arch/mips/ralink/common.h
+===================================================================
+--- linux-3.10.13.orig/arch/mips/ralink/common.h       2013-10-02 16:59:28.532051276 +0200
++++ linux-3.10.13/arch/mips/ralink/common.h    2013-10-02 16:59:29.444051317 +0200
 @@ -11,25 +11,6 @@
  
  #define RAMIPS_SYS_TYPE_LEN   32
@@ -1052,8 +1074,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  struct ralink_soc_info {
        unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
        unsigned char *compatible;
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
+Index: linux-3.10.13/arch/mips/ralink/rt3883.c
+===================================================================
+--- linux-3.10.13.orig/arch/mips/ralink/rt3883.c       2013-09-27 02:18:49.000000000 +0200
++++ linux-3.10.13/arch/mips/ralink/rt3883.c    2013-10-02 16:59:29.444051317 +0200
 @@ -17,132 +17,50 @@
  #include <asm/mipsregs.h>
  #include <asm/mach-ralink/ralink_regs.h>
@@ -1225,7 +1249,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  static void rt3883_wdt_reset(void)
-@@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
+@@ -155,17 +73,6 @@
        rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
  }
  
@@ -1243,7 +1267,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  void __init ralink_clk_init(void)
  {
        unsigned long cpu_rate, sys_rate;
-@@ -243,4 +150,6 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -243,4 +150,6 @@
        soc_info->mem_base = RT3883_SDRAM_BASE;
        soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
        soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
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