--- /dev/null
+From 34a9a634432a95d8ae9af86d41fdaf32fb039c2c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 27 Mar 2013 21:10:14 +0100
+Subject: [PATCH 1/5] MIPS: ralink: fix uartmux group handling
+
+ * don't try get 'ralink,uartmux' porperty if the pinmux.uart is
+ not initialized,
+ * don't touch 'mode' value if mux mask is zero
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ralink/pinmux.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/ralink/pinmux.c
++++ b/arch/mips/ralink/pinmux.c
+@@ -56,15 +56,19 @@ void ralink_pinmux(void)
+ }
+ }
+
+- of_property_read_string(np, "ralink,uartmux", &uart);
++ uart = NULL;
++ if (rt_pinmux.uart)
++ of_property_read_string(np, "ralink,uartmux", &uart);
++
+ if (uart) {
+ int m = ralink_mux_mask(uart, rt_pinmux.uart);
+- mode |= rt_pinmux.uart_mask << rt_pinmux.uart_shift;
++
+ if (m) {
+- mode &= ~(m << rt_pinmux.uart_shift);
++ mode &= ~(rt_pinmux.uart_mask << rt_pinmux.uart_shift);
++ mode |= m << rt_pinmux.uart_shift;
+ pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
+ } else {
+- pr_debug("pinmux: registered uartmux \"gpio\"\n");
++ pr_debug("pinmux: unknown uartmux \"%s\"\n", uart);
+ }
+ }
+
--- /dev/null
+From 8818e2d260e7f98fd5388f9ba56f54b788e175f0 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 27 Mar 2013 20:42:18 +0100
+Subject: [PATCH 2/5] MIPS: ralink: add pci group to struct ralink_pinmux
+
+This will be used for RT3662/RT3883.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ralink/common.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -24,6 +24,9 @@ struct ralink_pinmux {
+ int uart_shift;
+ u32 uart_mask;
+ void (*wdt_reset)(void);
++ struct ralink_pinmux_grp *pci;
++ int pci_shift;
++ u32 pci_mask;
+ };
+ extern struct ralink_pinmux rt_pinmux;
+
--- /dev/null
+From fe26f3e7d1329fc2a5ac14808dbecb7d324d0a41 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 27 Mar 2013 20:56:22 +0100
+Subject: [PATCH 3/5] MIPS: ralink: process PCI pinmux group
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ralink/pinmux.c | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/pinmux.c
++++ b/arch/mips/ralink/pinmux.c
+@@ -29,7 +29,7 @@ void ralink_pinmux(void)
+ const __be32 *wdt;
+ struct device_node *np;
+ struct property *prop;
+- const char *uart, *pin;
++ const char *uart, *pci, *pin;
+ u32 mode = 0;
+
+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-sysc");
+@@ -76,5 +76,17 @@ void ralink_pinmux(void)
+ if (wdt && *wdt && rt_pinmux.wdt_reset)
+ rt_pinmux.wdt_reset();
+
++ of_property_read_string(np, "ralink,pcimux", &pci);
++ if (pci) {
++ int m = ralink_mux_mask(pci, rt_pinmux.pci);
++ mode &= ~(rt_pinmux.pci_mask << rt_pinmux.pci_shift);
++ if (m) {
++ mode |= (m << rt_pinmux.pci_shift);
++ pr_debug("pinmux: registered pcimux \"%s\"\n", pci);
++ } else {
++ pr_debug("pinmux: registered pcimux \"gpio\"\n");
++ }
++ }
++
+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
+ }
--- /dev/null
+From 2c868d77c161ce7dea8facf203c155924d776c33 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 27 Mar 2013 20:50:40 +0100
+Subject: [PATCH 4/5] MIPS: ralink: add PCI pinmux group for RT3883
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ralink/rt3883.c | 32 ++++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -113,6 +113,35 @@ struct ralink_pinmux_grp uart_mux[] = {
+ }, {0}
+ };
+
++struct ralink_pinmux_grp pci_mux[] = {
++ {
++ .name = "pci-dev",
++ .mask = 0,
++ .gpio_first = RT3883_GPIO_PCI_AD0,
++ .gpio_last = RT3883_GPIO_PCI_AD31,
++ }, {
++ .name = "pci-host2",
++ .mask = 1,
++ .gpio_first = RT3883_GPIO_PCI_AD0,
++ .gpio_last = RT3883_GPIO_PCI_AD31,
++ }, {
++ .name = "pci-host1",
++ .mask = 2,
++ .gpio_first = RT3883_GPIO_PCI_AD0,
++ .gpio_last = RT3883_GPIO_PCI_AD31,
++ }, {
++ .name = "pci-fnc",
++ .mask = 3,
++ .gpio_first = RT3883_GPIO_PCI_AD0,
++ .gpio_last = RT3883_GPIO_PCI_AD31,
++ }, {
++ .name = "pci-gpio",
++ .mask = 7,
++ .gpio_first = RT3883_GPIO_PCI_AD0,
++ .gpio_last = RT3883_GPIO_PCI_AD31,
++ }, {0}
++};
++
+ static void rt3883_wdt_reset(void)
+ {
+ u32 t;
+@@ -129,6 +158,9 @@ struct ralink_pinmux rt_pinmux = {
+ .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
+ .uart_mask = RT3883_GPIO_MODE_GPIO,
+ .wdt_reset = rt3883_wdt_reset,
++ .pci = pci_mux,
++ .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
++ .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
+ };
+
+ void __init ralink_clk_init(void)
--- /dev/null
+From 79a01992e15216544dcfdc0be9f2f7695952d047 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 27 Mar 2013 20:59:26 +0100
+Subject: [PATCH 5/5] MIPS: ralink: add GPIO mode to RT3883 UART pinmux group
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ralink/rt3883.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -110,6 +110,11 @@ struct ralink_pinmux_grp uart_mux[] = {
+ .mask = RT3883_GPIO_MODE_GPIO_I2S,
+ .gpio_first = RT3883_GPIO_7,
+ .gpio_last = RT3883_GPIO_14,
++ }, {
++ .name = "gpio",
++ .mask = RT3883_GPIO_MODE_GPIO,
++ .gpio_first = RT3883_GPIO_7,
++ .gpio_last = RT3883_GPIO_14,
+ }, {0}
+ };
+
projects / openwrt.git / commitdiff