+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_MT7628AN_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-# CONFIG_GPIO_MT7621 is not set
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INET_LRO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MT7621_WDT is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_MT7620=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MT7620=y
-# CONFIG_NET_RALINK_RT305X is not set
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-CONFIG_RA_NAT_NONE=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_BOARD_SCACHE=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_CEVT_GIC is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_EI=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7621_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_GIC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-CONFIG_MIPS_CMP=y
-CONFIG_MIPS_CPU_SCACHE=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=6
-CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT=y
-# CONFIG_MIPS_MT_DISABLED is not set
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-# CONFIG_MIPS_MT_SMTC is not set
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_TRX_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MT7620=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_SCHED_SMT=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-# CONFIG_SOC_MT7620 is not set
-CONFIG_SOC_MT7621=y
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_STOP_MACHINE=y
-CONFIG_SWCONFIG=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS_CMP=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TREE_RCU=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_MT7621_XHCI_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_XPS=y
-CONFIG_ZONE_DMA_FLAG=0
-# CONFIG_MTK_MTD_NAND is not set
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_MT7628AN_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INET_LRO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_MT7620=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_ESW_RT3052=y
-# CONFIG_NET_RALINK_MT7620 is not set
-CONFIG_NET_RALINK_RT305X=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RA_NAT_NONE=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-From 453850d315070678245f61202ae343153589e5a6 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:16:50 +0100
-Subject: [PATCH 01/57] MIPS: ralink: add verbose pmu info
-
-Print the PMU and LDO settings on boot.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -20,6 +20,22 @@
-
- #include "common.h"
-
-+/* analog */
-+#define PMU0_CFG 0x88
-+#define PMU_SW_SET BIT(28)
-+#define A_DCDC_EN BIT(24)
-+#define A_SSC_PERI BIT(19)
-+#define A_SSC_GEN BIT(18)
-+#define A_SSC_M 0x3
-+#define A_SSC_S 16
-+#define A_DLY_M 0x7
-+#define A_DLY_S 8
-+#define A_VTUNE_M 0xff
-+
-+/* digital */
-+#define PMU1_CFG 0x8C
-+#define DIG_SW_SEL BIT(25)
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-
-@@ -339,6 +355,8 @@ void prom_soc_init(struct ralink_soc_inf
- u32 n1;
- u32 rev;
- u32 cfg0;
-+ u32 pmu0;
-+ u32 pmu1;
-
- n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
- n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-@@ -386,4 +404,12 @@ void prom_soc_init(struct ralink_soc_inf
- BUG();
- }
- soc_info->mem_base = MT7620_DRAM_BASE;
-+
-+ pmu0 = __raw_readl(sysc + PMU0_CFG);
-+ pmu1 = __raw_readl(sysc + PMU1_CFG);
-+
-+ pr_info("Analog PMU set to %s control\n",
-+ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
-+ pr_info("Digital PMU set to %s control\n",
-+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
- }
+++ /dev/null
-From 1751f28d4779df83cc793c9d7ff75485c0ceaa23 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 04:53:02 +0000
-Subject: [PATCH 02/57] MIPS: ralink: add a helper for reading the ECO version
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -105,4 +105,9 @@
- #define MT7620_GPIO_MODE_EPHY BIT(15)
- #define MT7620_GPIO_MODE_WDT BIT(22)
-
-+static inline int mt7620_get_eco(void)
-+{
-+ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
-+}
-+
- #endif
+++ /dev/null
-From 0f0f041cd6a05eb865e391155d3299bb55ff00e3 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 19 May 2013 00:42:23 +0200
-Subject: [PATCH 03/57] MIPS: ralink: add rt_sysc_m32 helper
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/ralink_regs.h | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
-+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
-@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned r
- return __raw_readl(rt_sysc_membase + reg);
- }
-
-+static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
-+{
-+ u32 val = rt_sysc_r32(reg) & ~clr;
-+
-+ __raw_writel(val | set, rt_sysc_membase + reg);
-+}
-+
- static inline void rt_memc_w32(u32 val, unsigned reg)
- {
- __raw_writel(val, rt_memc_membase + reg);
+++ /dev/null
-From af03898c74172ab16d610f3eeaa65f66401eb7db Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 21 May 2013 15:50:31 +0200
-Subject: [PATCH 04/57] MIPS: ralink: adds a bootrom dumper module
-
-This patch adds a trivial driver that allows userland to extract the bootrom of
-a SoC via debugfs.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Makefile | 2 ++
- arch/mips/ralink/bootrom.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 50 insertions(+)
- create mode 100644 arch/mips/ralink/bootrom.c
-
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -17,4 +17,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
-+obj-$(CONFIG_DEBUG_FS) += bootrom.o
-+
- obj-y += dts/
---- /dev/null
-+++ b/arch/mips/ralink/bootrom.c
-@@ -0,0 +1,48 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/debugfs.h>
-+#include <linux/seq_file.h>
-+
-+#define BOOTROM_OFFSET 0x10118000
-+#define BOOTROM_SIZE 0x8000
-+
-+static void __iomem *membase = (void __iomem*) KSEG1ADDR(BOOTROM_OFFSET);
-+
-+static int bootrom_show(struct seq_file *s, void *unused)
-+{
-+ seq_write(s, membase, BOOTROM_SIZE);
-+
-+ return 0;
-+}
-+
-+static int bootrom_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, bootrom_show, NULL);
-+}
-+
-+static const struct file_operations bootrom_file_ops = {
-+ .open = bootrom_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+static int bootrom_setup(void)
-+{
-+ if (!debugfs_create_file("bootrom", 0444,
-+ NULL, NULL, &bootrom_file_ops)) {
-+ pr_err("Failed to create bootrom debugfs file\n");
-+
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+postcore_initcall(bootrom_setup);
+++ /dev/null
-From 60999174904c731e55992a4087999bbd4e5f2051 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 May 2013 23:28:23 +0200
-Subject: [PATCH 05/57] MIPS: ralink: add illegal access driver
-
-these SoCs have a special irq that fires upon an illegal memmory access.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Makefile | 2 +
- arch/mips/ralink/ill_acc.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 89 insertions(+)
- create mode 100644 arch/mips/ralink/ill_acc.c
-
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -10,6 +10,8 @@ obj-y := prom.o of.o reset.o clk.o irq.o
-
- obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
-
-+obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
-+
- obj-$(CONFIG_SOC_RT288X) += rt288x.o
- obj-$(CONFIG_SOC_RT305X) += rt305x.o
- obj-$(CONFIG_SOC_RT3883) += rt3883.o
---- /dev/null
-+++ b/arch/mips/ralink/ill_acc.c
-@@ -0,0 +1,87 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define REG_ILL_ACC_ADDR 0x10
-+#define REG_ILL_ACC_TYPE 0x14
-+
-+#define ILL_INT_STATUS BIT(31)
-+#define ILL_ACC_WRITE BIT(30)
-+#define ILL_ACC_LEN_M 0xff
-+#define ILL_ACC_OFF_M 0xf
-+#define ILL_ACC_OFF_S 16
-+#define ILL_ACC_ID_M 0x7
-+#define ILL_ACC_ID_S 8
-+
-+#define DRV_NAME "ill_acc"
-+
-+static const char *ill_acc_ids[] = {
-+ "cpu", "dma", "ppe", "pdma rx","pdma tx", "pci/e", "wmac", "usb",
-+};
-+
-+static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
-+{
-+ struct device *dev = (struct device *) _priv;
-+ u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
-+ u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
-+
-+ dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
-+ (type & ILL_ACC_WRITE) ? ("write") : ("read"),
-+ ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
-+ addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
-+ type & ILL_ACC_LEN_M);
-+
-+ rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int __init ill_acc_of_setup(void)
-+{
-+ struct platform_device *pdev;
-+ struct device_node *np;
-+ int irq;
-+
-+ /* somehow this driver breaks on RT5350 */
-+ if (of_machine_is_compatible("ralink,rt5350-soc"))
-+ return -EINVAL;
-+
-+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
-+ if (!np)
-+ return -EINVAL;
-+
-+ pdev = of_find_device_by_node(np);
-+ if (!pdev) {
-+ pr_err("%s: failed to lookup pdev\n", np->name);
-+ return -EINVAL;
-+ }
-+
-+ irq = irq_of_parse_and_map(np, 0);
-+ if (!irq) {
-+ dev_err(&pdev->dev, "failed to get irq\n");
-+ return -EINVAL;
-+ }
-+
-+ if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
-+ dev_err(&pdev->dev, "failed to request irq\n");
-+ return -EINVAL;
-+ }
-+
-+ rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
-+
-+ dev_info(&pdev->dev, "irq registered\n");
-+
-+ return 0;
-+}
-+
-+arch_initcall(ill_acc_of_setup);
+++ /dev/null
-From 979ad9f0324ad8fa5eb4a00b57d9feb061aa3200 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 04:38:07 +0000
-Subject: [PATCH 06/57] MIPS: ralink: add missing clk_set_rate() to clk.c
-
-This function was missing causing allmod to fail.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/clk.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/mips/ralink/clk.c
-+++ b/arch/mips/ralink/clk.c
-@@ -56,6 +56,12 @@ unsigned long clk_get_rate(struct clk *c
- }
- EXPORT_SYMBOL_GPL(clk_get_rate);
-
-+int clk_set_rate(struct clk *clk, unsigned long rate)
-+{
-+ return -1;
-+}
-+EXPORT_SYMBOL_GPL(clk_set_rate);
-+
- void __init plat_time_init(void)
- {
- struct clk *clk;
+++ /dev/null
-From efc0f99cebcab21dbabcc634b9dbb963bbbbcab8 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:23:36 +0100
-Subject: [PATCH 07/57] MIPS: ralink: add support for MT7620n
-
-This is the small version of MT7620a.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 7 ++-----
- arch/mips/ralink/mt7620.c | 19 ++++++++++++-------
- 2 files changed, 14 insertions(+), 12 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -25,11 +25,8 @@
- #define SYSC_REG_CPLL_CONFIG0 0x54
- #define SYSC_REG_CPLL_CONFIG1 0x58
-
--#define MT7620N_CHIP_NAME0 0x33365452
--#define MT7620N_CHIP_NAME1 0x20203235
--
--#define MT7620A_CHIP_NAME0 0x3637544d
--#define MT7620A_CHIP_NAME1 0x20203032
-+#define MT7620_CHIP_NAME0 0x3637544d
-+#define MT7620_CHIP_NAME1 0x20203032
-
- #define SYSCFG0_XTAL_FREQ_SEL BIT(6)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -357,22 +357,27 @@ void prom_soc_init(struct ralink_soc_inf
- u32 cfg0;
- u32 pmu0;
- u32 pmu1;
-+ u32 bga;
-
- n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
- n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
-+ bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
-
-- if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
-- name = "MT7620N";
-- soc_info->compatible = "ralink,mt7620n-soc";
-- } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
-+ if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
-+ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
-+
-+ if (bga) {
- name = "MT7620A";
- soc_info->compatible = "ralink,mt7620a-soc";
- } else {
-- panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1);
-+ name = "MT7620N";
-+ soc_info->compatible = "ralink,mt7620n-soc";
-+#ifdef CONFIG_PCI
-+ panic("mt7620n is only supported for non pci kernels");
-+#endif
- }
-
-- rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
--
- snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
- "Ralink %s ver:%u eco:%u",
- name,
+++ /dev/null
-From 071e97587a291d3a5bbd614a425f46b7f90310aa Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 04:40:48 +0000
-Subject: [PATCH 08/57] MIPS: ralink: allow manual memory override
-
-RT5350 relies on the bootloader setting up the memc correctly.
-On sme boards the setup is incorrect leading to 32 MB being available but only 16 being recognized. Allow these boards to manually override the memory range
-.
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c | 16 +++++++++++++++-
- 1 file changed, 15 insertions(+), 1 deletion(-)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -78,6 +78,17 @@ void __init device_tree_init(void)
- free_bootmem(base, size);
- }
-
-+static int memory_dtb;
-+
-+static int __init early_init_dt_find_memory(unsigned long node, const char *uname,
-+ int depth, void *data)
-+{
-+ if (depth == 1 && !strcmp(uname, "memory@0"))
-+ memory_dtb = 1;
-+
-+ return 0;
-+}
-+
- void __init plat_mem_setup(void)
- {
- set_io_port_base(KSEG1);
-@@ -88,7 +99,10 @@ void __init plat_mem_setup(void)
- */
- __dt_setup_arch(&__dtb_start);
-
-- if (soc_info.mem_size)
-+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
-+ if (memory_dtb)
-+ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
-+ else if (soc_info.mem_size)
- add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
- BOOT_MEM_RAM);
- else
+++ /dev/null
-From 1cb19fe02c830e278b91498edea09fbda37c4a21 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 10:13:43 +0100
-Subject: [PATCH 09/57] MIPS: ralink: define the wmac clock on mt7620
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -336,6 +336,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000500.uart", periph_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", periph_rate);
-+ ralink_clk_add("10180000.wmac", xtal_rate);
- }
-
- void __init ralink_of_remap(void)
+++ /dev/null
-From 1f17cf131fc2ae7fa2651dbe6a622dd125939718 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 10:14:30 +0100
-Subject: [PATCH 10/57] MIPS: ralink: define the wmac clock on rt3883
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/rt3883.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -204,6 +204,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", 40000000);
- ralink_clk_add("10100000.ethernet", sys_rate);
-+ ralink_clk_add("10180000.wmac", 40000000);
- }
-
- void __init ralink_of_remap(void)
+++ /dev/null
-From bf4f5250117cd65a78903b8ce302499806416ed1 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Aug 2014 09:52:22 +0200
-Subject: [PATCH 11/57] MIPS: ralink: add rt2880 wmac clock
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/rt288x.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/mips/ralink/rt288x.c
-+++ b/arch/mips/ralink/rt288x.c
-@@ -76,7 +76,7 @@ struct ralink_pinmux rt_gpio_pinmux = {
-
- void __init ralink_clk_init(void)
- {
-- unsigned long cpu_rate;
-+ unsigned long cpu_rate, wmac_rate = 40000000;
- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
- t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
-
-@@ -101,6 +101,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("300500.uart", cpu_rate / 2);
- ralink_clk_add("300c00.uartlite", cpu_rate / 2);
- ralink_clk_add("400000.ethernet", cpu_rate / 2);
-+ ralink_clk_add("480000.wmac", wmac_rate);
- }
-
- void __init ralink_of_remap(void)
+++ /dev/null
-From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 10:57:40 +0100
-Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/gic.h | 4 +
- arch/mips/include/asm/mach-ralink/irq.h | 9 +
- arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
- arch/mips/kernel/vmlinux.lds.S | 1 +
- arch/mips/ralink/Kconfig | 18 ++
- arch/mips/ralink/Makefile | 7 +-
- arch/mips/ralink/Platform | 5 +
- arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
- arch/mips/ralink/malta-amon.c | 81 +++++++++
- arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
- 10 files changed, 617 insertions(+), 1 deletion(-)
- create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
- create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
- create mode 100644 arch/mips/ralink/irq-gic.c
- create mode 100644 arch/mips/ralink/malta-amon.c
- create mode 100644 arch/mips/ralink/mt7621.c
-
---- a/arch/mips/include/asm/gic.h
-+++ b/arch/mips/include/asm/gic.h
-@@ -19,7 +19,11 @@
- #define GIC_TRIG_EDGE 1
- #define GIC_TRIG_LEVEL 0
-
-+#define GIC_NUM_INTRS 64
-+
-+#ifndef GIC_NUM_INTRS
- #define GIC_NUM_INTRS (24 + NR_CPUS * 2)
-+#endif
-
- #define MSK(n) ((1 << (n)) - 1)
- #define REG32(addr) (*(volatile unsigned int *) (addr))
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/irq.h
-@@ -0,0 +1,9 @@
-+#ifndef __ASM_MACH_RALINK_IRQ_H
-+#define __ASM_MACH_RALINK_IRQ_H
-+
-+#define GIC_NUM_INTRS 64
-+#define NR_IRQS 256
-+
-+#include_next <irq.h>
-+
-+#endif
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
-@@ -0,0 +1,39 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Parts of this file are based on Ralink's 2.6.21 BSP
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#ifndef _MT7621_REGS_H_
-+#define _MT7621_REGS_H_
-+
-+#define MT7621_SYSC_BASE 0x1E000000
-+
-+#define SYSC_REG_CHIP_NAME0 0x00
-+#define SYSC_REG_CHIP_NAME1 0x04
-+#define SYSC_REG_CHIP_REV 0x0c
-+#define SYSC_REG_SYSTEM_CONFIG0 0x10
-+#define SYSC_REG_SYSTEM_CONFIG1 0x14
-+
-+#define CHIP_REV_PKG_MASK 0x1
-+#define CHIP_REV_PKG_SHIFT 16
-+#define CHIP_REV_VER_MASK 0xf
-+#define CHIP_REV_VER_SHIFT 8
-+#define CHIP_REV_ECO_MASK 0xf
-+
-+#define MT7621_DRAM_BASE 0x0
-+#define MT7621_DDR2_SIZE_MIN 32
-+#define MT7621_DDR2_SIZE_MAX 256
-+
-+#define MT7621_CHIP_NAME0 0x3637544D
-+#define MT7621_CHIP_NAME1 0x20203132
-+
-+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
-+
-+#endif
---- a/arch/mips/kernel/vmlinux.lds.S
-+++ b/arch/mips/kernel/vmlinux.lds.S
-@@ -51,6 +51,7 @@ SECTIONS
- /* read-only */
- _text = .; /* Text and read-only data */
- .text : {
-+ /*. = . + 0x8000; */
- TEXT_TEXT
- SCHED_TEXT
- LOCK_TEXT
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -7,6 +7,11 @@ config CLKEVT_RT3352
- select CLKSRC_OF
- select CLKSRC_MMIO
-
-+config IRQ_INTC
-+ bool
-+ default y
-+ depends on !SOC_MT7621
-+
- choice
- prompt "Ralink SoC selection"
- default SOC_RT305X
-@@ -34,6 +39,15 @@ choice
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
-
-+ config SOC_MT7621
-+ bool "MT7621"
-+ select MIPS_CPU_SCACHE
-+ select SYS_SUPPORTS_MULTITHREADING
-+ select SYS_SUPPORTS_SMP
-+ select SYS_SUPPORTS_MIPS_CMP
-+ select IRQ_GIC
-+ select HW_HAS_PCI
-+
- endchoice
-
- choice
-@@ -61,6 +75,10 @@ choice
- bool "MT7620A eval kit"
- depends on SOC_MT7620
-
-+ config DTB_MT7621_EVAL
-+ bool "MT7621 eval kit"
-+ depends on SOC_MT7621
-+
- endchoice
-
- endif
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -6,16 +6,21 @@
- # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-
--obj-y := prom.o of.o reset.o clk.o irq.o timer.o
-+obj-y := prom.o of.o reset.o clk.o timer.o
-
- obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
-
- obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
-
-+obj-$(CONFIG_IRQ_INTC) += irq.o
-+obj-$(CONFIG_IRQ_GIC) += irq-gic.o
-+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
-+
- obj-$(CONFIG_SOC_RT288X) += rt288x.o
- obj-$(CONFIG_SOC_RT305X) += rt305x.o
- obj-$(CONFIG_SOC_RT3883) += rt3883.o
- obj-$(CONFIG_SOC_MT7620) += mt7620.o
-+obj-$(CONFIG_SOC_MT7621) += mt7621.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
---- a/arch/mips/ralink/Platform
-+++ b/arch/mips/ralink/Platform
-@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
- #
- load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
- cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
-+
-+# Ralink MT7621
-+#
-+load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
-+cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
---- /dev/null
-+++ b/arch/mips/ralink/irq-gic.c
-@@ -0,0 +1,271 @@
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/hardirq.h>
-+#include <linux/preempt.h>
-+#include <linux/irqdomain.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+
-+#include <asm/irq_cpu.h>
-+#include <asm/mipsregs.h>
-+
-+#include <asm/irq.h>
-+#include <asm/setup.h>
-+
-+#include <asm/gic.h>
-+#include <asm/gcmpregs.h>
-+
-+#include <asm/mach-ralink/mt7621.h>
-+
-+unsigned long _gcmp_base;
-+static int gic_resched_int_base = 56;
-+static int gic_call_int_base = 60;
-+static struct irq_chip *irq_gic;
-+static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
-+
-+#if defined(CONFIG_MIPS_MT_SMP)
-+static int gic_resched_int_base;
-+static int gic_call_int_base;
-+
-+#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
-+#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
-+
-+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
-+{
-+ scheduler_ipi();
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t
-+ipi_call_interrupt(int irq, void *dev_id)
-+{
-+ smp_call_function_interrupt();
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction irq_resched = {
-+ .handler = ipi_resched_interrupt,
-+ .flags = IRQF_DISABLED|IRQF_PERCPU,
-+ .name = "ipi resched"
-+};
-+
-+static struct irqaction irq_call = {
-+ .handler = ipi_call_interrupt,
-+ .flags = IRQF_DISABLED|IRQF_PERCPU,
-+ .name = "ipi call"
-+};
-+
-+#endif
-+
-+static void __init
-+gic_fill_map(void)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
-+ gic_intr_map[i].cpunum = 0;
-+ gic_intr_map[i].pin = GIC_CPU_INT0;
-+ gic_intr_map[i].polarity = GIC_POL_POS;
-+ gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
-+ gic_intr_map[i].flags = GIC_FLAG_IPI;
-+ }
-+
-+#if defined(CONFIG_MIPS_MT_SMP)
-+ {
-+ int cpu;
-+
-+ gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
-+ gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
-+
-+ i = gic_resched_int_base;
-+
-+ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
-+ gic_intr_map[i + cpu].cpunum = cpu;
-+ gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
-+ gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
-+
-+ gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
-+ gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
-+ gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
-+ }
-+ }
-+#endif
-+}
-+
-+void
-+gic_irq_ack(struct irq_data *d)
-+{
-+ int irq = (d->irq - gic_irq_base);
-+
-+ GIC_CLR_INTR_MASK(irq);
-+
-+ if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
-+ GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
-+}
-+
-+void
-+gic_finish_irq(struct irq_data *d)
-+{
-+ GIC_SET_INTR_MASK(d->irq - gic_irq_base);
-+}
-+
-+void __init
-+gic_platform_init(int irqs, struct irq_chip *irq_controller)
-+{
-+ irq_gic = irq_controller;
-+}
-+
-+static void
-+gic_irqdispatch(void)
-+{
-+ unsigned int irq = gic_get_int();
-+
-+ if (likely(irq < GIC_NUM_INTRS))
-+ do_IRQ(MIPS_GIC_IRQ_BASE + irq);
-+ else {
-+ pr_debug("Spurious GIC Interrupt!\n");
-+ spurious_interrupt();
-+ }
-+
-+}
-+
-+static void
-+vi_timer_irqdispatch(void)
-+{
-+ do_IRQ(cp0_compare_irq);
-+}
-+
-+#if defined(CONFIG_MIPS_MT_SMP)
-+unsigned int
-+plat_ipi_call_int_xlate(unsigned int cpu)
-+{
-+ return GIC_CALL_INT(cpu);
-+}
-+
-+unsigned int
-+plat_ipi_resched_int_xlate(unsigned int cpu)
-+{
-+ return GIC_RESCHED_INT(cpu);
-+}
-+#endif
-+
-+asmlinkage void
-+plat_irq_dispatch(void)
-+{
-+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
-+
-+ if (unlikely(!pending)) {
-+ pr_err("Spurious CP0 Interrupt!\n");
-+ spurious_interrupt();
-+ } else {
-+ if (pending & CAUSEF_IP7)
-+ do_IRQ(cp0_compare_irq);
-+
-+ if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
-+ gic_irqdispatch();
-+ }
-+}
-+
-+unsigned int __cpuinit
-+get_c0_compare_int(void)
-+{
-+ return CP0_LEGACY_COMPARE_IRQ;
-+}
-+
-+static int
-+gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, irq_gic,
-+#if defined(CONFIG_MIPS_MT_SMP)
-+ (hw >= gic_resched_int_base) ?
-+ handle_percpu_irq :
-+#endif
-+ handle_level_irq);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = gic_map,
-+};
-+
-+static int __init
-+of_gic_init(struct device_node *node,
-+ struct device_node *parent)
-+{
-+ struct irq_domain *domain;
-+ struct resource gcmp = { 0 }, gic = { 0 };
-+ unsigned int gic_rev;
-+ int i;
-+
-+ if (of_address_to_resource(node, 0, &gic))
-+ panic("Failed to get gic memory range");
-+ if (request_mem_region(gic.start, resource_size(&gic),
-+ gic.name) < 0)
-+ panic("Failed to request gic memory");
-+ if (of_address_to_resource(node, 2, &gcmp))
-+ panic("Failed to get gic memory range");
-+ if (request_mem_region(gcmp.start, resource_size(&gcmp),
-+ gcmp.name) < 0)
-+ panic("Failed to request gcmp memory");
-+
-+ _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
-+ if (!_gcmp_base)
-+ panic("Failed to remap gcmp memory\n");
-+
-+ if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
-+ panic("Failed to find gcmp core\n");
-+
-+ /* tell the gcmp where to find the gic */
-+ GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
-+ gic_present = 1;
-+ if (cpu_has_vint) {
-+ set_vi_handler(2, gic_irqdispatch);
-+ set_vi_handler(3, gic_irqdispatch);
-+ set_vi_handler(4, gic_irqdispatch);
-+ set_vi_handler(7, vi_timer_irqdispatch);
-+ }
-+
-+ gic_fill_map();
-+
-+ gic_init(gic.start, resource_size(&gic), gic_intr_map,
-+ ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
-+
-+ GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
-+ pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
-+
-+ domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
-+ 0, &irq_domain_ops, NULL);
-+ if (!domain)
-+ panic("Failed to add irqdomain");
-+
-+#if defined(CONFIG_MIPS_MT_SMP)
-+ for (i = 0; i < nr_cpu_ids; i++) {
-+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
-+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
-+ }
-+#endif
-+
-+ change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
-+ STATUSF_IP2);
-+ return 0;
-+}
-+
-+static struct of_device_id __initdata of_irq_ids[] = {
-+ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
-+ { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
-+ {},
-+};
-+
-+void __init
-+arch_init_irq(void)
-+{
-+ of_irq_init(of_irq_ids);
-+}
---- /dev/null
-+++ b/arch/mips/ralink/malta-amon.c
-@@ -0,0 +1,81 @@
-+/*
-+ * Copyright (C) 2007 MIPS Technologies, Inc.
-+ * All rights reserved.
-+
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * Arbitrary Monitor interface
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/smp.h>
-+
-+#include <asm/addrspace.h>
-+#include <asm/mips-boards/launch.h>
-+#include <asm/mipsmtregs.h>
-+
-+int amon_cpu_avail(int cpu)
-+{
-+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
-+
-+ if (cpu < 0 || cpu >= NCPULAUNCH) {
-+ pr_debug("avail: cpu%d is out of range\n", cpu);
-+ return 0;
-+ }
-+
-+ launch += cpu;
-+ if (!(launch->flags & LAUNCH_FREADY)) {
-+ pr_debug("avail: cpu%d is not ready\n", cpu);
-+ return 0;
-+ }
-+ if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
-+ pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+
-+void amon_cpu_start(int cpu,
-+ unsigned long pc, unsigned long sp,
-+ unsigned long gp, unsigned long a0)
-+{
-+ volatile struct cpulaunch *launch =
-+ (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
-+
-+ if (!amon_cpu_avail(cpu))
-+ return;
-+ if (cpu == smp_processor_id()) {
-+ pr_debug("launch: I am cpu%d!\n", cpu);
-+ return;
-+ }
-+ launch += cpu;
-+
-+ pr_debug("launch: starting cpu%d\n", cpu);
-+
-+ launch->pc = pc;
-+ launch->gp = gp;
-+ launch->sp = sp;
-+ launch->a0 = a0;
-+
-+ smp_wmb(); /* Target must see parameters before go */
-+ launch->flags |= LAUNCH_FGO;
-+ smp_wmb(); /* Target must see go before we poll */
-+
-+ while ((launch->flags & LAUNCH_FGONE) == 0)
-+ ;
-+ smp_rmb(); /* Target will be updating flags soon */
-+ pr_debug("launch: cpu%d gone!\n", cpu);
-+}
---- /dev/null
-+++ b/arch/mips/ralink/mt7621.c
-@@ -0,0 +1,183 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Parts of this file are based on Ralink's 2.6.21 BSP
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <asm/gcmpregs.h>
-+
-+#include <asm/mipsregs.h>
-+#include <asm/smp-ops.h>
-+#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/mach-ralink/mt7621.h>
-+
-+#include <pinmux.h>
-+
-+#include "common.h"
-+
-+#define SYSC_REG_SYSCFG 0x10
-+#define SYSC_REG_CPLL_CLKCFG0 0x2c
-+#define SYSC_REG_CUR_CLK_STS 0x44
-+#define CPU_CLK_SEL (BIT(30) | BIT(31))
-+
-+#define MT7621_GPIO_MODE_UART1 1
-+#define MT7621_GPIO_MODE_I2C 2
-+#define MT7621_GPIO_MODE_UART2 3
-+#define MT7621_GPIO_MODE_UART3 5
-+#define MT7621_GPIO_MODE_JTAG 7
-+#define MT7621_GPIO_MODE_WDT_MASK 0x3
-+#define MT7621_GPIO_MODE_WDT_SHIFT 8
-+#define MT7621_GPIO_MODE_WDT_GPIO 1
-+#define MT7621_GPIO_MODE_PCIE_RST 0
-+#define MT7621_GPIO_MODE_PCIE_REF 2
-+#define MT7621_GPIO_MODE_PCIE_MASK 0x3
-+#define MT7621_GPIO_MODE_PCIE_SHIFT 10
-+#define MT7621_GPIO_MODE_PCIE_GPIO 1
-+#define MT7621_GPIO_MODE_MDIO 12
-+#define MT7621_GPIO_MODE_RGMII1 14
-+#define MT7621_GPIO_MODE_RGMII2 15
-+#define MT7621_GPIO_MODE_SPI_MASK 0x3
-+#define MT7621_GPIO_MODE_SPI_SHIFT 16
-+#define MT7621_GPIO_MODE_SPI_GPIO 1
-+#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
-+#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
-+#define MT7621_GPIO_MODE_SDHCI_GPIO 1
-+
-+static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart", 0, 1, 2) };
-+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
-+static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart", 0, 5, 4) };
-+static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart", 0, 9, 4) };
-+static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
-+static struct rt2880_pmx_func wdt_grp[] = {
-+ FUNC("wdt rst", 0, 18, 1),
-+ FUNC("wdt refclk", 2, 18, 1),
-+};
-+static struct rt2880_pmx_func pcie_rst_grp[] = {
-+ FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
-+ FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
-+};
-+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
-+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
-+static struct rt2880_pmx_func spi_grp[] = {
-+ FUNC("spi", 0, 34, 7),
-+ FUNC("nand", 2, 34, 8),
-+};
-+static struct rt2880_pmx_func sdhci_grp[] = {
-+ FUNC("sdhci", 0, 41, 8),
-+ FUNC("nand", 2, 41, 8),
-+};
-+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii", 0, 49, 12) };
-+
-+static struct rt2880_pmx_group mt7621_pinmux_data[] = {
-+ GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
-+ GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
-+ GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
-+ GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
-+ GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
-+ GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
-+ MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
-+ GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
-+ MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
-+ GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
-+ GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
-+ GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
-+ MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
-+ GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
-+ MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
-+ GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
-+ { 0 }
-+};
-+
-+void __init ralink_clk_init(void)
-+{
-+ int cpu_fdiv = 0;
-+ int cpu_ffrac = 0;
-+ int fbdiv = 0;
-+ u32 clk_sts, syscfg;
-+ u8 clk_sel = 0, xtal_mode;
-+ u32 cpu_clk;
-+
-+ if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
-+ clk_sel = 1;
-+
-+ switch (clk_sel) {
-+ case 0:
-+ clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
-+ cpu_fdiv = ((clk_sts >> 8) & 0x1F);
-+ cpu_ffrac = (clk_sts & 0x1F);
-+ cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
-+ break;
-+
-+ case 1:
-+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
-+ syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
-+ xtal_mode = (syscfg >> 6) & 0x7;
-+ if(xtal_mode >= 6) { //25Mhz Xtal
-+ cpu_clk = 25 * fbdiv * 1000 * 1000;
-+ } else if(xtal_mode >=3) { //40Mhz Xtal
-+ cpu_clk = 40 * fbdiv * 1000 * 1000;
-+ } else { // 20Mhz Xtal
-+ cpu_clk = 20 * fbdiv * 1000 * 1000;
-+ }
-+ break;
-+ }
-+ cpu_clk = 880000000;
-+ ralink_clk_add("cpu", cpu_clk);
-+ ralink_clk_add("1e000b00.spi", 50000000);
-+ ralink_clk_add("1e000c00.uartlite", 50000000);
-+ ralink_clk_add("1e000d00.uart", 50000000);
-+}
-+
-+void __init ralink_of_remap(void)
-+{
-+ rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-+ rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
-+
-+ if (!rt_sysc_membase || !rt_memc_membase)
-+ panic("Failed to remap core resources");
-+}
-+
-+void prom_soc_init(struct ralink_soc_info *soc_info)
-+{
-+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
-+ unsigned char *name = NULL;
-+ u32 n0;
-+ u32 n1;
-+ u32 rev;
-+
-+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
-+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-+
-+ if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
-+ name = "MT7621";
-+ soc_info->compatible = "mtk,mt7621-soc";
-+ } else {
-+ panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
-+ }
-+
-+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
-+
-+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
-+ "Mediatek %s ver:%u eco:%u",
-+ name,
-+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
-+ (rev & CHIP_REV_ECO_MASK));
-+
-+ soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
-+ soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
-+ soc_info->mem_base = MT7621_DRAM_BASE;
-+
-+ rt2880_pinmux_data = mt7621_pinmux_data;
-+
-+ if (register_cmp_smp_ops())
-+ panic("failed to register_vsmp_smp_ops()");
-+}
+++ /dev/null
-From 8f92eac5ace0f834ec069b4bb8e9ad38f162de0e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 27 Jan 2014 13:12:41 +0000
-Subject: [PATCH 13/57] MIPS: ralink: add MT7621 defconfig
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/configs/mt7621_defconfig | 197 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 197 insertions(+)
- create mode 100644 arch/mips/configs/mt7621_defconfig
-
---- /dev/null
-+++ b/arch/mips/configs/mt7621_defconfig
-@@ -0,0 +1,197 @@
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_RCU_FANOUT=32
-+CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-mipsel_24kec+dsp_uClibc-0.9.33.2/root-ramips /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
-+CONFIG_INITRAMFS_ROOT_UID=1000
-+CONFIG_INITRAMFS_ROOT_GID=1000
-+# CONFIG_RD_GZIP is not set
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+# CONFIG_AIO is not set
-+CONFIG_EMBEDDED=y
-+# CONFIG_VM_EVENT_COUNTERS is not set
-+# CONFIG_SLUB_DEBUG is not set
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_BLK_DEV_BSG is not set
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_IOSCHED_CFQ is not set
-+CONFIG_SMP=y
-+CONFIG_NR_CPUS=4
-+CONFIG_SCHED_SMT=y
-+# CONFIG_COMPACTION is not set
-+# CONFIG_CROSS_MEMORY_ATTACH is not set
-+# CONFIG_SECCOMP is not set
-+CONFIG_HZ_100=y
-+CONFIG_CMDLINE_BOOL=y
-+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_ARPD=y
-+CONFIG_SYN_COOKIES=y
-+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_BEET is not set
-+# CONFIG_INET_LRO is not set
-+# CONFIG_INET_DIAG is not set
-+CONFIG_TCP_CONG_ADVANCED=y
-+# CONFIG_TCP_CONG_BIC is not set
-+# CONFIG_TCP_CONG_WESTWOOD is not set
-+# CONFIG_TCP_CONG_HTCP is not set
-+CONFIG_IPV6_PRIVACY=y
-+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET6_XFRM_MODE_BEET is not set
-+# CONFIG_IPV6_SIT is not set
-+CONFIG_IPV6_MULTIPLE_TABLES=y
-+CONFIG_IPV6_SUBTREES=y
-+CONFIG_IPV6_MROUTE=y
-+CONFIG_NETFILTER=y
-+# CONFIG_BRIDGE_NETFILTER is not set
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NETFILTER_XT_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_LOG=m
-+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_MAC=m
-+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+CONFIG_NETFILTER_XT_MATCH_TIME=m
-+CONFIG_NF_CONNTRACK_IPV4=m
-+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_NF_NAT_IPV4=m
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_IP_NF_TARGET_REDIRECT=m
-+CONFIG_IP_NF_MANGLE=m
-+CONFIG_IP_NF_RAW=m
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_AH=m
-+CONFIG_IP6_NF_MATCH_EUI64=m
-+CONFIG_IP6_NF_MATCH_FRAG=m
-+CONFIG_IP6_NF_MATCH_OPTS=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_MATCH_MH=m
-+CONFIG_IP6_NF_MATCH_RT=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+CONFIG_IP6_NF_RAW=m
-+CONFIG_BRIDGE=m
-+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-+CONFIG_VLAN_8021Q=y
-+CONFIG_NET_SCHED=y
-+CONFIG_NET_SCH_FQ_CODEL=y
-+CONFIG_HAMRADIO=y
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+# CONFIG_FIRMWARE_IN_KERNEL is not set
-+CONFIG_MTD=y
-+CONFIG_MTD_CMDLINE_PARTS=y
-+CONFIG_MTD_BLOCK=y
-+CONFIG_MTD_CFI=y
-+CONFIG_MTD_CFI_AMDSTD=y
-+CONFIG_MTD_COMPLEX_MAPPINGS=y
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_M25P80=y
-+CONFIG_EEPROM_93CX6=m
-+CONFIG_SCSI=y
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_NETDEVICES=y
-+# CONFIG_NET_PACKET_ENGINE is not set
-+# CONFIG_NET_VENDOR_WIZNET is not set
-+CONFIG_PHYLIB=y
-+CONFIG_SWCONFIG=y
-+CONFIG_PPP=m
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_MULTILINK=y
-+CONFIG_PPPOE=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_ISDN=y
-+# CONFIG_INPUT is not set
-+# CONFIG_SERIO is not set
-+# CONFIG_VT is not set
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_8250=y
-+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-+CONFIG_SERIAL_8250_CONSOLE=y
-+# CONFIG_SERIAL_8250_PCI is not set
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-+CONFIG_SPI=y
-+CONFIG_GPIOLIB=y
-+CONFIG_GPIO_SYSFS=y
-+# CONFIG_HWMON is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_WATCHDOG_CORE=y
-+# CONFIG_VGA_ARB is not set
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_PLATFORM=y
-+CONFIG_USB_MT7621_XHCI_PLATFORM=y
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_PHY=y
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_GPIO=m
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_STAGING=y
-+CONFIG_USB_DWC2=m
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_RESET_CONTROLLER=y
-+# CONFIG_FIRMWARE_MEMMAP is not set
-+# CONFIG_DNOTIFY is not set
-+# CONFIG_PROC_PAGE_MONITOR is not set
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_XATTR=y
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_SUMMARY=y
-+CONFIG_JFFS2_FS_XATTR=y
-+# CONFIG_JFFS2_FS_POSIX_ACL is not set
-+# CONFIG_JFFS2_FS_SECURITY is not set
-+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-+# CONFIG_JFFS2_ZLIB is not set
-+CONFIG_SQUASHFS=y
-+# CONFIG_SQUASHFS_ZLIB is not set
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_PRINTK_TIME=y
-+# CONFIG_ENABLE_MUST_CHECK is not set
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+CONFIG_STRIP_ASM_SYMS=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_SCHED_DEBUG is not set
-+CONFIG_DEBUG_INFO=y
-+CONFIG_DEBUG_INFO_REDUCED=y
-+CONFIG_RCU_CPU_STALL_TIMEOUT=60
-+# CONFIG_FTRACE is not set
-+CONFIG_CRYPTO_ARC4=m
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_VIRTUALIZATION is not set
-+CONFIG_CRC_ITU_T=m
-+CONFIG_CRC32_SARWATE=y
-+# CONFIG_XZ_DEC_X86 is not set
-+CONFIG_AVERAGE=y
+++ /dev/null
-From 34e2a5ededc6140f311b3b3c88edf4e18e88126a Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 24 Jan 2014 17:01:22 +0100
-Subject: [PATCH 14/57] MIPS: ralink: add MT7621 dts file
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/dts/Makefile | 1 +
- arch/mips/ralink/dts/mt7621.dtsi | 257 ++++++++++++++++++++++++++++++++++
- arch/mips/ralink/dts/mt7621_eval.dts | 16 +++
- 3 files changed, 274 insertions(+)
- create mode 100644 arch/mips/ralink/dts/mt7621.dtsi
- create mode 100644 arch/mips/ralink/dts/mt7621_eval.dts
-
---- a/arch/mips/ralink/dts/Makefile
-+++ b/arch/mips/ralink/dts/Makefile
-@@ -2,3 +2,4 @@ obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_
- obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
- obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
- obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
-+obj-$(CONFIG_DTB_MT7621_EVAL) := mt7621_eval.dtb.o
---- /dev/null
-+++ b/arch/mips/ralink/dts/mt7621.dtsi
-@@ -0,0 +1,257 @@
-+/ {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "ralink,mtk7620a-soc";
-+
-+ cpus {
-+ cpu@0 {
-+ compatible = "mips,mips24KEc";
-+ };
-+ };
-+
-+ cpuintc: cpuintc@0 {
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-controller;
-+ compatible = "mti,cpu-interrupt-controller";
-+ };
-+
-+ palmbus@1E000000 {
-+ compatible = "palmbus";
-+ reg = <0x1E000000 0x100000>;
-+ ranges = <0x0 0x1E000000 0x0FFFFF>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ sysc@0 {
-+ compatible = "mtk,mt7621-sysc";
-+ reg = <0x0 0x100>;
-+ };
-+
-+ wdt@100 {
-+ compatible = "mtk,mt7621-wdt";
-+ reg = <0x100 0x100>;
-+ };
-+
-+ gpio@600 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ compatible = "mtk,mt7621-gpio";
-+ reg = <0x600 0x100>;
-+
-+ gpio0: bank@0 {
-+ reg = <0>;
-+ compatible = "mtk,mt7621-gpio-bank";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ };
-+
-+ gpio1: bank@1 {
-+ reg = <1>;
-+ compatible = "mtk,mt7621-gpio-bank";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ };
-+
-+ gpio2: bank@2 {
-+ reg = <2>;
-+ compatible = "mtk,mt7621-gpio-bank";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ };
-+ };
-+
-+ memc@5000 {
-+ compatible = "mtk,mt7621-memc";
-+ reg = <0x300 0x100>;
-+ };
-+
-+ uartlite@c00 {
-+ compatible = "ns16550a";
-+ reg = <0xc00 0x100>;
-+
-+ interrupt-parent = <&gic>;
-+ interrupts = <26>;
-+
-+ reg-shift = <2>;
-+ reg-io-width = <4>;
-+ no-loopback-test;
-+ };
-+
-+ uart@d00 {
-+ compatible = "ns16550a";
-+ reg = <0xd00 0x100>;
-+
-+ interrupt-parent = <&gic>;
-+ interrupts = <27>;
-+
-+ fifo-size = <16>;
-+ reg-shift = <2>;
-+ reg-io-width = <4>;
-+ no-loopback-test;
-+ };
-+
-+ spi@b00 {
-+ status = "okay";
-+
-+ compatible = "ralink,mt7621-spi";
-+ reg = <0xb00 0x100>;
-+
-+ resets = <&rstctrl 18>;
-+ reset-names = "spi";
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+/* pinctrl-names = "default";
-+ pinctrl-0 = <&spi_pins>;*/
-+
-+ m25p80@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "en25q64";
-+ reg = <0 0>;
-+ linux,modalias = "m25p80", "en25q64";
-+ spi-max-frequency = <10000000>;
-+
-+ m25p,chunked-io;
-+
-+ partition@0 {
-+ label = "u-boot";
-+ reg = <0x0 0x30000>;
-+ read-only;
-+ };
-+
-+ partition@30000 {
-+ label = "u-boot-env";
-+ reg = <0x30000 0x10000>;
-+ read-only;
-+ };
-+
-+ factory: partition@40000 {
-+ label = "factory";
-+ reg = <0x40000 0x10000>;
-+ read-only;
-+ };
-+
-+ partition@50000 {
-+ label = "firmware";
-+ reg = <0x50000 0x7a0000>;
-+ };
-+
-+ partition@7f0000 {
-+ label = "test";
-+ reg = <0x7f0000 0x10000>;
-+ };
-+ };
-+ };
-+ };
-+
-+ rstctrl: rstctrl {
-+ compatible = "ralink,rt2880-reset";
-+ #reset-cells = <1>;
-+ };
-+
-+ sdhci@1E130000 {
-+ compatible = "ralink,mt7620a-sdhci";
-+ reg = <0x1E130000 4000>;
-+
-+ interrupt-parent = <&gic>;
-+ interrupts = <20>;
-+ };
-+
-+ xhci@1E1C0000 {
-+ compatible = "xhci-platform";
-+ reg = <0x1E1C0000 4000>;
-+
-+ interrupt-parent = <&gic>;
-+ interrupts = <22>;
-+ };
-+
-+ gic: gic@1fbc0000 {
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-controller;
-+ compatible = "ralink,mt7621-gic";
-+ reg = < 0x1fbc0000 0x80 /* gic */
-+ 0x1fbf0000 0x8000 /* cpc */
-+ 0x1fbf8000 0x8000 /* gpmc */
-+ >;
-+ };
-+
-+ nand@1e003000 {
-+ compatible = "mtk,mt7621-nand";
-+ bank-width = <2>;
-+ reg = <0x1e003000 0x800
-+ 0x1e003800 0x800>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "uboot";
-+ reg = <0x00000 0x80000>; /* 64 KB */
-+ };
-+ partition@80000 {
-+ label = "uboot_env";
-+ reg = <0x80000 0x80000>; /* 64 KB */
-+ };
-+ partition@100000 {
-+ label = "factory";
-+ reg = <0x100000 0x40000>;
-+ };
-+ partition@140000 {
-+ label = "rootfs";
-+ reg = <0x140000 0xec0000>;
-+ };
-+ };
-+
-+ ethernet@1e100000 {
-+ compatible = "ralink,mt7621-eth";
-+ reg = <0x1e100000 10000>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ralink,port-map = "llllw";
-+
-+ interrupt-parent = <&gic>;
-+ interrupts = <3>;
-+
-+/* resets = <&rstctrl 21 &rstctrl 23>;
-+ reset-names = "fe", "esw";
-+
-+ port@4 {
-+ compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
-+ reg = <4>;
-+
-+ status = "disabled";
-+ };
-+
-+ port@5 {
-+ compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
-+ reg = <5>;
-+
-+ status = "disabled";
-+ };
-+*/
-+ mdio-bus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy1f: ethernet-phy@1f {
-+ reg = <0x1f>;
-+ phy-mode = "rgmii";
-+
-+/* interrupt-parent = <&gic>;
-+ interrupts = <23>;
-+*/ };
-+ };
-+ };
-+
-+ gsw@1e110000 {
-+ compatible = "ralink,mt7620a-gsw";
-+ reg = <0x1e110000 8000>;
-+ };
-+};
---- /dev/null
-+++ b/arch/mips/ralink/dts/mt7621_eval.dts
-@@ -0,0 +1,16 @@
-+/dts-v1/;
-+
-+/include/ "mt7621.dtsi"
-+
-+/ {
-+ compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc";
-+ model = "Ralink MT7621 evaluation board";
-+
-+ memory@0 {
-+ reg = <0x0 0x2000000>;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,57600";
-+ };
-+};
+++ /dev/null
-From e410b0069ee7c318a5b556f39b8b16814330a208 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 24 Jan 2014 17:01:17 +0100
-Subject: [PATCH 15/57] MIPS: ralink: cleanup early_printk
-
-Add support for the new MT7621/8 SoC and kill ifdefs.
-Cleanup some whitespace error while we are at it.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/early_printk.c | 45 ++++++++++++++++++++++++++-------------
- 1 file changed, 30 insertions(+), 15 deletions(-)
-
---- a/arch/mips/ralink/early_printk.c
-+++ b/arch/mips/ralink/early_printk.c
-@@ -12,21 +12,24 @@
- #include <asm/addrspace.h>
-
- #ifdef CONFIG_SOC_RT288X
--#define EARLY_UART_BASE 0x300c00
-+#define EARLY_UART_BASE 0x300c00
-+#define CHIPID_BASE 0x300004
-+#elif defined(CONFIG_SOC_MT7621)
-+#define EARLY_UART_BASE 0x1E000c00
-+#define CHIPID_BASE 0x1E000004
- #else
--#define EARLY_UART_BASE 0x10000c00
-+#define EARLY_UART_BASE 0x10000c00
-+#define CHIPID_BASE 0x10000004
- #endif
-
--#define UART_REG_RX 0x00
--#define UART_REG_TX 0x04
--#define UART_REG_IER 0x08
--#define UART_REG_IIR 0x0c
--#define UART_REG_FCR 0x10
--#define UART_REG_LCR 0x14
--#define UART_REG_MCR 0x18
--#define UART_REG_LSR 0x1c
-+#define MT7628_CHIP_NAME1 0x20203832
-+
-+#define UART_REG_TX 0x04
-+#define UART_REG_LSR 0x14
-+#define UART_REG_LSR_RT2880 0x1c
-
- static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
-+static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
-
- static inline void uart_w32(u32 val, unsigned reg)
- {
-@@ -38,11 +41,23 @@ static inline u32 uart_r32(unsigned reg)
- return __raw_readl(uart_membase + reg);
- }
-
-+static inline int soc_is_mt7628(void)
-+{
-+ return IS_ENABLED(CONFIG_SOC_MT7620) &&
-+ (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
-+}
-+
- void prom_putchar(unsigned char ch)
- {
-- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
-- ;
-- uart_w32(ch, UART_REG_TX);
-- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
-- ;
-+ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
-+ uart_w32(ch, UART_TX);
-+ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
-+ ;
-+ } else {
-+ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
-+ ;
-+ uart_w32(ch, UART_REG_TX);
-+ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
-+ ;
-+ }
- }
+++ /dev/null
-From 95d7eb13a864ef666cea7f0e86349e86d80d28ce Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 05:22:39 +0000
-Subject: [PATCH 16/57] MIPS: ralink: add MT7621 pcie driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-mt7621.c | 797 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 798 insertions(+)
- create mode 100644 arch/mips/pci/pci-mt7621.c
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
- obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
- obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
---- /dev/null
-+++ b/arch/mips/pci/pci-mt7621.c
-@@ -0,0 +1,813 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * PCI init for Ralink RT2880 solution
-+ *
-+ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2007 Bruce Chang
-+ * Initial Release
-+ *
-+ * May 2009 Bruce Chang
-+ * support RT2880/RT3883 PCIe
-+ *
-+ * May 2011 Bruce Chang
-+ * support RT6855/MT7620 PCIe
-+ *
-+ **************************************************************************
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/version.h>
-+#include <asm/pci.h>
-+#include <asm/io.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/of.h>
-+#include <linux/of_pci.h>
-+#include <linux/platform_device.h>
-+
-+#include <ralink_regs.h>
-+
-+extern void pcie_phy_init(void);
-+extern void chk_phy_pll(void);
-+
-+/*
-+ * These functions and structures provide the BIOS scan and mapping of the PCI
-+ * devices.
-+ */
-+
-+#define CONFIG_PCIE_PORT0
-+#define CONFIG_PCIE_PORT1
-+#define CONFIG_PCIE_PORT2
-+#define RALINK_PCIE0_CLK_EN (1<<24)
-+#define RALINK_PCIE1_CLK_EN (1<<25)
-+#define RALINK_PCIE2_CLK_EN (1<<26)
-+
-+#define RALINK_PCI_CONFIG_ADDR 0x20
-+#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
-+#define SURFBOARDINT_PCIE0 12 /* PCIE0 */
-+#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
-+#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
-+#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
-+#define SURFBOARDINT_PCIE1 32 /* PCIE1 */
-+#define SURFBOARDINT_PCIE2 33 /* PCIE2 */
-+#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
-+#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
-+#define RALINK_PCIE0_RST (1<<24)
-+#define RALINK_PCIE1_RST (1<<25)
-+#define RALINK_PCIE2_RST (1<<26)
-+#define RALINK_SYSCTL_BASE 0xBE000000
-+
-+#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
-+#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
-+#define RALINK_PCI_BASE 0xBE140000
-+
-+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-+#define RT6855_PCIE0_OFFSET 0x2000
-+#define RT6855_PCIE1_OFFSET 0x3000
-+#define RT6855_PCIE2_OFFSET 0x4000
-+
-+#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
-+#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
-+#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
-+#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
-+#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
-+#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
-+#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
-+#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
-+
-+#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
-+#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
-+#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
-+#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
-+#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
-+#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
-+#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
-+#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
-+
-+#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
-+#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
-+#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
-+#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
-+#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
-+#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
-+#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
-+#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
-+
-+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-+#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
-+
-+
-+#define MV_WRITE(ofs, data) \
-+ *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
-+#define MV_READ(ofs, data) \
-+ *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-+#define MV_READ_DATA(ofs) \
-+ le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-+
-+#define MV_WRITE_16(ofs, data) \
-+ *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-+#define MV_READ_16(ofs, data) \
-+ *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-+
-+#define MV_WRITE_8(ofs, data) \
-+ *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-+#define MV_READ_8(ofs, data) \
-+ *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
-+
-+
-+
-+#define RALINK_PCI_MM_MAP_BASE 0x60000000
-+#define RALINK_PCI_IO_MAP_BASE 0x1e160000
-+
-+#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
-+#define GPIO_PERST
-+#define ASSERT_SYSRST_PCIE(val) do { \
-+ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
-+ RALINK_RSTCTRL |= val; \
-+ else \
-+ RALINK_RSTCTRL &= ~val; \
-+ } while(0)
-+#define DEASSERT_SYSRST_PCIE(val) do { \
-+ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
-+ RALINK_RSTCTRL &= ~val; \
-+ else \
-+ RALINK_RSTCTRL |= val; \
-+ } while(0)
-+#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
-+#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
-+#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
-+#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
-+#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
-+#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
-+#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
-+#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
-+//RALINK_SYSCFG1 bit
-+#define RALINK_PCI_HOST_MODE_EN (1<<7)
-+#define RALINK_PCIE_RC_MODE_EN (1<<8)
-+//RALINK_RSTCTRL bit
-+#define RALINK_PCIE_RST (1<<23)
-+#define RALINK_PCI_RST (1<<24)
-+//RALINK_CLKCFG1 bit
-+#define RALINK_PCI_CLK_EN (1<<19)
-+#define RALINK_PCIE_CLK_EN (1<<21)
-+//RALINK_GPIOMODE bit
-+#define PCI_SLOTx2 (1<<11)
-+#define PCI_SLOTx1 (2<<11)
-+//MTK PCIE PLL bit
-+#define PDRV_SW_SET (1<<31)
-+#define LC_CKDRVPD_ (1<<19)
-+
-+#define MEMORY_BASE 0x0
-+static int pcie_link_status = 0;
-+
-+#define PCI_ACCESS_READ_1 0
-+#define PCI_ACCESS_READ_2 1
-+#define PCI_ACCESS_READ_4 2
-+#define PCI_ACCESS_WRITE_1 3
-+#define PCI_ACCESS_WRITE_2 4
-+#define PCI_ACCESS_WRITE_4 5
-+
-+static int config_access(unsigned char access_type, struct pci_bus *bus,
-+ unsigned int devfn, unsigned int where, u32 * data)
-+{
-+ unsigned int slot = PCI_SLOT(devfn);
-+ u8 func = PCI_FUNC(devfn);
-+ uint32_t address_reg, data_reg;
-+ unsigned int address;
-+
-+ address_reg = RALINK_PCI_CONFIG_ADDR;
-+ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-+
-+ address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+ MV_WRITE(address_reg, address);
-+
-+ switch(access_type) {
-+ case PCI_ACCESS_WRITE_1:
-+ MV_WRITE_8(data_reg+(where&0x3), *data);
-+ break;
-+ case PCI_ACCESS_WRITE_2:
-+ MV_WRITE_16(data_reg+(where&0x3), *data);
-+ break;
-+ case PCI_ACCESS_WRITE_4:
-+ MV_WRITE(data_reg, *data);
-+ break;
-+ case PCI_ACCESS_READ_1:
-+ MV_READ_8( data_reg+(where&0x3), data);
-+ break;
-+ case PCI_ACCESS_READ_2:
-+ MV_READ_16(data_reg+(where&0x3), data);
-+ break;
-+ case PCI_ACCESS_READ_4:
-+ MV_READ(data_reg, data);
-+ break;
-+ default:
-+ printk("no specify access type\n");
-+ break;
-+ }
-+ return 0;
-+}
-+
-+static int
-+read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
-+{
-+ return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
-+}
-+
-+static int
-+read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
-+{
-+ return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
-+}
-+
-+static int
-+read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
-+{
-+ return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
-+}
-+
-+static int
-+write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-+{
-+ if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
-+ return -1;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int
-+write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
-+{
-+ if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
-+ return -1;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int
-+write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-+{
-+ if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
-+ return -1;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+
-+static int
-+pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
-+{
-+ switch (size) {
-+ case 1:
-+ return read_config_byte(bus, devfn, where, (u8 *) val);
-+ case 2:
-+ return read_config_word(bus, devfn, where, (u16 *) val);
-+ default:
-+ return read_config_dword(bus, devfn, where, val);
-+ }
-+}
-+
-+static int
-+pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-+{
-+ switch (size) {
-+ case 1:
-+ return write_config_byte(bus, devfn, where, (u8) val);
-+ case 2:
-+ return write_config_word(bus, devfn, where, (u16) val);
-+ default:
-+ return write_config_dword(bus, devfn, where, val);
-+ }
-+}
-+
-+struct pci_ops mt7621_pci_ops= {
-+ .read = pci_config_read,
-+ .write = pci_config_write,
-+};
-+
-+static struct resource mt7621_res_pci_mem1 = {
-+ .name = "PCI MEM1",
-+ .start = RALINK_PCI_MM_MAP_BASE,
-+ .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
-+ .flags = IORESOURCE_MEM,
-+};
-+static struct resource mt7621_res_pci_io1 = {
-+ .name = "PCI I/O1",
-+ .start = RALINK_PCI_IO_MAP_BASE,
-+ .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct pci_controller mt7621_controller = {
-+ .pci_ops = &mt7621_pci_ops,
-+ .mem_resource = &mt7621_res_pci_mem1,
-+ .io_resource = &mt7621_res_pci_io1,
-+ .mem_offset = 0x00000000UL,
-+ .io_offset = 0x00000000UL,
-+ .io_map_base = 0xa0000000,
-+};
-+
-+static void
-+read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
-+{
-+ unsigned int address_reg, data_reg, address;
-+
-+ address_reg = RALINK_PCI_CONFIG_ADDR;
-+ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-+ address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
-+ MV_WRITE(address_reg, address);
-+ MV_READ(data_reg, val);
-+ return;
-+}
-+
-+static void
-+write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
-+{
-+ unsigned int address_reg, data_reg, address;
-+
-+ address_reg = RALINK_PCI_CONFIG_ADDR;
-+ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-+ address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
-+ MV_WRITE(address_reg, address);
-+ MV_WRITE(data_reg, val);
-+ return;
-+}
-+
-+
-+int __init
-+pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ u16 cmd;
-+ u32 val;
-+ int irq = 0;
-+
-+ if ((dev->bus->number == 0) && (slot == 0)) {
-+ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-+ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
-+ printk("BAR0 at slot 0 = %x\n", val);
-+ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
-+ } else if((dev->bus->number == 0) && (slot == 0x1)) {
-+ write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-+ read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
-+ printk("BAR0 at slot 1 = %x\n", val);
-+ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
-+ } else if((dev->bus->number == 0) && (slot == 0x2)) {
-+ write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-+ read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
-+ printk("BAR0 at slot 2 = %x\n", val);
-+ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
-+ } else if ((dev->bus->number == 1) && (slot == 0x0)) {
-+ switch (pcie_link_status) {
-+ case 2:
-+ case 6:
-+ irq = RALINK_INT_PCIE1;
-+ break;
-+ case 4:
-+ irq = RALINK_INT_PCIE2;
-+ break;
-+ default:
-+ irq = RALINK_INT_PCIE0;
-+ }
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number == 2) && (slot == 0x0)) {
-+ switch (pcie_link_status) {
-+ case 5:
-+ case 6:
-+ irq = RALINK_INT_PCIE2;
-+ break;
-+ default:
-+ irq = RALINK_INT_PCIE1;
-+ }
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number == 2) && (slot == 0x1)) {
-+ switch (pcie_link_status) {
-+ case 5:
-+ case 6:
-+ irq = RALINK_INT_PCIE2;
-+ break;
-+ default:
-+ irq = RALINK_INT_PCIE1;
-+ }
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number ==3) && (slot == 0x0)) {
-+ irq = RALINK_INT_PCIE2;
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number ==3) && (slot == 0x1)) {
-+ irq = RALINK_INT_PCIE2;
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number ==3) && (slot == 0x2)) {
-+ irq = RALINK_INT_PCIE2;
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else {
-+ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
-+ return 0;
-+ }
-+
-+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
-+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
-+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
-+ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-+ pci_write_config_word(dev, PCI_COMMAND, cmd);
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-+ return irq;
-+}
-+
-+void
-+set_pcie_phy(u32 *addr, int start_b, int bits, int val)
-+{
-+// printk("0x%p:", addr);
-+// printk(" %x", *addr);
-+ *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
-+ *(unsigned int *)(addr) |= val << start_b;
-+// printk(" -> %x\n", *addr);
-+}
-+
-+void
-+bypass_pipe_rst(void)
-+{
-+#if defined (CONFIG_PCIE_PORT0)
-+ /* PCIe Port 0 */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ /* PCIe Port 1 */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ /* PCIe Port 2 */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
-+#endif
-+}
-+
-+void
-+set_phy_for_ssc(void)
-+{
-+ unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
-+
-+ reg = (reg >> 6) & 0x7;
-+#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
-+ /* Set PCIe Port0 & Port1 PHY to disable SSC */
-+ /* Debug Xtal Type */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
-+ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
-+ printk("***** Xtal 40MHz *****\n");
-+ } else { // 25MHz | 20MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
-+ if (reg >= 6) {
-+ printk("***** Xtal 25MHz *****\n");
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
-+ } else {
-+ printk("***** Xtal 20MHz *****\n");
-+ }
-+ }
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
-+ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
-+ }
-+ /* Enable PHY and disable force mode */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ /* Set PCIe Port2 PHY to disable SSC */
-+ /* Debug Xtal Type */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
-+ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
-+ } else { // 25MHz | 20MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
-+ if (reg >= 6) { // 25MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
-+ }
-+ }
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
-+ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
-+ }
-+ /* Enable PHY and disable force mode */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
-+#endif
-+}
-+
-+static int mt7621_pci_probe(struct platform_device *pdev)
-+{
-+ unsigned long val = 0;
-+
-+ iomem_resource.start = 0;
-+ iomem_resource.end= ~0;
-+ ioport_resource.start= 0;
-+ ioport_resource.end = ~0;
-+
-+#if defined (CONFIG_PCIE_PORT0)
-+ val = RALINK_PCIE0_RST;
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ val |= RALINK_PCIE1_RST;
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ val |= RALINK_PCIE2_RST;
-+#endif
-+ ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
-+ printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
-+#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
-+ *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
-+ *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
-+ mdelay(100);
-+ *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
-+ mdelay(100);
-+ *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
-+
-+ mdelay(100);
-+#else
-+ *(unsigned int *)(0xbe000060) &= ~0x00000c00;
-+#endif
-+#if defined (CONFIG_PCIE_PORT0)
-+ val = RALINK_PCIE0_RST;
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ val |= RALINK_PCIE1_RST;
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ val |= RALINK_PCIE2_RST;
-+#endif
-+ DEASSERT_SYSRST_PCIE(val);
-+ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
-+
-+ if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
-+ bypass_pipe_rst();
-+ set_phy_for_ssc();
-+ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
-+
-+#if defined (CONFIG_PCIE_PORT0)
-+ read_config(0, 0, 0, 0x70c, &val);
-+ printk("Port 0 N_FTS = %x\n", (unsigned int)val);
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ read_config(0, 1, 0, 0x70c, &val);
-+ printk("Port 1 N_FTS = %x\n", (unsigned int)val);
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ read_config(0, 2, 0, 0x70c, &val);
-+ printk("Port 2 N_FTS = %x\n", (unsigned int)val);
-+#endif
-+
-+ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
-+ RALINK_SYSCFG1 &= ~(0x30);
-+ RALINK_SYSCFG1 |= (2<<4);
-+ RALINK_PCIE_CLK_GEN &= 0x7fffffff;
-+ RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
-+ RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
-+ RALINK_PCIE_CLK_GEN |= 0x80000000;
-+ mdelay(50);
-+ RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
-+
-+
-+#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
-+ *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
-+ mdelay(100);
-+#else
-+ RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
-+#endif
-+ mdelay(500);
-+
-+
-+ mdelay(500);
-+#if defined (CONFIG_PCIE_PORT0)
-+ if(( RALINK_PCI0_STATUS & 0x1) == 0)
-+ {
-+ printk("PCIE0 no card, disable it(RST&CLK)\n");
-+ ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
-+ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
-+ pcie_link_status &= ~(1<<0);
-+ } else {
-+ pcie_link_status |= 1<<0;
-+ RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
-+ }
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ if(( RALINK_PCI1_STATUS & 0x1) == 0)
-+ {
-+ printk("PCIE1 no card, disable it(RST&CLK)\n");
-+ ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
-+ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
-+ pcie_link_status &= ~(1<<1);
-+ } else {
-+ pcie_link_status |= 1<<1;
-+ RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
-+ }
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ if (( RALINK_PCI2_STATUS & 0x1) == 0) {
-+ printk("PCIE2 no card, disable it(RST&CLK)\n");
-+ ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
-+ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
-+ pcie_link_status &= ~(1<<2);
-+ } else {
-+ pcie_link_status |= 1<<2;
-+ RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
-+ }
-+#endif
-+ if (pcie_link_status == 0)
-+ return 0;
-+
-+/*
-+pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
-+3'b000 x x x
-+3'b001 x x 0
-+3'b010 x 0 x
-+3'b011 x 1 0
-+3'b100 0 x x
-+3'b101 1 x 0
-+3'b110 1 0 x
-+3'b111 2 1 0
-+*/
-+ switch(pcie_link_status) {
-+ case 2:
-+ RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
-+ RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
-+ RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
-+ break;
-+ case 4:
-+ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-+ RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
-+ RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
-+ RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
-+ break;
-+ case 5:
-+ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-+ RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
-+ RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
-+ RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
-+ break;
-+ case 6:
-+ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-+ RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
-+ RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
-+ RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
-+ break;
-+ }
-+ printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
-+ //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
-+
-+/*
-+ ioport_resource.start = mt7621_res_pci_io1.start;
-+ ioport_resource.end = mt7621_res_pci_io1.end;
-+*/
-+
-+ RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
-+ RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
-+
-+#if defined (CONFIG_PCIE_PORT0)
-+ //PCIe0
-+ if((pcie_link_status & 0x1) != 0) {
-+ RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
-+ RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
-+ RALINK_PCI0_CLASS = 0x06040001;
-+ printk("PCIE0 enabled\n");
-+ }
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ //PCIe1
-+ if ((pcie_link_status & 0x2) != 0) {
-+ RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
-+ RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
-+ RALINK_PCI1_CLASS = 0x06040001;
-+ printk("PCIE1 enabled\n");
-+ }
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ //PCIe2
-+ if ((pcie_link_status & 0x4) != 0) {
-+ RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
-+ RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
-+ RALINK_PCI2_CLASS = 0x06040001;
-+ printk("PCIE2 enabled\n");
-+ }
-+#endif
-+
-+
-+ switch(pcie_link_status) {
-+ case 7:
-+ read_config(0, 2, 0, 0x4, &val);
-+ write_config(0, 2, 0, 0x4, val|0x4);
-+ // write_config(0, 1, 0, 0x4, val|0x7);
-+ read_config(0, 2, 0, 0x70c, &val);
-+ val &= ~(0xff)<<8;
-+ val |= 0x50<<8;
-+ write_config(0, 2, 0, 0x70c, val);
-+ case 3:
-+ case 5:
-+ case 6:
-+ read_config(0, 1, 0, 0x4, &val);
-+ write_config(0, 1, 0, 0x4, val|0x4);
-+ // write_config(0, 1, 0, 0x4, val|0x7);
-+ read_config(0, 1, 0, 0x70c, &val);
-+ val &= ~(0xff)<<8;
-+ val |= 0x50<<8;
-+ write_config(0, 1, 0, 0x70c, val);
-+ default:
-+ read_config(0, 0, 0, 0x4, &val);
-+ write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
-+ // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
-+ read_config(0, 0, 0, 0x70c, &val);
-+ val &= ~(0xff)<<8;
-+ val |= 0x50<<8;
-+ write_config(0, 0, 0, 0x70c, val);
-+ }
-+
-+ pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
-+ register_pci_controller(&mt7621_controller);
-+ return 0;
-+
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+static const struct of_device_id mt7621_pci_ids[] = {
-+ { .compatible = "mediatek,mt7621-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
-+
-+static struct platform_driver mt7621_pci_driver = {
-+ .probe = mt7621_pci_probe,
-+ .driver = {
-+ .name = "mt7621-pci",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(mt7621_pci_ids),
-+ },
-+};
-+
-+static int __init mt7621_pci_init(void)
-+{
-+ return platform_driver_register(&mt7621_pci_driver);
-+}
-+
-+arch_initcall(mt7621_pci_init);
+++ /dev/null
-From f8da5caf65926d44581d4e7914b28ceab3d28a7c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:08:11 +0200
-Subject: [PATCH 17/57] MIPS: use set_mode() to enable/disable the cevt-r4k
- irq
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/kernel/cevt-r4k.c | 37 +++++++++++++++++++++++++++++++------
- 1 file changed, 31 insertions(+), 6 deletions(-)
-
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -38,12 +38,6 @@ static int mips_next_event(unsigned long
-
- #endif /* CONFIG_MIPS_MT_SMTC */
-
--void mips_set_clock_mode(enum clock_event_mode mode,
-- struct clock_event_device *evt)
--{
-- /* Nothing to do ... */
--}
--
- DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
- int cp0_timer_irq_installed;
-
-@@ -90,9 +84,38 @@ struct irqaction c0_compare_irqaction =
- .name = "timer",
- };
-
-+void mips_set_clock_mode(enum clock_event_mode mode,
-+ struct clock_event_device *evt)
-+{
-+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_ONESHOT:
-+ if (cp0_timer_irq_installed)
-+ break;
-+
-+ cp0_timer_irq_installed = 1;
-+
-+ setup_irq(evt->irq, &c0_compare_irqaction);
-+ break;
-+
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ if (!cp0_timer_irq_installed)
-+ break;
-+
-+ cp0_timer_irq_installed = 0;
-+ free_irq(evt->irq, &c0_compare_irqaction);
-+ break;
-+
-+ default:
-+ pr_err("Unhandeled mips clock_mode\n");
-+ break;
-+ }
-+#endif
-+}
-
- void mips_event_handler(struct clock_event_device *dev)
- {
-+
- }
-
- /*
-@@ -215,12 +238,14 @@ int r4k_clockevent_init(void)
- #endif
- clockevents_register_device(cd);
-
-+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
- if (cp0_timer_irq_installed)
- return 0;
-
- cp0_timer_irq_installed = 1;
-
- setup_irq(irq, &c0_compare_irqaction);
-+#endif
-
- return 0;
- }
+++ /dev/null
-From 35297af46f17092785930f32a616331c8df8f75c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 23 May 2013 18:50:56 +0200
-Subject: [PATCH 18/57] MIPS: ralink: workaround DTB memory issue
-
-If the DTB is too big a bug happens on boot when init ram is freed.
-This is a temporary fix until the real cause is found.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -75,7 +75,7 @@ void __init device_tree_init(void)
- unflatten_device_tree();
-
- /* free the space reserved for the dt blob */
-- free_bootmem(base, size);
-+ //free_bootmem(base, size);
- }
-
- static int memory_dtb;
+++ /dev/null
-From 9de00286e20a5f5edc419698373010f1cb6ff0ce Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:25:02 +0100
-Subject: [PATCH 19/57] MIPS: ralink: add pseudo pwm led trigger based on
- timer0
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/timer.c | 213 ++++++++++++++++++++++++++++++++++++++++++----
- 1 file changed, 197 insertions(+), 16 deletions(-)
-
---- a/arch/mips/ralink/timer.c
-+++ b/arch/mips/ralink/timer.c
-@@ -12,6 +12,8 @@
- #include <linux/timer.h>
- #include <linux/of_gpio.h>
- #include <linux/clk.h>
-+#include <linux/leds.h>
-+#include <linux/slab.h>
-
- #include <asm/mach-ralink/ralink_regs.h>
-
-@@ -23,16 +25,34 @@
-
- #define TMR0CTL_ENABLE BIT(7)
- #define TMR0CTL_MODE_PERIODIC BIT(4)
--#define TMR0CTL_PRESCALER 1
-+#define TMR0CTL_PRESCALER 2
- #define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
- #define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
-
-+struct rt_timer_gpio {
-+ struct list_head list;
-+ struct led_classdev *led;
-+};
-+
- struct rt_timer {
-- struct device *dev;
-- void __iomem *membase;
-- int irq;
-- unsigned long timer_freq;
-- unsigned long timer_div;
-+ struct device *dev;
-+ void __iomem *membase;
-+ int irq;
-+
-+ unsigned long timer_freq;
-+ unsigned long timer_div;
-+
-+ struct list_head gpios;
-+ struct led_trigger led_trigger;
-+ unsigned int duty_cycle;
-+ unsigned int duty;
-+
-+ unsigned int fade;
-+ unsigned int fade_min;
-+ unsigned int fade_max;
-+ unsigned int fade_speed;
-+ unsigned int fade_dir;
-+ unsigned int fade_count;
- };
-
- static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
-@@ -48,18 +68,46 @@ static inline u32 rt_timer_r32(struct rt
- static irqreturn_t rt_timer_irq(int irq, void *_rt)
- {
- struct rt_timer *rt = (struct rt_timer *) _rt;
-+ struct rt_timer_gpio *gpio;
-+ unsigned int val;
-
-- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
-+ if (rt->fade && (rt->fade_count++ > rt->fade_speed)) {
-+ rt->fade_count = 0;
-+ if (rt->duty_cycle <= rt->fade_min)
-+ rt->fade_dir = 1;
-+ else if (rt->duty_cycle >= rt->fade_max)
-+ rt->fade_dir = 0;
-+
-+ if (rt->fade_dir)
-+ rt->duty_cycle += 1;
-+ else
-+ rt->duty_cycle -= 1;
-+
-+ }
-+
-+ val = rt->timer_freq / rt->timer_div;
-+ if (rt->duty)
-+ val *= rt->duty_cycle;
-+ else
-+ val *= (100 - rt->duty_cycle);
-+ val /= 100;
-+
-+ if (!list_empty(&rt->gpios))
-+ list_for_each_entry(gpio, &rt->gpios, list)
-+ led_set_brightness(gpio->led, !!rt->duty);
-+
-+ rt->duty = !rt->duty;
-+
-+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, val + 1);
- rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
-
- return IRQ_HANDLED;
- }
-
--
- static int rt_timer_request(struct rt_timer *rt)
- {
-- int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
-- dev_name(rt->dev), rt);
-+ int err = devm_request_irq(rt->dev, rt->irq, rt_timer_irq,
-+ IRQF_DISABLED, dev_name(rt->dev), rt);
- if (err) {
- dev_err(rt->dev, "failed to request irq\n");
- } else {
-@@ -81,8 +129,6 @@ static int rt_timer_config(struct rt_tim
- else
- rt->timer_div = divisor;
-
-- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
--
- return 0;
- }
-
-@@ -108,11 +154,128 @@ static void rt_timer_disable(struct rt_t
- rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
- }
-
-+static ssize_t led_fade_show(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+
-+ return sprintf(buf, "speed: %d, min: %d, max: %d\n", rt->fade_speed, rt->fade_min, rt->fade_max);
-+}
-+
-+static ssize_t led_fade_store(struct device *dev,
-+ struct device_attribute *attr, const char *buf, size_t size)
-+{
-+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+ unsigned int speed = 0, min = 0, max = 0;
-+ ssize_t ret = -EINVAL;
-+
-+ ret = sscanf(buf, "%u %u %u", &speed, &min, &max);
-+
-+ if (ret == 3) {
-+ rt->fade_speed = speed;
-+ rt->fade_min = min;
-+ rt->fade_max = max;
-+ rt->fade = 1;
-+ } else {
-+ rt->fade = 0;
-+ }
-+
-+ return size;
-+}
-+
-+static DEVICE_ATTR(fade, 0644, led_fade_show, led_fade_store);
-+
-+static ssize_t led_duty_cycle_show(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+
-+ return sprintf(buf, "%u\n", rt->duty_cycle);
-+}
-+
-+static ssize_t led_duty_cycle_store(struct device *dev,
-+ struct device_attribute *attr, const char *buf, size_t size)
-+{
-+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+ unsigned long state;
-+ ssize_t ret = -EINVAL;
-+
-+ ret = kstrtoul(buf, 10, &state);
-+ if (ret)
-+ return ret;
-+
-+ if (state <= 100)
-+ rt->duty_cycle = state;
-+ else
-+ rt->duty_cycle = 100;
-+
-+ rt->fade = 0;
-+
-+ return size;
-+}
-+
-+static DEVICE_ATTR(duty_cycle, 0644, led_duty_cycle_show, led_duty_cycle_store);
-+
-+static void rt_timer_trig_activate(struct led_classdev *led_cdev)
-+{
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+ struct rt_timer_gpio *gpio_data;
-+ int rc;
-+
-+ led_cdev->trigger_data = NULL;
-+ gpio_data = kzalloc(sizeof(*gpio_data), GFP_KERNEL);
-+ if (!gpio_data)
-+ return;
-+
-+ rc = device_create_file(led_cdev->dev, &dev_attr_duty_cycle);
-+ if (rc)
-+ goto err_gpio;
-+ rc = device_create_file(led_cdev->dev, &dev_attr_fade);
-+ if (rc)
-+ goto err_out_duty_cycle;
-+
-+ led_cdev->activated = true;
-+ led_cdev->trigger_data = gpio_data;
-+ gpio_data->led = led_cdev;
-+ list_add(&gpio_data->list, &rt->gpios);
-+ led_cdev->trigger_data = gpio_data;
-+ rt_timer_enable(rt);
-+ return;
-+
-+err_out_duty_cycle:
-+ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
-+
-+err_gpio:
-+ kfree(gpio_data);
-+}
-+
-+static void rt_timer_trig_deactivate(struct led_classdev *led_cdev)
-+{
-+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
-+ struct rt_timer_gpio *gpio_data = (struct rt_timer_gpio*) led_cdev->trigger_data;
-+
-+ if (led_cdev->activated) {
-+ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
-+ device_remove_file(led_cdev->dev, &dev_attr_fade);
-+ led_cdev->activated = false;
-+ }
-+
-+ list_del(&gpio_data->list);
-+ rt_timer_disable(rt);
-+ led_set_brightness(led_cdev, LED_OFF);
-+}
-+
- static int rt_timer_probe(struct platform_device *pdev)
- {
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ const __be32 *divisor;
- struct rt_timer *rt;
- struct clk *clk;
-+ int ret;
-
- rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
- if (!rt) {
-@@ -140,12 +303,29 @@ static int rt_timer_probe(struct platfor
- if (!rt->timer_freq)
- return -EINVAL;
-
-+ rt->duty_cycle = 100;
- rt->dev = &pdev->dev;
- platform_set_drvdata(pdev, rt);
-
-- rt_timer_request(rt);
-- rt_timer_config(rt, 2);
-- rt_timer_enable(rt);
-+ ret = rt_timer_request(rt);
-+ if (ret)
-+ return ret;
-+
-+ divisor = of_get_property(pdev->dev.of_node, "ralink,divisor", NULL);
-+ if (divisor)
-+ rt_timer_config(rt, be32_to_cpu(*divisor));
-+ else
-+ rt_timer_config(rt, 200);
-+
-+ rt->led_trigger.name = "pwmtimer",
-+ rt->led_trigger.activate = rt_timer_trig_activate,
-+ rt->led_trigger.deactivate = rt_timer_trig_deactivate,
-+
-+ ret = led_trigger_register(&rt->led_trigger);
-+ if (ret)
-+ return ret;
-+
-+ INIT_LIST_HEAD(&rt->gpios);
-
- dev_info(&pdev->dev, "maximum frequency is %luHz\n", rt->timer_freq);
-
-@@ -156,6 +336,7 @@ static int rt_timer_remove(struct platfo
- {
- struct rt_timer *rt = platform_get_drvdata(pdev);
-
-+ led_trigger_unregister(&rt->led_trigger);
- rt_timer_disable(rt);
- rt_timer_free(rt);
-
-@@ -180,6 +361,6 @@ static struct platform_driver rt_timer_d
-
- module_platform_driver(rt_timer_driver);
-
--MODULE_DESCRIPTION("Ralink RT2880 timer");
-+MODULE_DESCRIPTION("Ralink RT2880 timer / pseudo pwm");
- MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
- MODULE_LICENSE("GPL");
+++ /dev/null
-From 0c1e8630dca36c2d5a9bf98a5f1f8c15f75d0253 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 12 Aug 2013 18:11:33 +0200
-Subject: [PATCH 20/57] MIPS: ralink: update dts files
-
-Add the devicetree nodes needed to make the newly merged drivers work.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/dts/mt7620a.dtsi | 135 +++++++++++++++++++++++
- arch/mips/ralink/dts/rt3050.dtsi | 156 ++++++++++++++++++++++++++
- arch/mips/ralink/dts/rt3883.dtsi | 219 +++++++++++++++++++++++++++++++++++++
- 3 files changed, 510 insertions(+)
-
---- a/arch/mips/ralink/dts/mt7620a.dtsi
-+++ b/arch/mips/ralink/dts/mt7620a.dtsi
-@@ -29,10 +29,32 @@
- reg = <0x0 0x100>;
- };
-
-+ timer@100 {
-+ compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
-+ reg = <0x100 0x20>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
-+ watchdog@120 {
-+ compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
-+ reg = <0x120 0x10>;
-+
-+ resets = <&rstctrl 8>;
-+ reset-names = "wdt";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
- intc: intc@200 {
- compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
- reg = <0x200 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "intc";
-+
- interrupt-controller;
- #interrupt-cells = <1>;
-
-@@ -43,16 +65,129 @@
- memc@300 {
- compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
- reg = <0x300 0x100>;
-+
-+ resets = <&rstctrl 20>;
-+ reset-names = "mc";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <3>;
-+ };
-+
-+ uart@500 {
-+ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
-+ reg = <0x500 0x100>;
-+
-+ resets = <&rstctrl 12>;
-+ reset-names = "uart";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <5>;
-+
-+ reg-shift = <2>;
-+
-+ status = "disabled";
-+ };
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
-+ reg = <0x600 0x34>;
-+
-+ resets = <&rstctrl 13>;
-+ reset-names = "pio";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio1: gpio@638 {
-+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
-+ reg = <0x638 0x24>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <24>;
-+ ralink,num-gpios = <16>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio2: gpio@660 {
-+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
-+ reg = <0x660 0x24>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <40>;
-+ ralink,num-gpios = <32>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ spi@b00 {
-+ compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
-+ reg = <0xb00 0x100>;
-+
-+ resets = <&rstctrl 18>;
-+ reset-names = "spi";
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ status = "disabled";
- };
-
- uartlite@c00 {
- compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
- reg = <0xc00 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "uartl";
-+
- interrupt-parent = <&intc>;
- interrupts = <12>;
-
- reg-shift = <2>;
- };
-+
-+ systick@d00 {
-+ compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
-+ reg = <0xd00 0x10>;
-+
-+ resets = <&rstctrl 28>;
-+ reset-names = "intc";
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <7>;
-+ };
-+ };
-+
-+ rstctrl: rstctrl {
-+ compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
-+ #reset-cells = <1>;
- };
- };
---- a/arch/mips/ralink/dts/rt3050.dtsi
-+++ b/arch/mips/ralink/dts/rt3050.dtsi
-@@ -9,6 +9,10 @@
- };
- };
-
-+ chosen {
-+ bootargs = "console=ttyS0,57600";
-+ };
-+
- cpuintc: cpuintc@0 {
- #address-cells = <0>;
- #interrupt-cells = <1>;
-@@ -29,10 +33,32 @@
- reg = <0x0 0x100>;
- };
-
-+ timer@100 {
-+ compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
-+ reg = <0x100 0x20>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
-+ watchdog@120 {
-+ compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
-+ reg = <0x120 0x10>;
-+
-+ resets = <&rstctrl 8>;
-+ reset-names = "wdt";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
- intc: intc@200 {
- compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
- reg = <0x200 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "intc";
-+
- interrupt-controller;
- #interrupt-cells = <1>;
-
-@@ -43,17 +69,144 @@
- memc@300 {
- compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
- reg = <0x300 0x100>;
-+
-+ resets = <&rstctrl 20>;
-+ reset-names = "mc";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <3>;
-+ };
-+
-+ uart@500 {
-+ compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
-+ reg = <0x500 0x100>;
-+
-+ resets = <&rstctrl 12>;
-+ reset-names = "uart";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <5>;
-+
-+ reg-shift = <2>;
-+
-+ status = "disabled";
-+ };
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
-+ reg = <0x600 0x34>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ resets = <&rstctrl 13>;
-+ reset-names = "pio";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ status = "disabled";
-+ };
-+
-+ gpio1: gpio@638 {
-+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
-+ reg = <0x638 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <24>;
-+ ralink,num-gpios = <16>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio2: gpio@660 {
-+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
-+ reg = <0x660 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <40>;
-+ ralink,num-gpios = <12>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ spi@b00 {
-+ compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
-+ reg = <0xb00 0x100>;
-+
-+ resets = <&rstctrl 18>;
-+ reset-names = "spi";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ status = "disabled";
- };
-
- uartlite@c00 {
- compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
- reg = <0xc00 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "uartl";
-+
- interrupt-parent = <&intc>;
- interrupts = <12>;
-
- reg-shift = <2>;
- };
-+
-+ };
-+
-+ rstctrl: rstctrl {
-+ compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
-+ #reset-cells = <1>;
-+ };
-+
-+ ethernet@10100000 {
-+ compatible = "ralink,rt3050-eth";
-+ reg = <0x10100000 10000>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <5>;
-+
-+ status = "disabled";
-+ };
-+
-+ esw@10110000 {
-+ compatible = "ralink,rt3050-esw";
-+ reg = <0x10110000 8000>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <17>;
-+
-+ status = "disabled";
-+ };
-+
-+ wmac@10180000 {
-+ compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
-+ reg = <0x10180000 40000>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <6>;
-+
-+ status = "disabled";
- };
-
- usb@101c0000 {
-@@ -63,6 +216,9 @@
- interrupt-parent = <&intc>;
- interrupts = <18>;
-
-+ resets = <&rstctrl 22>;
-+ reset-names = "otg";
-+
- status = "disabled";
- };
- };
---- a/arch/mips/ralink/dts/rt3883.dtsi
-+++ b/arch/mips/ralink/dts/rt3883.dtsi
-@@ -29,10 +29,32 @@
- reg = <0x0 0x100>;
- };
-
-+ timer@100 {
-+ compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
-+ reg = <0x100 0x20>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
-+ watchdog@120 {
-+ compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
-+ reg = <0x120 0x10>;
-+
-+ resets = <&rstctrl 8>;
-+ reset-names = "wdt";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <1>;
-+ };
-+
- intc: intc@200 {
- compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
- reg = <0x200 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "intc";
-+
- interrupt-controller;
- #interrupt-cells = <1>;
-
-@@ -43,16 +65,213 @@
- memc@300 {
- compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
- reg = <0x300 0x100>;
-+
-+ resets = <&rstctrl 20>;
-+ reset-names = "mc";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <3>;
-+ };
-+
-+ uart@500 {
-+ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
-+ reg = <0x500 0x100>;
-+
-+ resets = <&rstctrl 12>;
-+ reset-names = "uart";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <5>;
-+
-+ reg-shift = <2>;
-+
-+ status = "disabled";
-+ };
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
-+ reg = <0x600 0x34>;
-+
-+ resets = <&rstctrl 13>;
-+ reset-names = "pio";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio1: gpio@638 {
-+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
-+ reg = <0x638 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <24>;
-+ ralink,num-gpios = <16>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio2: gpio@660 {
-+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
-+ reg = <0x660 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <40>;
-+ ralink,num-gpios = <32>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ gpio3: gpio@688 {
-+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
-+ reg = <0x688 0x24>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ ralink,gpio-base = <72>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 10 14 18 1c
-+ 20 24 ];
-+
-+ status = "disabled";
-+ };
-+
-+ spi0: spi@b00 {
-+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
-+ reg = <0xb00 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ resets = <&rstctrl 18>;
-+ reset-names = "spi";
-+
-+ status = "disabled";
- };
-
- uartlite@c00 {
- compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
- reg = <0xc00 0x100>;
-
-+ resets = <&rstctrl 19>;
-+ reset-names = "uartl";
-+
- interrupt-parent = <&intc>;
- interrupts = <12>;
-
- reg-shift = <2>;
- };
- };
-+
-+ rstctrl: rstctrl {
-+ compatible = "ralink,rt3883-reset", "ralink,rt2880-reset";
-+ #reset-cells = <1>;
-+ };
-+
-+ pci@10140000 {
-+ compatible = "ralink,rt3883-pci";
-+ reg = <0x10140000 0x20000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges; /* direct mapping */
-+
-+ status = "disabled";
-+
-+ pciintc: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <4>;
-+ };
-+
-+ host-bridge {
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+
-+ device_type = "pci";
-+
-+ bus-range = <0 255>;
-+ ranges = <
-+ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
-+ 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
-+ >;
-+
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ interrupt-map = <
-+ /* IDSEL 17 */
-+ 0x8800 0 0 1 &pciintc 18
-+ 0x8800 0 0 2 &pciintc 18
-+ 0x8800 0 0 3 &pciintc 18
-+ 0x8800 0 0 4 &pciintc 18
-+ /* IDSEL 18 */
-+ 0x9000 0 0 1 &pciintc 19
-+ 0x9000 0 0 2 &pciintc 19
-+ 0x9000 0 0 3 &pciintc 19
-+ 0x9000 0 0 4 &pciintc 19
-+ >;
-+
-+ pci-bridge@1 {
-+ reg = <0x0800 0 0 0 0>;
-+ device_type = "pci";
-+ #interrupt-cells = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ status = "disabled";
-+
-+ ralink,pci-slot = <1>;
-+
-+ interrupt-map-mask = <0x0 0 0 0>;
-+ interrupt-map = <0x0 0 0 0 &pciintc 20>;
-+ };
-+
-+ pci-slot@17 {
-+ reg = <0x8800 0 0 0 0>;
-+ device_type = "pci";
-+ #interrupt-cells = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ ralink,pci-slot = <17>;
-+
-+ status = "disabled";
-+ };
-+
-+ pci-slot@18 {
-+ reg = <0x9000 0 0 0 0>;
-+ device_type = "pci";
-+ #interrupt-cells = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ ralink,pci-slot = <18>;
-+
-+ status = "disabled";
-+ };
-+ };
-+ };
- };
+++ /dev/null
-From e76ecd496c9b074ab21b17f12494d823a407e89a Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 16:26:41 +0200
-Subject: [PATCH 21/57] MIPS: ralink: add cpu frequency scaling
-
-This feature will break udelay() and cause the delay loop to have longer delays
-when the frequency is scaled causing a performance hit.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/cevt-rt3352.c | 36 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/arch/mips/ralink/cevt-rt3352.c
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -29,6 +29,10 @@
- /* enable the counter */
- #define CFG_CNT_EN 0x1
-
-+/* mt7620 frequency scaling defines */
-+#define CLK_LUT_CFG 0x40
-+#define SLEEP_EN BIT(31)
-+
- struct systick_device {
- void __iomem *membase;
- struct clock_event_device dev;
-@@ -36,6 +40,8 @@ struct systick_device {
- int freq_scale;
- };
-
-+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
-+
- static void systick_set_clock_mode(enum clock_event_mode mode,
- struct clock_event_device *evt);
-
-@@ -87,6 +93,21 @@ static struct irqaction systick_irqactio
- .dev_id = &systick.dev,
- };
-
-+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
-+{
-+ if (sdev->freq_scale == status)
-+ return;
-+
-+ sdev->freq_scale = status;
-+
-+ pr_info("%s: %s autosleep mode\n", systick.dev.name,
-+ (status) ? ("enable") : ("disable"));
-+ if (status)
-+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
-+ else
-+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
-+}
-+
- static void systick_set_clock_mode(enum clock_event_mode mode,
- struct clock_event_device *evt)
- {
-@@ -101,9 +122,13 @@ static void systick_set_clock_mode(enum
- sdev->irq_requested = 1;
- iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
- systick.membase + SYSTICK_CONFIG);
-+ if (systick_freq_scaling)
-+ systick_freq_scaling(sdev, 1);
- break;
-
- case CLOCK_EVT_MODE_SHUTDOWN:
-+ if (systick_freq_scaling)
-+ systick_freq_scaling(sdev, 0);
- if (sdev->irq_requested)
- free_irq(systick.dev.irq, &systick_irqaction);
- sdev->irq_requested = 0;
-@@ -116,12 +141,23 @@ static void systick_set_clock_mode(enum
- }
- }
-
-+static const struct of_device_id systick_match[] = {
-+ { .compatible = "ralink,mt7620-systick", .data = mt7620_freq_scaling},
-+ {},
-+};
-+
- static void __init ralink_systick_init(struct device_node *np)
- {
-+ const struct of_device_id *match;
-+
- systick.membase = of_iomap(np, 0);
- if (!systick.membase)
- return;
-
-+ match = of_match_node(systick_match, np);
-+ if (match)
-+ systick_freq_scaling = match->data;
-+
- systick_irqaction.name = np->name;
- systick.dev.name = np->name;
- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
+++ /dev/null
-From ec26251ea980b1ee88733f178a4e86e3c70fd244 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Aug 2014 18:46:02 +0200
-Subject: [PATCH 22/57] MIPS: ralink: copy the commandline from the devicetree
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -99,6 +99,8 @@ void __init plat_mem_setup(void)
- */
- __dt_setup_arch(&__dtb_start);
-
-+ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
-+
- of_scan_flat_dt(early_init_dt_find_memory, NULL);
- if (memory_dtb)
- of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+++ /dev/null
-From 1f1c12e85defba9459b41ec95b86f23b4791f1ab Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Aug 2014 20:43:25 +0200
-Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency
- scaling
-
- If the USB HCD is running and the cpu is scaled too low, then the USB stops
- working. Increase the idle speed of the core to fix this if the kernel is
- built with USB support.
-
- The values are taken from the Ralink SDK Kernel.
-
- Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -36,6 +36,12 @@
- #define PMU1_CFG 0x8C
- #define DIG_SW_SEL BIT(25)
-
-+/* clock scaling */
-+#define CLKCFG_FDIV_MASK 0x1f00
-+#define CLKCFG_FDIV_USB_VAL 0x0300
-+#define CLKCFG_FFRAC_MASK 0x001f
-+#define CLKCFG_FFRAC_USB_VAL 0x0003
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-
-@@ -337,6 +343,19 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", periph_rate);
- ralink_clk_add("10180000.wmac", xtal_rate);
-+
-+ if (IS_ENABLED(CONFIG_USB)) {
-+ /*
-+ * When the CPU goes into sleep mode, the BUS clock will be too low for
-+ * USB to function properly
-+ */
-+ u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
-+
-+ val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
-+ val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
-+
-+ rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
-+ }
- }
-
- void __init ralink_of_remap(void)
+++ /dev/null
-From fbc9fb0c2d30f2141e1b0b824f473276c3aef528 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 6 Aug 2014 17:53:24 +0200
-Subject: [PATCH 24/57] MIPS: ralink: add mt7628an devicetree files
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig | 4 +
- arch/mips/ralink/dts/Makefile | 1 +
- arch/mips/ralink/dts/mt7628an.dtsi | 184 ++++++++++++++++++++++++++++++++
- arch/mips/ralink/dts/mt7628an_eval.dts | 54 ++++++++++
- 4 files changed, 243 insertions(+)
- create mode 100644 arch/mips/ralink/dts/mt7628an.dtsi
- create mode 100644 arch/mips/ralink/dts/mt7628an_eval.dts
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -75,6 +75,10 @@ choice
- bool "MT7620A eval kit"
- depends on SOC_MT7620
-
-+ config DTB_MT7628AN_EVAL
-+ bool "MT7620A eval kit"
-+ depends on SOC_MT7620
-+
- config DTB_MT7621_EVAL
- bool "MT7621 eval kit"
- depends on SOC_MT7621
---- a/arch/mips/ralink/dts/Makefile
-+++ b/arch/mips/ralink/dts/Makefile
-@@ -3,3 +3,4 @@ obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_
- obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
- obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
- obj-$(CONFIG_DTB_MT7621_EVAL) := mt7621_eval.dtb.o
-+obj-$(CONFIG_DTB_MT7628AN_EVAL) := mt7628an_eval.dtb.o
---- /dev/null
-+++ b/arch/mips/ralink/dts/mt7628an.dtsi
-@@ -0,0 +1,184 @@
-+/ {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "ralink,mtk7628an-soc";
-+
-+ cpus {
-+ cpu@0 {
-+ compatible = "mips,mips24KEc";
-+ };
-+ };
-+
-+ cpuintc: cpuintc@0 {
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-controller;
-+ compatible = "mti,cpu-interrupt-controller";
-+ };
-+
-+ palmbus@10000000 {
-+ compatible = "palmbus";
-+ reg = <0x10000000 0x200000>;
-+ ranges = <0x0 0x10000000 0x1FFFFF>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ sysc@0 {
-+ compatible = "ralink,mt7620a-sysc";
-+ reg = <0x0 0x100>;
-+ };
-+
-+ watchdog@120 {
-+ compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
-+ reg = <0x120 0x10>;
-+
-+ resets = <&rstctrl 8>;
-+ reset-names = "wdt";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <24>;
-+ };
-+
-+ intc: intc@200 {
-+ compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
-+ reg = <0x200 0x100>;
-+
-+ resets = <&rstctrl 9>;
-+ reset-names = "intc";
-+
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+
-+ interrupt-parent = <&cpuintc>;
-+ interrupts = <2>;
-+
-+ ralink,intc-registers = <0x9c 0xa0
-+ 0x6c 0xa4
-+ 0x80 0x78>;
-+ };
-+
-+ memc@300 {
-+ compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
-+ reg = <0x300 0x100>;
-+
-+ resets = <&rstctrl 20>;
-+ reset-names = "mc";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <3>;
-+ };
-+
-+ gpio@600 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
-+ reg = <0x600 0x100>;
-+
-+ gpio0: bank@0 {
-+ reg = <0>;
-+ compatible = "mtk,mt7621-gpio-bank";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ };
-+
-+ gpio1: bank@1 {
-+ reg = <1>;
-+ compatible = "mtk,mt7621-gpio-bank";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ };
-+
-+ gpio2: bank@2 {
-+ reg = <2>;
-+ compatible = "mtk,mt7621-gpio-bank";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ };
-+ };
-+
-+ spi@b00 {
-+ compatible = "ralink,mt7621-spi";
-+ reg = <0xb00 0x100>;
-+
-+ resets = <&rstctrl 18>;
-+ reset-names = "spi";
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi_pins>;
-+
-+ status = "disabled";
-+ };
-+
-+ uartlite@c00 {
-+ compatible = "ns16550a";
-+ reg = <0xc00 0x100>;
-+
-+ reg-shift = <2>;
-+ reg-io-width = <4>;
-+ no-loopback-test;
-+
-+ resets = <&rstctrl 12>;
-+ reset-names = "uartl";
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <20>;
-+
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pins>;
-+ };
-+ };
-+
-+ pinctrl {
-+ compatible = "ralink,rt2880-pinmux";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&state_default>;
-+ state_default: pinctrl0 {
-+ };
-+ spi_pins: spi {
-+ spi {
-+ ralink,group = "spi";
-+ ralink,function = "spi";
-+ };
-+ };
-+ uart0_pins: uartlite {
-+ uart {
-+ ralink,group = "uart0";
-+ ralink,function = "uart";
-+ };
-+ };
-+ };
-+
-+ rstctrl: rstctrl {
-+ compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
-+ #reset-cells = <1>;
-+ };
-+
-+ usbphy {
-+ compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
-+
-+ resets = <&rstctrl 22>;
-+ reset-names = "host";
-+ };
-+
-+ ehci@101c0000 {
-+ compatible = "ralink,rt3xxx-ehci";
-+ reg = <0x101c0000 0x1000>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <18>;
-+ };
-+
-+ ohci@101c1000 {
-+ compatible = "ralink,rt3xxx-ohci";
-+ reg = <0x101c1000 0x1000>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <18>;
-+ };
-+
-+};
---- /dev/null
-+++ b/arch/mips/ralink/dts/mt7628an_eval.dts
-@@ -0,0 +1,54 @@
-+/dts-v1/;
-+
-+/include/ "mt7628an.dtsi"
-+
-+/ {
-+ compatible = "ralink,mt7628an-eval-board", "ralink,mt7628an-soc";
-+ model = "Ralink MT7628AN evaluation board";
-+
-+ memory@0 {
-+ reg = <0x0 0x2000000>;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,57600 init=/init";
-+ };
-+
-+ palmbus@10000000 {
-+ spi@b00 {
-+ status = "okay";
-+
-+ m25p80@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "en25q64";
-+ reg = <0 0>;
-+ linux,modalias = "m25p80", "en25q64";
-+ spi-max-frequency = <10000000>;
-+
-+ partition@0 {
-+ label = "u-boot";
-+ reg = <0x0 0x30000>;
-+ read-only;
-+ };
-+
-+ partition@30000 {
-+ label = "u-boot-env";
-+ reg = <0x30000 0x10000>;
-+ read-only;
-+ };
-+
-+ factory: partition@40000 {
-+ label = "factory";
-+ reg = <0x40000 0x10000>;
-+ read-only;
-+ };
-+
-+ partition@50000 {
-+ label = "firmware";
-+ reg = <0x50000 0x7b0000>;
-+ };
-+ };
-+ };
-+ };
-+};
+++ /dev/null
-From b1cc9a15f6ead8dbd849257e42d69a5799fb7597 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 6 Aug 2014 18:24:36 +0200
-Subject: [PATCH 25/57] MIPS: ralink: allow loading irq registers from the
- devicetree
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/irq.c | 33 +++++++++++++++++++++++----------
- 1 file changed, 23 insertions(+), 10 deletions(-)
-
---- a/arch/mips/ralink/irq.c
-+++ b/arch/mips/ralink/irq.c
-@@ -20,14 +20,6 @@
-
- #include "common.h"
-
--/* INTC register offsets */
--#define INTC_REG_STATUS0 0x00
--#define INTC_REG_STATUS1 0x04
--#define INTC_REG_TYPE 0x20
--#define INTC_REG_RAW_STATUS 0x30
--#define INTC_REG_ENABLE 0x34
--#define INTC_REG_DISABLE 0x38
--
- #define INTC_INT_GLOBAL BIT(31)
-
- #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
-@@ -44,16 +36,34 @@
-
- #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
-
-+enum rt_intc_regs_enum {
-+ INTC_REG_STATUS0 = 0,
-+ INTC_REG_STATUS1,
-+ INTC_REG_TYPE,
-+ INTC_REG_RAW_STATUS,
-+ INTC_REG_ENABLE,
-+ INTC_REG_DISABLE,
-+};
-+
-+static u32 rt_intc_regs[] = {
-+ [INTC_REG_STATUS0] = 0x00,
-+ [INTC_REG_STATUS1] = 0x04,
-+ [INTC_REG_TYPE] = 0x20,
-+ [INTC_REG_RAW_STATUS] = 0x30,
-+ [INTC_REG_ENABLE] = 0x34,
-+ [INTC_REG_DISABLE] = 0x38,
-+};
-+
- static void __iomem *rt_intc_membase;
-
- static inline void rt_intc_w32(u32 val, unsigned reg)
- {
-- __raw_writel(val, rt_intc_membase + reg);
-+ __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
- }
-
- static inline u32 rt_intc_r32(unsigned reg)
- {
-- return __raw_readl(rt_intc_membase + reg);
-+ return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
- }
-
- static void ralink_intc_irq_unmask(struct irq_data *d)
-@@ -134,6 +144,9 @@ static int __init intc_of_init(struct de
- struct irq_domain *domain;
- int irq;
-
-+ if (!of_property_read_u32_array(node, "ralink,intc-registers", rt_intc_regs, 6))
-+ pr_info("intc: using register map from devicetree\n");
-+
- irq = irq_of_parse_and_map(node, 0);
- if (!irq)
- panic("Failed to get INTC IRQ");
+++ /dev/null
-From a375beba066516ecafddebc765454ac6ec599f3d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 6 Aug 2014 18:26:08 +0200
-Subject: [PATCH 26/57] MIPS: ralink: add mt7628an support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 11 ++
- arch/mips/ralink/Kconfig | 2 +-
- arch/mips/ralink/mt7620.c | 266 +++++++++++++++++++++++-----
- 3 files changed, 232 insertions(+), 47 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -13,6 +13,13 @@
- #ifndef _MT7620_REGS_H_
- #define _MT7620_REGS_H_
-
-+enum mt762x_soc_type {
-+ MT762X_SOC_UNKNOWN = 0,
-+ MT762X_SOC_MT7620A,
-+ MT762X_SOC_MT7620N,
-+ MT762X_SOC_MT7628AN,
-+};
-+
- #define MT7620_SYSC_BASE 0x10000000
-
- #define SYSC_REG_CHIP_NAME0 0x00
-@@ -27,6 +34,7 @@
-
- #define MT7620_CHIP_NAME0 0x3637544d
- #define MT7620_CHIP_NAME1 0x20203032
-+#define MT7628_CHIP_NAME1 0x20203832
-
- #define SYSCFG0_XTAL_FREQ_SEL BIT(6)
-
-@@ -71,6 +79,9 @@
- #define SYSCFG0_DRAM_TYPE_DDR1 1
- #define SYSCFG0_DRAM_TYPE_DDR2 2
-
-+#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
-+#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
-+
- #define MT7620_DRAM_BASE 0x0
- #define MT7620_SDRAM_SIZE_MIN 2
- #define MT7620_SDRAM_SIZE_MAX 64
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -35,7 +35,7 @@ choice
- select HW_HAS_PCI
-
- config SOC_MT7620
-- bool "MT7620"
-+ bool "MT7620/8"
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -42,6 +42,8 @@
- #define CLKCFG_FFRAC_MASK 0x001f
- #define CLKCFG_FFRAC_USB_VAL 0x0003
-
-+enum mt762x_soc_type mt762x_soc;
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-
-@@ -159,6 +161,125 @@ struct ralink_pinmux rt_gpio_pinmux = {
- .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
- };
-
-+static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
-+ FUNC("sdcx", 3, 19, 1),
-+ FUNC("utif", 2, 19, 1),
-+ FUNC("gpio", 1, 19, 1),
-+ FUNC("pwm", 0, 19, 1),
-+};
-+
-+static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
-+ FUNC("sdcx", 3, 18, 1),
-+ FUNC("utif", 2, 18, 1),
-+ FUNC("gpio", 1, 18, 1),
-+ FUNC("pwm", 0, 18, 1),
-+};
-+
-+static struct rt2880_pmx_func uart2_grp_mt7628[] = {
-+ FUNC("sdcx", 3, 20, 2),
-+ FUNC("pwm", 2, 20, 2),
-+ FUNC("gpio", 1, 20, 2),
-+ FUNC("uart", 0, 20, 2),
-+};
-+
-+static struct rt2880_pmx_func uart1_grp_mt7628[] = {
-+ FUNC("sdcx", 3, 45, 2),
-+ FUNC("pwm", 2, 45, 2),
-+ FUNC("gpio", 1, 45, 2),
-+ FUNC("uart", 0, 45, 2),
-+};
-+
-+static struct rt2880_pmx_func i2c_grp_mt7628[] = {
-+ FUNC("-", 3, 4, 2),
-+ FUNC("debug", 2, 4, 2),
-+ FUNC("gpio", 1, 4, 2),
-+ FUNC("i2c", 0, 4, 2),
-+};
-+
-+static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
-+static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
-+static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
-+static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
-+
-+static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
-+ FUNC("jtag", 3, 22, 8),
-+ FUNC("utif", 2, 22, 8),
-+ FUNC("gpio", 1, 22, 8),
-+ FUNC("sdcx", 0, 22, 8),
-+};
-+
-+static struct rt2880_pmx_func uart0_grp_mt7628[] = {
-+ FUNC("-", 3, 12, 2),
-+ FUNC("-", 2, 12, 2),
-+ FUNC("gpio", 1, 12, 2),
-+ FUNC("uart", 0, 12, 2),
-+};
-+
-+static struct rt2880_pmx_func i2s_grp_mt7628[] = {
-+ FUNC("antenna", 3, 0, 4),
-+ FUNC("pcm", 2, 0, 4),
-+ FUNC("gpio", 1, 0, 4),
-+ FUNC("i2s", 0, 0, 4),
-+};
-+
-+static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
-+ FUNC("-", 3, 6, 1),
-+ FUNC("refclk", 2, 6, 1),
-+ FUNC("gpio", 1, 6, 1),
-+ FUNC("spi", 0, 6, 1),
-+};
-+
-+static struct rt2880_pmx_func spis_grp_mt7628[] = {
-+ FUNC("pwm", 3, 14, 4),
-+ FUNC("util", 2, 14, 4),
-+ FUNC("gpio", 1, 14, 4),
-+ FUNC("spis", 0, 14, 4),
-+};
-+
-+static struct rt2880_pmx_func gpio_grp_mt7628[] = {
-+ FUNC("pcie", 3, 11, 1),
-+ FUNC("refclk", 2, 11, 1),
-+ FUNC("gpio", 1, 11, 1),
-+ FUNC("gpio", 0, 11, 1),
-+};
-+
-+#define MT7628_GPIO_MODE_MASK 0x3
-+
-+#define MT7628_GPIO_MODE_PWM1 30
-+#define MT7628_GPIO_MODE_PWM0 28
-+#define MT7628_GPIO_MODE_UART2 26
-+#define MT7628_GPIO_MODE_UART1 24
-+#define MT7628_GPIO_MODE_I2C 20
-+#define MT7628_GPIO_MODE_REFCLK 18
-+#define MT7628_GPIO_MODE_PERST 16
-+#define MT7628_GPIO_MODE_WDT 14
-+#define MT7628_GPIO_MODE_SPI 12
-+#define MT7628_GPIO_MODE_SDMODE 10
-+#define MT7628_GPIO_MODE_UART0 8
-+#define MT7628_GPIO_MODE_I2S 6
-+#define MT7628_GPIO_MODE_CS1 4
-+#define MT7628_GPIO_MODE_SPIS 2
-+#define MT7628_GPIO_MODE_GPIO 0
-+
-+static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
-+ GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM1),
-+ GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM0),
-+ GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART2),
-+ GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART1),
-+ GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2C),
-+ GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
-+ GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
-+ GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
-+ GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
-+ GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SDMODE),
-+ GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART0),
-+ GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2S),
-+ GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_CS1),
-+ GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SPIS),
-+ GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_GPIO),
-+ { 0 }
-+};
-+
- static __init u32
- mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
- {
-@@ -309,29 +430,42 @@ void __init ralink_clk_init(void)
-
- xtal_rate = mt7620_get_xtal_rate();
-
-- cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
-- pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
--
-- cpu_rate = mt7620_get_cpu_rate(pll_rate);
-- dram_rate = mt7620_get_dram_rate(pll_rate);
-- sys_rate = mt7620_get_sys_rate(cpu_rate);
-- periph_rate = mt7620_get_periph_rate(xtal_rate);
--
- #define RFMT(label) label ":%lu.%03luMHz "
- #define RINT(x) ((x) / 1000000)
- #define RFRAC(x) (((x) / 1000) % 1000)
-
-- pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
-- RINT(xtal_rate), RFRAC(xtal_rate),
-- RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
-- RINT(pll_rate), RFRAC(pll_rate));
-+ if (mt762x_soc == MT762X_SOC_MT7628AN) {
-+ if (xtal_rate == MHZ(40))
-+ cpu_rate = MHZ(580);
-+ else
-+ cpu_rate = MHZ(575);
-+ dram_rate = sys_rate = cpu_rate / 3;
-+ periph_rate = MHZ(40);
-+
-+ ralink_clk_add("10000d00.uartlite", periph_rate);
-+ ralink_clk_add("10000e00.uartlite", periph_rate);
-+ } else {
-+ cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
-+ pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
-+
-+ cpu_rate = mt7620_get_cpu_rate(pll_rate);
-+ dram_rate = mt7620_get_dram_rate(pll_rate);
-+ sys_rate = mt7620_get_sys_rate(cpu_rate);
-+ periph_rate = mt7620_get_periph_rate(xtal_rate);
-+
-+ pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
-+ RINT(xtal_rate), RFRAC(xtal_rate),
-+ RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
-+ RINT(pll_rate), RFRAC(pll_rate));
-+
-+ ralink_clk_add("10000500.uart", periph_rate);
-+ }
-
- pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
- RINT(cpu_rate), RFRAC(cpu_rate),
- RINT(dram_rate), RFRAC(dram_rate),
- RINT(sys_rate), RFRAC(sys_rate),
- RINT(periph_rate), RFRAC(periph_rate));
--
- #undef RFRAC
- #undef RINT
- #undef RFMT
-@@ -339,12 +473,11 @@ void __init ralink_clk_init(void)
- ralink_clk_add("cpu", cpu_rate);
- ralink_clk_add("10000100.timer", periph_rate);
- ralink_clk_add("10000120.watchdog", periph_rate);
-- ralink_clk_add("10000500.uart", periph_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", periph_rate);
- ralink_clk_add("10180000.wmac", xtal_rate);
-
-- if (IS_ENABLED(CONFIG_USB)) {
-+ if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
- /*
- * When the CPU goes into sleep mode, the BUS clock will be too low for
- * USB to function properly
-@@ -367,6 +500,52 @@ void __init ralink_of_remap(void)
- panic("Failed to remap core resources");
- }
-
-+static __init void
-+mt7620_dram_init(struct ralink_soc_info *soc_info)
-+{
-+ switch (dram_type) {
-+ case SYSCFG0_DRAM_TYPE_SDRAM:
-+ pr_info("Board has SDRAM\n");
-+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
-+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
-+ break;
-+
-+ case SYSCFG0_DRAM_TYPE_DDR1:
-+ pr_info("Board has DDR1\n");
-+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
-+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
-+ break;
-+
-+ case SYSCFG0_DRAM_TYPE_DDR2:
-+ pr_info("Board has DDR2\n");
-+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
-+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
-+ break;
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static __init void
-+mt7628_dram_init(struct ralink_soc_info *soc_info)
-+{
-+ switch (dram_type) {
-+ case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
-+ pr_info("Board has DDR1\n");
-+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
-+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
-+ break;
-+
-+ case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
-+ pr_info("Board has DDR2\n");
-+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
-+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
-+ break;
-+ default:
-+ BUG();
-+ }
-+}
-+
- void prom_soc_init(struct ralink_soc_info *soc_info)
- {
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
-@@ -384,18 +563,25 @@ void prom_soc_init(struct ralink_soc_inf
- rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
- bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
-
-- if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
-- panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
--
-- if (bga) {
-- name = "MT7620A";
-- soc_info->compatible = "ralink,mt7620a-soc";
-- } else {
-- name = "MT7620N";
-- soc_info->compatible = "ralink,mt7620n-soc";
-+ if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
-+ if (bga) {
-+ mt762x_soc = MT762X_SOC_MT7620A;
-+ name = "MT7620A";
-+ soc_info->compatible = "ralink,mt7620a-soc";
-+ } else {
-+ mt762x_soc = MT762X_SOC_MT7620N;
-+ name = "MT7620N";
-+ soc_info->compatible = "ralink,mt7620n-soc";
- #ifdef CONFIG_PCI
-- panic("mt7620n is only supported for non pci kernels");
-+ panic("mt7620n is only supported for non pci kernels");
- #endif
-+ }
-+ } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
-+ mt762x_soc = MT762X_SOC_MT7628AN;
-+ name = "MT7628AN";
-+ soc_info->compatible = "ralink,mt7628an-soc";
-+ } else {
-+ panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
- }
-
- snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
-@@ -407,28 +593,11 @@ void prom_soc_init(struct ralink_soc_inf
- cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
- dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
-
-- switch (dram_type) {
-- case SYSCFG0_DRAM_TYPE_SDRAM:
-- pr_info("Board has SDRAM\n");
-- soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
-- soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
-- break;
--
-- case SYSCFG0_DRAM_TYPE_DDR1:
-- pr_info("Board has DDR1\n");
-- soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
-- soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
-- break;
--
-- case SYSCFG0_DRAM_TYPE_DDR2:
-- pr_info("Board has DDR2\n");
-- soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
-- soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
-- break;
-- default:
-- BUG();
-- }
- soc_info->mem_base = MT7620_DRAM_BASE;
-+ if (mt762x_soc == MT762X_SOC_MT7628AN)
-+ mt7628_dram_init(soc_info);
-+ else
-+ mt7620_dram_init(soc_info);
-
- pmu0 = __raw_readl(sysc + PMU0_CFG);
- pmu1 = __raw_readl(sysc + PMU1_CFG);
-@@ -437,4 +606,9 @@ void prom_soc_init(struct ralink_soc_inf
- (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
- pr_info("Digital PMU set to %s control\n",
- (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
-+
-+ if (mt762x_soc == MT762X_SOC_MT7628AN)
-+ rt2880_pinmux_data = mt7628an_pinmux_data;
-+ else
-+ rt2880_pinmux_data = mt7620a_pinmux_data;
- }
+++ /dev/null
-From 0b24e0e6bf2d9a1ca5f95446bc025dafc226998c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 15 Mar 2013 18:16:01 +0100
-Subject: [PATCH 27/57] serial: ralink: adds mt7620 serial
-
-Add the config symbol for Mediatek7620 SoC to SERIAL_8250_RT288X
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/tty/serial/8250/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/tty/serial/8250/Kconfig
-+++ b/drivers/tty/serial/8250/Kconfig
-@@ -301,7 +301,7 @@ config SERIAL_8250_EM
-
- config SERIAL_8250_RT288X
- bool "Ralink RT288x/RT305x/RT3662/RT3883 serial port support"
-- depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883)
-+ depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
- help
- If you have a Ralink RT288x/RT305x SoC based board and want to use the
- serial port, say Y to this option. The driver can handle up to 2 serial
+++ /dev/null
-From b9ba09038dab4d824176ea2c2f2b73f49b567217 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 04:52:01 +0000
-Subject: [PATCH 28/57] serial: ralink: the core has a size of 0x100 and not
- 0x1000
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/tty/serial/8250/8250_core.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/tty/serial/8250/8250_core.c
-+++ b/drivers/tty/serial/8250/8250_core.c
-@@ -2517,7 +2517,7 @@ serial8250_pm(struct uart_port *port, un
- static unsigned int serial8250_port_size(struct uart_8250_port *pt)
- {
- if (pt->port.iotype == UPIO_AU)
-- return 0x1000;
-+ return 0x100;
- if (is_omap1_8250(pt))
- return 0x16 << pt->port.regshift;
-
+++ /dev/null
-From 49b47dfcef1353cd28eac8f64170e75d28ce4311 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:18:57 +0200
-Subject: [PATCH 29/57] serial: of: allow au1x00 and rt288x to load from OF
-
-In order to make serial_8250 loadable via OF on Au1x00 and Ralink WiSoC we need
-to default the iotype to UPIO_AU.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/tty/serial/of_serial.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/tty/serial/of_serial.c
-+++ b/drivers/tty/serial/of_serial.c
-@@ -102,7 +102,10 @@ static int of_platform_serial_setup(stru
- port->fifosize = prop;
-
- port->irq = irq_of_parse_and_map(np, 0);
-- port->iotype = UPIO_MEM;
-+ if (of_device_is_compatible(np, "ralink,rt2880-uart"))
-+ port->iotype = UPIO_AU;
-+ else
-+ port->iotype = UPIO_MEM;
- if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
- switch (prop) {
- case 1:
+++ /dev/null
-From 675c6ddd9432c39f508f9d6bdda17d9c675788cf Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:34:05 +0100
-Subject: [PATCH 30/57] pinctrl: ralink: add pinctrl driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/Kconfig | 2 +
- arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++-
- arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++
- arch/mips/include/asm/mach-ralink/rt305x.h | 35 ++-
- arch/mips/include/asm/mach-ralink/rt3883.h | 16 +-
- arch/mips/ralink/common.h | 19 --
- arch/mips/ralink/mt7620.c | 159 +++-------
- arch/mips/ralink/rt288x.c | 62 ++--
- arch/mips/ralink/rt305x.c | 151 ++++-----
- arch/mips/ralink/rt3883.c | 173 +++--------
- drivers/pinctrl/Kconfig | 5 +
- drivers/pinctrl/Makefile | 1 +
- drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++
- 13 files changed, 764 insertions(+), 420 deletions(-)
- create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h
- create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -436,6 +436,8 @@ config RALINK
- select CLKDEV_LOOKUP
- select ARCH_HAS_RESET_CONTROLLER
- select RESET_CONTROLLER
-+ select PINCTRL
-+ select PINCTRL_RT2880
-
- config SGI_IP22
- bool "SGI IP22 (Indy/Indigo2)"
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -90,7 +90,6 @@ enum mt762x_soc_type {
- #define MT7620_DDR2_SIZE_MIN 32
- #define MT7620_DDR2_SIZE_MAX 256
-
--#define MT7620_GPIO_MODE_I2C BIT(0)
- #define MT7620_GPIO_MODE_UART0_SHIFT 2
- #define MT7620_GPIO_MODE_UART0_MASK 0x7
- #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
-@@ -102,16 +101,36 @@ enum mt762x_soc_type {
- #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
- #define MT7620_GPIO_MODE_GPIO_I2S 0x6
- #define MT7620_GPIO_MODE_GPIO 0x7
--#define MT7620_GPIO_MODE_UART1 BIT(5)
--#define MT7620_GPIO_MODE_MDIO BIT(8)
--#define MT7620_GPIO_MODE_RGMII1 BIT(9)
--#define MT7620_GPIO_MODE_RGMII2 BIT(10)
--#define MT7620_GPIO_MODE_SPI BIT(11)
--#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
--#define MT7620_GPIO_MODE_WLED BIT(13)
--#define MT7620_GPIO_MODE_JTAG BIT(15)
--#define MT7620_GPIO_MODE_EPHY BIT(15)
--#define MT7620_GPIO_MODE_WDT BIT(22)
-+
-+#define MT7620_GPIO_MODE_NAND 0
-+#define MT7620_GPIO_MODE_SD 1
-+#define MT7620_GPIO_MODE_ND_SD_GPIO 2
-+#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
-+#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
-+
-+#define MT7620_GPIO_MODE_PCIE_RST 0
-+#define MT7620_GPIO_MODE_PCIE_REF 1
-+#define MT7620_GPIO_MODE_PCIE_GPIO 2
-+#define MT7620_GPIO_MODE_PCIE_MASK 0x3
-+#define MT7620_GPIO_MODE_PCIE_SHIFT 16
-+
-+#define MT7620_GPIO_MODE_WDT_RST 0
-+#define MT7620_GPIO_MODE_WDT_REF 1
-+#define MT7620_GPIO_MODE_WDT_GPIO 2
-+#define MT7620_GPIO_MODE_WDT_MASK 0x3
-+#define MT7620_GPIO_MODE_WDT_SHIFT 21
-+
-+#define MT7620_GPIO_MODE_I2C 0
-+#define MT7620_GPIO_MODE_UART1 5
-+#define MT7620_GPIO_MODE_MDIO 8
-+#define MT7620_GPIO_MODE_RGMII1 9
-+#define MT7620_GPIO_MODE_RGMII2 10
-+#define MT7620_GPIO_MODE_SPI 11
-+#define MT7620_GPIO_MODE_SPI_REF_CLK 12
-+#define MT7620_GPIO_MODE_WLED 13
-+#define MT7620_GPIO_MODE_JTAG 15
-+#define MT7620_GPIO_MODE_EPHY 15
-+#define MT7620_GPIO_MODE_PA 20
-
- static inline int mt7620_get_eco(void)
- {
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/pinmux.h
-@@ -0,0 +1,53 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#ifndef _RT288X_PINMUX_H__
-+#define _RT288X_PINMUX_H__
-+
-+#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
-+#define GRP(_name, _func, _mask, _shift) \
-+ { .name = _name, .mask = _mask, .shift = _shift, \
-+ .func = _func, .gpio = _mask, \
-+ .func_count = ARRAY_SIZE(_func) }
-+
-+#define GRP_G(_name, _func, _mask, _gpio, _shift) \
-+ { .name = _name, .mask = _mask, .shift = _shift, \
-+ .func = _func, .gpio = _gpio, \
-+ .func_count = ARRAY_SIZE(_func) }
-+
-+struct rt2880_pmx_group;
-+
-+struct rt2880_pmx_func {
-+ const char *name;
-+ const char value;
-+
-+ int pin_first;
-+ int pin_count;
-+ int *pins;
-+
-+ int *groups;
-+ int group_count;
-+
-+ int enabled;
-+};
-+
-+struct rt2880_pmx_group {
-+ const char *name;
-+ int enabled;
-+
-+ const u32 shift;
-+ const char mask;
-+ const char gpio;
-+
-+ struct rt2880_pmx_func *func;
-+ int func_count;
-+};
-+
-+extern struct rt2880_pmx_group *rt2880_pinmux_data;
-+
-+#endif
---- a/arch/mips/include/asm/mach-ralink/rt305x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
-@@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void)
- #define RT305X_GPIO_GE0_TXD0 40
- #define RT305X_GPIO_GE0_RXCLK 51
-
--#define RT305X_GPIO_MODE_I2C BIT(0)
--#define RT305X_GPIO_MODE_SPI BIT(1)
- #define RT305X_GPIO_MODE_UART0_SHIFT 2
- #define RT305X_GPIO_MODE_UART0_MASK 0x7
- #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
--#define RT305X_GPIO_MODE_UARTF 0x0
--#define RT305X_GPIO_MODE_PCM_UARTF 0x1
--#define RT305X_GPIO_MODE_PCM_I2S 0x2
--#define RT305X_GPIO_MODE_I2S_UARTF 0x3
--#define RT305X_GPIO_MODE_PCM_GPIO 0x4
--#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
--#define RT305X_GPIO_MODE_GPIO_I2S 0x6
--#define RT305X_GPIO_MODE_GPIO 0x7
--#define RT305X_GPIO_MODE_UART1 BIT(5)
--#define RT305X_GPIO_MODE_JTAG BIT(6)
--#define RT305X_GPIO_MODE_MDIO BIT(7)
--#define RT305X_GPIO_MODE_SDRAM BIT(8)
--#define RT305X_GPIO_MODE_RGMII BIT(9)
-+#define RT305X_GPIO_MODE_UARTF 0
-+#define RT305X_GPIO_MODE_PCM_UARTF 1
-+#define RT305X_GPIO_MODE_PCM_I2S 2
-+#define RT305X_GPIO_MODE_I2S_UARTF 3
-+#define RT305X_GPIO_MODE_PCM_GPIO 4
-+#define RT305X_GPIO_MODE_GPIO_UARTF 5
-+#define RT305X_GPIO_MODE_GPIO_I2S 6
-+#define RT305X_GPIO_MODE_GPIO 7
-+
-+#define RT305X_GPIO_MODE_I2C 0
-+#define RT305X_GPIO_MODE_SPI 1
-+#define RT305X_GPIO_MODE_UART1 5
-+#define RT305X_GPIO_MODE_JTAG 6
-+#define RT305X_GPIO_MODE_MDIO 7
-+#define RT305X_GPIO_MODE_SDRAM 8
-+#define RT305X_GPIO_MODE_RGMII 9
-+#define RT5350_GPIO_MODE_PHY_LED 14
-+#define RT5350_GPIO_MODE_SPI_CS1 21
-+#define RT3352_GPIO_MODE_LNA 18
-+#define RT3352_GPIO_MODE_PA 20
-
- #define RT3352_SYSC_REG_SYSCFG0 0x010
- #define RT3352_SYSC_REG_SYSCFG1 0x014
---- a/arch/mips/include/asm/mach-ralink/rt3883.h
-+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
-@@ -112,8 +112,6 @@
- #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
- #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
-
--#define RT3883_GPIO_MODE_I2C BIT(0)
--#define RT3883_GPIO_MODE_SPI BIT(1)
- #define RT3883_GPIO_MODE_UART0_SHIFT 2
- #define RT3883_GPIO_MODE_UART0_MASK 0x7
- #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
-@@ -125,11 +123,15 @@
- #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
- #define RT3883_GPIO_MODE_GPIO_I2S 0x6
- #define RT3883_GPIO_MODE_GPIO 0x7
--#define RT3883_GPIO_MODE_UART1 BIT(5)
--#define RT3883_GPIO_MODE_JTAG BIT(6)
--#define RT3883_GPIO_MODE_MDIO BIT(7)
--#define RT3883_GPIO_MODE_GE1 BIT(9)
--#define RT3883_GPIO_MODE_GE2 BIT(10)
-+
-+#define RT3883_GPIO_MODE_I2C 0
-+#define RT3883_GPIO_MODE_SPI 1
-+#define RT3883_GPIO_MODE_UART1 5
-+#define RT3883_GPIO_MODE_JTAG 6
-+#define RT3883_GPIO_MODE_MDIO 7
-+#define RT3883_GPIO_MODE_GE1 9
-+#define RT3883_GPIO_MODE_GE2 10
-+
- #define RT3883_GPIO_MODE_PCI_SHIFT 11
- #define RT3883_GPIO_MODE_PCI_MASK 0x7
- #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -11,25 +11,6 @@
-
- #define RAMIPS_SYS_TYPE_LEN 32
-
--struct ralink_pinmux_grp {
-- const char *name;
-- u32 mask;
-- int gpio_first;
-- int gpio_last;
--};
--
--struct ralink_pinmux {
-- struct ralink_pinmux_grp *mode;
-- struct ralink_pinmux_grp *uart;
-- int uart_shift;
-- u32 uart_mask;
-- void (*wdt_reset)(void);
-- struct ralink_pinmux_grp *pci;
-- int pci_shift;
-- u32 pci_mask;
--};
--extern struct ralink_pinmux rt_gpio_pinmux;
--
- struct ralink_soc_info {
- unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
- unsigned char *compatible;
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -17,6 +17,7 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/mt7620.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
-@@ -47,118 +48,58 @@ enum mt762x_soc_type mt762x_soc;
- /* does the board have sdram or ddram */
- static int dram_type;
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = MT7620_GPIO_MODE_I2C,
-- .gpio_first = 1,
-- .gpio_last = 2,
-- }, {
-- .name = "spi",
-- .mask = MT7620_GPIO_MODE_SPI,
-- .gpio_first = 3,
-- .gpio_last = 6,
-- }, {
-- .name = "uartlite",
-- .mask = MT7620_GPIO_MODE_UART1,
-- .gpio_first = 15,
-- .gpio_last = 16,
-- }, {
-- .name = "wdt",
-- .mask = MT7620_GPIO_MODE_WDT,
-- .gpio_first = 17,
-- .gpio_last = 17,
-- }, {
-- .name = "mdio",
-- .mask = MT7620_GPIO_MODE_MDIO,
-- .gpio_first = 22,
-- .gpio_last = 23,
-- }, {
-- .name = "rgmii1",
-- .mask = MT7620_GPIO_MODE_RGMII1,
-- .gpio_first = 24,
-- .gpio_last = 35,
-- }, {
-- .name = "spi refclk",
-- .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
-- .gpio_first = 37,
-- .gpio_last = 39,
-- }, {
-- .name = "jtag",
-- .mask = MT7620_GPIO_MODE_JTAG,
-- .gpio_first = 40,
-- .gpio_last = 44,
-- }, {
-- /* shared lines with jtag */
-- .name = "ephy",
-- .mask = MT7620_GPIO_MODE_EPHY,
-- .gpio_first = 40,
-- .gpio_last = 44,
-- }, {
-- .name = "nand",
-- .mask = MT7620_GPIO_MODE_JTAG,
-- .gpio_first = 45,
-- .gpio_last = 59,
-- }, {
-- .name = "rgmii2",
-- .mask = MT7620_GPIO_MODE_RGMII2,
-- .gpio_first = 60,
-- .gpio_last = 71,
-- }, {
-- .name = "wled",
-- .mask = MT7620_GPIO_MODE_WLED,
-- .gpio_first = 72,
-- .gpio_last = 72,
-- }, {0}
-+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
-+static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
-+static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
-+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
-+static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
-+static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
-+static struct rt2880_pmx_func uartf_grp[] = {
-+ FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
- };
--
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = MT7620_GPIO_MODE_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm uartf",
-- .mask = MT7620_GPIO_MODE_PCM_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm i2s",
-- .mask = MT7620_GPIO_MODE_PCM_I2S,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "i2s uartf",
-- .mask = MT7620_GPIO_MODE_I2S_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm gpio",
-- .mask = MT7620_GPIO_MODE_PCM_GPIO,
-- .gpio_first = 11,
-- .gpio_last = 14,
-- }, {
-- .name = "gpio uartf",
-- .mask = MT7620_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 10,
-- }, {
-- .name = "gpio i2s",
-- .mask = MT7620_GPIO_MODE_GPIO_I2S,
-- .gpio_first = 7,
-- .gpio_last = 10,
-- }, {
-- .name = "gpio",
-- .mask = MT7620_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_func wdt_grp[] = {
-+ FUNC("wdt rst", 0, 17, 1),
-+ FUNC("wdt refclk", 0, 17, 1),
-+ };
-+static struct rt2880_pmx_func pcie_rst_grp[] = {
-+ FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
-+ FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
-+};
-+static struct rt2880_pmx_func nd_sd_grp[] = {
-+ FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
-+ FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
- };
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
-+static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
-+ GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
-+ GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
-+ MT7620_GPIO_MODE_UART0_SHIFT),
-+ GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
-+ GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
-+ GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
-+ MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
-+ GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
-+ GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
-+ GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
-+ GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
-+ MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
-+ GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
-+ MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
-+ GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
-+ GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
-+ GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
-+ GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
-+ { 0 }
- };
-
- static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
---- a/arch/mips/ralink/rt288x.c
-+++ b/arch/mips/ralink/rt288x.c
-@@ -17,46 +17,27 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/rt288x.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = RT2880_GPIO_MODE_I2C,
-- .gpio_first = 1,
-- .gpio_last = 2,
-- }, {
-- .name = "spi",
-- .mask = RT2880_GPIO_MODE_SPI,
-- .gpio_first = 3,
-- .gpio_last = 6,
-- }, {
-- .name = "uartlite",
-- .mask = RT2880_GPIO_MODE_UART0,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "jtag",
-- .mask = RT2880_GPIO_MODE_JTAG,
-- .gpio_first = 17,
-- .gpio_last = 21,
-- }, {
-- .name = "mdio",
-- .mask = RT2880_GPIO_MODE_MDIO,
-- .gpio_first = 22,
-- .gpio_last = 23,
-- }, {
-- .name = "sdram",
-- .mask = RT2880_GPIO_MODE_SDRAM,
-- .gpio_first = 24,
-- .gpio_last = 39,
-- }, {
-- .name = "pci",
-- .mask = RT2880_GPIO_MODE_PCI,
-- .gpio_first = 40,
-- .gpio_last = 71,
-- }, {0}
-+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
-+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
-+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
-+static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
-+
-+static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
-+ GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
-+ GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
-+ GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
-+ GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
-+ GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
-+ { 0 }
- };
-
- static void rt288x_wdt_reset(void)
-@@ -69,11 +50,6 @@ static void rt288x_wdt_reset(void)
- rt_sysc_w32(t, SYSC_REG_CLKCFG);
- }
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .wdt_reset = rt288x_wdt_reset,
--};
--
- void __init ralink_clk_init(void)
- {
- unsigned long cpu_rate, wmac_rate = 40000000;
-@@ -141,4 +117,6 @@ void prom_soc_init(struct ralink_soc_inf
- soc_info->mem_base = RT2880_SDRAM_BASE;
- soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
-+
-+ rt2880_pinmux_data = rt2880_pinmux_data_act;
- }
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -17,90 +17,76 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/rt305x.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
- enum rt305x_soc_type rt305x_soc;
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = RT305X_GPIO_MODE_I2C,
-- .gpio_first = RT305X_GPIO_I2C_SD,
-- .gpio_last = RT305X_GPIO_I2C_SCLK,
-- }, {
-- .name = "spi",
-- .mask = RT305X_GPIO_MODE_SPI,
-- .gpio_first = RT305X_GPIO_SPI_EN,
-- .gpio_last = RT305X_GPIO_SPI_CLK,
-- }, {
-- .name = "uartlite",
-- .mask = RT305X_GPIO_MODE_UART1,
-- .gpio_first = RT305X_GPIO_UART1_TXD,
-- .gpio_last = RT305X_GPIO_UART1_RXD,
-- }, {
-- .name = "jtag",
-- .mask = RT305X_GPIO_MODE_JTAG,
-- .gpio_first = RT305X_GPIO_JTAG_TDO,
-- .gpio_last = RT305X_GPIO_JTAG_TDI,
-- }, {
-- .name = "mdio",
-- .mask = RT305X_GPIO_MODE_MDIO,
-- .gpio_first = RT305X_GPIO_MDIO_MDC,
-- .gpio_last = RT305X_GPIO_MDIO_MDIO,
-- }, {
-- .name = "sdram",
-- .mask = RT305X_GPIO_MODE_SDRAM,
-- .gpio_first = RT305X_GPIO_SDRAM_MD16,
-- .gpio_last = RT305X_GPIO_SDRAM_MD31,
-- }, {
-- .name = "rgmii",
-- .mask = RT305X_GPIO_MODE_RGMII,
-- .gpio_first = RT305X_GPIO_GE0_TXD0,
-- .gpio_last = RT305X_GPIO_GE0_RXCLK,
-- }, {0}
-+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartf_func[] = {
-+ FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
-+};
-+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
-+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
-+static struct rt2880_pmx_func rt5350_cs1_func[] = {
-+ FUNC("spi_cs1", 0, 27, 1),
-+ FUNC("wdg_cs1", 1, 27, 1),
-+};
-+static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
-+static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
-+static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
-+static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
-+static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
-+static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
-+
-+static struct rt2880_pmx_group rt3050_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
-+ GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
-+ GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
-+ { 0 }
-+};
-+
-+static struct rt2880_pmx_group rt3352_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
-+ GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
-+ GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
-+ GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
-+ GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
-+ { 0 }
- };
-
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = RT305X_GPIO_MODE_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm uartf",
-- .mask = RT305X_GPIO_MODE_PCM_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm i2s",
-- .mask = RT305X_GPIO_MODE_PCM_I2S,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "i2s uartf",
-- .mask = RT305X_GPIO_MODE_I2S_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm gpio",
-- .mask = RT305X_GPIO_MODE_PCM_GPIO,
-- .gpio_first = RT305X_GPIO_10,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "gpio uartf",
-- .mask = RT305X_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_10,
-- }, {
-- .name = "gpio i2s",
-- .mask = RT305X_GPIO_MODE_GPIO_I2S,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_10,
-- }, {
-- .name = "gpio",
-- .mask = RT305X_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_group rt5350_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
-+ GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
-+ { 0 }
- };
-
- static void rt305x_wdt_reset(void)
-@@ -114,14 +100,6 @@ static void rt305x_wdt_reset(void)
- rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
- }
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
-- .wdt_reset = rt305x_wdt_reset,
--};
--
- static unsigned long rt5350_get_mem_size(void)
- {
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
-@@ -290,11 +268,14 @@ void prom_soc_init(struct ralink_soc_inf
- soc_info->mem_base = RT305X_SDRAM_BASE;
- if (soc_is_rt5350()) {
- soc_info->mem_size = rt5350_get_mem_size();
-+ rt2880_pinmux_data = rt5350_pinmux_data;
- } else if (soc_is_rt305x() || soc_is_rt3350()) {
- soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
-+ rt2880_pinmux_data = rt3050_pinmux_data;
- } else if (soc_is_rt3352()) {
- soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
-+ rt2880_pinmux_data = rt3352_pinmux_data;
- }
- }
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -17,132 +17,50 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/rt3883.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = RT3883_GPIO_MODE_I2C,
-- .gpio_first = RT3883_GPIO_I2C_SD,
-- .gpio_last = RT3883_GPIO_I2C_SCLK,
-- }, {
-- .name = "spi",
-- .mask = RT3883_GPIO_MODE_SPI,
-- .gpio_first = RT3883_GPIO_SPI_CS0,
-- .gpio_last = RT3883_GPIO_SPI_MISO,
-- }, {
-- .name = "uartlite",
-- .mask = RT3883_GPIO_MODE_UART1,
-- .gpio_first = RT3883_GPIO_UART1_TXD,
-- .gpio_last = RT3883_GPIO_UART1_RXD,
-- }, {
-- .name = "jtag",
-- .mask = RT3883_GPIO_MODE_JTAG,
-- .gpio_first = RT3883_GPIO_JTAG_TDO,
-- .gpio_last = RT3883_GPIO_JTAG_TCLK,
-- }, {
-- .name = "mdio",
-- .mask = RT3883_GPIO_MODE_MDIO,
-- .gpio_first = RT3883_GPIO_MDIO_MDC,
-- .gpio_last = RT3883_GPIO_MDIO_MDIO,
-- }, {
-- .name = "ge1",
-- .mask = RT3883_GPIO_MODE_GE1,
-- .gpio_first = RT3883_GPIO_GE1_TXD0,
-- .gpio_last = RT3883_GPIO_GE1_RXCLK,
-- }, {
-- .name = "ge2",
-- .mask = RT3883_GPIO_MODE_GE2,
-- .gpio_first = RT3883_GPIO_GE2_TXD0,
-- .gpio_last = RT3883_GPIO_GE2_RXCLK,
-- }, {
-- .name = "pci",
-- .mask = RT3883_GPIO_MODE_PCI,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "lna a",
-- .mask = RT3883_GPIO_MODE_LNA_A,
-- .gpio_first = RT3883_GPIO_LNA_PE_A0,
-- .gpio_last = RT3883_GPIO_LNA_PE_A2,
-- }, {
-- .name = "lna g",
-- .mask = RT3883_GPIO_MODE_LNA_G,
-- .gpio_first = RT3883_GPIO_LNA_PE_G0,
-- .gpio_last = RT3883_GPIO_LNA_PE_G2,
-- }, {0}
-+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartf_func[] = {
-+ FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
- };
--
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = RT3883_GPIO_MODE_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm uartf",
-- .mask = RT3883_GPIO_MODE_PCM_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm i2s",
-- .mask = RT3883_GPIO_MODE_PCM_I2S,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "i2s uartf",
-- .mask = RT3883_GPIO_MODE_I2S_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm gpio",
-- .mask = RT3883_GPIO_MODE_PCM_GPIO,
-- .gpio_first = RT3883_GPIO_11,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "gpio uartf",
-- .mask = RT3883_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_10,
-- }, {
-- .name = "gpio i2s",
-- .mask = RT3883_GPIO_MODE_GPIO_I2S,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_10,
-- }, {
-- .name = "gpio",
-- .mask = RT3883_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
-+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
-+static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
-+static struct rt2880_pmx_func pci_func[] = {
-+ FUNC("pci-dev", 0, 40, 32),
-+ FUNC("pci-host2", 1, 40, 32),
-+ FUNC("pci-host1", 2, 40, 32),
-+ FUNC("pci-fnc", 3, 40, 32)
- };
-+static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
-+static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
-
--static struct ralink_pinmux_grp pci_mux[] = {
-- {
-- .name = "pci-dev",
-- .mask = 0,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-host2",
-- .mask = 1,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-host1",
-- .mask = 2,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-fnc",
-- .mask = 3,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-gpio",
-- .mask = 7,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {0}
-+static struct rt2880_pmx_group rt3883_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
-+ RT3883_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
-+ GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
-+ GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
-+ GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
-+ RT3883_GPIO_MODE_PCI_SHIFT),
-+ GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
-+ GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
-+ { 0 }
- };
-
- static void rt3883_wdt_reset(void)
-@@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
- rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
- }
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
-- .wdt_reset = rt3883_wdt_reset,
-- .pci = pci_mux,
-- .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
-- .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
--};
--
- void __init ralink_clk_init(void)
- {
- unsigned long cpu_rate, sys_rate;
-@@ -244,4 +151,6 @@ void prom_soc_init(struct ralink_soc_inf
- soc_info->mem_base = RT3883_SDRAM_BASE;
- soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
-+
-+ rt2880_pinmux_data = rt3883_pinmux_data;
- }
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -198,6 +198,11 @@ config PINCTRL_LANTIQ
- select PINMUX
- select PINCONF
-
-+config PINCTRL_RT2880
-+ bool
-+ depends on RALINK
-+ select PINMUX
-+
- config PINCTRL_FALCON
- bool
- depends on SOC_FALCON
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-
- obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
- obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
- obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
-+obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
- obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
- obj-$(CONFIG_PINCTRL_SIRF) += sirf/
- obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-rt2880.c
-@@ -0,0 +1,467 @@
-+/*
-+ * linux/drivers/pinctrl/pinctrl-rt2880.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinconf.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/pinctrl/machine.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/mach-ralink/pinmux.h>
-+#include <asm/mach-ralink/mt7620.h>
-+
-+#include "core.h"
-+
-+#define SYSC_REG_GPIO_MODE 0x60
-+
-+struct rt2880_priv {
-+ struct device *dev;
-+
-+ struct pinctrl_pin_desc *pads;
-+ struct pinctrl_desc *desc;
-+
-+ struct rt2880_pmx_func **func;
-+ int func_count;
-+
-+ struct rt2880_pmx_group *groups;
-+ const char **group_names;
-+ int group_count;
-+
-+ uint8_t *gpio;
-+ int max_pins;
-+};
-+
-+struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
-+
-+static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->group_count;
-+}
-+
-+static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
-+ unsigned group)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (group >= p->group_count)
-+ return NULL;
-+
-+ return p->group_names[group];
-+}
-+
-+static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
-+ unsigned group,
-+ const unsigned **pins,
-+ unsigned *num_pins)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (group >= p->group_count)
-+ return -EINVAL;
-+
-+ *pins = p->groups[group].func[0].pins;
-+ *num_pins = p->groups[group].func[0].pin_count;
-+
-+ return 0;
-+}
-+
-+static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_map *map, unsigned num_maps)
-+{
-+ int i;
-+
-+ for (i = 0; i < num_maps; i++)
-+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
-+ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
-+ kfree(map[i].data.configs.configs);
-+ kfree(map);
-+}
-+
-+static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
-+ struct seq_file *s,
-+ unsigned offset)
-+{
-+ seq_printf(s, "ralink pio");
-+}
-+
-+static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
-+ struct device_node *np,
-+ struct pinctrl_map **map)
-+{
-+ const char *function;
-+ int func = of_property_read_string(np, "ralink,function", &function);
-+ int grps = of_property_count_strings(np, "ralink,group");
-+ int i;
-+
-+ if (func || !grps)
-+ return;
-+
-+ for (i = 0; i < grps; i++) {
-+ const char *group;
-+
-+ of_property_read_string_index(np, "ralink,group", i, &group);
-+
-+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
-+ (*map)->name = function;
-+ (*map)->data.mux.group = group;
-+ (*map)->data.mux.function = function;
-+ (*map)++;
-+ }
-+}
-+
-+static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
-+ struct device_node *np_config,
-+ struct pinctrl_map **map,
-+ unsigned *num_maps)
-+{
-+ int max_maps = 0;
-+ struct pinctrl_map *tmp;
-+ struct device_node *np;
-+
-+ for_each_child_of_node(np_config, np) {
-+ int ret = of_property_count_strings(np, "ralink,group");
-+
-+ if (ret >= 0)
-+ max_maps += ret;
-+ }
-+
-+ if (!max_maps)
-+ return max_maps;
-+
-+ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
-+ if (!*map)
-+ return -ENOMEM;
-+
-+ tmp = *map;
-+
-+ for_each_child_of_node(np_config, np)
-+ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
-+ *num_maps = max_maps;
-+
-+ return 0;
-+}
-+
-+static const struct pinctrl_ops rt2880_pctrl_ops = {
-+ .get_groups_count = rt2880_get_group_count,
-+ .get_group_name = rt2880_get_group_name,
-+ .get_group_pins = rt2880_get_group_pins,
-+ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
-+ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
-+ .dt_free_map = rt2880_pinctrl_dt_free_map,
-+};
-+
-+static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->func_count;
-+}
-+
-+static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
-+ unsigned func)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->func[func]->name;
-+}
-+
-+static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ const char * const **groups,
-+ unsigned * const num_groups)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (p->func[func]->group_count == 1)
-+ *groups = &p->group_names[p->func[func]->groups[0]];
-+ else
-+ *groups = p->group_names;
-+
-+ *num_groups = p->func[func]->group_count;
-+
-+ return 0;
-+}
-+
-+static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ unsigned group)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+ u32 mode = 0;
-+ int i;
-+
-+ /* dont allow double use */
-+ if (p->groups[group].enabled) {
-+ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
-+ return -EBUSY;
-+ }
-+
-+ p->groups[group].enabled = 1;
-+ p->func[func]->enabled = 1;
-+
-+ mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
-+ mode &= ~(p->groups[group].mask << p->groups[group].shift);
-+
-+ /* mark the pins as gpio */
-+ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
-+ p->gpio[p->groups[group].func[0].pins[i]] = 1;
-+
-+ /* function 0 is gpio and needs special handling */
-+ if (func == 0) {
-+ mode |= p->groups[group].gpio << p->groups[group].shift;
-+ } else {
-+ for (i = 0; i < p->func[func]->pin_count; i++)
-+ p->gpio[p->func[func]->pins[i]] = 0;
-+ mode |= p->func[func]->value << p->groups[group].shift;
-+ }
-+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
-+
-+
-+ return 0;
-+}
-+
-+static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_gpio_range *range,
-+ unsigned pin)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (!p->gpio[pin]) {
-+ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct pinmux_ops rt2880_pmx_group_ops = {
-+ .get_functions_count = rt2880_pmx_func_count,
-+ .get_function_name = rt2880_pmx_func_name,
-+ .get_function_groups = rt2880_pmx_group_get_groups,
-+ .enable = rt2880_pmx_group_enable,
-+ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
-+};
-+
-+static struct pinctrl_desc rt2880_pctrl_desc = {
-+ .owner = THIS_MODULE,
-+ .name = "rt2880-pinmux",
-+ .pctlops = &rt2880_pctrl_ops,
-+ .pmxops = &rt2880_pmx_group_ops,
-+};
-+
-+static struct rt2880_pmx_func gpio_func = {
-+ .name = "gpio",
-+};
-+
-+static int rt2880_pinmux_index(struct rt2880_priv *p)
-+{
-+ struct rt2880_pmx_func **f;
-+ struct rt2880_pmx_group *mux = p->groups;
-+ int i, j, c = 0;
-+
-+ /* count the mux functions */
-+ while (mux->name) {
-+ p->group_count++;
-+ mux++;
-+ }
-+
-+ /* allocate the group names array needed by the gpio function */
-+ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
-+ if (!p->group_names)
-+ return -1;
-+
-+ for (i = 0; i < p->group_count; i++) {
-+ p->group_names[i] = p->groups[i].name;
-+ p->func_count += p->groups[i].func_count;
-+ }
-+
-+ /* we have a dummy function[0] for gpio */
-+ p->func_count++;
-+
-+ /* allocate our function and group mapping index buffers */
-+ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
-+ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
-+ if (!f || !gpio_func.groups)
-+ return -1;
-+
-+ /* add a backpointer to the function so it knows its group */
-+ gpio_func.group_count = p->group_count;
-+ for (i = 0; i < gpio_func.group_count; i++)
-+ gpio_func.groups[i] = i;
-+
-+ f[c] = &gpio_func;
-+ c++;
-+
-+ /* add remaining functions */
-+ for (i = 0; i < p->group_count; i++) {
-+ for (j = 0; j < p->groups[i].func_count; j++) {
-+ f[c] = &p->groups[i].func[j];
-+ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
-+ f[c]->groups[0] = i;
-+ f[c]->group_count = 1;
-+ c++;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static int rt2880_pinmux_pins(struct rt2880_priv *p)
-+{
-+ int i, j;
-+
-+ /* loop over the functions and initialize the pins array. also work out the highest pin used */
-+ for (i = 0; i < p->func_count; i++) {
-+ int pin;
-+
-+ if (!p->func[i]->pin_count)
-+ continue;
-+
-+ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
-+ for (j = 0; j < p->func[i]->pin_count; j++)
-+ p->func[i]->pins[j] = p->func[i]->pin_first + j;
-+
-+ pin = p->func[i]->pin_first + p->func[i]->pin_count;
-+ if (pin > p->max_pins)
-+ p->max_pins = pin;
-+ }
-+
-+ /* the buffer that tells us which pins are gpio */
-+ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
-+ GFP_KERNEL);
-+ /* the pads needed to tell pinctrl about our pins */
-+ p->pads = devm_kzalloc(p->dev,
-+ sizeof(struct pinctrl_pin_desc) * p->max_pins,
-+ GFP_KERNEL);
-+ if (!p->pads || !p->gpio ) {
-+ dev_err(p->dev, "Failed to allocate gpio data\n");
-+ return -ENOMEM;
-+ }
-+
-+ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
-+ for (i = 0; i < p->func_count; i++) {
-+ if (!p->func[i]->pin_count)
-+ continue;
-+
-+ for (j = 0; j < p->func[i]->pin_count; j++)
-+ p->gpio[p->func[i]->pins[j]] = 0;
-+ }
-+
-+ /* pin 0 is always a gpio */
-+ p->gpio[0] = 1;
-+
-+ /* set the pads */
-+ for (i = 0; i < p->max_pins; i++) {
-+ /* strlen("ioXY") + 1 = 5 */
-+ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
-+
-+ if (!name) {
-+ dev_err(p->dev, "Failed to allocate pad name\n");
-+ return -ENOMEM;
-+ }
-+ snprintf(name, 5, "io%d", i);
-+ p->pads[i].number = i;
-+ p->pads[i].name = name;
-+ }
-+ p->desc->pins = p->pads;
-+ p->desc->npins = p->max_pins;
-+
-+ return 0;
-+}
-+
-+static int rt2880_pinmux_probe(struct platform_device *pdev)
-+{
-+ struct rt2880_priv *p;
-+ struct pinctrl_dev *dev;
-+ struct device_node *np;
-+
-+ if (!rt2880_pinmux_data)
-+ return -ENOSYS;
-+
-+ /* setup the private data */
-+ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
-+ if (!p)
-+ return -ENOMEM;
-+
-+ p->dev = &pdev->dev;
-+ p->desc = &rt2880_pctrl_desc;
-+ p->groups = rt2880_pinmux_data;
-+ platform_set_drvdata(pdev, p);
-+
-+ /* init the device */
-+ if (rt2880_pinmux_index(p)) {
-+ dev_err(&pdev->dev, "failed to load index\n");
-+ return -EINVAL;
-+ }
-+ if (rt2880_pinmux_pins(p)) {
-+ dev_err(&pdev->dev, "failed to load pins\n");
-+ return -EINVAL;
-+ }
-+ dev = pinctrl_register(p->desc, &pdev->dev, p);
-+ if (IS_ERR(dev))
-+ return PTR_ERR(dev);
-+
-+ /* finalize by adding gpio ranges for enables gpio controllers */
-+ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
-+ const __be32 *ngpio, *gpiobase;
-+ struct pinctrl_gpio_range *range;
-+ char *name;
-+
-+ if (!of_device_is_available(np))
-+ continue;
-+
-+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
-+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
-+ if (!ngpio || !gpiobase) {
-+ dev_err(&pdev->dev, "failed to load chip info\n");
-+ return -EINVAL;
-+ }
-+
-+ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
-+ range->name = name = (char *) &range[1];
-+ sprintf(name, "pio");
-+ range->npins = __be32_to_cpu(*ngpio);
-+ range->base = __be32_to_cpu(*gpiobase);
-+ range->pin_base = range->base;
-+ pinctrl_add_gpio_range(dev, range);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id rt2880_pinmux_match[] = {
-+ { .compatible = "ralink,rt2880-pinmux" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
-+
-+static struct platform_driver rt2880_pinmux_driver = {
-+ .probe = rt2880_pinmux_probe,
-+ .driver = {
-+ .name = "rt2880-pinmux",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt2880_pinmux_match,
-+ },
-+};
-+
-+int __init rt2880_pinmux_init(void)
-+{
-+ return platform_driver_register(&rt2880_pinmux_driver);
-+}
-+
-+core_initcall_sync(rt2880_pinmux_init);
+++ /dev/null
-From 5b0bcc314005dd14eeae190948165a81eef7da1f Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:36:02 +0100
-Subject: [PATCH 31/57] PCI: MIPS: adds rt2880 pci support
-
-Add support for the pci found on the rt2880 SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-rt2880.c | 281 ++++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ralink/Kconfig | 1 +
- 3 files changed, 283 insertions(+)
- create mode 100644 arch/mips/pci/pci-rt2880.c
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
- obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
-+obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
- obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
---- /dev/null
-+++ b/arch/mips/pci/pci-rt2880.c
-@@ -0,0 +1,281 @@
-+/*
-+ * Ralink RT288x SoC PCI register definitions
-+ *
-+ * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
-+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * Parts of this file are based on Ralink's 2.6.21 BSP
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+
-+#include <asm/mach-ralink/rt288x.h>
-+
-+#define RT2880_PCI_BASE 0x00440000
-+#define RT288X_CPU_IRQ_PCI 4
-+
-+#define RT2880_PCI_MEM_BASE 0x20000000
-+#define RT2880_PCI_MEM_SIZE 0x10000000
-+#define RT2880_PCI_IO_BASE 0x00460000
-+#define RT2880_PCI_IO_SIZE 0x00010000
-+
-+#define RT2880_PCI_REG_PCICFG_ADDR 0x00
-+#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
-+#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
-+#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
-+#define RT2880_PCI_REG_CONFIG_ADDR 0x20
-+#define RT2880_PCI_REG_CONFIG_DATA 0x24
-+#define RT2880_PCI_REG_MEMBASE 0x28
-+#define RT2880_PCI_REG_IOBASE 0x2c
-+#define RT2880_PCI_REG_ID 0x30
-+#define RT2880_PCI_REG_CLASS 0x34
-+#define RT2880_PCI_REG_SUBID 0x38
-+#define RT2880_PCI_REG_ARBCTL 0x80
-+
-+static void __iomem *rt2880_pci_base;
-+static DEFINE_SPINLOCK(rt2880_pci_lock);
-+
-+static u32 rt2880_pci_reg_read(u32 reg)
-+{
-+ return readl(rt2880_pci_base + reg);
-+}
-+
-+static void rt2880_pci_reg_write(u32 val, u32 reg)
-+{
-+ writel(val, rt2880_pci_base + reg);
-+}
-+
-+static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
-+ unsigned int func, unsigned int where)
-+{
-+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
-+ 0x80000000);
-+}
-+
-+static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *val)
-+{
-+ unsigned long flags;
-+ u32 address;
-+ u32 data;
-+
-+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), where);
-+
-+ spin_lock_irqsave(&rt2880_pci_lock, flags);
-+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+ switch (size) {
-+ case 1:
-+ *val = (data >> ((where & 3) << 3)) & 0xff;
-+ break;
-+ case 2:
-+ *val = (data >> ((where & 3) << 3)) & 0xffff;
-+ break;
-+ case 4:
-+ *val = data;
-+ break;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 val)
-+{
-+ unsigned long flags;
-+ u32 address;
-+ u32 data;
-+
-+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), where);
-+
-+ spin_lock_irqsave(&rt2880_pci_lock, flags);
-+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+
-+ switch (size) {
-+ case 1:
-+ data = (data & ~(0xff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 2:
-+ data = (data & ~(0xffff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 4:
-+ data = val;
-+ break;
-+ }
-+
-+ rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
-+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops rt2880_pci_ops = {
-+ .read = rt2880_pci_config_read,
-+ .write = rt2880_pci_config_write,
-+};
-+
-+static struct resource rt2880_pci_mem_resource = {
-+ .name = "PCI MEM space",
-+ .start = RT2880_PCI_MEM_BASE,
-+ .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct resource rt2880_pci_io_resource = {
-+ .name = "PCI IO space",
-+ .start = RT2880_PCI_IO_BASE,
-+ .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct pci_controller rt2880_pci_controller = {
-+ .pci_ops = &rt2880_pci_ops,
-+ .mem_resource = &rt2880_pci_mem_resource,
-+ .io_resource = &rt2880_pci_io_resource,
-+};
-+
-+static inline u32 rt2880_pci_read_u32(unsigned long reg)
-+{
-+ unsigned long flags;
-+ u32 address;
-+ u32 ret;
-+
-+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
-+
-+ spin_lock_irqsave(&rt2880_pci_lock, flags);
-+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+ ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+
-+ return ret;
-+}
-+
-+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
-+{
-+ unsigned long flags;
-+ u32 address;
-+
-+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
-+
-+ spin_lock_irqsave(&rt2880_pci_lock, flags);
-+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-+ rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
-+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ u16 cmd;
-+ int irq = -1;
-+
-+ if (dev->bus->number != 0)
-+ return irq;
-+
-+ switch (PCI_SLOT(dev->devfn)) {
-+ case 0x00:
-+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
-+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
-+ break;
-+ case 0x11:
-+ irq = RT288X_CPU_IRQ_PCI;
-+ break;
-+ default:
-+ printk("%s:%s[%d] trying to alloc unknown pci irq\n",
-+ __FILE__, __func__, __LINE__);
-+ BUG();
-+ break;
-+ }
-+
-+ pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
-+ pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
-+ pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
-+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
-+ PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
-+ pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
-+ pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
-+ dev->irq);
-+ return irq;
-+}
-+
-+static int rt288x_pci_probe(struct platform_device *pdev)
-+{
-+ void __iomem *io_map_base;
-+ int i;
-+
-+ rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
-+
-+ io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
-+ rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
-+ set_io_port_base((unsigned long) io_map_base);
-+
-+ ioport_resource.start = RT2880_PCI_IO_BASE;
-+ ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
-+
-+ rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
-+ for(i = 0; i < 0xfffff; i++) {}
-+
-+ rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
-+ rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
-+ rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
-+ rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
-+ rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
-+ rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
-+ rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
-+ rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
-+ rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
-+
-+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
-+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
-+
-+ register_pci_controller(&rt2880_pci_controller);
-+ return 0;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+static const struct of_device_id rt288x_pci_match[] = {
-+ { .compatible = "ralink,rt288x-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt288x_pci_match);
-+
-+static struct platform_driver rt288x_pci_driver = {
-+ .probe = rt288x_pci_probe,
-+ .driver = {
-+ .name = "rt288x-pci",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt288x_pci_match,
-+ },
-+};
-+
-+int __init pcibios_init(void)
-+{
-+ int ret = platform_driver_register(&rt288x_pci_driver);
-+ if (ret)
-+ pr_info("rt288x-pci: Error registering platform driver!");
-+ return ret;
-+}
-+
-+arch_initcall(pcibios_init);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -21,6 +21,7 @@ choice
- config SOC_RT288X
- bool "RT288x"
- select MIPS_L1_CACHE_SHIFT_4
-+ select HW_HAS_PCI
-
- config SOC_RT305X
- bool "RT305x"
+++ /dev/null
-From 307b7a71a634ae3848fb7c5c05759d647e140e12 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sat, 18 May 2013 22:06:15 +0200
-Subject: [PATCH 32/57] PCI: MIPS: adds mt7620a pcie driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-mt7620.c | 363 +++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ralink/Kconfig | 1 +
- 3 files changed, 365 insertions(+)
- create mode 100644 arch/mips/pci/pci-mt7620.c
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
- obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
-+obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
- obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
---- /dev/null
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -0,0 +1,396 @@
-+/*
-+ * Ralink MT7620A SoC PCI support
-+ *
-+ * Copyright (C) 2007-2013 Bruce Chang
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+#include <linux/reset.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/mach-ralink/mt7620.h>
-+
-+#define RALINK_PCI_MM_MAP_BASE 0x20000000
-+#define RALINK_PCI_IO_MAP_BASE 0x10160000
-+
-+#define RALINK_INT_PCIE0 4
-+#define RALINK_SYSCFG1 0x14
-+#define RALINK_CLKCFG1 0x30
-+#define RALINK_GPIOMODE 0x60
-+#define RALINK_PCIE_CLK_GEN 0x7c
-+#define RALINK_PCIE_CLK_GEN1 0x80
-+#define PCIEPHY0_CFG 0x90
-+#define PPLL_CFG1 0x9c
-+#define PPLL_DRV 0xa0
-+#define PDRV_SW_SET (1<<31)
-+#define LC_CKDRVPD_ (1<<19)
-+
-+#define RALINK_PCI_CONFIG_ADDR 0x20
-+#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
-+#define MEMORY_BASE 0x0
-+#define RALINK_PCIE0_RST (1<<26)
-+#define RALINK_PCI_BASE 0xB0140000
-+#define RALINK_PCI_MEMBASE 0x28
-+#define RALINK_PCI_IOBASE 0x2C
-+
-+#define RT6855_PCIE0_OFFSET 0x2000
-+
-+#define RALINK_PCI_PCICFG_ADDR 0x00
-+#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
-+#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
-+#define RALINK_PCI0_ID 0x30
-+#define RALINK_PCI0_CLASS 0x34
-+#define RALINK_PCI0_SUBID 0x38
-+#define RALINK_PCI0_STATUS 0x50
-+#define RALINK_PCI_PCIMSK_ADDR 0x0C
-+
-+#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
-+#define RALINK_PCIE0_CLK_EN (1 << 26)
-+
-+#define BUSY 0x80000000
-+#define WAITRETRY_MAX 10
-+#define WRITE_MODE (1UL << 23)
-+#define DATA_SHIFT 0
-+#define ADDR_SHIFT 8
-+
-+static void __iomem *bridge_base;
-+static void __iomem *pcie_base;
-+
-+static struct reset_control *rstpcie0;
-+
-+static inline void bridge_w32(u32 val, unsigned reg)
-+{
-+ iowrite32(val, bridge_base + reg);
-+}
-+
-+static inline u32 bridge_r32(unsigned reg)
-+{
-+ return ioread32(bridge_base + reg);
-+}
-+
-+static inline void pcie_w32(u32 val, unsigned reg)
-+{
-+ iowrite32(val, pcie_base + reg);
-+}
-+
-+static inline u32 pcie_r32(unsigned reg)
-+{
-+ return ioread32(pcie_base + reg);
-+}
-+
-+static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
-+{
-+ u32 val = pcie_r32(reg);
-+
-+ val &= ~clr;
-+ val |= set;
-+ pcie_w32(val, reg);
-+}
-+
-+static int wait_pciephy_busy(void)
-+{
-+ unsigned long reg_value = 0x0, retry = 0;
-+
-+ while (1) {
-+ reg_value = pcie_r32(PCIEPHY0_CFG);
-+
-+ if (reg_value & BUSY)
-+ mdelay(100);
-+ else
-+ break;
-+ if (retry++ > WAITRETRY_MAX){
-+ printk("PCIE-PHY retry failed.\n");
-+ return -1;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static void pcie_phy(unsigned long addr, unsigned long val)
-+{
-+ wait_pciephy_busy();
-+ pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
-+ mdelay(1);
-+ wait_pciephy_busy();
-+}
-+
-+static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
-+{
-+ unsigned int slot = PCI_SLOT(devfn);
-+ u8 func = PCI_FUNC(devfn);
-+ u32 address;
-+ u32 data;
-+ u32 num = 0;
-+
-+ if (bus)
-+ num = bus->number;
-+
-+ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
-+
-+ switch (size) {
-+ case 1:
-+ *val = (data >> ((where & 3) << 3)) & 0xff;
-+ break;
-+ case 2:
-+ *val = (data >> ((where & 3) << 3)) & 0xffff;
-+ break;
-+ case 4:
-+ *val = data;
-+ break;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-+{
-+ unsigned int slot = PCI_SLOT(devfn);
-+ u8 func = PCI_FUNC(devfn);
-+ u32 address;
-+ u32 data;
-+ u32 num = 0;
-+
-+ if (bus)
-+ num = bus->number;
-+
-+ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
-+
-+ switch (size) {
-+ case 1:
-+ data = (data & ~(0xff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 2:
-+ data = (data & ~(0xffff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 4:
-+ data = val;
-+ break;
-+ }
-+
-+ bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+struct pci_ops mt7620_pci_ops= {
-+ .read = pci_config_read,
-+ .write = pci_config_write,
-+};
-+
-+static struct resource mt7620_res_pci_mem1;
-+static struct resource mt7620_res_pci_io1;
-+struct pci_controller mt7620_controller = {
-+ .pci_ops = &mt7620_pci_ops,
-+ .mem_resource = &mt7620_res_pci_mem1,
-+ .mem_offset = 0x00000000UL,
-+ .io_resource = &mt7620_res_pci_io1,
-+ .io_offset = 0x00000000UL,
-+ .io_map_base = 0xa0000000,
-+};
-+
-+static int mt7620_pci_hw_init(struct platform_device *pdev) {
-+ /* PCIE: bypass PCIe DLL */
-+ pcie_phy(0x0, 0x80);
-+ pcie_phy(0x1, 0x04);
-+
-+ /* PCIE: Elastic buffer control */
-+ pcie_phy(0x68, 0xB4);
-+
-+ pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
-+
-+ reset_control_assert(rstpcie0);
-+
-+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+ rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
-+
-+ reset_control_deassert(rstpcie0);
-+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
-+
-+ mdelay(100);
-+
-+ if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
-+ dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
-+ reset_control_assert(rstpcie0);
-+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+ return -1;
-+ }
-+ rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
-+
-+ return 0;
-+}
-+
-+static int mt7628_pci_hw_init(struct platform_device *pdev) {
-+ u32 val = 0;
-+
-+ rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
-+ reset_control_deassert(rstpcie0);
-+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
-+ mdelay(100);
-+
-+ pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
-+
-+ pci_config_read(NULL, 0, 0x70c, 4, &val);
-+ val &= ~(0xff) << 8;
-+ val |= 0x50 << 8;
-+ pci_config_write(NULL, 0, 0x70c, 4, val);
-+
-+ pci_config_read(NULL, 0, 0x70c, 4, &val);
-+ dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
-+
-+ return 0;
-+}
-+
-+static int mt7620_pci_probe(struct platform_device *pdev)
-+{
-+ struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+ u32 val = 0;
-+
-+ rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
-+ if (IS_ERR(rstpcie0))
-+ return PTR_ERR(rstpcie0);
-+
-+ bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
-+ if (!bridge_base)
-+ return -ENOMEM;
-+
-+ pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
-+ if (!pcie_base)
-+ return -ENOMEM;
-+
-+ iomem_resource.start = 0;
-+ iomem_resource.end = ~0;
-+ ioport_resource.start = 0;
-+ ioport_resource.end = ~0;
-+
-+ /* bring up the pci core */
-+ switch (ralink_soc) {
-+ case MT762X_SOC_MT7620A:
-+ if (mt7620_pci_hw_init(pdev))
-+ return -1;
-+ break;
-+
-+ case MT762X_SOC_MT7628AN:
-+ if (mt7628_pci_hw_init(pdev))
-+ return -1;
-+ break;
-+
-+ default:
-+ dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
-+ return -1;
-+ }
-+ mdelay(50);
-+
-+ /* enable write access */
-+ pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
-+ mdelay(100);
-+
-+ /* check if there is a card present */
-+ if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
-+ reset_control_assert(rstpcie0);
-+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+ if (ralink_soc == MT762X_SOC_MT7620A)
-+ rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
-+ dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
-+ return -1;
-+ }
-+
-+ /* setup ranges */
-+ bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
-+ bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
-+
-+ pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
-+ pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
-+ pcie_w32(0x06040001, RALINK_PCI0_CLASS);
-+
-+ /* enable interrupts */
-+ pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
-+
-+ /* voodoo from the SDK driver */
-+ pci_config_read(NULL, 0, 4, 4, &val);
-+ pci_config_write(NULL, 0, 4, 4, val | 0x7);
-+
-+ pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
-+ register_pci_controller(&mt7620_controller);
-+
-+ return 0;
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ u16 cmd;
-+ u32 val;
-+ int irq = 0;
-+
-+ if ((dev->bus->number == 0) && (slot == 0)) {
-+ pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
-+ pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
-+ pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
-+ } else if ((dev->bus->number == 1) && (slot == 0x0)) {
-+ irq = RALINK_INT_PCIE0;
-+ } else {
-+ dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
-+ return 0;
-+ }
-+ dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
-+
-+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
-+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
-+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
-+
-+ // FIXME
-+ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-+ pci_write_config_word(dev, PCI_COMMAND, cmd);
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-+ //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
-+
-+ return irq;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+static const struct of_device_id mt7620_pci_ids[] = {
-+ { .compatible = "mediatek,mt7620-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
-+
-+static struct platform_driver mt7620_pci_driver = {
-+ .probe = mt7620_pci_probe,
-+ .driver = {
-+ .name = "mt7620-pci",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(mt7620_pci_ids),
-+ },
-+};
-+
-+static int __init mt7620_pci_init(void)
-+{
-+ return platform_driver_register(&mt7620_pci_driver);
-+}
-+
-+arch_initcall(mt7620_pci_init);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -39,6 +39,7 @@ choice
- bool "MT7620/8"
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
-+ select HW_HAS_PCI
-
- config SOC_MT7621
- bool "MT7621"
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -19,6 +19,7 @@ enum mt762x_soc_type {
- MT762X_SOC_MT7620N,
- MT762X_SOC_MT7628AN,
- };
-+extern enum mt762x_soc_type mt762x_soc;
-
- #define MT7620_SYSC_BASE 0x10000000
-
+++ /dev/null
-From 9c34372c25519234add1cfdfe2b69c0847f2037e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:38:50 +0100
-Subject: [PATCH 33/57] NET: multi phy support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/phy.c | 9 ++++++---
- include/linux/phy.h | 1 +
- 2 files changed, 7 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -764,7 +764,8 @@ void phy_state_machine(struct work_struc
- /* If the link is down, give up on negotiation for now */
- if (!phydev->link) {
- phydev->state = PHY_NOLINK;
-- netif_carrier_off(phydev->attached_dev);
-+ if (!phydev->no_auto_carrier_off)
-+ netif_carrier_off(phydev->attached_dev);
- phydev->adjust_link(phydev->attached_dev);
- break;
- }
-@@ -841,7 +842,8 @@ void phy_state_machine(struct work_struc
- netif_carrier_on(phydev->attached_dev);
- } else {
- phydev->state = PHY_NOLINK;
-- netif_carrier_off(phydev->attached_dev);
-+ if (!phydev->no_auto_carrier_off)
-+ netif_carrier_off(phydev->attached_dev);
- }
-
- phydev->adjust_link(phydev->attached_dev);
-@@ -853,7 +855,8 @@ void phy_state_machine(struct work_struc
- case PHY_HALTED:
- if (phydev->link) {
- phydev->link = 0;
-- netif_carrier_off(phydev->attached_dev);
-+ if (!phydev->no_auto_carrier_off)
-+ netif_carrier_off(phydev->attached_dev);
- phydev->adjust_link(phydev->attached_dev);
- do_suspend = true;
- }
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -308,6 +308,7 @@ struct phy_device {
- struct phy_c45_device_ids c45_ids;
- bool is_c45;
- bool is_internal;
-+ bool no_auto_carrier_off;
-
- enum phy_state state;
-
+++ /dev/null
-From 92f38460229a8816404408f036f0a374f1013d0e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:40:01 +0100
-Subject: [PATCH 34/57] NET: add of_get_mac_address_mtd()
-
-Many embedded devices have information such as mac addresses stored inside mtd
-devices. This patch allows us to add a property inside a node describing a
-network interface. The new property points at a mtd partition with an offset
-where the mac address can be found.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++
- include/linux/of_net.h | 1 +
- 2 files changed, 38 insertions(+)
-
---- a/drivers/of/of_net.c
-+++ b/drivers/of/of_net.c
-@@ -10,6 +10,7 @@
- #include <linux/of_net.h>
- #include <linux/phy.h>
- #include <linux/export.h>
-+#include <linux/mtd/mtd.h>
-
- /**
- * It maps 'enum phy_interface_t' found in include/linux/phy.h
-@@ -94,3 +95,39 @@ const void *of_get_mac_address(struct de
- return NULL;
- }
- EXPORT_SYMBOL(of_get_mac_address);
-+
-+int of_get_mac_address_mtd(struct device_node *np, void *mac)
-+{
-+ struct device_node *mtd_np = NULL;
-+ size_t retlen;
-+ int size, ret;
-+ struct mtd_info *mtd;
-+ const char *part;
-+ const __be32 *list;
-+ phandle phandle;
-+
-+ list = of_get_property(np, "mtd-mac-address", &size);
-+ if (!list || (size != (2 * sizeof(*list))))
-+ return -ENOENT;
-+
-+ phandle = be32_to_cpup(list++);
-+ if (phandle)
-+ mtd_np = of_find_node_by_phandle(phandle);
-+
-+ if (!mtd_np)
-+ return -ENOENT;
-+
-+ part = of_get_property(mtd_np, "label", NULL);
-+ if (!part)
-+ part = mtd_np->name;
-+
-+ mtd = get_mtd_device_nm(part);
-+ if (IS_ERR(mtd))
-+ return PTR_ERR(mtd);
-+
-+ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, (u_char *) mac);
-+ put_mtd_device(mtd);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(of_get_mac_address_mtd);
---- a/include/linux/of_net.h
-+++ b/include/linux/of_net.h
-@@ -11,6 +11,7 @@
- #include <linux/of.h>
- extern int of_get_phy_mode(struct device_node *np);
- extern const void *of_get_mac_address(struct device_node *np);
-+extern int of_get_mac_address_mtd(struct device_node *np, void *mac);
- #else
- static inline int of_get_phy_mode(struct device_node *np)
- {
+++ /dev/null
-From c55d6cf3e2c593bf7d228c6532ec9bd8da82e09d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Apr 2013 23:20:03 +0200
-Subject: [PATCH 35/57] NET: MIPS: add ralink SoC ethernet driver
-
-Add support for Ralink FE and ESW.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -199,6 +199,7 @@ void __init ralink_clk_init(void)
- }
-
- ralink_clk_add("cpu", cpu_rate);
-+ ralink_clk_add("sys", sys_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000100.timer", wdt_rate);
- ralink_clk_add("10000120.watchdog", wdt_rate);
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -134,6 +134,7 @@ config ETHOC
- source "drivers/net/ethernet/packetengines/Kconfig"
- source "drivers/net/ethernet/pasemi/Kconfig"
- source "drivers/net/ethernet/qlogic/Kconfig"
-+source "drivers/net/ethernet/ralink/Kconfig"
- source "drivers/net/ethernet/realtek/Kconfig"
- source "drivers/net/ethernet/renesas/Kconfig"
- source "drivers/net/ethernet/rdc/Kconfig"
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -56,6 +56,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
- obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
- obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
- obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
-+obj-$(CONFIG_NET_RALINK) += ralink/
- obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
- obj-$(CONFIG_SH_ETH) += renesas/
- obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
+++ /dev/null
-From 900fa0abfea0cb7562c523769981dadc25f1f8cd Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:43:42 +0100
-Subject: [PATCH 37/57] USB: phy: add ralink SoC driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/usb/phy/Kconfig | 8 ++
- drivers/usb/phy/Makefile | 1 +
- drivers/usb/phy/ralink-phy.c | 190 ++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 199 insertions(+)
- create mode 100644 drivers/usb/phy/ralink-phy.c
-
---- a/drivers/usb/phy/Kconfig
-+++ b/drivers/usb/phy/Kconfig
-@@ -251,6 +251,14 @@ config USB_RCAR_GEN2_PHY
- To compile this driver as a module, choose M here: the
- module will be called phy-rcar-gen2-usb.
-
-+config RALINK_USBPHY
-+ bool "Ralink USB PHY controller Driver"
-+ depends on MIPS && RALINK
-+ select USB_PHY
-+ help
-+ Enable this to support ralink USB phy controller for ralink
-+ SoCs.
-+
- config USB_ULPI
- bool "Generic ULPI Transceiver Driver"
- depends on ARM
---- a/drivers/usb/phy/Makefile
-+++ b/drivers/usb/phy/Makefile
-@@ -33,3 +33,4 @@ obj-$(CONFIG_USB_RCAR_GEN2_PHY) += phy-
- obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
- obj-$(CONFIG_USB_ULPI_VIEWPORT) += phy-ulpi-viewport.o
- obj-$(CONFIG_KEYSTONE_USB_PHY) += phy-keystone.o
-+obj-$(CONFIG_RALINK_USBPHY) += ralink-phy.o
---- /dev/null
-+++ b/drivers/usb/phy/ralink-phy.c
-@@ -0,0 +1,193 @@
-+/*
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ *
-+ * based on: Renesas R-Car USB phy driver
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/usb/otg.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+#include <linux/spinlock.h>
-+#include <linux/module.h>
-+#include <linux/reset.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define RT_SYSC_REG_SYSCFG1 0x014
-+#define RT_SYSC_REG_CLKCFG1 0x030
-+#define RT_SYSC_REG_USB_PHY_CFG 0x05c
-+
-+#define RT_RSTCTRL_UDEV BIT(25)
-+#define RT_RSTCTRL_UHST BIT(22)
-+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
-+
-+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
-+#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
-+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
-+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
-+
-+#define USB_PHY_UTMI_8B60M BIT(1)
-+#define UDEV_WAKEUP BIT(0)
-+
-+static atomic_t usb_pwr_ref = ATOMIC_INIT(0);
-+static struct reset_control *rstdev;
-+static struct reset_control *rsthost;
-+static u32 phy_clk;
-+
-+static void usb_phy_enable(int state)
-+{
-+ if (state)
-+ rt_sysc_m32(0, phy_clk, RT_SYSC_REG_CLKCFG1);
-+ else
-+ rt_sysc_m32(phy_clk, 0, RT_SYSC_REG_CLKCFG1);
-+ mdelay(100);
-+}
-+
-+static int usb_power_on(struct usb_phy *phy)
-+{
-+ if (atomic_inc_return(&usb_pwr_ref) == 1) {
-+ u32 t;
-+
-+ usb_phy_enable(1);
-+
-+// reset_control_assert(rstdev);
-+// reset_control_assert(rsthost);
-+
-+ if (OTG_STATE_B_HOST) {
-+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
-+ if (!IS_ERR(rsthost))
-+ reset_control_deassert(rsthost);
-+ if (!IS_ERR(rstdev))
-+ reset_control_deassert(rstdev);
-+ } else {
-+ rt_sysc_m32(RT_SYSCFG1_USB0_HOST_MODE, 0, RT_SYSC_REG_SYSCFG1);
-+ if (!IS_ERR(rstdev))
-+ reset_control_deassert(rstdev);
-+ }
-+ mdelay(100);
-+
-+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
-+ dev_info(phy->dev, "remote usb device wakeup %s\n",
-+ (t & UDEV_WAKEUP) ? ("enabbled") : ("disabled"));
-+ if (t & USB_PHY_UTMI_8B60M)
-+ dev_info(phy->dev, "UTMI 8bit 60MHz\n");
-+ else
-+ dev_info(phy->dev, "UTMI 16bit 30MHz\n");
-+ }
-+
-+ return 0;
-+}
-+
-+static void usb_power_off(struct usb_phy *phy)
-+{
-+ if (atomic_dec_return(&usb_pwr_ref) == 0) {
-+ usb_phy_enable(0);
-+ if (!IS_ERR(rstdev))
-+ reset_control_assert(rstdev);
-+ if (!IS_ERR(rsthost))
-+ reset_control_assert(rsthost);
-+ }
-+}
-+
-+static int usb_set_host(struct usb_otg *otg, struct usb_bus *host)
-+{
-+ otg->gadget = NULL;
-+ otg->host = host;
-+
-+ return 0;
-+}
-+
-+static int usb_set_peripheral(struct usb_otg *otg,
-+ struct usb_gadget *gadget)
-+{
-+ otg->host = NULL;
-+ otg->gadget = gadget;
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id ralink_usbphy_dt_match[] = {
-+ { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) },
-+ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN | MT7620_CLKCFG1_UPHY0_CLK_EN) },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, ralink_usbphy_dt_match);
-+
-+static int usb_phy_probe(struct platform_device *pdev)
-+{
-+ const struct of_device_id *match;
-+ struct device *dev = &pdev->dev;
-+ struct usb_otg *otg;
-+ struct usb_phy *phy;
-+ int ret;
-+
-+ match = of_match_device(ralink_usbphy_dt_match, &pdev->dev);
-+ phy_clk = (int) match->data;
-+
-+ rsthost = devm_reset_control_get(&pdev->dev, "host");
-+ rstdev = devm_reset_control_get(&pdev->dev, "device");
-+
-+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
-+ if (!phy) {
-+ dev_err(&pdev->dev, "unable to allocate memory for USB PHY\n");
-+ return -ENOMEM;
-+ }
-+
-+ otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
-+ if (!otg) {
-+ dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
-+ return -ENOMEM;
-+ }
-+
-+ phy->dev = dev;
-+ phy->label = dev_name(dev);
-+ phy->init = usb_power_on;
-+ phy->shutdown = usb_power_off;
-+ otg->set_host = usb_set_host;
-+ otg->set_peripheral = usb_set_peripheral;
-+ otg->phy = phy;
-+ phy->otg = otg;
-+ ret = usb_add_phy(phy, USB_PHY_TYPE_USB2);
-+
-+ if (ret < 0) {
-+ dev_err(dev, "usb phy addition error\n");
-+ return ret;
-+ }
-+
-+ platform_set_drvdata(pdev, phy);
-+
-+ dev_info(&pdev->dev, "loaded\n");
-+
-+ return ret;
-+}
-+
-+static int usb_phy_remove(struct platform_device *pdev)
-+{
-+ struct usb_phy *phy = platform_get_drvdata(pdev);
-+
-+ usb_remove_phy(phy);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver usb_phy_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "rt3xxx-usbphy",
-+ .of_match_table = of_match_ptr(ralink_usbphy_dt_match),
-+ },
-+ .probe = usb_phy_probe,
-+ .remove = usb_phy_remove,
-+};
-+
-+module_platform_driver(usb_phy_driver);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_DESCRIPTION("Ralink USB phy");
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+++ /dev/null
-From ffb27de4760595c356ef619c97f25722c8db28e7 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:49:07 +0100
-Subject: [PATCH 38/57] USB: add OHCI/EHCI OF binding
-
-based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/usb/Makefile | 3 ++-
- drivers/usb/host/ehci-platform.c | 21 +++++++++++++++++----
- drivers/usb/host/ohci-platform.c | 37 +++++++++++++++++++++++++++++++------
- 3 files changed, 50 insertions(+), 11 deletions(-)
-
---- a/drivers/usb/Makefile
-+++ b/drivers/usb/Makefile
-@@ -11,6 +11,8 @@ obj-$(CONFIG_USB_DWC2) += dwc2/
-
- obj-$(CONFIG_USB_MON) += mon/
-
-+obj-$(CONFIG_USB_PHY) += phy/
-+
- obj-$(CONFIG_PCI) += host/
- obj-$(CONFIG_USB_EHCI_HCD) += host/
- obj-$(CONFIG_USB_ISP116X_HCD) += host/
-@@ -41,7 +43,6 @@ obj-$(CONFIG_USB_TMC) += class/
- obj-$(CONFIG_USB_STORAGE) += storage/
- obj-$(CONFIG_USB) += storage/
-
--obj-$(CONFIG_USB_MDC800) += image/
- obj-$(CONFIG_USB_MICROTEK) += image/
-
- obj-$(CONFIG_USB_SERIAL) += serial/
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -29,6 +29,8 @@
- #include <linux/usb.h>
- #include <linux/usb/hcd.h>
- #include <linux/usb/ehci_pdriver.h>
-+#include <linux/usb/phy.h>
-+#include <linux/usb/otg.h>
-
- #include "ehci.h"
-
-@@ -124,6 +126,15 @@ static int ehci_platform_probe(struct pl
- hcd->rsrc_start = res_mem->start;
- hcd->rsrc_len = resource_size(res_mem);
-
-+#ifdef CONFIG_USB_PHY
-+ hcd->phy = devm_usb_get_phy(&dev->dev, USB_PHY_TYPE_USB2);
-+ if (!IS_ERR_OR_NULL(hcd->phy)) {
-+ otg_set_host(hcd->phy->otg,
-+ &hcd->self);
-+ usb_phy_init(hcd->phy);
-+ }
-+#endif
-+
- hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
- if (IS_ERR(hcd->regs)) {
- err = PTR_ERR(hcd->regs);
-@@ -161,6 +172,9 @@ static int ehci_platform_remove(struct p
- if (pdata == &ehci_platform_defaults)
- dev->dev.platform_data = NULL;
-
-+ if (pdata == &ehci_platform_defaults)
-+ dev->dev.platform_data = NULL;
-+
- return 0;
- }
-
-@@ -205,9 +219,8 @@ static int ehci_platform_resume(struct d
- #define ehci_platform_resume NULL
- #endif /* CONFIG_PM */
-
--static const struct of_device_id vt8500_ehci_ids[] = {
-- { .compatible = "via,vt8500-ehci", },
-- { .compatible = "wm,prizm-ehci", },
-+static const struct of_device_id ralink_ehci_ids[] = {
-+ { .compatible = "ralink,rt3xxx-ehci", },
- {}
- };
-
-@@ -231,7 +244,7 @@ static struct platform_driver ehci_platf
- .owner = THIS_MODULE,
- .name = "ehci-platform",
- .pm = &ehci_platform_pm_ops,
-- .of_match_table = vt8500_ehci_ids,
-+ .of_match_table = ralink_ehci_ids,
- }
- };
-
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -22,18 +22,22 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ohci_pdriver.h>
- #include <linux/usb.h>
-+#include <linux/usb/phy.h>
- #include <linux/usb/hcd.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/of.h>
-
- #include "ohci.h"
-
- #define DRIVER_DESC "OHCI generic platform driver"
-
-+static struct usb_ohci_pdata ohci_platform_defaults;
- static const char hcd_name[] = "ohci-platform";
-
- static int ohci_platform_reset(struct usb_hcd *hcd)
- {
- struct platform_device *pdev = to_platform_device(hcd->self.controller);
-- struct usb_ohci_pdata *pdata = dev_get_platdata(&pdev->dev);
-+ struct usb_ohci_pdata *pdata = dev_get_platdata(&pdev->dev);;
- struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-
- if (pdata->big_endian_desc)
-@@ -63,11 +67,18 @@ static int ohci_platform_probe(struct pl
- int irq;
- int err = -ENOMEM;
-
-- if (!pdata) {
-- WARN_ON(1);
-- return -ENODEV;
-- }
-+ /*
-+ * use reasonable defaults so platforms don't have to provide these.
-+ * with DT probing on ARM, none of these are set.
-+ */
-+ if (!dev->dev.platform_data)
-+ dev->dev.platform_data = &ohci_platform_defaults;
-+ if (!dev->dev.dma_mask)
-+ dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
-+ if (!dev->dev.coherent_dma_mask)
-+ dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
-+ pdata = dev->dev.platform_data;
- if (usb_disabled())
- return -ENODEV;
-
-@@ -99,6 +110,12 @@ static int ohci_platform_probe(struct pl
- hcd->rsrc_start = res_mem->start;
- hcd->rsrc_len = resource_size(res_mem);
-
-+#ifdef CONFIG_USB_PHY
-+ hcd->phy = devm_usb_get_phy(&dev->dev, USB_PHY_TYPE_USB2);
-+ if (!IS_ERR_OR_NULL(hcd->phy))
-+ usb_phy_init(hcd->phy);
-+#endif
-+
- hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
- if (IS_ERR(hcd->regs)) {
- err = PTR_ERR(hcd->regs);
-@@ -134,6 +151,9 @@ static int ohci_platform_remove(struct p
- if (pdata->power_off)
- pdata->power_off(dev);
-
-+ if (pdata == &ohci_platform_defaults)
-+ dev->dev.platform_data = NULL;
-+
- return 0;
- }
-
-@@ -180,6 +200,11 @@ static int ohci_platform_resume(struct d
- #define ohci_platform_resume NULL
- #endif /* CONFIG_PM */
-
-+static const struct of_device_id ralink_ohci_ids[] = {
-+ { .compatible = "ralink,rt3xxx-ohci", },
-+ {}
-+};
-+
- static const struct platform_device_id ohci_platform_table[] = {
- { "ohci-platform", 0 },
- { }
-@@ -200,6 +225,7 @@ static struct platform_driver ohci_platf
- .owner = THIS_MODULE,
- .name = "ohci-platform",
- .pm = &ohci_platform_pm_ops,
-+ .of_match_table = of_match_ptr(ralink_ohci_ids),
- }
- };
-
+++ /dev/null
-From 023e31c036fef5daf7711878590e0930544b5ad7 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 11:10:49 +0100
-Subject: [PATCH 40/57] USB: add mt7621 xhci support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/usb/core/hcd-pci.c | 6 +-
- drivers/usb/core/hub.c | 2 +-
- drivers/usb/core/port.c | 3 +-
- drivers/usb/host/Kconfig | 8 +-
- drivers/usb/host/Makefile | 8 +
- drivers/usb/host/mtk-phy-7621.c | 445 +++++
- drivers/usb/host/mtk-phy-7621.h | 2871 +++++++++++++++++++++++++++++++++
- drivers/usb/host/mtk-phy-ahb.c | 58 +
- drivers/usb/host/mtk-phy.c | 102 ++
- drivers/usb/host/mtk-phy.h | 179 ++
- drivers/usb/host/pci-quirks.h | 2 +-
- drivers/usb/host/xhci-dbg.c | 3 +
- drivers/usb/host/xhci-mem.c | 11 +
- drivers/usb/host/xhci-mtk-power.c | 115 ++
- drivers/usb/host/xhci-mtk-power.h | 13 +
- drivers/usb/host/xhci-mtk-scheduler.c | 608 +++++++
- drivers/usb/host/xhci-mtk-scheduler.h | 77 +
- drivers/usb/host/xhci-mtk.c | 265 +++
- drivers/usb/host/xhci-mtk.h | 120 ++
- drivers/usb/host/xhci-plat.c | 18 +
- drivers/usb/host/xhci-ring.c | 109 +-
- drivers/usb/host/xhci.c | 201 ++-
- drivers/usb/host/xhci.h | 23 +-
- 23 files changed, 5234 insertions(+), 13 deletions(-)
- create mode 100644 drivers/usb/host/mtk-phy-7621.c
- create mode 100644 drivers/usb/host/mtk-phy-7621.h
- create mode 100644 drivers/usb/host/mtk-phy-ahb.c
- create mode 100644 drivers/usb/host/mtk-phy.c
- create mode 100644 drivers/usb/host/mtk-phy.h
- create mode 100644 drivers/usb/host/xhci-mtk-power.c
- create mode 100644 drivers/usb/host/xhci-mtk-power.h
- create mode 100644 drivers/usb/host/xhci-mtk-scheduler.c
- create mode 100644 drivers/usb/host/xhci-mtk-scheduler.h
- create mode 100644 drivers/usb/host/xhci-mtk.c
- create mode 100644 drivers/usb/host/xhci-mtk.h
-
---- a/drivers/usb/core/hcd-pci.c
-+++ b/drivers/usb/core/hcd-pci.c
-@@ -215,9 +215,13 @@ int usb_hcd_pci_probe(struct pci_dev *de
- goto disable_pci;
- }
-
-+
-+#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
-+ hcd->amd_resume_bug = 0;
-+#else
- hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
- driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
--
-+#endif
- if (driver->flags & HCD_MEMORY) {
- /* EHCI, OHCI */
- hcd->rsrc_start = pci_resource_start(dev, 0);
---- a/drivers/usb/core/hub.c
-+++ b/drivers/usb/core/hub.c
-@@ -1270,7 +1270,7 @@ static void hub_quiesce(struct usb_hub *
- if (type != HUB_SUSPEND) {
- /* Disconnect all the children */
- for (i = 0; i < hdev->maxchild; ++i) {
-- if (hub->ports[i]->child)
-+ if (hub->ports[i] && hub->ports[i]->child)
- usb_disconnect(&hub->ports[i]->child);
- }
- }
---- a/drivers/usb/core/port.c
-+++ b/drivers/usb/core/port.c
-@@ -191,6 +191,7 @@ exit:
- void usb_hub_remove_port_device(struct usb_hub *hub,
- int port1)
- {
-- device_unregister(&hub->ports[port1 - 1]->dev);
-+ if (hub->ports[port1 - 1])
-+ device_unregister(&hub->ports[port1 - 1]->dev);
- }
-
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -27,7 +27,13 @@ config USB_XHCI_HCD
- if USB_XHCI_HCD
-
- config USB_XHCI_PLATFORM
-- tristate
-+ bool "xHCI platform"
-+ depends on SOC_MT7621
-+
-+config USB_MT7621_XHCI_PLATFORM
-+ bool "MTK MT7621 xHCI"
-+ depends on USB_XHCI_PLATFORM
-+ depends on SOC_MT7621
-
- endif # USB_XHCI_HCD
-
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -15,7 +15,13 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
- xhci-hcd-y := xhci.o xhci-mem.o
- xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
- xhci-hcd-y += xhci-trace.o
-+ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
- xhci-hcd-$(CONFIG_PCI) += xhci-pci.o
-+endif
-+
-+ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
-+xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
-+endif
-
- ifneq ($(CONFIG_USB_XHCI_PLATFORM), )
- xhci-hcd-y += xhci-plat.o
-@@ -23,7 +29,9 @@ endif
-
- obj-$(CONFIG_USB_WHCI_HCD) += whci/
-
-+ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
- obj-$(CONFIG_PCI) += pci-quirks.o
-+endif
-
- obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
- obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
---- /dev/null
-+++ b/drivers/usb/host/mtk-phy-7621.c
-@@ -0,0 +1,445 @@
-+#include "mtk-phy.h"
-+
-+#ifdef CONFIG_PROJECT_7621
-+#include "mtk-phy-7621.h"
-+
-+//not used on SoC
-+PHY_INT32 phy_init(struct u3phy_info *info){
-+ return PHY_TRUE;
-+}
-+
-+//not used on SoC
-+PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
-+ return PHY_TRUE;
-+}
-+
-+//--------------------------------------------------------
-+// Function : fgEyeScanHelper_CheckPtInRegion()
-+// Description : Check if the test point is in a rectangle region.
-+// If it is in the rectangle, also check if this point
-+// is on the multiple of deltaX and deltaY.
-+// Parameter : strucScanRegion * prEye - the region
-+// BYTE bX
-+// BYTE bY
-+// Return : BYTE - TRUE : This point needs to be tested
-+// FALSE: This point will be omitted
-+// Note : First check within the rectangle.
-+// Secondly, use modulous to check if the point will be tested.
-+//--------------------------------------------------------
-+static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
-+{
-+ PHY_INT8 fgValid = true;
-+
-+
-+ /// Be careful, the axis origin is on the TOP-LEFT corner.
-+ /// Therefore the top-left point has the minimum X and Y
-+ /// Botton-right point is the maximum X and Y
-+ if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
-+ && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
-+ {
-+ // With the region, now check whether or not the input test point is
-+ // on the multiples of X and Y
-+ // Do not have to worry about negative value, because we have already
-+ // check the input bX, and bY is within the region.
-+ if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
-+ || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
-+ {
-+ // if the division will have remainder, that means
-+ // the input test point is on the multiples of X and Y
-+ fgValid = false;
-+ }
-+ else
-+ {
-+ }
-+ }
-+ else
-+ {
-+
-+ fgValid = false;
-+ }
-+ return fgValid;
-+}
-+
-+//--------------------------------------------------------
-+// Function : EyeScanHelper_RunTest()
-+// Description : Enable the test, and wait til it is completed
-+// Parameter : None
-+// Return : None
-+// Note : None
-+//--------------------------------------------------------
-+static void EyeScanHelper_RunTest(struct u3phy_info *info)
-+{
-+ DRV_UDELAY(100);
-+ // Disable the test
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
-+ DRV_UDELAY(100);
-+ // Run the test
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
-+ DRV_UDELAY(100);
-+ // Wait til it's done
-+ //RGS_SSUSB_RX_EYE_CNT_RDY
-+ while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
-+ , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
-+}
-+
-+//--------------------------------------------------------
-+// Function : fgEyeScanHelper_CalNextPoint()
-+// Description : Calcualte the test point for the measurement
-+// Parameter : None
-+// Return : BOOL - TRUE : the next point is within the
-+// boundaryof HW limit
-+// FALSE: the next point is out of the HW limit
-+// Note : The next point is obtained by calculating
-+// from the bottom left of the region rectangle
-+// and then scanning up until it reaches the upper
-+// limit. At this time, the x will increment, and
-+// start scanning downwards until the y hits the
-+// zero.
-+//--------------------------------------------------------
-+static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
-+{
-+ if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
-+ || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
-+ )
-+ {
-+ /// Reaches the limit of Y axis
-+ /// Increment X
-+ _bXcurr++;
-+ _fgXChged = true;
-+ _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
-+
-+ if (_bXcurr > MAX_X)
-+ {
-+ return false;
-+ }
-+ }
-+ else
-+ {
-+ _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
-+ _fgXChged = false;
-+ }
-+ return PHY_TRUE;
-+}
-+
-+PHY_INT32 eyescan_init(struct u3phy_info *info){
-+ //initial PHY setting
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
-+ , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
-+ , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
-+ return PHY_TRUE;
-+}
-+
-+PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
-+ , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
-+ PHY_INT32 cOfst = 0;
-+ PHY_UINT8 bIdxX = 0;
-+ PHY_UINT8 bIdxY = 0;
-+ //PHY_INT8 bCnt = 0;
-+ PHY_UINT8 bIdxCycCnt = 0;
-+ PHY_INT8 fgValid;
-+ PHY_INT8 cX;
-+ PHY_INT8 cY;
-+ PHY_UINT8 bExtendCnt;
-+ PHY_INT8 isContinue;
-+ //PHY_INT8 isBreak;
-+ PHY_UINT32 wErr0 = 0, wErr1 = 0;
-+ //PHY_UINT32 temp;
-+
-+ PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-+ PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-+
-+ _rEye1.bX_tl = x_t1;
-+ _rEye1.bY_tl = y_t1;
-+ _rEye1.bX_br = x_br;
-+ _rEye1.bY_br = y_br;
-+ _rEye1.bDeltaX = delta_x;
-+ _rEye1.bDeltaY = delta_y;
-+
-+ _rEye2.bX_tl = x_t1;
-+ _rEye2.bY_tl = y_t1;
-+ _rEye2.bX_br = x_br;
-+ _rEye2.bY_br = y_br;
-+ _rEye2.bDeltaX = delta_x;
-+ _rEye2.bDeltaY = delta_y;
-+
-+ _rTestCycle.wEyeCnt = eye_cnt;
-+ _rTestCycle.bNumOfEyeCnt = num_cnt;
-+ _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
-+ _rTestCycle.bPICalEn = PI_cal_en;
-+
-+ _bXcurr = 0;
-+ _bYcurr = 0;
-+ _eScanDir = SCAN_DN;
-+ _fgXChged = false;
-+
-+ printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
-+ eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
-+ x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
-+
-+ //force SIGDET to OFF
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
-+ , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
-+
-+ // RX_TRI_DET_EN to Disable
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
-+ , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
-+
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
-+
-+
-+ if (PI_cal_en){
-+ // PI Calibration
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
-+
-+ DRV_UDELAY(20);
-+
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
-+ _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
-+ , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
-+
-+ printk(KERN_ERR "PI result: %d\n", _bPIResult);
-+ }
-+ // Read Initial DAC
-+ // Set CYCLE
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
-+ ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
-+
-+ // Eye Monitor Feature
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
-+ , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
-+
-+ // Move X,Y to the top-left corner
-+ for (cOfst = 0; cOfst >= -64; cOfst--)
-+ {
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
-+ }
-+ for (cOfst = 0; cOfst < 64; cOfst++)
-+ {
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
-+ }
-+ //ClearErrorResult
-+ for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
-+ for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
-+ {
-+ for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
-+ pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
-+ pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
-+ }
-+ }
-+ }
-+ isContinue = true;
-+ while(isContinue){
-+ //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
-+ // The point is within the boundary, then let's check if it is within
-+ // the testing region.
-+ // The point is only test-able if one of the eye region
-+ // includes this point.
-+ fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
-+ || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
-+ // Translate bX and bY to 2's complement from where the origin was on the
-+ // top left corner.
-+ // 0x40 and 0x3F needs a bit of thinking!!!! >"<
-+ cX = (_bXcurr ^ 0x40);
-+ cY = (_bYcurr ^ 0x3F);
-+
-+ // Set X if necessary
-+ if (_fgXChged == true)
-+ {
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
-+ }
-+ // Set Y
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
-+
-+ /// Test this point!
-+ if (fgValid){
-+ for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
-+ {
-+ //run test
-+ EyeScanHelper_RunTest(info);
-+ }
-+ for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
-+ {
-+ EyeScanHelper_RunTest(info);
-+ wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
-+ , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
-+ wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
-+ , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
-+
-+ pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
-+ pwErrCnt1[bExtendCnt][_bXcurr][_bYc
projects / openwrt.git / commitdiff