+++ /dev/null
-/*
- * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_RALINK_COMMON_H
-#define __ASM_MACH_RALINK_COMMON_H
-
-#define RAMIPS_SYS_TYPE_LEN 64
-extern unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN];
-extern unsigned long ramips_mem_base;
-extern unsigned long ramips_mem_size_min;
-extern unsigned long ramips_mem_size_max;
-extern unsigned long (*ramips_get_mem_size)(void);
-
-void ramips_intc_irq_init(unsigned intc_base, unsigned irq, unsigned irq_base);
-u32 ramips_intc_get_status(void);
-
-void ramips_soc_prom_init(void);
-void ramips_soc_setup(void);
-void ramips_early_serial_setup(int line, unsigned base, unsigned freq,
- unsigned irq);
-
-#endif /* __ASM_MACH_RALINK_COMMON_H */
+++ /dev/null
-/*
- * Ralink SoC GPIO button support
- *
- * Copyright (C) 2010-2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H
-#define __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H
-
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-#ifdef CONFIG_RALINK_DEV_GPIO_BUTTONS
-void
-ramips_register_gpio_buttons(int id, unsigned poll_interval, unsigned nbuttons,
- struct gpio_keys_button *buttons);
-#else
-static inline void
-ramips_register_gpio_buttons(int id, unsigned poll_interval, unsigned nbuttons,
- struct gpio_keys_button *buttons)
-{
-}
-#endif
-
-#endif /* __ASM_MACH_RALINK_DEV_GPIO_BUTTONS_H */
+++ /dev/null
-/*
- * Ralink SoC GPIO LED device support
- *
- * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_RALINK_DEV_GPIO_LEDS_H
-#define __ASM_MACH_RALINK_DEV_GPIO_LEDS_H
-
-#include <linux/leds.h>
-
-#ifdef CONFIG_RALINK_DEV_GPIO_LEDS
-void ramips_register_gpio_leds(int id, unsigned num_leds,
- struct gpio_led *leds);
-#else
-static inline void ramips_register_gpio_leds(int id, unsigned num_leds,
- struct gpio_led *leds)
-{
-}
-#endif
-
-#endif /* __ASM_MACH_RALINK_DEV_GPIO_LEDS_H */
+++ /dev/null
-/*
- * Ralink SoC GPIO API support
- *
- * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_MACH_RALINK_GPIO_H
-#define __ASM_MACH_RALINK_GPIO_H
-
-#define ARCH_NR_GPIOS 128
-#include <asm-generic/gpio.h>
-
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-#define gpio_cansleep __gpio_cansleep
-#define gpio_to_irq __gpio_to_irq
-
-#endif /* __ASM_MACH_RALINK_GPIO_H */
+++ /dev/null
-/*
- * Ralink machine types
- *
- * Copyright (C) 2010 Joonas Lahtinen <joonas.lahtinen@gmail.com>
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <asm/mips_machine.h>
-
-enum ramips_mach_type {
- RAMIPS_MACH_GENERIC,
- /* RT2880 based machines */
- RAMIPS_MACH_F5D8235_V1, /* Belkin F5D8235 v1 */
- RAMIPS_MACH_BR6524N, /* Edimax BR6524N */
- RAMIPS_MACH_RT_N15, /* Asus RT-N15 */
- RAMIPS_MACH_V11ST_FE, /* Ralink V11ST-FE */
- RAMIPS_MACH_WLI_TX4_AG300N, /* Buffalo WLI-TX4-AG300N */
- RAMIPS_MACH_WZR_AGL300NH, /* Buffalo WZR-AGL300NH */
-
- /* RT3050 based machines */
- RAMIPS_MACH_3G_6200N, /* Edimax 3G-6200N */
- RAMIPS_MACH_ALL0256N, /* Allnet ALL0256N */
- RAMIPS_MACH_CARAMBOLA, /* 8devices Carambola */
- RAMIPS_MACH_DIR_300_B1, /* D-Link DIR-300 B1 */
- RAMIPS_MACH_DIR_600_B1, /* D-Link DIR-600 B1 */
- RAMIPS_MACH_DIR_600_B2, /* D-Link DIR-600 B2 */
- RAMIPS_MACH_DIR_615_D, /* D-Link DIR-615 D */
- RAMIPS_MACH_DIR_620_A1, /* D-Link DIR-620 A1 */
- RAMIPS_MACH_RT_G32_B1, /* Asus RT-G32 B1 */
- RAMIPS_MACH_RT_N10_PLUS, /* Asus RT-N10+ */
- RAMIPS_MACH_NW718, /* Netcore NW718 */
- RAMIPS_MACH_WL_330N, /* Asus WL-330N */
- RAMIPS_MACH_WL_330N3G, /* Asus WL-330N3G */
-
- /* RT3052 based machines */
- RAMIPS_MACH_3G300M, /* Tenda 3G300M */
- RAMIPS_MACH_ALL0239_3G, /* ALL0239-3G */
- RAMIPS_MACH_ARGUS_ATP52B, /* Argus ATP-52B */
- RAMIPS_MACH_BC2, /* NexAira BC2 */
- RAMIPS_MACH_BR6425, /* Edimax BR-6425 */
- RAMIPS_MACH_BROADWAY, /* Hauppauge Broadway */
- RAMIPS_MACH_DAP_1350, /* D-Link DAP-1350 */
- RAMIPS_MACH_ESR_9753, /* Senao / EnGenius ESR-9753*/
- RAMIPS_MACH_F5D8235_V2, /* Belkin F5D8235 v2 */
- RAMIPS_MACH_FONERA20N, /* La Fonera 2.0N */
- RAMIPS_MACH_RT_N13U, /* ASUS RT-N13U */
- RAMIPS_MACH_FREESTATION5, /* ARC Freestation5 */
- RAMIPS_MACH_HW550_3G, /* Aztech HW550-3G */
- RAMIPS_MACH_MOFI3500_3GN, /* MoFi Network MOFI3500-3GN */
- RAMIPS_MACH_NBG_419N, /* ZyXEL NBG-419N */
- RAMIPS_MACH_OMNI_EMB, /* Omnima MiniEMBWiFi */
- RAMIPS_MACH_PSR_680W, /* Petatel PSR-680W Wireless 3G Router*/
- RAMIPS_MACH_PWH2004, /* Prolink 2004H / Abocom 5205 */
- RAMIPS_MACH_SL_R7205, /* Skylink SL-R7205 Wireless 3G Router*/
- RAMIPS_MACH_V22RW_2X2, /* Ralink AP-RT3052-V22RW-2X2 */
- RAMIPS_MACH_W306R_V20, /* Tenda W306R_V20 */
- RAMIPS_MACH_W502U, /* ALFA Networks W502U */
- RAMIPS_MACH_WCR150GN, /* Sparklan WCR-150GN */
- RAMIPS_MACH_WHR_G300N, /* Buffalo WHR-G300N */
- RAMIPS_MACH_WL341V3, /* Sitecom WL-341 v3 */
- RAMIPS_MACH_WL351, /* Sitecom WL-351 v1 002 */
- RAMIPS_MACH_WR512_3GN, /* SH-WR512NU/WS-WR512N1-like 3GN*/
- RAMIPS_MACH_WR6202, /* Accton WR6202 */
- RAMIPS_MACH_MZKW300NH2, /* Planex MZK-W300NH2 Router */
- RAMIPS_MACH_XDXRN502J, /* unknown XDX-RN502J */
- RAMIPS_MACH_UR_326N4G, /* UPVEL ROUTER */
- RAMIPS_MACH_UR_336UN, /* UPVEL ROUTER */
-
- /* RT3352 based machines */
- RAMIPS_MACH_ALL5002, /* Allnet ALL5002 */
- RAMIPS_MACH_DIR_615_H1,
-
- /* RT3662 based machines */
- RAMIPS_MACH_DIR_645, /* D-Link DIR-645 */
- RAMIPS_MACH_OMNI_EMB_HPM, /* Omnima EMB HPM */
- RAMIPS_MACH_RT_N56U, /* Asus RT-N56U */
-
- /* RT3883 based machines */
- RAMIPS_MACH_TEW_691GR, /* TRENDnet TEW-691GR */
- RAMIPS_MACH_TEW_692GR, /* TRENDnet TEW-692GR */
-
- /* RT5350 based machines */
- RAMIPS_MACH_AIR3GII, /* AirLive Air3GII */
-};
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * based on Ralink SDK3.3
- * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
- */
-
-#ifndef _RAMIPS_ETH_PLATFORM_H
-#define _RAMIPS_ETH_PLATFORM_H
-
-#include <linux/phy.h>
-
-struct ramips_eth_platform_data
-{
- unsigned char mac[6];
- void (*reset_fe)(void);
- int min_pkt_len;
- unsigned long sys_freq;
-
- int speed;
- int duplex;
- int tx_fc;
- int rx_fc;
-
- u32 phy_mask;
- phy_interface_t phy_if_mode;
-};
-
-#endif /* _RAMIPS_ETH_PLATFORM_H */
-
+++ /dev/null
-/*
- * Ralink SoC specific GPIO support
- *
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RAMIPS_GPIO_H
-#define _RAMIPS_GPIO_H
-
-#include <linux/gpio.h>
-#include <linux/spinlock.h>
-
-enum ramips_gpio_reg {
- RAMIPS_GPIO_REG_INT = 0, /* Interrupt status */
- RAMIPS_GPIO_REG_EDGE,
- RAMIPS_GPIO_REG_RENA,
- RAMIPS_GPIO_REG_FENA,
- RAMIPS_GPIO_REG_DATA,
- RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */
- RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */
- RAMIPS_GPIO_REG_SET,
- RAMIPS_GPIO_REG_RESET,
- RAMIPS_GPIO_REG_TOGGLE,
- RAMIPS_GPIO_REG_MAX
-};
-
-struct ramips_gpio_chip {
- struct gpio_chip chip;
- unsigned long map_base;
- unsigned long map_size;
- u8 regs[RAMIPS_GPIO_REG_MAX];
-
- spinlock_t lock;
- void __iomem *regs_base;
-};
-
-struct ramips_gpio_data {
- unsigned int num_chips;
- struct ramips_gpio_chip *chips;
-};
-
-int ramips_gpio_init(struct ramips_gpio_data *data);
-
-#endif /* _RAMIPS_GPIO_H */
+++ /dev/null
-/*
- * Platform data definition for the built-in NAND controller of the
- * Ralink RT305X/RT3662/RT3883 SoCs
- *
- * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RAMIPS_NAND_PLATFORM_H
-#define _RAMIPS_NAND_PLATFORM_H
-
-#define RAMIPS_NAND_DRIVER_NAME "ramips-nand"
-
-struct ramips_nand_platform_data {
- const char *name;
- struct mtd_partition *parts;
- int nr_parts;
-};
-
-#endif /* _RAMIPS_NAND_PLATFORM_H */
+++ /dev/null
-/*
- * Ralink RT288x SoC specific definitions
- *
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Ralink's 2.6.21 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT288X_H_
-#define _RT288X_H_
-
-#include <linux/init.h>
-#include <linux/io.h>
-
-#define RT288X_MEM_SIZE_MIN (2 * 1024 * 1024)
-#define RT288X_MEM_SIZE_MAX (128 * 1024 * 1024)
-
-#define RT288X_CPU_IRQ_BASE 0
-#define RT288X_INTC_IRQ_BASE 8
-#define RT288X_INTC_IRQ_COUNT 32
-#define RT288X_GPIO_IRQ_BASE 40
-
-#define RT288X_CPU_IRQ_INTC (RT288X_CPU_IRQ_BASE + 2)
-#define RT288X_CPU_IRQ_PCI (RT288X_CPU_IRQ_BASE + 4)
-#define RT288X_CPU_IRQ_FE (RT288X_CPU_IRQ_BASE + 5)
-#define RT288X_CPU_IRQ_WNIC (RT288X_CPU_IRQ_BASE + 6)
-#define RT288X_CPU_IRQ_COUNTER (RT288X_CPU_IRQ_BASE + 7)
-
-#define RT2880_INTC_IRQ_TIMER0 (RT288X_INTC_IRQ_BASE + 0)
-#define RT2880_INTC_IRQ_TIMER1 (RT288X_INTC_IRQ_BASE + 1)
-#define RT2880_INTC_IRQ_UART0 (RT288X_INTC_IRQ_BASE + 2)
-#define RT2880_INTC_IRQ_PIO (RT288X_INTC_IRQ_BASE + 3)
-#define RT2880_INTC_IRQ_PCM (RT288X_INTC_IRQ_BASE + 4)
-#define RT2880_INTC_IRQ_UART1 (RT288X_INTC_IRQ_BASE + 8)
-#define RT2880_INTC_IRQ_IA (RT288X_INTC_IRQ_BASE + 23)
-
-#define RT288X_GPIO_IRQ(x) (RT288X_GPIO_IRQ_BASE + (x))
-#define RT288X_GPIO_COUNT 32
-
-extern void __iomem *rt288x_sysc_base;
-extern void __iomem *rt288x_memc_base;
-
-static inline void rt288x_sysc_wr(u32 val, unsigned reg)
-{
- __raw_writel(val, rt288x_sysc_base + reg);
-}
-
-static inline u32 rt288x_sysc_rr(unsigned reg)
-{
- return __raw_readl(rt288x_sysc_base + reg);
-}
-
-static inline void rt288x_memc_wr(u32 val, unsigned reg)
-{
- __raw_writel(val, rt288x_memc_base + reg);
-}
-
-static inline u32 rt288x_memc_rr(unsigned reg)
-{
- return __raw_readl(rt288x_memc_base + reg);
-}
-
-void rt288x_gpio_init(u32 mode);
-
-#ifdef CONFIG_PCI
-int rt288x_register_pci(void);
-#else
-static inline int rt288x_register_pci(void) { return 0; }
-#endif /* CONFIG_PCI */
-
-#endif /* _RT228X_H_ */
+++ /dev/null
-/*
- * Ralink RT288x specific CPU feature overrides
- *
- * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This file was derived from: include/asm-mips/cpu-features.h
- * Copyright (C) 2003, 2004 Ralf Baechle
- * Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
-
-#define cpu_has_tlb 1
-#define cpu_has_4kex 1
-#define cpu_has_3k_cache 0
-#define cpu_has_4k_cache 1
-#define cpu_has_tx39_cache 0
-#define cpu_has_sb1_cache 0
-#define cpu_has_fpu 0
-#define cpu_has_32fpr 0
-#define cpu_has_counter 1
-#define cpu_has_watch 1
-#define cpu_has_divec 1
-
-#define cpu_has_prefetch 1
-#define cpu_has_ejtag 1
-#define cpu_has_llsc 1
-
-#define cpu_has_mips16 1
-#define cpu_has_mdmx 0
-#define cpu_has_mips3d 0
-#define cpu_has_smartmips 0
-
-#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 1
-#define cpu_has_mips64r1 0
-#define cpu_has_mips64r2 0
-
-#define cpu_has_dsp 0
-#define cpu_has_mipsmt 0
-
-#define cpu_has_64bits 0
-#define cpu_has_64bit_zero_reg 0
-#define cpu_has_64bit_gp_regs 0
-#define cpu_has_64bit_addresses 0
-
-#define cpu_dcache_line_size() 16
-#define cpu_icache_line_size() 16
-
-#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-#ifndef __ASM_MACH_RALINK_RT288X_IRQ_H
-#define __ASM_MACH_RALINK_RT288X_IRQ_H
-
-#define MIPS_CPU_IRQ_BASE 0
-#define NR_IRQS 48
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_RALINK_RT288X_IRQ_H */
+++ /dev/null
-/*
- * Ralink RT288x SoC register definitions
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT288X_REGS_H_
-#define _RT288X_REGS_H_
-
-#include <linux/bitops.h>
-
-#define RT2880_SYSC_BASE 0x00300000
-#define RT2880_TIMER_BASE 0x00300100
-#define RT2880_INTC_BASE 0x00300200
-#define RT2880_MEMC_BASE 0x00300300
-#define RT2880_UART0_BASE 0x00300500
-#define RT2880_PIO_BASE 0x00300600
-#define RT2880_I2C_BASE 0x00300900
-#define RT2880_SPI_BASE 0x00300b00
-#define RT2880_UART1_BASE 0x00300c00
-#define RT2880_FE_BASE 0x00400000
-#define RT2880_ROM_BASE 0x00410000
-#define RT2880_PCM_BASE 0x00420000
-#define RT2880_PCI_BASE 0x00440000
-#define RT2880_WMAC_BASE 0x00480000
-#define RT2880_FLASH1_BASE 0x01000000
-#define RT2880_FLASH0_BASE 0x1dc00000
-#define RT2880_SDRAM_BASE 0x08000000
-
-#define RT2880_SYSC_SIZE 0x100
-#define RT2880_TIMER_SIZE 0x100
-#define RT2880_INTC_SIZE 0x100
-#define RT2880_MEMC_SIZE 0x100
-#define RT2880_UART0_SIZE 0x100
-#define RT2880_PIO_SIZE 0x100
-#define RT2880_UART1_SIZE 0x100
-#define RT2880_FLASH1_SIZE (16 * 1024 * 1024)
-#define RT2880_FLASH0_SIZE (32 * 1024 * 1024)
-
-/* SYSC registers */
-#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
-#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
-#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
-#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
-#define SYSC_REG_CLKCFG 0x030
-#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
-#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
-#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
-#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
-#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
-
-#define CHIP_ID_ID_MASK 0xff
-#define CHIP_ID_ID_SHIFT 8
-#define CHIP_ID_REV_MASK 0xff
-
-#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
-#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
-#define SYSTEM_CONFIG_CPUCLK_250 0x0
-#define SYSTEM_CONFIG_CPUCLK_266 0x1
-#define SYSTEM_CONFIG_CPUCLK_280 0x2
-#define SYSTEM_CONFIG_CPUCLK_300 0x3
-
-#define CLKCFG_SRAM_CS_N_WDT BIT(9)
-
-#define RT2880_RESET_SYSTEM BIT(0)
-#define RT2880_RESET_TIMER BIT(1)
-#define RT2880_RESET_INTC BIT(2)
-#define RT2880_RESET_MEMC BIT(3)
-#define RT2880_RESET_CPU BIT(4)
-#define RT2880_RESET_UART0 BIT(5)
-#define RT2880_RESET_PIO BIT(6)
-#define RT2880_RESET_I2C BIT(9)
-#define RT2880_RESET_SPI BIT(11)
-#define RT2880_RESET_UART1 BIT(12)
-#define RT2880_RESET_PCI BIT(16)
-#define RT2880_RESET_WMAC BIT(17)
-#define RT2880_RESET_FE BIT(18)
-#define RT2880_RESET_PCM BIT(19)
-
-#define RT2880_GPIO_MODE_I2C BIT(0)
-#define RT2880_GPIO_MODE_UART0 BIT(1)
-#define RT2880_GPIO_MODE_SPI BIT(2)
-#define RT2880_GPIO_MODE_UART1 BIT(3)
-#define RT2880_GPIO_MODE_JTAG BIT(4)
-#define RT2880_GPIO_MODE_MDIO BIT(5)
-#define RT2880_GPIO_MODE_SDRAM BIT(6)
-#define RT2880_GPIO_MODE_PCI BIT(7)
-
-#define RT2880_INTC_INT_TIMER0 BIT(0)
-#define RT2880_INTC_INT_TIMER1 BIT(1)
-#define RT2880_INTC_INT_UART0 BIT(2)
-#define RT2880_INTC_INT_PIO BIT(3)
-#define RT2880_INTC_INT_PCM BIT(4)
-#define RT2880_INTC_INT_UART1 BIT(8)
-#define RT2880_INTC_INT_IA BIT(23)
-#define RT2880_INTC_INT_GLOBAL BIT(31)
-
-/* MEMC registers */
-#define MEMC_REG_SDRAM_CFG0 0x00
-#define MEMC_REG_SDRAM_CFG1 0x04
-#define MEMC_REG_FLASH_CFG0 0x08
-#define MEMC_REG_FLASH_CFG1 0x0c
-#define MEMC_REG_IA_ADDR 0x10
-#define MEMC_REG_IA_TYPE 0x14
-
-#define FLASH_CFG_WIDTH_SHIFT 26
-#define FLASH_CFG_WIDTH_MASK 0x3
-#define FLASH_CFG_WIDTH_8BIT 0x0
-#define FLASH_CFG_WIDTH_16BIT 0x1
-#define FLASH_CFG_WIDTH_32BIT 0x2
-
-/* UART registers */
-#define UART_REG_RX 0
-#define UART_REG_TX 1
-#define UART_REG_IER 2
-#define UART_REG_IIR 3
-#define UART_REG_FCR 4
-#define UART_REG_LCR 5
-#define UART_REG_MCR 6
-#define UART_REG_LSR 7
-
-#endif /* _RT288X_REGS_H_ */
+++ /dev/null
-/*
- * Ralink RT305x SoC specific definitions
- *
- * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * Parts of this file are based on Ralink's 2.6.21 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT305X_H_
-#define _RT305X_H_
-
-#include <linux/init.h>
-#include <linux/io.h>
-
-enum rt305x_soc_type {
- RT305X_SOC_UNKNOWN = 0,
- RT305X_SOC_RT3050,
- RT305X_SOC_RT3052,
- RT305X_SOC_RT3350,
- RT305X_SOC_RT3352,
- RT305X_SOC_RT5350,
-};
-
-extern enum rt305x_soc_type rt305x_soc;
-
-static inline int soc_is_rt3050(void)
-{
- return rt305x_soc == RT305X_SOC_RT3050;
-}
-
-static inline int soc_is_rt3052(void)
-{
- return rt305x_soc == RT305X_SOC_RT3052;
-}
-
-static inline int soc_is_rt305x(void)
-{
- return soc_is_rt3050() || soc_is_rt3052();
-}
-
-static inline int soc_is_rt3350(void)
-{
- return rt305x_soc == RT305X_SOC_RT3350;
-}
-
-static inline int soc_is_rt3352(void)
-{
- return rt305x_soc == RT305X_SOC_RT3352;
-}
-
-static inline int soc_is_rt5350(void)
-{
- return rt305x_soc == RT305X_SOC_RT5350;
-}
-
-#define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024)
-#define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024)
-
-#define RT3352_MEM_SIZE_MIN (2 * 1024 * 1024)
-#define RT3352_MEM_SIZE_MAX (256 * 1024 * 1024)
-
-#define RT305X_CPU_IRQ_BASE 0
-#define RT305X_INTC_IRQ_BASE 8
-#define RT305X_INTC_IRQ_COUNT 32
-#define RT305X_GPIO_IRQ_BASE 40
-
-#define RT305X_CPU_IRQ_INTC (RT305X_CPU_IRQ_BASE + 2)
-#define RT305X_CPU_IRQ_FE (RT305X_CPU_IRQ_BASE + 5)
-#define RT305X_CPU_IRQ_WNIC (RT305X_CPU_IRQ_BASE + 6)
-#define RT305X_CPU_IRQ_COUNTER (RT305X_CPU_IRQ_BASE + 7)
-
-#define RT305X_INTC_IRQ_SYSCTL (RT305X_INTC_IRQ_BASE + 0)
-#define RT305X_INTC_IRQ_TIMER0 (RT305X_INTC_IRQ_BASE + 1)
-#define RT305X_INTC_IRQ_TIMER1 (RT305X_INTC_IRQ_BASE + 2)
-#define RT305X_INTC_IRQ_IA (RT305X_INTC_IRQ_BASE + 3)
-#define RT305X_INTC_IRQ_PCM (RT305X_INTC_IRQ_BASE + 4)
-#define RT305X_INTC_IRQ_UART0 (RT305X_INTC_IRQ_BASE + 5)
-#define RT305X_INTC_IRQ_PIO (RT305X_INTC_IRQ_BASE + 6)
-#define RT305X_INTC_IRQ_DMA (RT305X_INTC_IRQ_BASE + 7)
-#define RT305X_INTC_IRQ_NAND (RT305X_INTC_IRQ_BASE + 8)
-#define RT305X_INTC_IRQ_PERFC (RT305X_INTC_IRQ_BASE + 9)
-#define RT305X_INTC_IRQ_I2S (RT305X_INTC_IRQ_BASE + 10)
-#define RT305X_INTC_IRQ_UART1 (RT305X_INTC_IRQ_BASE + 12)
-#define RT305X_INTC_IRQ_ESW (RT305X_INTC_IRQ_BASE + 17)
-#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18)
-
-extern void __iomem *rt305x_sysc_base;
-extern void __iomem *rt305x_memc_base;
-
-static inline void rt305x_sysc_wr(u32 val, unsigned reg)
-{
- __raw_writel(val, rt305x_sysc_base + reg);
-}
-
-static inline u32 rt305x_sysc_rr(unsigned reg)
-{
- return __raw_readl(rt305x_sysc_base + reg);
-}
-
-static inline void rt305x_memc_wr(u32 val, unsigned reg)
-{
- __raw_writel(val, rt305x_memc_base + reg);
-}
-
-static inline u32 rt305x_memc_rr(unsigned reg)
-{
- return __raw_readl(rt305x_memc_base + reg);
-}
-
-#define RT305X_GPIO_I2C_SD 1
-#define RT305X_GPIO_I2C_SCLK 2
-#define RT305X_GPIO_SPI_EN 3
-#define RT305X_GPIO_SPI_CLK 4
-#define RT305X_GPIO_SPI_DOUT 5
-#define RT305X_GPIO_SPI_DIN 6
-/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
-#define RT305X_GPIO_7 7
-#define RT305X_GPIO_8 8
-#define RT305X_GPIO_9 9
-#define RT305X_GPIO_10 10
-#define RT305X_GPIO_11 11
-#define RT305X_GPIO_12 12
-#define RT305X_GPIO_13 13
-#define RT305X_GPIO_14 14
-#define RT305X_GPIO_UART1_TXD 15
-#define RT305X_GPIO_UART1_RXD 16
-#define RT305X_GPIO_JTAG_TDO 17
-#define RT305X_GPIO_JTAG_TDI 18
-#define RT305X_GPIO_JTAG_TMS 19
-#define RT305X_GPIO_JTAG_TCLK 20
-#define RT305X_GPIO_JTAG_TRST_N 21
-#define RT305X_GPIO_MDIO_MDC 22
-#define RT305X_GPIO_MDIO_MDIO 23
-#define RT305X_GPIO_SDRAM_MD16 24
-#define RT305X_GPIO_SDRAM_MD17 25
-#define RT305X_GPIO_SDRAM_MD18 26
-#define RT305X_GPIO_SDRAM_MD19 27
-#define RT305X_GPIO_SDRAM_MD20 28
-#define RT305X_GPIO_SDRAM_MD21 29
-#define RT305X_GPIO_SDRAM_MD22 30
-#define RT305X_GPIO_SDRAM_MD23 31
-#define RT305X_GPIO_SDRAM_MD24 32
-#define RT305X_GPIO_SDRAM_MD25 33
-#define RT305X_GPIO_SDRAM_MD26 34
-#define RT305X_GPIO_SDRAM_MD27 35
-#define RT305X_GPIO_SDRAM_MD28 36
-#define RT305X_GPIO_SDRAM_MD29 37
-#define RT305X_GPIO_SDRAM_MD30 38
-#define RT305X_GPIO_SDRAM_MD31 39
-#define RT305X_GPIO_GE0_TXD0 40
-#define RT305X_GPIO_GE0_TXD1 41
-#define RT305X_GPIO_GE0_TXD2 42
-#define RT305X_GPIO_GE0_TXD3 43
-#define RT305X_GPIO_GE0_TXEN 44
-#define RT305X_GPIO_GE0_TXCLK 45
-#define RT305X_GPIO_GE0_RXD0 46
-#define RT305X_GPIO_GE0_RXD1 47
-#define RT305X_GPIO_GE0_RXD2 48
-#define RT305X_GPIO_GE0_RXD3 49
-#define RT305X_GPIO_GE0_RXDV 50
-#define RT305X_GPIO_GE0_RXCLK 51
-
-void rt305x_gpio_init(u32 mode);
-
-#endif /* _RT305X_H_ */
+++ /dev/null
-/*
- * Ralink RT305x specific CPU feature overrides
- *
- * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This file was derived from: include/asm-mips/cpu-features.h
- * Copyright (C) 2003, 2004 Ralf Baechle
- * Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
-
-#define cpu_has_tlb 1
-#define cpu_has_4kex 1
-#define cpu_has_3k_cache 0
-#define cpu_has_4k_cache 1
-#define cpu_has_tx39_cache 0
-#define cpu_has_sb1_cache 0
-#define cpu_has_fpu 0
-#define cpu_has_32fpr 0
-#define cpu_has_counter 1
-#define cpu_has_watch 1
-#define cpu_has_divec 1
-
-#define cpu_has_prefetch 1
-#define cpu_has_ejtag 1
-#define cpu_has_llsc 1
-
-#define cpu_has_mips16 1
-#define cpu_has_mdmx 0
-#define cpu_has_mips3d 0
-#define cpu_has_smartmips 0
-
-#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 1
-#define cpu_has_mips64r1 0
-#define cpu_has_mips64r2 0
-
-#define cpu_has_dsp 1
-#define cpu_has_mipsmt 0
-
-#define cpu_has_64bits 0
-#define cpu_has_64bit_zero_reg 0
-#define cpu_has_64bit_gp_regs 0
-#define cpu_has_64bit_addresses 0
-
-#define cpu_dcache_line_size() 32
-#define cpu_icache_line_size() 32
-
-#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-#ifndef __ASM_MACH_RALINK_RT305X_IRQ_H
-#define __ASM_MACH_RALINK_RT305X_IRQ_H
-
-#define MIPS_CPU_IRQ_BASE 0
-#define NR_IRQS 48
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_RALINK_RT305X_IRQ_H */
+++ /dev/null
-/*
- * Ralink RT305x SoC platform device registration
- *
- * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT305X_ESW_PLATFORM_H
-#define _RT305X_ESW_PLATFORM_H
-
-enum {
- RT305X_ESW_VLAN_CONFIG_NONE = 0,
- RT305X_ESW_VLAN_CONFIG_LLLLW,
- RT305X_ESW_VLAN_CONFIG_WLLLL,
-};
-
-struct rt305x_esw_platform_data
-{
- u8 vlan_config;
- u32 reg_initval_fct2;
- u32 reg_initval_fpa2;
-};
-
-#endif /* _RT305X_ESW_PLATFORM_H */
+++ /dev/null
-/*
- * Ralink RT305 SoC register definitions
- *
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT305X_REGS_H_
-#define _RT305X_REGS_H_
-
-#include <linux/bitops.h>
-
-#define RT305X_SDRAM_BASE 0x00000000
-#define RT305X_SYSC_BASE 0x10000000
-#define RT305X_TIMER_BASE 0x10000100
-#define RT305X_INTC_BASE 0x10000200
-#define RT305X_MEMC_BASE 0x10000300
-#define RT305X_PCM_BASE 0x10000400
-#define RT305X_UART0_BASE 0x10000500
-#define RT305X_PIO_BASE 0x10000600
-#define RT305X_GDMA_BASE 0x10000700
-#define RT305X_NANDC_BASE 0x10000800
-#define RT305X_I2C_BASE 0x10000900
-#define RT305X_I2S_BASE 0x10000a00
-#define RT305X_SPI_BASE 0x10000b00
-#define RT305X_UART1_BASE 0x10000c00
-#define RT305X_FE_BASE 0x10100000
-#define RT305X_SWITCH_BASE 0x10110000
-#define RT305X_WMAC_BASE 0x10180000
-#define RT305X_OTG_BASE 0x101c0000
-#define RT305X_ROM_BASE 0x00400000
-#define RT305X_FLASH1_BASE 0x1b000000
-#define RT305X_FLASH0_BASE 0x1f000000
-
-#define RT305X_SYSC_SIZE 0x100
-#define RT305X_TIMER_SIZE 0x100
-#define RT305X_INTC_SIZE 0x100
-#define RT305X_MEMC_SIZE 0x100
-#define RT305X_UART0_SIZE 0x100
-#define RT305X_PIO_SIZE 0x100
-#define RT305X_UART1_SIZE 0x100
-#define RT305X_SPI_SIZE 0x100
-#define RT305X_FLASH1_SIZE (16 * 1024 * 1024)
-#define RT305X_FLASH0_SIZE (8 * 1024 * 1024)
-
-#define RT3352_EHCI_BASE 0x101c0000
-#define RT3352_EHCI_SIZE 0x1000
-#define RT3352_OHCI_BASE 0x101c1000
-#define RT3352_OHCI_SIZE 0x1000
-
-/* SYSC registers */
-#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
-#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
-#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
-#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
-#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
-#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
-#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
-#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
-#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
-
-#define RT3352_SYSC_REG_SYSCFG1 0x014
-#define RT3352_SYSC_REG_CLKCFG1 0x030
-#define RT3352_SYSC_REG_RSTCTRL 0x034
-#define RT3352_SYSC_REG_USB_PS 0x05c
-
-#define RT3052_CHIP_NAME0 0x30335452
-#define RT3052_CHIP_NAME1 0x20203235
-
-#define RT3350_CHIP_NAME0 0x33335452
-#define RT3350_CHIP_NAME1 0x20203035
-
-#define RT3352_CHIP_NAME0 0x33335452
-#define RT3352_CHIP_NAME1 0x20203235
-
-#define RT5350_CHIP_NAME0 0x33355452
-#define RT5350_CHIP_NAME1 0x20203035
-
-#define CHIP_ID_ID_MASK 0xff
-#define CHIP_ID_ID_SHIFT 8
-#define CHIP_ID_REV_MASK 0xff
-
-#define RT305X_SYSCFG_CPUCLK_SHIFT 18
-#define RT305X_SYSCFG_CPUCLK_MASK 0x1
-#define RT305X_SYSCFG_CPUCLK_LOW 0x0
-#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
-#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
-#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3
-#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0
-#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1
-#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2
-
-#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
-#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
-#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
-#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
-
-#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
-#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
-#define RT5350_SYSCFG0_CPUCLK_360 0x0
-#define RT5350_SYSCFG0_CPUCLK_320 0x2
-#define RT5350_SYSCFG0_CPUCLK_300 0x3
-#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
-#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
-#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
-#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
-#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
-#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
-#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
-
-#define RT3352_SYSCFG0_XTAL_SEL BIT(20)
-
-#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
-
-#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
-#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
-
-#define RT305X_GPIO_MODE_I2C BIT(0)
-#define RT305X_GPIO_MODE_SPI BIT(1)
-#define RT305X_GPIO_MODE_UART0_SHIFT 2
-#define RT305X_GPIO_MODE_UART0_MASK 0x7
-#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
-#define RT305X_GPIO_MODE_UARTF 0x0
-#define RT305X_GPIO_MODE_PCM_UARTF 0x1
-#define RT305X_GPIO_MODE_PCM_I2S 0x2
-#define RT305X_GPIO_MODE_I2S_UARTF 0x3
-#define RT305X_GPIO_MODE_PCM_GPIO 0x4
-#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
-#define RT305X_GPIO_MODE_GPIO_I2S 0x6
-#define RT305X_GPIO_MODE_GPIO 0x7
-#define RT305X_GPIO_MODE_UART1 BIT(5)
-#define RT305X_GPIO_MODE_JTAG BIT(6)
-#define RT305X_GPIO_MODE_MDIO BIT(7)
-#define RT305X_GPIO_MODE_SDRAM BIT(8)
-#define RT305X_GPIO_MODE_RGMII BIT(9)
-
-#define RT305X_RESET_SYSTEM BIT(0)
-#define RT305X_RESET_TIMER BIT(8)
-#define RT305X_RESET_INTC BIT(9)
-#define RT305X_RESET_MEMC BIT(10)
-#define RT305X_RESET_PCM BIT(11)
-#define RT305X_RESET_UART0 BIT(12)
-#define RT305X_RESET_PIO BIT(13)
-#define RT305X_RESET_DMA BIT(14)
-#define RT305X_RESET_I2C BIT(16)
-#define RT305X_RESET_I2S BIT(17)
-#define RT305X_RESET_SPI BIT(18)
-#define RT305X_RESET_UART1 BIT(19)
-#define RT305X_RESET_WNIC BIT(20)
-#define RT305X_RESET_FE BIT(21)
-#define RT305X_RESET_OTG BIT(22)
-#define RT305X_RESET_ESW BIT(23)
-
-#define RT3352_RSTCTRL_SYS BIT(0)
-#define RT3352_RSTCTRL_TIMER BIT(8)
-#define RT3352_RSTCTRL_INTC BIT(9)
-#define RT3352_RSTCTRL_MEMC BIT(10)
-#define RT3352_RSTCTRL_PCM BIT(11)
-#define RT3352_RSTCTRL_UART0 BIT(12)
-#define RT3352_RSTCTRL_PIO BIT(13)
-#define RT3352_RSTCTRL_DMA BIT(14)
-#define RT3352_RSTCTRL_I2C BIT(16)
-#define RT3352_RSTCTRL_I2S BIT(17)
-#define RT3352_RSTCTRL_SPI BIT(18)
-#define RT3352_RSTCTRL_UART1 BIT(19)
-#define RT3352_RSTCTRL_WNIC BIT(20)
-#define RT3352_RSTCTRL_FE BIT(21)
-#define RT3352_RSTCTRL_UHST BIT(22)
-#define RT3352_RSTCTRL_ESW BIT(23)
-#define RT3352_RSTCTRL_EPHY BIT(24)
-#define RT3352_RSTCTRL_UDEV BIT(25)
-
-#define RT305X_INTC_INT_SYSCTL BIT(0)
-#define RT305X_INTC_INT_TIMER0 BIT(1)
-#define RT305X_INTC_INT_TIMER1 BIT(2)
-#define RT305X_INTC_INT_IA BIT(3)
-#define RT305X_INTC_INT_PCM BIT(4)
-#define RT305X_INTC_INT_UART0 BIT(5)
-#define RT305X_INTC_INT_PIO BIT(6)
-#define RT305X_INTC_INT_DMA BIT(7)
-#define RT305X_INTC_INT_NAND BIT(8)
-#define RT305X_INTC_INT_PERFC BIT(9)
-#define RT305X_INTC_INT_I2S BIT(10)
-#define RT305X_INTC_INT_UART1 BIT(12)
-#define RT305X_INTC_INT_ESW BIT(17)
-#define RT305X_INTC_INT_OTG BIT(18)
-#define RT305X_INTC_INT_GLOBAL BIT(31)
-
-/* MEMC registers */
-#define MEMC_REG_SDRAM_CFG0 0x00
-#define MEMC_REG_SDRAM_CFG1 0x04
-#define MEMC_REG_FLASH_CFG0 0x08
-#define MEMC_REG_FLASH_CFG1 0x0c
-#define MEMC_REG_IA_ADDR 0x10
-#define MEMC_REG_IA_TYPE 0x14
-
-#define FLASH_CFG_WIDTH_SHIFT 26
-#define FLASH_CFG_WIDTH_MASK 0x3
-#define FLASH_CFG_WIDTH_8BIT 0x0
-#define FLASH_CFG_WIDTH_16BIT 0x1
-#define FLASH_CFG_WIDTH_32BIT 0x2
-
-/* UART registers */
-#define UART_REG_RX 0
-#define UART_REG_TX 1
-#define UART_REG_IER 2
-#define UART_REG_IIR 3
-#define UART_REG_FCR 4
-#define UART_REG_LCR 5
-#define UART_REG_MCR 6
-#define UART_REG_LSR 7
-
-#endif /* _RT305X_REGS_H_ */
+++ /dev/null
-/*
- * Ralink RT3662/RT3883 SoC specific definitions
- *
- * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * Parts of this file are based on Ralink's 2.6.21 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT3883_H_
-#define _RT3883_H_
-
-#include <linux/init.h>
-#include <linux/io.h>
-
-#define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024)
-#define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024)
-
-#define RT3883_CPU_IRQ_BASE 0
-#define RT3883_CPU_IRQ_COUNT 8
-#define RT3883_INTC_IRQ_BASE (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT)
-#define RT3883_INTC_IRQ_COUNT 32
-#define RT3883_GPIO_IRQ_BASE (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT)
-#define RT3883_GPIO_IRQ_COUNT 96
-#define RT3883_PCI_IRQ_BASE (RT3883_GPIO_IRQ_BASE + RT3883_GPIO_IRQ_COUNT)
-#define RT3883_PCI_IRQ_COUNT 3
-
-#define RT3883_CPU_IRQ_INTC (RT3883_CPU_IRQ_BASE + 2)
-#define RT3883_CPU_IRQ_PCI (RT3883_CPU_IRQ_BASE + 4)
-#define RT3883_CPU_IRQ_FE (RT3883_CPU_IRQ_BASE + 5)
-#define RT3883_CPU_IRQ_WLAN (RT3883_CPU_IRQ_BASE + 6)
-#define RT3883_CPU_IRQ_COUNTER (RT3883_CPU_IRQ_BASE + 7)
-
-#define RT3883_INTC_IRQ_SYSCTL (RT3883_INTC_IRQ_BASE + 0)
-#define RT3883_INTC_IRQ_TIMER0 (RT3883_INTC_IRQ_BASE + 1)
-#define RT3883_INTC_IRQ_TIMER1 (RT3883_INTC_IRQ_BASE + 2)
-#define RT3883_INTC_IRQ_IA (RT3883_INTC_IRQ_BASE + 3)
-#define RT3883_INTC_IRQ_PCM (RT3883_INTC_IRQ_BASE + 4)
-#define RT3883_INTC_IRQ_UART0 (RT3883_INTC_IRQ_BASE + 5)
-#define RT3883_INTC_IRQ_PIO (RT3883_INTC_IRQ_BASE + 6)
-#define RT3883_INTC_IRQ_DMA (RT3883_INTC_IRQ_BASE + 7)
-#define RT3883_INTC_IRQ_NAND (RT3883_INTC_IRQ_BASE + 8)
-#define RT3883_INTC_IRQ_PERFC (RT3883_INTC_IRQ_BASE + 9)
-#define RT3883_INTC_IRQ_I2S (RT3883_INTC_IRQ_BASE + 10)
-#define RT3883_INTC_IRQ_UART1 (RT3883_INTC_IRQ_BASE + 12)
-#define RT3883_INTC_IRQ_UHST (RT3883_INTC_IRQ_BASE + 18)
-#define RT3883_INTC_IRQ_UDEV (RT3883_INTC_IRQ_BASE + 19)
-
-#define RT3883_PCI_IRQ_PCI0 (RT3883_PCI_IRQ_BASE + 0)
-#define RT3883_PCI_IRQ_PCI1 (RT3883_PCI_IRQ_BASE + 1)
-#define RT3883_PCI_IRQ_PCIE (RT3883_PCI_IRQ_BASE + 2)
-
-extern void __iomem *rt3883_sysc_base;
-extern void __iomem *rt3883_memc_base;
-
-static inline void rt3883_sysc_wr(u32 val, unsigned reg)
-{
- __raw_writel(val, rt3883_sysc_base + reg);
-}
-
-static inline u32 rt3883_sysc_rr(unsigned reg)
-{
- return __raw_readl(rt3883_sysc_base + reg);
-}
-
-static inline void rt3883_memc_wr(u32 val, unsigned reg)
-{
- __raw_writel(val, rt3883_memc_base + reg);
-}
-
-static inline u32 rt3883_memc_rr(unsigned reg)
-{
- return __raw_readl(rt3883_memc_base + reg);
-}
-
-#define RT3883_GPIO_I2C_SD 1
-#define RT3883_GPIO_I2C_SCLK 2
-#define RT3883_GPIO_SPI_CS0 3
-#define RT3883_GPIO_SPI_CLK 4
-#define RT3883_GPIO_SPI_MOSI 5
-#define RT3883_GPIO_SPI_MISO 6
-/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
-#define RT3883_GPIO_7 7
-#define RT3883_GPIO_8 8
-#define RT3883_GPIO_9 9
-#define RT3883_GPIO_10 10
-#define RT3883_GPIO_11 11
-#define RT3883_GPIO_12 12
-#define RT3883_GPIO_13 13
-#define RT3883_GPIO_14 14
-#define RT3883_GPIO_UART1_TXD 15
-#define RT3883_GPIO_UART1_RXD 16
-#define RT3883_GPIO_JTAG_TDO 17
-#define RT3883_GPIO_JTAG_TDI 18
-#define RT3883_GPIO_JTAG_TMS 19
-#define RT3883_GPIO_JTAG_TCLK 20
-#define RT3883_GPIO_JTAG_TRST_N 21
-#define RT3883_GPIO_MDIO_MDC 22
-#define RT3883_GPIO_MDIO_MDIO 23
-#define RT3883_GPIO_LNA_PE_A0 32
-#define RT3883_GPIO_LNA_PE_A1 33
-#define RT3883_GPIO_LNA_PE_A2 34
-#define RT3883_GPIO_LNA_PE_G0 35
-#define RT3883_GPIO_LNA_PE_G1 36
-#define RT3883_GPIO_LNA_PE_G2 37
-#define RT3883_GPIO_PCI_AD0 40
-#define RT3883_GPIO_PCI_AD31 71
-#define RT3883_GPIO_GE2_TXD0 72
-#define RT3883_GPIO_GE2_TXD1 73
-#define RT3883_GPIO_GE2_TXD2 74
-#define RT3883_GPIO_GE2_TXD3 75
-#define RT3883_GPIO_GE2_TXEN 76
-#define RT3883_GPIO_GE2_TXCLK 77
-#define RT3883_GPIO_GE2_RXD0 78
-#define RT3883_GPIO_GE2_RXD1 79
-#define RT3883_GPIO_GE2_RXD2 80
-#define RT3883_GPIO_GE2_RXD3 81
-#define RT3883_GPIO_GE2_RXDV 82
-#define RT3883_GPIO_GE2_RXCLK 83
-#define RT3883_GPIO_GE1_TXD0 84
-#define RT3883_GPIO_GE1_TXD1 85
-#define RT3883_GPIO_GE1_TXD2 86
-#define RT3883_GPIO_GE1_TXD3 87
-#define RT3883_GPIO_GE1_TXEN 88
-#define RT3883_GPIO_GE1_TXCLK 89
-#define RT3883_GPIO_GE1_RXD0 90
-#define RT3883_GPIO_GE1_RXD1 91
-#define RT3883_GPIO_GE1_RXD2 92
-#define RT3883_GPIO_GE1_RXD3 93
-#define RT3883_GPIO_GE1_RXDV 94
-#define RT3883_GPIO_GE1_RXCLK 95
-
-void rt3883_gpio_init(u32 mode);
-
-#define RT3883_PCI_MODE_PCI 0x01
-#define RT3883_PCI_MODE_PCIE 0x02
-#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
-
-struct pci_dev;
-
-#ifdef CONFIG_PCI
-void rt3883_pci_init(unsigned mode);
-void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *));
-#else
-static inline void rt3883_pci_init(unsigned mode) {}
-static inline void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)) {}
-#endif /* CONFIG_PCI */
-
-#endif /* _RT3883_H_ */
+++ /dev/null
-/*
- * Ralink RT3662/RT3883 specific CPU feature overrides
- *
- * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: include/asm-mips/cpu-features.h
- * Copyright (C) 2003, 2004 Ralf Baechle
- * Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
-
-#define cpu_has_tlb 1
-#define cpu_has_4kex 1
-#define cpu_has_3k_cache 0
-#define cpu_has_4k_cache 1
-#define cpu_has_tx39_cache 0
-#define cpu_has_sb1_cache 0
-#define cpu_has_fpu 0
-#define cpu_has_32fpr 0
-#define cpu_has_counter 1
-#define cpu_has_watch 1
-#define cpu_has_divec 1
-
-#define cpu_has_prefetch 1
-#define cpu_has_ejtag 1
-#define cpu_has_llsc 1
-
-#define cpu_has_mips16 1
-#define cpu_has_mdmx 0
-#define cpu_has_mips3d 0
-#define cpu_has_smartmips 0
-
-#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 1
-#define cpu_has_mips64r1 0
-#define cpu_has_mips64r2 0
-
-#define cpu_has_dsp 1
-#define cpu_has_mipsmt 0
-
-#define cpu_has_64bits 0
-#define cpu_has_64bit_zero_reg 0
-#define cpu_has_64bit_gp_regs 0
-#define cpu_has_64bit_addresses 0
-
-#define cpu_dcache_line_size() 32
-#define cpu_icache_line_size() 32
-
-#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */
+++ /dev/null
-/*
- * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-#ifndef __ASM_MACH_RALINK_RT3883_IRQ_H
-#define __ASM_MACH_RALINK_RT3883_IRQ_H
-
-#define MIPS_CPU_IRQ_BASE 0
-#define NR_IRQS 140
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_RALINK_RT3883_IRQ_H */
+++ /dev/null
-/*
- * Ralink RT3662/RT3883 SoC register definitions
- *
- * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT3883_REGS_H_
-#define _RT3883_REGS_H_
-
-#include <linux/bitops.h>
-
-#define RT3883_SDRAM_BASE 0x00000000
-#define RT3883_SYSC_BASE 0x10000000
-#define RT3883_TIMER_BASE 0x10000100
-#define RT3883_INTC_BASE 0x10000200
-#define RT3883_MEMC_BASE 0x10000300
-#define RT3883_UART0_BASE 0x10000500
-#define RT3883_PIO_BASE 0x10000600
-#define RT3883_FSCC_BASE 0x10000700
-#define RT3883_NANDC_BASE 0x10000810
-#define RT3883_I2C_BASE 0x10000900
-#define RT3883_I2S_BASE 0x10000a00
-#define RT3883_SPI_BASE 0x10000b00
-#define RT3883_UART1_BASE 0x10000c00
-#define RT3883_PCM_BASE 0x10002000
-#define RT3883_GDMA_BASE 0x10002800
-#define RT3883_CODEC1_BASE 0x10003000
-#define RT3883_CODEC2_BASE 0x10003800
-#define RT3883_FE_BASE 0x10100000
-#define RT3883_ROM_BASE 0x10118000
-#define RT3883_USBDEV_BASE 0x10112000
-#define RT3883_PCI_BASE 0x10140000
-#define RT3883_WLAN_BASE 0x10180000
-#define RT3883_USBHOST_BASE 0x101c0000
-#define RT3883_BOOT_BASE 0x1c000000
-#define RT3883_SRAM_BASE 0x1e000000
-#define RT3883_PCIMEM_BASE 0x20000000
-
-#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
-#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
-
-#define RT3883_SYSC_SIZE 0x100
-#define RT3883_TIMER_SIZE 0x100
-#define RT3883_INTC_SIZE 0x100
-#define RT3883_MEMC_SIZE 0x100
-#define RT3883_UART0_SIZE 0x100
-#define RT3883_UART1_SIZE 0x100
-#define RT3883_PIO_SIZE 0x100
-#define RT3883_FSCC_SIZE 0x100
-#define RT3883_NANDC_SIZE 0x0f0
-#define RT3883_I2C_SIZE 0x100
-#define RT3883_I2S_SIZE 0x100
-#define RT3883_SPI_SIZE 0x100
-#define RT3883_PCM_SIZE 0x800
-#define RT3883_GDMA_SIZE 0x800
-#define RT3883_CODEC1_SIZE 0x800
-#define RT3883_CODEC2_SIZE 0x800
-#define RT3883_FE_SIZE 0x10000
-#define RT3883_ROM_SIZE 0x4000
-#define RT3883_USBDEV_SIZE 0x4000
-#define RT3883_PCI_SIZE 0x40000
-#define RT3883_WLAN_SIZE 0x40000
-#define RT3883_USBHOST_SIZE 0x40000
-#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
-#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
-
-/* SYSC registers */
-#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
-#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
-#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
-#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
-#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
-#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
-#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
-#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
-#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
-#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
-#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
-#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
-#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
-#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
-#define RT3883_SYSC_REG_PMU 0x88
-#define RT3883_SYSC_REG_PMU1 0x8c
-
-#define RT3883_REVID_VER_ID_MASK 0x0f
-#define RT3883_REVID_VER_ID_SHIFT 8
-#define RT3883_REVID_ECO_ID_MASK 0x0f
-
-#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
-#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
-#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
-#define RT3883_SYSCFG0_CPUCLK_250 0x0
-#define RT3883_SYSCFG0_CPUCLK_384 0x1
-#define RT3883_SYSCFG0_CPUCLK_480 0x2
-#define RT3883_SYSCFG0_CPUCLK_500 0x3
-
-#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
-#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
-#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
-#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
-#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
-
-#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
-#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
-#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
-#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
-
-#define RT3883_GPIO_MODE_I2C BIT(0)
-#define RT3883_GPIO_MODE_SPI BIT(1)
-#define RT3883_GPIO_MODE_UART0_SHIFT 2
-#define RT3883_GPIO_MODE_UART0_MASK 0x7
-#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
-#define RT3883_GPIO_MODE_UARTF 0x0
-#define RT3883_GPIO_MODE_PCM_UARTF 0x1
-#define RT3883_GPIO_MODE_PCM_I2S 0x2
-#define RT3883_GPIO_MODE_I2S_UARTF 0x3
-#define RT3883_GPIO_MODE_PCM_GPIO 0x4
-#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
-#define RT3883_GPIO_MODE_GPIO_I2S 0x6
-#define RT3883_GPIO_MODE_GPIO 0x7
-#define RT3883_GPIO_MODE_UART1 BIT(5)
-#define RT3883_GPIO_MODE_JTAG BIT(6)
-#define RT3883_GPIO_MODE_MDIO BIT(7)
-#define RT3883_GPIO_MODE_GE1 BIT(9)
-#define RT3883_GPIO_MODE_GE2 BIT(10)
-#define RT3883_GPIO_MODE_PCI_SHIFT 11
-#define RT3883_GPIO_MODE_PCI_MASK 0x7
-#define RT3883_GPIO_MODE_PCI(_x) ((_x) << RT3883_GPIO_MODE_PCI_SHIFT)
-#define RT3883_GPIO_MODE_PCI_DEV 0
-#define RT3883_GPIO_MODE_PCI_HOST2 1
-#define RT3883_GPIO_MODE_PCI_HOST1 2
-#define RT3883_GPIO_MODE_PCI_FNC 3
-#define RT3883_GPIO_MODE_PCI_GPIO 7
-#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
-#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
-#define RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
-#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
-#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
-#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
-#define RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
-#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
-
-#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
-#define RT3883_RSTCTRL_FLASH BIT(26)
-#define RT3883_RSTCTRL_UDEV BIT(25)
-#define RT3883_RSTCTRL_PCI BIT(24)
-#define RT3883_RSTCTRL_PCIE BIT(23)
-#define RT3883_RSTCTRL_UHST BIT(22)
-#define RT3883_RSTCTRL_FE BIT(21)
-#define RT3883_RSTCTRL_WLAN BIT(20)
-#define RT3883_RSTCTRL_UART1 BIT(29)
-#define RT3883_RSTCTRL_SPI BIT(18)
-#define RT3883_RSTCTRL_I2S BIT(17)
-#define RT3883_RSTCTRL_I2C BIT(16)
-#define RT3883_RSTCTRL_NAND BIT(15)
-#define RT3883_RSTCTRL_DMA BIT(14)
-#define RT3883_RSTCTRL_PIO BIT(13)
-#define RT3883_RSTCTRL_UART BIT(12)
-#define RT3883_RSTCTRL_PCM BIT(11)
-#define RT3883_RSTCTRL_MC BIT(10)
-#define RT3883_RSTCTRL_INTC BIT(9)
-#define RT3883_RSTCTRL_TIMER BIT(8)
-#define RT3883_RSTCTRL_SYS BIT(0)
-
-#define RT3883_INTC_INT_SYSCTL BIT(0)
-#define RT3883_INTC_INT_TIMER0 BIT(1)
-#define RT3883_INTC_INT_TIMER1 BIT(2)
-#define RT3883_INTC_INT_IA BIT(3)
-#define RT3883_INTC_INT_PCM BIT(4)
-#define RT3883_INTC_INT_UART0 BIT(5)
-#define RT3883_INTC_INT_PIO BIT(6)
-#define RT3883_INTC_INT_DMA BIT(7)
-#define RT3883_INTC_INT_NAND BIT(8)
-#define RT3883_INTC_INT_PERFC BIT(9)
-#define RT3883_INTC_INT_I2S BIT(10)
-#define RT3883_INTC_INT_UART1 BIT(12)
-#define RT3883_INTC_INT_UHST BIT(18)
-#define RT3883_INTC_INT_UDEV BIT(19)
-
-/* FLASH/SRAM/Codec Controller registers */
-#define RT3883_FSCC_REG_FLASH_CFG0 0x00
-#define RT3883_FSCC_REG_FLASH_CFG1 0x04
-#define RT3883_FSCC_REG_CODEC_CFG0 0x40
-#define RT3883_FSCC_REG_CODEC_CFG1 0x44
-
-#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
-#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
-#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
-#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
-#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
-
-
-/* UART registers */
-#define RT3883_UART_REG_RX 0
-#define RT3883_UART_REG_TX 1
-#define RT3883_UART_REG_IER 2
-#define RT3883_UART_REG_IIR 3
-#define RT3883_UART_REG_FCR 4
-#define RT3883_UART_REG_LCR 5
-#define RT3883_UART_REG_MCR 6
-#define RT3883_UART_REG_LSR 7
-
-#endif /* _RT3883_REGS_H_ */
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MACH_RALINK_WAR_H
-#define __ASM_MACH_RALINK_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define RM9000_CDEX_SMP_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif /* __ASM_MACH_RALINK_WAR_H */
+++ /dev/null
-/*
- * Ralink RT288x SoC PCI register definitions
- *
- * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * Parts of this file are based on Ralink's 2.6.21 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/io.h>
-#include <linux/init.h>
-
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-
-#define RT2880_PCI_MEM_BASE 0x20000000
-#define RT2880_PCI_MEM_SIZE 0x10000000
-#define RT2880_PCI_IO_BASE 0x00460000
-#define RT2880_PCI_IO_SIZE 0x00010000
-
-#define RT2880_PCI_REG_PCICFG_ADDR 0x00
-#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
-#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
-#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
-#define RT2880_PCI_REG_CONFIG_ADDR 0x20
-#define RT2880_PCI_REG_CONFIG_DATA 0x24
-#define RT2880_PCI_REG_MEMBASE 0x28
-#define RT2880_PCI_REG_IOBASE 0x2c
-#define RT2880_PCI_REG_ID 0x30
-#define RT2880_PCI_REG_CLASS 0x34
-#define RT2880_PCI_REG_SUBID 0x38
-#define RT2880_PCI_REG_ARBCTL 0x80
-
-static void __iomem *rt2880_pci_base;
-static DEFINE_SPINLOCK(rt2880_pci_lock);
-
-static u32 rt2880_pci_reg_read(u32 reg)
-{
- return readl(rt2880_pci_base + reg);
-}
-
-static void rt2880_pci_reg_write(u32 val, u32 reg)
-{
- writel(val, rt2880_pci_base + reg);
-}
-
-static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
- unsigned int func, unsigned int where)
-{
- return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
- 0x80000000);
-}
-
-static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
-{
- unsigned long flags;
- u32 address;
- u32 data;
-
- address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where);
-
- spin_lock_irqsave(&rt2880_pci_lock, flags);
- rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
- data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
- spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-
- switch (size) {
- case 1:
- *val = (data >> ((where & 3) << 3)) & 0xff;
- break;
- case 2:
- *val = (data >> ((where & 3) << 3)) & 0xffff;
- break;
- case 4:
- *val = data;
- break;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- unsigned long flags;
- u32 address;
- u32 data;
-
- address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where);
-
- spin_lock_irqsave(&rt2880_pci_lock, flags);
- rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
- data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
-
- switch (size) {
- case 1:
- data = (data & ~(0xff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- break;
- case 2:
- data = (data & ~(0xffff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- break;
- case 4:
- data = val;
- break;
- }
-
- rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
- spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops rt2880_pci_ops = {
- .read = rt2880_pci_config_read,
- .write = rt2880_pci_config_write,
-};
-
-static struct resource rt2880_pci_mem_resource = {
- .name = "PCI MEM space",
- .start = RT2880_PCI_MEM_BASE,
- .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct resource rt2880_pci_io_resource = {
- .name = "PCI IO space",
- .start = RT2880_PCI_IO_BASE,
- .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
- .flags = IORESOURCE_IO,
-};
-
-static struct pci_controller rt2880_pci_controller = {
- .pci_ops = &rt2880_pci_ops,
- .mem_resource = &rt2880_pci_mem_resource,
- .io_resource = &rt2880_pci_io_resource,
-};
-
-static inline u32 rt2880_pci_read_u32(unsigned long reg)
-{
- unsigned long flags;
- u32 address;
- u32 ret;
-
- address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
-
- spin_lock_irqsave(&rt2880_pci_lock, flags);
- rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
- ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
- spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-
- return ret;
-}
-
-static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
-{
- unsigned long flags;
- u32 address;
-
- address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
-
- spin_lock_irqsave(&rt2880_pci_lock, flags);
- rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
- rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
- spin_unlock_irqrestore(&rt2880_pci_lock, flags);
-}
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- u16 cmd;
- int irq = -1;
-
- if (dev->bus->number != 0)
- return irq;
-
- switch (PCI_SLOT(dev->devfn)) {
- case 0x00:
- rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
- (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
- break;
- case 0x11:
- irq = RT288X_CPU_IRQ_PCI;
- break;
- default:
- printk("%s:%s[%d] trying to alloc unknown pci irq\n",
- __FILE__, __func__, __LINE__);
- BUG();
- break;
- }
-
- pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
- pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
- pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
- PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
- pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
- pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
- dev->irq);
- return irq;
-}
-
-int __init rt288x_register_pci(void)
-{
- void __iomem *io_map_base;
- int i;
-
- rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
-
- io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
- rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
- set_io_port_base((unsigned long) io_map_base);
-
- ioport_resource.start = RT2880_PCI_IO_BASE;
- ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
-
- rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
- for(i = 0; i < 0xfffff; i++) {}
-
- rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
- rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
- rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
- rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
- rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
- rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
- rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
- rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
- rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
-
- rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
- (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
-
- register_pci_controller(&rt2880_pci_controller);
- return 0;
-}
-
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
+++ /dev/null
-/*
- * Ralink RT3883 SoC PCI support
- *
- * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * Parts of this file are based on Ralink's 2.6.21 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach-ralink/rt3883.h>
-#include <asm/mach-ralink/rt3883_regs.h>
-
-#define RT3883_MEMORY_BASE 0x00000000
-#define RT3883_MEMORY_SIZE 0x02000000
-
-#define RT3883_PCI_MEM_BASE 0x20000000
-#define RT3883_PCI_MEM_SIZE 0x10000000
-#define RT3883_PCI_IO_BASE 0x10160000
-#define RT3883_PCI_IO_SIZE 0x00010000
-
-#define RT3883_PCI_REG_PCICFG_ADDR 0x00
-#define RT3883_PCI_REG_PCIRAW_ADDR 0x04
-#define RT3883_PCI_REG_PCIINT_ADDR 0x08
-#define RT3883_PCI_REG_PCIMSK_ADDR 0x0c
-#define RT3833_PCI_PCIINT_PCIE BIT(20)
-#define RT3833_PCI_PCIINT_PCI1 BIT(19)
-#define RT3833_PCI_PCIINT_PCI0 BIT(18)
-
-#define RT3883_PCI_REG_CONFIG_ADDR 0x20
-#define RT3883_PCI_REG_CONFIG_DATA 0x24
-#define RT3883_PCI_REG_MEMBASE 0x28
-#define RT3883_PCI_REG_IOBASE 0x2c
-#define RT3883_PCI_REG_ARBCTL 0x80
-
-#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
-#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
-#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
-#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
-#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
-#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
-#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
-
-static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
-static void __iomem *rt3883_pci_base;
-static DEFINE_SPINLOCK(rt3883_pci_lock);
-
-static inline u32 rt3883_pci_rr(unsigned reg)
-{
- return readl(rt3883_pci_base + reg);
-}
-
-static inline void rt3883_pci_wr(u32 val, unsigned reg)
-{
- writel(val, rt3883_pci_base + reg);
-}
-
-static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
- unsigned int func, unsigned int where)
-{
- return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
- 0x80000000);
-}
-
-static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
- unsigned func, unsigned reg)
-{
- unsigned long flags;
- u32 address;
- u32 ret;
-
- address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
-
- spin_lock_irqsave(&rt3883_pci_lock, flags);
- rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
- ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
- spin_unlock_irqrestore(&rt3883_pci_lock, flags);
-
- return ret;
-}
-
-static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
- unsigned func, unsigned reg, u32 val)
-{
- unsigned long flags;
- u32 address;
-
- address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
-
- spin_lock_irqsave(&rt3883_pci_lock, flags);
- rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
- rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
- spin_unlock_irqrestore(&rt3883_pci_lock, flags);
-}
-
-static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
- u32 pending;
-
- pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
- rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
-
- if (!pending) {
- spurious_interrupt();
- return;
- }
-
- if (pending & RT3833_PCI_PCIINT_PCI0)
- generic_handle_irq(RT3883_PCI_IRQ_PCI0);
-
- if (pending & RT3833_PCI_PCIINT_PCI1)
- generic_handle_irq(RT3883_PCI_IRQ_PCI1);
-
- if (pending & RT3833_PCI_PCIINT_PCIE)
- generic_handle_irq(RT3883_PCI_IRQ_PCIE);
-}
-
-static void rt3883_pci_irq_unmask(struct irq_data *d)
-{
- int irq = d->irq;
- u32 mask;
- u32 t;
-
- switch (irq) {
- case RT3883_PCI_IRQ_PCI0:
- mask = RT3833_PCI_PCIINT_PCI0;
- break;
- case RT3883_PCI_IRQ_PCI1:
- mask = RT3833_PCI_PCIINT_PCI1;
- break;
- case RT3883_PCI_IRQ_PCIE:
- mask = RT3833_PCI_PCIINT_PCIE;
- break;
- default:
- BUG();
- }
-
- t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
- rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
- /* flush write */
- rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
-}
-
-static void rt3883_pci_irq_mask(struct irq_data *d)
-{
- int irq = d->irq;
- u32 mask;
- u32 t;
-
- switch (irq) {
- case RT3883_PCI_IRQ_PCI0:
- mask = RT3833_PCI_PCIINT_PCI0;
- break;
- case RT3883_PCI_IRQ_PCI1:
- mask = RT3833_PCI_PCIINT_PCI1;
- break;
- case RT3883_PCI_IRQ_PCIE:
- mask = RT3833_PCI_PCIINT_PCIE;
- break;
- default:
- BUG();
- }
-
- t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
- rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
- /* flush write */
- rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
-}
-
-static struct irq_chip rt3883_pci_irq_chip = {
- .name = "RT3883 PCI",
- .irq_mask = rt3883_pci_irq_mask,
- .irq_unmask = rt3883_pci_irq_unmask,
- .irq_mask_ack = rt3883_pci_irq_mask,
-};
-
-static void __init rt3883_pci_irq_init(void)
-{
- int i;
-
- /* disable all interrupts */
- rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
-
- for (i = RT3883_PCI_IRQ_BASE;
- i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
- irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
- handle_level_irq);
- }
-
- irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
-}
-
-static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
-{
- unsigned long flags;
- u32 address;
- u32 data;
-
- address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where);
-
- spin_lock_irqsave(&rt3883_pci_lock, flags);
- rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
- data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
- spin_unlock_irqrestore(&rt3883_pci_lock, flags);
-
- switch (size) {
- case 1:
- *val = (data >> ((where & 3) << 3)) & 0xff;
- break;
- case 2:
- *val = (data >> ((where & 3) << 3)) & 0xffff;
- break;
- case 4:
- *val = data;
- break;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- unsigned long flags;
- u32 address;
- u32 data;
-
- address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where);
-
- spin_lock_irqsave(&rt3883_pci_lock, flags);
- rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
- data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
-
- switch (size) {
- case 1:
- data = (data & ~(0xff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- break;
- case 2:
- data = (data & ~(0xffff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- break;
- case 4:
- data = val;
- break;
- }
-
- rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
- spin_unlock_irqrestore(&rt3883_pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops rt3883_pci_ops = {
- .read = rt3883_pci_config_read,
- .write = rt3883_pci_config_write,
-};
-
-static struct resource rt3883_pci_mem_resource = {
- .name = "PCI MEM space",
- .start = RT3883_PCI_MEM_BASE,
- .end = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct resource rt3883_pci_io_resource = {
- .name = "PCI IO space",
- .start = RT3883_PCI_IO_BASE,
- .end = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
- .flags = IORESOURCE_IO,
-};
-
-static struct pci_controller rt3883_pci_controller = {
- .pci_ops = &rt3883_pci_ops,
- .mem_resource = &rt3883_pci_mem_resource,
- .io_resource = &rt3883_pci_io_resource,
-};
-
-static void rt3883_pci_preinit(unsigned mode)
-{
- u32 syscfg1;
- u32 rstctrl;
- u32 clkcfg1;
-
- if (mode & RT3883_PCI_MODE_PCIE) {
- u32 val;
-
- val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
- val &= ~(0x30);
- val |= (2 << 4);
- rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
-
- val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
- val &= ~BIT(31);
- rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
-
- val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
- val &= 0x80ffffff;
- rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
-
- val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
- val |= 0xa << 24;
- rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
-
- val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
- val |= BIT(31);
- rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
-
- msleep(50);
- }
-
- syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
- syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
- RT3883_SYSCFG1_PCI_HOST_MODE);
-
- rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
- rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
-
- clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
- clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
- RT3883_CLKCFG1_PCIE_CLK_EN);
-
- if (mode & RT3883_PCI_MODE_PCI) {
- syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
- clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
- rstctrl &= ~RT3883_RSTCTRL_PCI;
- }
- if (mode & RT3883_PCI_MODE_PCIE) {
- syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
- RT3883_SYSCFG1_PCIE_RC_MODE;
- clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
- rstctrl &= ~RT3883_RSTCTRL_PCIE;
- }
-
- rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
- rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
- rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
-
- msleep(500);
-}
-
-static int rt3883_pcie_ready(void)
-{
- u32 status;
-
- msleep(500);
-
- status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
- if (status & BIT(0))
- return 0;
-
- /* TODO: reset PCIe and turn off PCIe clock */
-
- return -ENODEV;
-}
-
-void __init rt3883_pci_init(unsigned mode)
-{
- u32 val;
- int err;
-
- rt3883_pci_preinit(mode);
-
- rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
- if (rt3883_pci_base == NULL) {
- pr_err("failed to ioremap PCI registers\n");
- return;
- }
-
- rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
- if (mode & RT3883_PCI_MODE_PCI)
- rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
-
- msleep(500);
-
- if (mode & RT3883_PCI_MODE_PCIE) {
- err = rt3883_pcie_ready();
- if (err)
- return;
- }
-
- if (mode & RT3883_PCI_MODE_PCI)
- rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
-
- rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
- rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
-
- /* PCI */
- rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
- rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
- rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
- rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
- rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
-
- /* PCIe */
- rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
- rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
- rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
- rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
- rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
-
- rt3883_pci_irq_init();
-
- /* PCIe */
- val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
- val |= 0x7;
- rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
-
- /* PCI */
- val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
- val |= 0x7;
- rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
-
- ioport_resource.start = rt3883_pci_io_resource.start;
- ioport_resource.end = rt3883_pci_io_resource.end;
-
- register_pci_controller(&rt3883_pci_controller);
-}
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq = -1;
-
- switch (dev->bus->number) {
- case 0:
- switch (PCI_SLOT(dev->devfn)) {
- case 0x00:
- rt3883_pci_wr(0x03ff0001,
- RT3883_PCI_REG_BAR0SETUP_ADDR(0));
- rt3883_pci_wr(0x03ff0001,
- RT3883_PCI_REG_BAR0SETUP_ADDR(1));
-
- rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
- RT3883_MEMORY_BASE);
- rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
-
- irq = RT3883_CPU_IRQ_PCI;
- break;
- case 0x01:
- rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
- 0x00000101);
- break;
- case 0x11:
- irq = RT3883_PCI_IRQ_PCI0;
- break;
- case 0x12:
- irq = RT3883_PCI_IRQ_PCI1;
- break;
- }
- break;
-
- case 1:
- irq = RT3883_PCI_IRQ_PCIE;
- break;
-
- default:
- dev_err(&dev->dev, "no IRQ specified\n");
- return irq;
- }
-
- return irq;
-}
-
-void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
-{
- rt3883_pci_plat_dev_init = f;
-}
-
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- if (rt3883_pci_plat_dev_init)
- return rt3883_pci_plat_dev_init(dev);
-
- return 0;
-}
+++ /dev/null
-if MIPS_RALINK
-
-choice
- prompt "Ralink SoC selection"
- default SOC_RT288X
- help
- Select Ralink MIPS SoC type.
-
- config RALINK_RT288X
- bool "RT288x"
- select SOC_RT288X
-
- config RALINK_RT305X
- bool "RT305x"
- select SOC_RT305X
-
- config RALINK_RT3883
- bool "RT3883"
- select SOC_RT3883
-
-endchoice
-
-source "arch/mips/ralink/rt288x/Kconfig"
-source "arch/mips/ralink/rt305x/Kconfig"
-source "arch/mips/ralink/rt3883/Kconfig"
-
-config SOC_RT288X
- bool
- select CEVT_R4K
- select CSRC_R4K
- select DMA_NONCOHERENT
- select IRQ_CPU
- select ARCH_REQUIRE_GPIOLIB
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_HAS_EARLY_PRINTK
- select MIPS_MACHINE
- select HAVE_CLK
-
-config SOC_RT305X
- bool
- select CEVT_R4K
- select CSRC_R4K
- select DMA_NONCOHERENT
- select IRQ_CPU
- select ARCH_REQUIRE_GPIOLIB
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_HAS_EARLY_PRINTK
- select MIPS_MACHINE
- select USB_ARCH_HAS_HCD
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
- select HAVE_CLK
-
-config SOC_RT3883
- bool
- select CEVT_R4K
- select CSRC_R4K
- select DMA_NONCOHERENT
- select IRQ_CPU
- select ARCH_REQUIRE_GPIOLIB
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_HAS_EARLY_PRINTK
- select MIPS_MACHINE
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
- select HAVE_CLK
-
-config RALINK_DEV_GPIO_BUTTONS
- def_bool n
-
-config RALINK_DEV_GPIO_LEDS
- def_bool n
-
-endif
+++ /dev/null
-#
-# Ralink SoC common stuff
-#
-core-$(CONFIG_MIPS_RALINK) += arch/mips/ralink/common/
-cflags-$(CONFIG_MIPS_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
-
-#
-# Ralink RT288x
-#
-core-$(CONFIG_RALINK_RT288X) += arch/mips/ralink/rt288x/
-cflags-$(CONFIG_RALINK_RT288X) += -I$(srctree)//arch/mips/include/asm/mach-ralink/rt288x
-load-$(CONFIG_RALINK_RT288X) += 0xffffffff88000000
-
-#
-# Ralink RT305x
-#
-core-$(CONFIG_RALINK_RT305X) += arch/mips/ralink/rt305x/
-cflags-$(CONFIG_RALINK_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
-load-$(CONFIG_RALINK_RT305X) += 0xffffffff80000000
-
-#
-# Ralink RT3883
-#
-core-$(CONFIG_RALINK_RT3883) += arch/mips/ralink/rt3883/
-cflags-$(CONFIG_RALINK_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
-load-$(CONFIG_RALINK_RT3883) += 0xffffffff80000000
+++ /dev/null
-#
-# Makefile for the Ralink common stuff
-#
-# Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License version 2 as published
-# by the Free Software Foundation.
-
-obj-y := prom.o setup.o intc.o gpio.o
-
-obj-$(CONFIG_RALINK_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
-obj-$(CONFIG_RALINK_DEV_GPIO_LEDS) += dev-gpio-leds.o
+++ /dev/null
-/*
- * Ralink SoC GPIO button support
- *
- * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include "linux/init.h"
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-
-void __init ramips_register_gpio_buttons(int id,
- unsigned poll_interval,
- unsigned nbuttons,
- struct gpio_keys_button *buttons)
-{
- struct platform_device *pdev;
- struct gpio_keys_platform_data pdata;
- struct gpio_keys_button *p;
- int err;
-
- p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
- if (!p)
- return;
-
- memcpy(p, buttons, nbuttons * sizeof(*p));
-
- pdev = platform_device_alloc("gpio-keys-polled", id);
- if (!pdev)
- goto err_free_buttons;
-
- memset(&pdata, 0, sizeof(pdata));
- pdata.poll_interval = poll_interval;
- pdata.nbuttons = nbuttons;
- pdata.buttons = p;
-
- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
- if (err)
- goto err_put_pdev;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put_pdev;
-
- return;
-
-err_put_pdev:
- platform_device_put(pdev);
-
-err_free_buttons:
- kfree(p);
-}
+++ /dev/null
-/*
- * Ralink SoC GPIO LED device support
- *
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include <asm/mach-ralink/dev-gpio-leds.h>
-
-void __init ramips_register_gpio_leds(int id, unsigned num_leds,
- struct gpio_led *leds)
-{
- struct platform_device *pdev;
- struct gpio_led_platform_data pdata;
- struct gpio_led *p;
- int err;
-
- p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
- if (!p)
- return;
-
- memcpy(p, leds, num_leds * sizeof(*p));
-
- pdev = platform_device_alloc("leds-gpio", id);
- if (!pdev)
- goto err_free_leds;
-
- memset(&pdata, 0, sizeof(pdata));
- pdata.num_leds = num_leds;
- pdata.leds = p;
-
- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
- if (err)
- goto err_put_pdev;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put_pdev;
-
- return;
-
-err_put_pdev:
- platform_device_put(pdev);
-
-err_free_leds:
- kfree(p);
-}
+++ /dev/null
-/*
- * Ralink SoC specific GPIO support
- *
- * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/mach-ralink/ramips_gpio.h>
-
-static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip)
-{
- struct ramips_gpio_chip *rg;
-
- rg = container_of(chip, struct ramips_gpio_chip, chip);
- return rg;
-}
-
-static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val)
-{
- __raw_writel(val, rg->regs_base + rg->regs[reg]);
-}
-
-static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg)
-{
- return __raw_readl(rg->regs_base + rg->regs[reg]);
-}
-
-static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
- unsigned long flags;
- u32 t;
-
- spin_lock_irqsave(&rg->lock, flags);
- t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
- t &= ~(1 << offset);
- ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
- spin_unlock_irqrestore(&rg->lock, flags);
-
- return 0;
-}
-
-static int ramips_gpio_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
- unsigned long flags;
- u32 reg;
- u32 t;
-
- reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
-
- spin_lock_irqsave(&rg->lock, flags);
- ramips_gpio_wr(rg, reg, 1 << offset);
-
- t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
- t |= 1 << offset;
- ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
- spin_unlock_irqrestore(&rg->lock, flags);
-
- return 0;
-}
-
-static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
- struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
- u32 reg;
-
- reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
- ramips_gpio_wr(rg, reg, 1 << offset);
-}
-
-static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
- u32 t;
-
- t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA);
- return !!(t & (1 << offset));
-}
-
-static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
-{
- spin_lock_init(&rg->lock);
-
- rg->regs_base = ioremap(rg->map_base, rg->map_size);
-
- rg->chip.direction_input = ramips_gpio_direction_input;
- rg->chip.direction_output = ramips_gpio_direction_output;
- rg->chip.get = ramips_gpio_get;
- rg->chip.set = ramips_gpio_set;
-
- /* set polarity to low for all lines */
- ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0);
-
- gpiochip_add(&rg->chip);
-}
-
-__init int ramips_gpio_init(struct ramips_gpio_data *data)
-{
- int i;
-
- for (i = 0; i < data->num_chips; i++)
- ramips_gpio_chip_add(&data->chips[i]);
-
- return 0;
-}
+++ /dev/null
-/*
- * Ralink SoC Interrupt controller routines
- *
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/bitops.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-
-#include <asm/mach-ralink/common.h>
-
-/* INTC register offsets */
-#define INTC_REG_STATUS0 0x00
-#define INTC_REG_STATUS1 0x04
-#define INTC_REG_TYPE 0x20
-#define INTC_REG_RAW_STATUS 0x30
-#define INTC_REG_ENABLE 0x34
-#define INTC_REG_DISABLE 0x38
-
-#define INTC_INT_GLOBAL BIT(31)
-#define INTC_IRQ_COUNT 32
-
-static unsigned int ramips_intc_irq_base;
-static void __iomem *ramips_intc_base;
-
-static inline void ramips_intc_wr(u32 val, unsigned reg)
-{
- __raw_writel(val, ramips_intc_base + reg);
-}
-
-static inline u32 ramips_intc_rr(unsigned reg)
-{
- return __raw_readl(ramips_intc_base + reg);
-}
-
-static void ramips_intc_irq_unmask(struct irq_data *d)
-{
- unsigned int irq = d->irq - ramips_intc_irq_base;
-
- ramips_intc_wr((1 << irq), INTC_REG_ENABLE);
-}
-
-static void ramips_intc_irq_mask(struct irq_data *d)
-{
- unsigned int irq = d->irq - ramips_intc_irq_base;
-
- ramips_intc_wr((1 << irq), INTC_REG_DISABLE);
-}
-
-static struct irq_chip ramips_intc_irq_chip = {
- .name = "INTC",
- .irq_unmask = ramips_intc_irq_unmask,
- .irq_mask = ramips_intc_irq_mask,
- .irq_mask_ack = ramips_intc_irq_mask,
-};
-
-static struct irqaction ramips_intc_irqaction = {
- .handler = no_action,
- .name = "cascade [INTC]",
-};
-
-void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
- unsigned irq_base)
-{
- int i;
-
- ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE);
- ramips_intc_irq_base = irq_base;
-
- /* disable all interrupts */
- ramips_intc_wr(~0, INTC_REG_DISABLE);
-
- /* route all INTC interrupts to MIPS HW0 interrupt */
- ramips_intc_wr(0, INTC_REG_TYPE);
-
- for (i = ramips_intc_irq_base;
- i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++)
- irq_set_chip_and_handler(i, &ramips_intc_irq_chip,
- handle_level_irq);
-
- setup_irq(irq, &ramips_intc_irqaction);
- ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE);
-}
-
-u32 ramips_intc_get_status(void)
-{
- return ramips_intc_rr(INTC_REG_STATUS0);
-}
+++ /dev/null
-/*
- * Ralink SoC specific prom routines
- *
- * Copyright (C) 2010 Joonas Lahtinen <joonas.lahtinen@gmail.com>
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <asm/mach-ralink/common.h>
-#include <asm/mach-ralink/machine.h>
-
-unsigned long ramips_mem_base;
-unsigned long ramips_mem_size_min;
-unsigned long ramips_mem_size_max;
-
-static inline void *to_ram_addr(void *addr)
-{
- u32 base;
-
- base = KSEG0ADDR(ramips_mem_base);
- if (((u32) addr > base) &&
- ((u32) addr < (base + ramips_mem_size_max)))
- return addr;
-
- base = KSEG1ADDR(ramips_mem_base);
- if (((u32) addr > base) &&
- ((u32) addr < (base + ramips_mem_size_max)))
- return addr;
-
- /* some U-Boot variants uses physical addresses */
- base = ramips_mem_base;
- if (((u32) addr > base) &&
- ((u32) addr < (base + ramips_mem_size_max)))
- return (void *)KSEG0ADDR(addr);
-
- return NULL;
-}
-
-static char ramips_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
-static void __init prom_append_cmdline(const char *name,
- const char *value)
-{
- snprintf(ramips_cmdline_buf, sizeof(ramips_cmdline_buf),
- " %s=%s", name, value);
- strlcat(arcs_cmdline, ramips_cmdline_buf, sizeof(arcs_cmdline));
-}
-
-#ifdef CONFIG_IMAGE_CMDLINE_HACK
-extern char __image_cmdline[];
-
-static int __init use_image_cmdline(void)
-{
- char *p = __image_cmdline;
- int replace = 0;
-
- if (*p == '-') {
- replace = 1;
- p++;
- }
-
- if (*p == '\0')
- return 0;
-
- if (replace) {
- strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
- } else {
- strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
- strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
- }
-
- return 1;
-}
-#else
-static int inline use_image_cmdline(void) { return 0; }
-#endif
-
-static __init void prom_init_cmdline(int argc, char **argv)
-{
- int i;
-
- if (use_image_cmdline())
- return;
-
- if (!argv) {
- printk(KERN_DEBUG "argv=%p is invalid, skipping\n",
- argv);
- return;
- }
-
- for (i = 0; i < argc; i++) {
- char *p = to_ram_addr(argv[i]);
-
- if (!p) {
- printk(KERN_DEBUG
- "argv[%d]=%p is invalid, skipping\n",
- i, argv[i]);
- continue;
- }
-
- printk(KERN_DEBUG "argv[%d]: %s\n", i, p);
- strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
- strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
- }
-}
-
-static __init char *prom_append_env(char **env, const char *envname)
-{
-#define PROM_MAX_ENVS 256
- int len = strlen(envname);
- int i;
-
- if (!env) {
- printk(KERN_DEBUG "env=%p is not in RAM, skipping\n",
- env);
- return NULL;
- }
-
- for (i = 0; i < PROM_MAX_ENVS; i++) {
- char *p = to_ram_addr(env[i]);
-
- if (!p)
- break;
-
- printk(KERN_DEBUG "env[%d]: %s\n", i, p);
- if (strncmp(envname, p, len) == 0 && p[len] == '=')
- prom_append_cmdline(envname, p + len + 1);
- }
-
- return NULL;
-#undef PROM_MAX_ENVS
-}
-
-void __init prom_init(void)
-{
- int argc;
- char **envp;
- char **argv;
-
- ramips_soc_prom_init();
-
- printk(KERN_DEBUG
- "prom: fw_arg0=%08x, fw_arg1=%08x, fw_arg2=%08x, fw_arg3=%08x\n",
- (unsigned int)fw_arg0, (unsigned int)fw_arg1,
- (unsigned int)fw_arg2, (unsigned int)fw_arg3);
-
- argc = fw_arg0;
- argv = to_ram_addr((void *)fw_arg1);
- prom_init_cmdline(argc, argv);
-
- envp = to_ram_addr((void *)fw_arg2);
- prom_append_env(envp, "board");
- prom_append_env(envp, "ethaddr");
-}
-
-void __init prom_free_prom_memory(void)
-{
- /* We do not have to prom memory to free */
-}
+++ /dev/null
-/*
- * Ralink SoC common setup
- *
- * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/serial_8250.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <asm/mach-ralink/common.h>
-#include <asm/mach-ralink/machine.h>
-
-unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN];
-unsigned long (*ramips_get_mem_size)(void);
-
-const char *get_system_type(void)
-{
- return ramips_sys_type;
-}
-
-static void __init detect_mem_size(void)
-{
- unsigned long size;
-
- if (ramips_get_mem_size) {
- size = ramips_get_mem_size();
- } else {
- void *base;
-
- base = (void *) KSEG1ADDR(detect_mem_size);
- for (size = ramips_mem_size_min; size < ramips_mem_size_max;
- size <<= 1 ) {
- if (!memcmp(base, base + size, 1024))
- break;
- }
- }
-
- add_memory_region(ramips_mem_base, size, BOOT_MEM_RAM);
-}
-
-void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq,
- unsigned irq)
-{
- struct uart_port p;
- int err;
-
- memset(&p, 0, sizeof(p));
- p.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
- p.iotype = UPIO_AU;
- p.uartclk = freq;
- p.regshift = 2;
- p.type = PORT_16550A;
-
- p.mapbase = base;
- p.membase = ioremap_nocache(p.mapbase, PAGE_SIZE);
- p.line = line;
- p.irq = irq;
-
- err = early_serial_setup(&p);
- if (err)
- printk(KERN_ERR "early serial%d registration failed %d\n",
- line, err);
-}
-
-void __init plat_mem_setup(void)
-{
- set_io_port_base(KSEG1);
-
- detect_mem_size();
- ramips_soc_setup();
-}
-
-__setup("board=", mips_machtype_setup);
-
-static int __init ramips_machine_setup(void)
-{
- mips_machine_setup();
- return 0;
-}
-
-arch_initcall(ramips_machine_setup);
-
-static void __init ramips_generic_init(void)
-{
-}
-
-MIPS_MACHINE(RAMIPS_MACH_GENERIC, "Generic", "Generic Ralink board",
- ramips_generic_init);
+++ /dev/null
-if RALINK_RT288X
-
-menu "Ralink RT288x machine selection"
-
-config RT288X_MACH_F5D8235_V1
- bool "Belkin F5D8235 V1 board support"
- select RALINK_DEV_GPIO_LEDS
-
-config RT288X_MACH_BR6524N
- bool "Edimax BR6524N support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT288X_MACH_RT_N15
- bool "Asus RT-N15 board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT288X_MACH_V11ST_FE
- bool "Ralink V11ST-FE board support"
- select HW_HAS_PCI
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT288X_MACH_WLI_TX4_AG300N
- bool "Buffalo WLI-TX4-AG300N board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT288X_MACH_WZR_AGL300NH
- bool "Buffalo WZR-AGL300NH board support"
- select RALINK_DEV_GPIO_LEDS
-
-endmenu
-
-endif
+++ /dev/null
-#
-# Makefile for the Ralink RT288x SoC specific parts of the kernel
-#
-# Copyright (C) 2010 Joonas Lahtinen <joonas.lahtinen@gmail.com>
-# Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-# Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License version 2 as published
-# by the Free Software Foundation.
-
-obj-y := irq.o setup.o rt288x.o devices.o clock.o
-
-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
-obj-$(CONFIG_RT288X_MACH_F5D8235_V1) += mach-f5d8235-v1.o
-obj-$(CONFIG_RT288X_MACH_BR6524N) += mach-br6524n.o
-obj-$(CONFIG_RT288X_MACH_RT_N15) += mach-rt-n15.o
-obj-$(CONFIG_RT288X_MACH_V11ST_FE) += mach-v11st-fe.o
-obj-$(CONFIG_RT288X_MACH_WLI_TX4_AG300N) += mach-wli-tx4-ag300n.o
-obj-$(CONFIG_RT288X_MACH_WZR_AGL300NH) += mach-wzr-agl300nh.o
+++ /dev/null
-/*
- * Ralink RT288X clock API
- *
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-
-#include <asm/mach-ralink/common.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-#include "common.h"
-
-struct clk {
- unsigned long rate;
-};
-
-static struct clk rt288x_cpu_clk;
-static struct clk rt288x_sys_clk;
-static struct clk rt288x_wdt_clk;
-static struct clk rt288x_uart_clk;
-
-void __init rt288x_clocks_init(void)
-{
- u32 t;
-
- t = rt288x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
- t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
-
- switch (t) {
- case SYSTEM_CONFIG_CPUCLK_250:
- rt288x_cpu_clk.rate = 250000000;
- break;
- case SYSTEM_CONFIG_CPUCLK_266:
- rt288x_cpu_clk.rate = 266666667;
- break;
- case SYSTEM_CONFIG_CPUCLK_280:
- rt288x_cpu_clk.rate = 280000000;
- break;
- case SYSTEM_CONFIG_CPUCLK_300:
- rt288x_cpu_clk.rate = 300000000;
- break;
- }
-
- rt288x_sys_clk.rate = rt288x_cpu_clk.rate / 2;
- rt288x_uart_clk.rate = rt288x_sys_clk.rate;
- rt288x_wdt_clk.rate = rt288x_sys_clk.rate;
-}
-
-/*
- * Linux clock API
- */
-struct clk *clk_get(struct device *dev, const char *id)
-{
- if (!strcmp(id, "sys"))
- return &rt288x_sys_clk;
-
- if (!strcmp(id, "cpu"))
- return &rt288x_cpu_clk;
-
- if (!strcmp(id, "wdt"))
- return &rt288x_wdt_clk;
-
- if (!strcmp(id, "uart"))
- return &rt288x_uart_clk;
-
- return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
+++ /dev/null
-/*
- * Ralink RT288X SoC common defines
- *
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT288X_COMMON_H
-#define _RT288X_COMMON_H
-
-void rt288x_clocks_init(void);
-
-#endif /* _RT288X_COMMON_H */
\ No newline at end of file
+++ /dev/null
-/*
- * Ralink RT288x SoC platform device registration
- *
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/etherdevice.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/rt2x00_platform.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-#include <asm/mach-ralink/ramips_eth_platform.h>
-
-#include "devices.h"
-
-static struct resource rt288x_flash0_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = KSEG1ADDR(RT2880_FLASH0_BASE),
- .end = KSEG1ADDR(RT2880_FLASH0_BASE) +
- RT2880_FLASH0_SIZE - 1,
- },
-};
-
-struct physmap_flash_data rt288x_flash0_data;
-static struct platform_device rt288x_flash0_device = {
- .name = "physmap-flash",
- .resource = rt288x_flash0_resources,
- .num_resources = ARRAY_SIZE(rt288x_flash0_resources),
- .dev = {
- .platform_data = &rt288x_flash0_data,
- },
-};
-
-static struct resource rt288x_flash1_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = KSEG1ADDR(RT2880_FLASH1_BASE),
- .end = KSEG1ADDR(RT2880_FLASH1_BASE) +
- RT2880_FLASH1_SIZE - 1,
- },
-};
-
-struct physmap_flash_data rt288x_flash1_data;
-static struct platform_device rt288x_flash1_device = {
- .name = "physmap-flash",
- .resource = rt288x_flash1_resources,
- .num_resources = ARRAY_SIZE(rt288x_flash1_resources),
- .dev = {
- .platform_data = &rt288x_flash1_data,
- },
-};
-
-static int rt288x_flash_instance __initdata;
-void __init rt288x_register_flash(unsigned int id)
-{
- struct platform_device *pdev;
- struct physmap_flash_data *pdata;
- u32 t;
- int reg;
-
- switch (id) {
- case 0:
- pdev = &rt288x_flash0_device;
- reg = MEMC_REG_FLASH_CFG0;
- break;
- case 1:
- pdev = &rt288x_flash1_device;
- reg = MEMC_REG_FLASH_CFG1;
- break;
- default:
- return;
- }
-
- t = rt288x_memc_rr(reg);
- t = (t >> FLASH_CFG_WIDTH_SHIFT) & FLASH_CFG_WIDTH_MASK;
-
- pdata = pdev->dev.platform_data;
- switch (t) {
- case FLASH_CFG_WIDTH_8BIT:
- pdata->width = 1;
- break;
- case FLASH_CFG_WIDTH_16BIT:
- pdata->width = 2;
- break;
- case FLASH_CFG_WIDTH_32BIT:
- pdata->width = 4;
- break;
- default:
- printk(KERN_ERR "RT288x: flash bank%u witdh is invalid\n", id);
- return;
- }
-
- pdev->id = rt288x_flash_instance;
-
- platform_device_register(pdev);
- rt288x_flash_instance++;
-}
-
-static struct resource rt288x_wifi_resources[] = {
- {
- .start = RT2880_WMAC_BASE,
- .end = RT2880_WMAC_BASE + 0x3FFFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = RT288X_CPU_IRQ_WNIC,
- .end = RT288X_CPU_IRQ_WNIC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct rt2x00_platform_data rt288x_wifi_data;
-static struct platform_device rt288x_wifi_device = {
- .name = "rt2800_wmac",
- .resource = rt288x_wifi_resources,
- .num_resources = ARRAY_SIZE(rt288x_wifi_resources),
- .dev = {
- .platform_data = &rt288x_wifi_data,
- }
-};
-
-void __init rt288x_register_wifi(void)
-{
- rt288x_wifi_data.eeprom_file_name = "soc_wmac.eeprom";
- platform_device_register(&rt288x_wifi_device);
-}
-
-static void rt288x_fe_reset(void)
-{
- rt288x_sysc_wr(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
-}
-
-static struct resource rt288x_eth_resources[] = {
- {
- .start = RT2880_FE_BASE,
- .end = RT2880_FE_BASE + PAGE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = RT288X_CPU_IRQ_FE,
- .end = RT288X_CPU_IRQ_FE,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct ramips_eth_platform_data rt288x_eth_data;
-static struct platform_device rt288x_eth_device = {
- .name = "ramips_eth",
- .resource = rt288x_eth_resources,
- .num_resources = ARRAY_SIZE(rt288x_eth_resources),
- .dev = {
- .platform_data = &rt288x_eth_data,
- }
-};
-
-void __init rt288x_register_ethernet(void)
-{
- struct clk *clk;
-
- clk = clk_get(NULL, "sys");
- if (IS_ERR(clk))
- panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
-
- rt288x_eth_data.sys_freq = clk_get_rate(clk);
- rt288x_eth_data.reset_fe = rt288x_fe_reset;
- rt288x_eth_data.min_pkt_len = 64;
-
- if (!is_valid_ether_addr(rt288x_eth_data.mac))
- random_ether_addr(rt288x_eth_data.mac);
-
- platform_device_register(&rt288x_eth_device);
-}
-
-static struct resource rt288x_wdt_resources[] = {
- {
- .start = RT2880_TIMER_BASE,
- .end = RT2880_TIMER_BASE + RT2880_TIMER_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device rt288x_wdt_device = {
- .name = "ramips-wdt",
- .id = -1,
- .resource = rt288x_wdt_resources,
- .num_resources = ARRAY_SIZE(rt288x_wdt_resources),
-};
-
-void __init rt288x_register_wdt(void)
-{
- u32 t;
-
- /* enable WDT reset output on pin SRAM_CS_N */
- t = rt288x_sysc_rr(SYSC_REG_CLKCFG);
- t |= CLKCFG_SRAM_CS_N_WDT;
- rt288x_sysc_wr(t, SYSC_REG_CLKCFG);
-
- platform_device_register(&rt288x_wdt_device);
-}
+++ /dev/null
-/*
- * Ralink RT288x SoC specific platform definitions
- *
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_RT288X_PLATFORM_H
-#define __ASM_MACH_RT288X_PLATFORM_H
-
-struct physmap_flash_data;
-
-extern struct physmap_flash_data rt288x_flash0_data;
-extern struct physmap_flash_data rt288x_flash1_data;
-void rt288x_register_flash(unsigned int id);
-
-void rt288x_register_wifi(void);
-
-extern struct ramips_eth_platform_data rt288x_eth_data;
-void rt288x_register_ethernet(void);
-
-void rt288x_register_wdt(void);
-
-#endif /* __ASM_MACH_RT288X_PLATFORM_H */
+++ /dev/null
-/*
- * Ralink RT288x SoC early printk support
- *
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/serial_reg.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mach-ralink/rt288x_regs.h>
-
-#define UART_READ(r) \
- __raw_readl((void __iomem *)(KSEG1ADDR(RT2880_UART1_BASE) + 4 * (r)))
-
-#define UART_WRITE(r, v) \
- __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT2880_UART1_BASE) + 4 * (r)))
-
-void prom_putchar(unsigned char ch)
-{
- while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0);
- UART_WRITE(UART_REG_TX, ch);
- while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0);
-}
+++ /dev/null
-/*
- * Ralink RT288x SoC specific interrupt handling
- *
- * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-
-#include <asm/mach-ralink/common.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-
-static void rt288x_intc_irq_dispatch(void)
-{
- u32 pending;
-
- pending = ramips_intc_get_status();
-
- if (pending & RT2880_INTC_INT_TIMER0)
- do_IRQ(RT2880_INTC_IRQ_TIMER0);
-
- else if (pending & RT2880_INTC_INT_TIMER1)
- do_IRQ(RT2880_INTC_IRQ_TIMER1);
-
- else if (pending & RT2880_INTC_INT_UART0)
- do_IRQ(RT2880_INTC_IRQ_UART0);
-
- else if (pending & RT2880_INTC_INT_PCM)
- do_IRQ(RT2880_INTC_IRQ_PCM);
-
- else if (pending & RT2880_INTC_INT_UART1)
- do_IRQ(RT2880_INTC_IRQ_UART1);
-
- /* TODO: handle PIO interrupts as well */
-
- else
- spurious_interrupt();
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned long pending;
-
- pending = read_c0_status() & read_c0_cause() & ST0_IM;
-
- if (pending & STATUSF_IP7)
- do_IRQ(RT288X_CPU_IRQ_COUNTER);
-
- else if (pending & STATUSF_IP4)
- do_IRQ(RT288X_CPU_IRQ_PCI);
-
- else if (pending & STATUSF_IP5)
- do_IRQ(RT288X_CPU_IRQ_FE);
-
- else if (pending & STATUSF_IP6)
- do_IRQ(RT288X_CPU_IRQ_WNIC);
-
- else if (pending & STATUSF_IP2)
- rt288x_intc_irq_dispatch();
-
- else
- spurious_interrupt();
-}
-
-void __init arch_init_irq(void)
-{
- mips_cpu_irq_init();
- ramips_intc_irq_init(RT2880_INTC_BASE, RT288X_CPU_IRQ_INTC,
- RT288X_INTC_IRQ_BASE);
-}
+++ /dev/null
-/*
- * Edimax BR6524N board support
- *
- * Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ethtool.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-#include <asm/mach-ralink/ramips_eth_platform.h>
-
-#include "devices.h"
-
-#define BR6524N_GPIO_STATUS_LED 12
-#define BR6524N_GPIO_BUTTON_WPS 0
-
-#define BR6524N_KEYS_POLL_INTERVAL 20
-#define BR6524N_KEYS_DEBOUNCE_INTERVAL (3 * BR6524N_KEYS_POLL_INTERVAL)
-
-static struct gpio_led br6524n_leds_gpio[] __initdata = {
- {
- .name = "br6524n:green:status",
- .gpio = BR6524N_GPIO_STATUS_LED,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button br6524n_gpio_buttons[] __initdata = {
- {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = BR6524N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = BR6524N_GPIO_BUTTON_WPS,
- }
-};
-
-static void __init br6524n_fe_init(void)
-{
- rt288x_gpio_init(RT2880_GPIO_MODE_UART0);
-
- rt288x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(br6524n_leds_gpio),
- br6524n_leds_gpio);
-
- ramips_register_gpio_buttons(-1, BR6524N_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(br6524n_gpio_buttons),
- br6524n_gpio_buttons);
-
- rt288x_register_wifi();
-
- /* Board is connected to an IC+ IP175C Fast Ethernet switch */
- rt288x_eth_data.speed = SPEED_100;
- rt288x_eth_data.duplex = DUPLEX_FULL;
- rt288x_eth_data.tx_fc = 1;
- rt288x_eth_data.rx_fc = 1;
- rt288x_eth_data.phy_mask = BIT(0);
- rt288x_register_ethernet();
-
- rt288x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_BR6524N, "BR6524N", "Edimax BR6524N", br6524n_fe_init);
+++ /dev/null
-/*
- * Belkin F5D825 V1 board support
- *
- * Copyright (C) 2011 Cezary Jackiewicz <cezary.jackiewicz@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-
-#include "devices.h"
-
-#include <linux/rtl8366.h>
-#include <linux/ethtool.h>
-
-#include <asm/mach-ralink/ramips_eth_platform.h>
-
-#define F5D8235_GPIO_RTL8366_SCK 2
-#define F5D8235_GPIO_RTL8366_SDA 1
-
-#define F5D8235_GPIO_LED_USB_BLUE 7
-#define F5D8235_GPIO_LED_USB_ORANGE 8
-#define F5D8235_GPIO_BUTTON_WPS 0
-#define F5D8235_GPIO_BUTTON_RESET 9
-
-#define F5D8235_KEYS_POLL_INTERVAL 20
-#define F5D8235_KEYS_DEBOUNCE_INTERVAL (3 * F5D8235_KEYS_POLL_INTERVAL)
-
-static struct rtl8366_platform_data f5d8235_rtl8366s_data = {
- .gpio_sda = F5D8235_GPIO_RTL8366_SDA,
- .gpio_sck = F5D8235_GPIO_RTL8366_SCK,
-};
-
-static struct platform_device f5d8235_rtl8366s_device = {
- .name = RTL8366S_DRIVER_NAME,
- .id = -1,
- .dev = {
- .platform_data = &f5d8235_rtl8366s_data,
- }
-};
-
-static struct gpio_led f5d8235_leds_gpio[] __initdata = {
- {
- .name = "f5d8235-v1:blue:storage",
- .gpio = F5D8235_GPIO_LED_USB_BLUE,
- .active_low = 1,
- },{
- .name = "f5d8235-v1:orange:storage",
- .gpio = F5D8235_GPIO_LED_USB_ORANGE,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button f5d8235_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = F5D8235_KEYS_DEBOUNCE_INTERVAL,
- .gpio = F5D8235_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = F5D8235_KEYS_DEBOUNCE_INTERVAL,
- .gpio = F5D8235_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static void __init f5d8235_init(void)
-{
- rt288x_gpio_init(RT2880_GPIO_MODE_UART0 | RT2880_GPIO_MODE_I2C);
-
- rt288x_register_flash(0);
- rt288x_register_wifi();
- rt288x_register_wdt();
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(f5d8235_leds_gpio),
- f5d8235_leds_gpio);
-
- ramips_register_gpio_buttons(-1, F5D8235_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(f5d8235_gpio_buttons),
- f5d8235_gpio_buttons);
-
- platform_device_register(&f5d8235_rtl8366s_device);
-
- rt288x_eth_data.speed = SPEED_1000;
- rt288x_eth_data.duplex = DUPLEX_FULL;
- rt288x_eth_data.tx_fc = 1;
- rt288x_eth_data.rx_fc = 1;
- rt288x_register_ethernet();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_F5D8235_V1, "F5D8235_V1",
- "Belkin F5D8235 v1", f5d8235_init);
+++ /dev/null
-/*
- * Asus RT-N15 board support
- *
- * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/rtl8366.h>
-#include <linux/ethtool.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-#include <asm/mach-ralink/ramips_eth_platform.h>
-
-#include "devices.h"
-
-#define RT_N15_GPIO_LED_POWER 11
-#define RT_N15_GPIO_BUTTON_WPS 0
-#define RT_N15_GPIO_BUTTON_RESET 12
-
-#define RT_N15_GPIO_RTL8366_SCK 2
-#define RT_N15_GPIO_RTL8366_SDA 1
-
-#define RT_N15_KEYS_POLL_INTERVAL 20
-#define RT_N15_KEYS_DEBOUNCE_INTERVAL (3 * RT_N15_KEYS_POLL_INTERVAL)
-
-static struct gpio_led rt_n15_leds_gpio[] __initdata = {
- {
- .name = "rt-n15:blue:power",
- .gpio = RT_N15_GPIO_LED_POWER,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button rt_n15_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = RT_N15_KEYS_DEBOUNCE_INTERVAL,
- .gpio = RT_N15_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = RT_N15_KEYS_DEBOUNCE_INTERVAL,
- .gpio = RT_N15_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static struct rtl8366_platform_data rt_n15_rtl8366s_data = {
- .gpio_sda = RT_N15_GPIO_RTL8366_SDA,
- .gpio_sck = RT_N15_GPIO_RTL8366_SCK,
-};
-
-static struct platform_device rt_n15_rtl8366s_device = {
- .name = RTL8366S_DRIVER_NAME,
- .id = -1,
- .dev = {
- .platform_data = &rt_n15_rtl8366s_data,
- }
-};
-
-static void __init rt_n15_init(void)
-{
- rt288x_gpio_init(RT2880_GPIO_MODE_UART0 | RT2880_GPIO_MODE_I2C);
-
- rt288x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n15_leds_gpio),
- rt_n15_leds_gpio);
-
- ramips_register_gpio_buttons(-1, RT_N15_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(rt_n15_gpio_buttons),
- rt_n15_gpio_buttons);
-
- platform_device_register(&rt_n15_rtl8366s_device);
-
- rt288x_register_wifi();
-
- rt288x_eth_data.speed = SPEED_1000;
- rt288x_eth_data.duplex = DUPLEX_FULL;
- rt288x_eth_data.tx_fc = 1;
- rt288x_eth_data.rx_fc = 1;
- rt288x_register_ethernet();
- rt288x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_RT_N15, "RT-N15", "Asus RT-N15", rt_n15_init);
+++ /dev/null
-/*
- * Ralink V11ST-FE board support
- *
- * Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ethtool.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-#include <asm/mach-ralink/ramips_eth_platform.h>
-
-#include "devices.h"
-
-#define V11ST_FE_GPIO_STATUS_LED 12
-#define V11ST_FE_GPIO_BUTTON_WPS 0
-
-#define V11ST_FE_KEYS_POLL_INTERVAL 20
-#define V11ST_FE_KEYS_DEBOUNCE_INTERVAL (3 * V11ST_FE_KEYS_POLL_INTERVAL)
-
-static struct gpio_led v11st_fe_leds_gpio[] __initdata = {
- {
- .name = "v11st-fe:green:status",
- .gpio = V11ST_FE_GPIO_STATUS_LED,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button v11st_fe_gpio_buttons[] __initdata = {
- {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = V11ST_FE_KEYS_DEBOUNCE_INTERVAL,
- .gpio = V11ST_FE_GPIO_BUTTON_WPS,
- }
-};
-
-static void __init rt_v11st_fe_init(void)
-{
- rt288x_gpio_init(RT2880_GPIO_MODE_UART0);
-
- rt288x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(v11st_fe_leds_gpio),
- v11st_fe_leds_gpio);
-
- ramips_register_gpio_buttons(-1, V11ST_FE_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(v11st_fe_gpio_buttons),
- v11st_fe_gpio_buttons);
-
- rt288x_register_wifi();
-
- /* Board is connected to an IC+ IP175C Fast Ethernet switch */
- rt288x_eth_data.speed = SPEED_100;
- rt288x_eth_data.duplex = DUPLEX_FULL;
- rt288x_eth_data.tx_fc = 1;
- rt288x_eth_data.rx_fc = 1;
- rt288x_eth_data.phy_mask = BIT(0);
- rt288x_register_ethernet();
-
- rt288x_register_wdt();
- rt288x_register_pci();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_V11ST_FE, "V11ST-FE", "Ralink V11ST-FE", rt_v11st_fe_init);
+++ /dev/null
-/*
- * Buffalo WLI-TX4-AG300N board support
- *
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/ethtool.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-#include <asm/mach-ralink/ramips_eth_platform.h>
-
-#include "devices.h"
-
-#define WLI_TX4_AG300N_GPIO_LED_DIAG 10
-#define WLI_TX4_AG300N_GPIO_LED_POWER 12
-#define WLI_TX4_AG300N_GPIO_LED_SECURITY 13
-
-#define WLI_TX4_AG300N_GPIO_BUTTON_AOSS 0
-#define WLI_TX4_AG300N_GPIO_BUTTON_BW_SWITCH 8
-#define WLI_TX4_AG300N_GPIO_BUTTON_RESET 9
-
-#define WLI_TX4_AG300N_KEYS_POLL_INTERVAL 20
-#define WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL (3 * WLI_TX4_AG300N_KEYS_POLL_INTERVAL)
-
-static struct gpio_led wli_tx4_ag300n_leds_gpio[] __initdata = {
- {
- .name = "buffalo:blue:power",
- .gpio = WLI_TX4_AG300N_GPIO_LED_POWER,
- .active_low = 1,
- },
- {
- .name = "buffalo:red:diag",
- .gpio = WLI_TX4_AG300N_GPIO_LED_DIAG,
- .active_low = 1,
- },
- {
- .name = "buffalo:blue:security",
- .gpio = WLI_TX4_AG300N_GPIO_LED_SECURITY,
- .active_low = 0,
- },
-};
-
-static struct gpio_keys_button wli_tx4_ag300n_gpio_buttons[] __initdata = {
- {
- .desc = "Reset button",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = WLI_TX4_AG300N_GPIO_BUTTON_RESET,
- .active_low = 1,
- },
- {
- .desc = "AOSS button",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = WLI_TX4_AG300N_GPIO_BUTTON_AOSS,
- .active_low = 1,
- },
- {
- .desc = "Bandwidth switch",
- .type = EV_KEY,
- .code = BTN_0,
- .debounce_interval = WLI_TX4_AG300N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = WLI_TX4_AG300N_GPIO_BUTTON_BW_SWITCH,
- .active_low = 0,
- },
-};
-
-static void __init wli_tx4_ag300n_init(void)
-{
- rt288x_gpio_init(RT2880_GPIO_MODE_UART0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(wli_tx4_ag300n_leds_gpio),
- wli_tx4_ag300n_leds_gpio);
- ramips_register_gpio_buttons(-1, WLI_TX4_AG300N_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(wli_tx4_ag300n_gpio_buttons),
- wli_tx4_ag300n_gpio_buttons);
-
- rt288x_register_flash(0);
- rt288x_register_wifi();
- rt288x_register_wdt();
-
- rt288x_eth_data.speed = SPEED_100;
- rt288x_eth_data.duplex = DUPLEX_FULL;
- rt288x_eth_data.tx_fc = 1;
- rt288x_eth_data.rx_fc = 1;
- rt288x_register_ethernet();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_WLI_TX4_AG300N, "WLI-TX4-AG300N",
- "Buffalo WLI-TX4-AG300N", wli_tx4_ag300n_init);
+++ /dev/null
-/*
- * Buffalo WZR-AGL300NH board support
- *
- * Copyright (C) 2010 Joonas Lahtinen <joonas.lahtinen@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-
-#include "devices.h"
-
-/*
- * MTD layout from stock firmware:
- * mtd0: 00030000 00010000 "uboot"
- * mtd1: 00010000 00010000 "uboot_environ"
- * mtd2: 00010000 00010000 "factory_default"
- * mtd3: 000b0000 00010000 "linux"
- * mtd4: 002f0000 00010000 "rootfs"
- * mtd5: 00010000 00010000 "user_property"
- */
-
-static struct mtd_partition wzr_agl300nh_partitions[] = {
- {
- .name = "uboot",
- .offset = 0,
- .size = 0x030000,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "uboot_environ",
- .offset = 0x030000,
- .size = 0x010000,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "factory_default",
- .offset = 0x040000,
- .size = 0x010000,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "linux",
- .offset = 0x050000,
- .size = 0x0b0000,
- }, {
- .name = "rootfs",
- .offset = 0x100000,
- .size = 0x2f0000,
- }, {
- .name = "user_property",
- .offset = 0x3f0000,
- .size = 0x010000,
- }
-};
-
-static void __init wzr_agl300nh_init(void)
-{
- rt288x_gpio_init(RT2880_GPIO_MODE_UART0);
-
- rt288x_flash0_data.nr_parts = ARRAY_SIZE(wzr_agl300nh_partitions);
- rt288x_flash0_data.parts = wzr_agl300nh_partitions;
- rt288x_register_flash(0);
-
- rt288x_register_wifi();
- rt288x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_WZR_AGL300NH, "WZR-AGL300NH",
- "Buffalo WZR-AGL300NH", wzr_agl300nh_init);
+++ /dev/null
-/*
- * Ralink RT288x SoC specific setup
- *
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Ralink's 2.6.21 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-
-#include <asm/mach-ralink/common.h>
-#include <asm/mach-ralink/ramips_gpio.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-
-void __iomem * rt288x_sysc_base;
-void __iomem * rt288x_memc_base;
-
-void __init ramips_soc_prom_init(void)
-{
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
- u32 n0;
- u32 n1;
- u32 id;
-
- n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
- n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
- id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
-
- snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
- "Ralink %c%c%c%c%c%c%c%c id:%u rev:%u",
- (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
- (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
- (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
- (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
- (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
- (id & CHIP_ID_REV_MASK));
-
- ramips_mem_base = RT2880_SDRAM_BASE;
- ramips_mem_size_min = RT288X_MEM_SIZE_MIN;
- ramips_mem_size_max = RT288X_MEM_SIZE_MAX;
-}
-
-static struct ramips_gpio_chip rt288x_gpio_chips[] = {
- {
- .chip = {
- .label = "RT288X-GPIO0",
- .base = 0,
- .ngpio = 24,
- },
- .regs = {
- [RAMIPS_GPIO_REG_INT] = 0x00,
- [RAMIPS_GPIO_REG_EDGE] = 0x04,
- [RAMIPS_GPIO_REG_RENA] = 0x08,
- [RAMIPS_GPIO_REG_FENA] = 0x0c,
- [RAMIPS_GPIO_REG_DATA] = 0x20,
- [RAMIPS_GPIO_REG_DIR] = 0x24,
- [RAMIPS_GPIO_REG_POL] = 0x28,
- [RAMIPS_GPIO_REG_SET] = 0x2c,
- [RAMIPS_GPIO_REG_RESET] = 0x30,
- [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
- },
- .map_base = RT2880_PIO_BASE,
- .map_size = RT2880_PIO_SIZE,
- },
- {
- .chip = {
- .label = "RT288X-GPIO1",
- .base = 24,
- .ngpio = 16,
- },
- .regs = {
- [RAMIPS_GPIO_REG_INT] = 0x38,
- [RAMIPS_GPIO_REG_EDGE] = 0x3c,
- [RAMIPS_GPIO_REG_RENA] = 0x40,
- [RAMIPS_GPIO_REG_FENA] = 0x44,
- [RAMIPS_GPIO_REG_DATA] = 0x48,
- [RAMIPS_GPIO_REG_DIR] = 0x4c,
- [RAMIPS_GPIO_REG_POL] = 0x50,
- [RAMIPS_GPIO_REG_SET] = 0x54,
- [RAMIPS_GPIO_REG_RESET] = 0x58,
- [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
- },
- .map_base = RT2880_PIO_BASE,
- .map_size = RT2880_PIO_SIZE,
- },
- {
- .chip = {
- .label = "RT288X-GPIO2",
- .base = 40,
- .ngpio = 32,
- },
- .regs = {
- [RAMIPS_GPIO_REG_INT] = 0x60,
- [RAMIPS_GPIO_REG_EDGE] = 0x64,
- [RAMIPS_GPIO_REG_RENA] = 0x68,
- [RAMIPS_GPIO_REG_FENA] = 0x6c,
- [RAMIPS_GPIO_REG_DATA] = 0x70,
- [RAMIPS_GPIO_REG_DIR] = 0x74,
- [RAMIPS_GPIO_REG_POL] = 0x78,
- [RAMIPS_GPIO_REG_SET] = 0x7c,
- [RAMIPS_GPIO_REG_RESET] = 0x80,
- [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
- },
- .map_base = RT2880_PIO_BASE,
- .map_size = RT2880_PIO_SIZE,
- },
-};
-
-static struct ramips_gpio_data rt288x_gpio_data = {
- .chips = rt288x_gpio_chips,
- .num_chips = ARRAY_SIZE(rt288x_gpio_chips),
-};
-
-static void rt288x_gpio_reserve(int first, int last)
-{
- for (; first <= last; first++)
- gpio_request(first, "reserved");
-}
-
-void __init rt288x_gpio_init(u32 mode)
-{
- rt288x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
-
- ramips_gpio_init(&rt288x_gpio_data);
- if ((mode & RT2880_GPIO_MODE_I2C) == 0)
- rt288x_gpio_reserve(1, 2);
-
- if ((mode & RT2880_GPIO_MODE_SPI) == 0)
- rt288x_gpio_reserve(3, 6);
-
- if ((mode & RT2880_GPIO_MODE_UART0) == 0)
- rt288x_gpio_reserve(7, 14);
-
- if ((mode & RT2880_GPIO_MODE_JTAG) == 0)
- rt288x_gpio_reserve(17, 21);
-
- if ((mode & RT2880_GPIO_MODE_MDIO) == 0)
- rt288x_gpio_reserve(22, 23);
-
- if ((mode & RT2880_GPIO_MODE_SDRAM) == 0)
- rt288x_gpio_reserve(24, 39);
-
- if ((mode & RT2880_GPIO_MODE_PCI) == 0)
- rt288x_gpio_reserve(40, 71);
-}
+++ /dev/null
-/*
- * Ralink RT288x SoC specific setup
- *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Ralink's 2.6.21 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-
-#include <asm/mips_machine.h>
-#include <asm/reboot.h>
-#include <asm/time.h>
-
-#include <asm/mach-ralink/common.h>
-#include <asm/mach-ralink/rt288x.h>
-#include <asm/mach-ralink/rt288x_regs.h>
-#include "common.h"
-
-static void rt288x_restart(char *command)
-{
- rt288x_sysc_wr(RT2880_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
- while (1)
- if (cpu_wait)
- cpu_wait();
-}
-
-static void rt288x_halt(void)
-{
- while (1)
- cpu_wait();
-}
-
-unsigned int __cpuinit get_c0_compare_irq(void)
-{
- return CP0_LEGACY_COMPARE_IRQ;
-}
-
-void __init ramips_soc_setup(void)
-{
- struct clk *clk;
-
- rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE);
- rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE);
-
- rt288x_clocks_init();
-
- clk = clk_get(NULL, "cpu");
- if (IS_ERR(clk))
- panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
-
- printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
- clk_get_rate(clk) / 1000000,
- (clk_get_rate(clk) % 1000000) * 100 / 1000000);
-
- _machine_restart = rt288x_restart;
- _machine_halt = rt288x_halt;
- pm_power_off = rt288x_halt;
-
- clk = clk_get(NULL, "uart");
- if (IS_ERR(clk))
- panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
-
- ramips_early_serial_setup(0, RT2880_UART0_BASE, clk_get_rate(clk),
- RT2880_INTC_IRQ_UART0);
- ramips_early_serial_setup(1, RT2880_UART1_BASE, clk_get_rate(clk),
- RT2880_INTC_IRQ_UART1);
-}
-
-void __init plat_time_init(void)
-{
- struct clk *clk;
-
- clk = clk_get(NULL, "cpu");
- if (IS_ERR(clk))
- panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
-
- mips_hpt_frequency = clk_get_rate(clk) / 2;
-}
+++ /dev/null
-if RALINK_RT305X
-
-menu "Ralink RT350x machine selection"
-
-config RT305X_MACH_CARAMBOLA
- bool "8devices Carambola dev board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_3G_6200N
- bool "Edimax 3G-6200N board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_3G300M
- bool "Tenda 3G300M board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_BR6425
- bool "Edimax BR-6425 board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_WR6202
- bool "Accton WR6202"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_AIR3GII
- bool "AirLive Air3GII board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_ALL0256N
- bool "Allnet ALL0256N support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_ALL5002
- bool "Allnet ALL5002 support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_W502U
- bool "ALFA Networks W502U board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_ARGUS_ATP52B
- bool "Argus ATP-52B support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_RT_G32_REVB
- bool "Asus RT-G32 revB board support"
- select RALINK_DEV_GPIO_BUTTONS
-
-config RT305X_MACH_RT_N10_PLUS
- bool "Asus RT-N10+ board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_WL_330N
- bool "Asus WL-330N board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_WL_330N3G
- bool "Asus WL-330N3G board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_HW550_3G
- bool "Aztech HW550-3G support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_F5D8235_V2
- bool "Belkin F5D8235 v2 support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_WHR_G300N
- bool "Buffalo WHR-G300N support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_DIR_300_REVB
- bool "D-Link DIR-300 revB board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_DIR_615_H1
- bool "D-Link DIR-615 H1 board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_DAP_1350
- bool "D-Link DAP-1350 board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_ESR_9753
- bool "EnGenius ESR-9753 support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_BROADWAY
- bool "Hauppauge Broadway support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_FONERA20N
- bool "La Fonera20N board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_RT_N13U
- bool "ASUS RT-N13U board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_FREESTATION5
- bool "ARC FreeStation5"
-
-config RT305X_MACH_MOFI3500_3GN
- bool "MoFi Network MOFI3500-3GN support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_WR512_3GN
- bool "SH-WR512NU/WS-WR512N1-like 3GN router"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_UR_326N4G
- bool "UR-326N4G Wireless N router"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_UR_336UN
- bool "UR-336UN Wireless N router"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_NW718
- bool "Netcore NW718"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_BC2
- bool "NexAira BC2"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_OMNI_EMB
- bool "Omnima MiniEMBWiFi"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_PSR_680W
- bool "Petatel PSR-680W Wireless 3G Router support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_PWH2004
- bool "Prolink PWH2004 / Abocom WR5205 support (32M RAM, 8M flash)"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_V22RW_2X2
- bool "Ralink AP-RT3052-V22RW-2X2 board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_W306R_V20
- bool "Tenda W306R V2.0 board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_WL341V3
- bool "Sitecom WL-341 v3 board support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_WL351
- bool "Sitecom WL-351 support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_SL_R7205
- bool "Skyline SL-R7205 Wireless 3G Router support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_WCR150GN
- bool "Sparklan WCR-150GN support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_NBG_419N
- bool "ZyXEL NBG-419N support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_MZKW300NH2
- bool "Planex MZK-W300NH2 Router support"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-config RT305X_MACH_XDX_RN502J
- bool "Unknown board XDX-RN502J"
- select RALINK_DEV_GPIO_BUTTONS
- select RALINK_DEV_GPIO_LEDS
-
-endmenu
-
-endif
+++ /dev/null
-#
-# Makefile for the Ralink RT305x SoC specific parts of the kernel
-#
-# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License version 2 as published
-# by the Free Software Foundation.
-
-obj-y := irq.o setup.o devices.o rt305x.o clock.o
-
-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
-obj-$(CONFIG_RT305X_MACH_3G_6200N) += mach-3g-6200n.o
-obj-$(CONFIG_RT305X_MACH_3G300M) += mach-3g300m.o
-obj-$(CONFIG_RT305X_MACH_ARGUS_ATP52B) += mach-argus-atp52b.o
-obj-$(CONFIG_RT305X_MACH_BC2) += mach-bc2.o
-obj-$(CONFIG_RT305X_MACH_AIR3GII) += mach-air3gii.o
-obj-$(CONFIG_RT305X_MACH_ALL0256N) += mach-all0256n.o
-obj-$(CONFIG_RT305X_MACH_ALL5002) += mach-all5002.o
-obj-$(CONFIG_RT305X_MACH_BR6425) += mach-br6425.o
-obj-$(CONFIG_RT305X_MACH_BROADWAY) += mach-broadway.o
-obj-$(CONFIG_RT305X_MACH_CARAMBOLA) += mach-carambola.o
-obj-$(CONFIG_RT305X_MACH_DIR_300_REVB) += mach-dir-300-revb.o
-obj-$(CONFIG_RT305X_MACH_DIR_615_H1) += mach-dir-615-h1.o
-obj-$(CONFIG_RT305X_MACH_DAP_1350) += mach-dap-1350.o
-obj-$(CONFIG_RT305X_MACH_ESR_9753) += mach-esr-9753.o
-obj-$(CONFIG_RT305X_MACH_F5D8235_V2) += mach-f5d8235-v2.o
-obj-$(CONFIG_RT305X_MACH_FONERA20N) += mach-fonera20n.o
-obj-$(CONFIG_RT305X_MACH_RT_N13U) += mach-rt-n13u.o
-obj-$(CONFIG_RT305X_MACH_FREESTATION5) += mach-freestation5.o
-obj-$(CONFIG_RT305X_MACH_HW550_3G) += mach-hw550-3g.o
-obj-$(CONFIG_RT305X_MACH_MOFI3500_3GN) += mach-mofi3500-3gn.o
-obj-$(CONFIG_RT305X_MACH_NBG_419N) += mach-nbg-419n.o
-obj-$(CONFIG_RT305X_MACH_NW718) += mach-nw718.o
-obj-$(CONFIG_RT305X_MACH_OMNI_EMB) += mach-omni-emb.o
-obj-$(CONFIG_RT305X_MACH_PSR_680W) += mach-psr-680w.o
-obj-$(CONFIG_RT305X_MACH_PWH2004) += mach-pwh2004.o
-obj-$(CONFIG_RT305X_MACH_RT_G32_REVB) += mach-rt-g32-revb.o
-obj-$(CONFIG_RT305X_MACH_RT_N10_PLUS) += mach-rt-n10-plus.o
-obj-$(CONFIG_RT305X_MACH_SL_R7205) += mach-sl-r7205.o
-obj-$(CONFIG_RT305X_MACH_V22RW_2X2) += mach-v22rw-2x2.o
-obj-$(CONFIG_RT305X_MACH_W306R_V20) += mach-w306r-v20.o
-obj-$(CONFIG_RT305X_MACH_W502U) += mach-w502u.o
-obj-$(CONFIG_RT305X_MACH_WCR150GN) += mach-wcr150gn.o
-obj-$(CONFIG_RT305X_MACH_WHR_G300N) += mach-whr-g300n.o
-obj-$(CONFIG_RT305X_MACH_WR512_3GN) += mach-wr512-3gn.o
-obj-$(CONFIG_RT305X_MACH_UR_326N4G) += mach-ur-326n4g.o
-obj-$(CONFIG_RT305X_MACH_UR_336UN) += mach-ur-336un.o
-obj-$(CONFIG_RT305X_MACH_WL_330N) += mach-wl-330n.o
-obj-$(CONFIG_RT305X_MACH_WL_330N3G) += mach-wl-330n3g.o
-obj-$(CONFIG_RT305X_MACH_WL341V3) += mach-wl341v3.o
-obj-$(CONFIG_RT305X_MACH_WL351) += mach-wl351.o
-obj-$(CONFIG_RT305X_MACH_WR6202) += mach-wr6202.o
-obj-$(CONFIG_RT305X_MACH_MZKW300NH2) += mach-mzk-w300nh2.o
-obj-$(CONFIG_RT305X_MACH_XDX_RN502J) += mach-xdx-rn502j.o
+++ /dev/null
-/*
- * Ralink RT305X clock API
- *
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-
-#include <asm/mach-ralink/common.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-#include "common.h"
-
-struct clk {
- unsigned long rate;
-};
-
-static struct clk rt305x_cpu_clk;
-static struct clk rt305x_sys_clk;
-static struct clk rt305x_wdt_clk;
-static struct clk rt305x_uart_clk;
-
-void __init rt305x_clocks_init(void)
-{
- u32 t;
-
- t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
-
- if (soc_is_rt305x() || soc_is_rt3350()) {
- t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
- RT305X_SYSCFG_CPUCLK_MASK;
- switch (t) {
- case RT305X_SYSCFG_CPUCLK_LOW:
- rt305x_cpu_clk.rate = 320000000;
- break;
- case RT305X_SYSCFG_CPUCLK_HIGH:
- rt305x_cpu_clk.rate = 384000000;
- break;
- }
- rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
- rt305x_uart_clk.rate = rt305x_sys_clk.rate;
- rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
- } else if (soc_is_rt3352()) {
- t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
- RT3352_SYSCFG0_CPUCLK_MASK;
- switch (t) {
- case RT3352_SYSCFG0_CPUCLK_LOW:
- rt305x_cpu_clk.rate = 384000000;
- break;
- case RT3352_SYSCFG0_CPUCLK_HIGH:
- rt305x_cpu_clk.rate = 400000000;
- break;
- }
- rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
- rt305x_uart_clk.rate = 40000000;
- rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
- } else if (soc_is_rt5350()) {
- t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
- RT5350_SYSCFG0_CPUCLK_MASK;
- switch (t) {
- case RT5350_SYSCFG0_CPUCLK_360:
- rt305x_cpu_clk.rate = 360000000;
- rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
- break;
- case RT5350_SYSCFG0_CPUCLK_320:
- rt305x_cpu_clk.rate = 320000000;
- rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4;
- break;
- case RT5350_SYSCFG0_CPUCLK_300:
- rt305x_cpu_clk.rate = 300000000;
- rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
- break;
- default:
- BUG();
- }
- rt305x_uart_clk.rate = 40000000;
- rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
- } else {
- BUG();
- }
-
-}
-
-/*
- * Linux clock API
- */
-struct clk *clk_get(struct device *dev, const char *id)
-{
- if (!strcmp(id, "sys"))
- return &rt305x_sys_clk;
-
- if (!strcmp(id, "cpu"))
- return &rt305x_cpu_clk;
-
- if (!strcmp(id, "wdt"))
- return &rt305x_wdt_clk;
-
- if (!strcmp(id, "uart"))
- return &rt305x_uart_clk;
-
- return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
+++ /dev/null
-/*
- * Ralink RT305x SoC common defines
- *
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _RT305X_COMMON_H
-#define _RT305X_COMMON_H
-
-void rt305x_clocks_init(void);
-
-#endif /* _RT305X_COMMON_H */
\ No newline at end of file
+++ /dev/null
-/*
- * Ralink RT305x SoC platform device registration
- *
- * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/rt2x00_platform.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/usb/ohci_pdriver.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-#include "devices.h"
-
-#include <ramips_eth_platform.h>
-#include <rt305x_esw_platform.h>
-
-static struct resource rt305x_flash0_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = KSEG1ADDR(RT305X_FLASH0_BASE),
- .end = KSEG1ADDR(RT305X_FLASH0_BASE) +
- RT305X_FLASH0_SIZE - 1,
- },
-};
-
-struct physmap_flash_data rt305x_flash0_data;
-static struct platform_device rt305x_flash0_device = {
- .name = "physmap-flash",
- .resource = rt305x_flash0_resources,
- .num_resources = ARRAY_SIZE(rt305x_flash0_resources),
- .dev = {
- .platform_data = &rt305x_flash0_data,
- },
-};
-
-static struct resource rt305x_flash1_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = KSEG1ADDR(RT305X_FLASH1_BASE),
- .end = KSEG1ADDR(RT305X_FLASH1_BASE) +
- RT305X_FLASH1_SIZE - 1,
- },
-};
-
-struct physmap_flash_data rt305x_flash1_data;
-static struct platform_device rt305x_flash1_device = {
- .name = "physmap-flash",
- .resource = rt305x_flash1_resources,
- .num_resources = ARRAY_SIZE(rt305x_flash1_resources),
- .dev = {
- .platform_data = &rt305x_flash1_data,
- },
-};
-
-static int rt305x_flash_instance __initdata;
-void __init rt305x_register_flash(unsigned int id)
-{
- struct platform_device *pdev;
- struct physmap_flash_data *pdata;
- u32 t;
- int reg;
-
- switch (id) {
- case 0:
- pdev = &rt305x_flash0_device;
- reg = MEMC_REG_FLASH_CFG0;
- break;
- case 1:
- pdev = &rt305x_flash1_device;
- reg = MEMC_REG_FLASH_CFG1;
- break;
- default:
- return;
- }
-
- t = rt305x_memc_rr(reg);
- t = (t >> FLASH_CFG_WIDTH_SHIFT) & FLASH_CFG_WIDTH_MASK;
-
- pdata = pdev->dev.platform_data;
- switch (t) {
- case FLASH_CFG_WIDTH_8BIT:
- pdata->width = 1;
- break;
- case FLASH_CFG_WIDTH_16BIT:
- pdata->width = 2;
- break;
- case FLASH_CFG_WIDTH_32BIT:
- pdata->width = 4;
- break;
- default:
- printk(KERN_ERR "RT305x: flash bank%u witdh is invalid\n", id);
- return;
- }
-
- pdev->id = rt305x_flash_instance;
-
- platform_device_register(pdev);
- rt305x_flash_instance++;
-}
-
-static void rt305x_fe_reset(void)
-{
- u32 reset_bits = RT305X_RESET_FE;
-
- if (soc_is_rt5350())
- reset_bits |= RT305X_RESET_ESW;
- rt305x_sysc_wr(reset_bits, SYSC_REG_RESET_CTRL);
- rt305x_sysc_wr(0, SYSC_REG_RESET_CTRL);
-}
-
-static struct resource rt305x_eth_resources[] = {
- {
- .start = RT305X_FE_BASE,
- .end = RT305X_FE_BASE + PAGE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = RT305X_CPU_IRQ_FE,
- .end = RT305X_CPU_IRQ_FE,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct ramips_eth_platform_data ramips_eth_data = {
- .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
- .reset_fe = rt305x_fe_reset,
- .min_pkt_len = 64,
-};
-
-static struct platform_device rt305x_eth_device = {
- .name = "ramips_eth",
- .resource = rt305x_eth_resources,
- .num_resources = ARRAY_SIZE(rt305x_eth_resources),
- .dev = {
- .platform_data = &ramips_eth_data,
- }
-};
-
-static struct resource rt305x_esw_resources[] = {
- {
- .start = RT305X_SWITCH_BASE,
- .end = RT305X_SWITCH_BASE + PAGE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct rt305x_esw_platform_data rt305x_esw_data = {
- /* All ports are LAN ports. */
- .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
- .reg_initval_fct2 = 0x00d6500c,
- /*
- * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
- * turbo mii off, rgmi 3.3v off
- * port5: disabled
- * port6: enabled, gige, full-duplex, rx/tx-flow-control
- */
- .reg_initval_fpa2 = 0x3f502b28,
-};
-
-static struct platform_device rt305x_esw_device = {
- .name = "rt305x-esw",
- .resource = rt305x_esw_resources,
- .num_resources = ARRAY_SIZE(rt305x_esw_resources),
- .dev = {
- .platform_data = &rt305x_esw_data,
- }
-};
-
-void __init rt305x_register_ethernet(void)
-{
- struct clk *clk;
-
- clk = clk_get(NULL, "sys");
- if (IS_ERR(clk))
- panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
-
- ramips_eth_data.sys_freq = clk_get_rate(clk);
-
- platform_device_register(&rt305x_esw_device);
- platform_device_register(&rt305x_eth_device);
-}
-
-static struct resource rt305x_wifi_resources[] = {
- {
- .start = RT305X_WMAC_BASE,
- .end = RT305X_WMAC_BASE + 0x3FFFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = RT305X_CPU_IRQ_WNIC,
- .end = RT305X_CPU_IRQ_WNIC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct rt2x00_platform_data rt305x_wifi_data;
-static struct platform_device rt305x_wifi_device = {
- .name = "rt2800_wmac",
- .resource = rt305x_wifi_resources,
- .num_resources = ARRAY_SIZE(rt305x_wifi_resources),
- .dev = {
- .platform_data = &rt305x_wifi_data,
- }
-};
-
-void __init rt305x_register_wifi(void)
-{
- u32 t;
-
- rt305x_wifi_data.eeprom_file_name = "soc_wmac.eeprom";
-
- if (soc_is_rt3352() || soc_is_rt5350()) {
- t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
- t &= RT3352_SYSCFG0_XTAL_SEL;
- if (!t)
- rt305x_wifi_data.clk_is_20mhz = 1;
- }
- platform_device_register(&rt305x_wifi_device);
-}
-
-static struct resource rt305x_wdt_resources[] = {
- {
- .start = RT305X_TIMER_BASE,
- .end = RT305X_TIMER_BASE + RT305X_TIMER_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device rt305x_wdt_device = {
- .name = "ramips-wdt",
- .id = -1,
- .resource = rt305x_wdt_resources,
- .num_resources = ARRAY_SIZE(rt305x_wdt_resources),
-};
-
-void __init rt305x_register_wdt(void)
-{
- u32 t;
-
- /* enable WDT reset output on pin SRAM_CS_N */
- t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
- t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
- RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
- rt305x_sysc_wr(t, SYSC_REG_SYSTEM_CONFIG);
-
- platform_device_register(&rt305x_wdt_device);
-}
-
-static struct resource rt305x_spi_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = RT305X_SPI_BASE,
- .end = RT305X_SPI_BASE + RT305X_SPI_SIZE - 1,
- },
-};
-
-static struct platform_device rt305x_spi_device = {
- .name = "ramips-spi",
- .id = 0,
- .resource = rt305x_spi_resources,
- .num_resources = ARRAY_SIZE(rt305x_spi_resources),
-};
-
-void __init rt305x_register_spi(struct spi_board_info *info, int n)
-{
- spi_register_board_info(info, n);
- platform_device_register(&rt305x_spi_device);
-}
-
-static struct resource rt305x_dwc_otg_resources[] = {
- {
- .start = RT305X_OTG_BASE,
- .end = RT305X_OTG_BASE + 0x3FFFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = RT305X_INTC_IRQ_OTG,
- .end = RT305X_INTC_IRQ_OTG,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device rt305x_dwc_otg_device = {
- .name = "dwc_otg",
- .resource = rt305x_dwc_otg_resources,
- .num_resources = ARRAY_SIZE(rt305x_dwc_otg_resources),
- .dev = {
- .platform_data = NULL,
- }
-};
-
-static atomic_t rt3352_usb_pwr_ref = ATOMIC_INIT(0);
-
-static int rt3352_usb_power_on(struct platform_device *pdev)
-{
-
- if (atomic_inc_return(&rt3352_usb_pwr_ref) == 1) {
- u32 t;
-
- t = rt305x_sysc_rr(RT3352_SYSC_REG_USB_PS);
-
- /* enable clock for port0's and port1's phys */
- t = rt305x_sysc_rr(RT3352_SYSC_REG_CLKCFG1);
- t |= RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN;
- rt305x_sysc_wr(t, RT3352_SYSC_REG_CLKCFG1);
- mdelay(500);
-
- /* pull USBHOST and USBDEV out from reset */
- t = rt305x_sysc_rr(RT3352_SYSC_REG_RSTCTRL);
- t &= ~(RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV);
- rt305x_sysc_wr(t, RT3352_SYSC_REG_RSTCTRL);
- mdelay(500);
-
- /* enable host mode */
- t = rt305x_sysc_rr(RT3352_SYSC_REG_SYSCFG1);
- t |= RT3352_SYSCFG1_USB0_HOST_MODE;
- rt305x_sysc_wr(t, RT3352_SYSC_REG_SYSCFG1);
-
- t = rt305x_sysc_rr(RT3352_SYSC_REG_USB_PS);
- }
-
- return 0;
-}
-
-static void rt3352_usb_power_off(struct platform_device *pdev)
-{
-
- if (atomic_dec_return(&rt3352_usb_pwr_ref) == 0) {
- u32 t;
-
- /* put USBHOST and USBDEV into reset */
- t = rt305x_sysc_rr(RT3352_SYSC_REG_RSTCTRL);
- t |= RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV;
- rt305x_sysc_wr(t, RT3352_SYSC_REG_RSTCTRL);
- udelay(10000);
-
- /* disable clock for port0's and port1's phys*/
- t = rt305x_sysc_rr(RT3352_SYSC_REG_CLKCFG1);
- t &= ~(RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN);
- rt305x_sysc_wr(t, RT3352_SYSC_REG_CLKCFG1);
- udelay(10000);
- }
-}
-
-static struct usb_ehci_pdata rt3352_ehci_data = {
- .power_on = rt3352_usb_power_on,
- .power_off = rt3352_usb_power_off,
-};
-
-static struct resource rt3352_ehci_resources[] = {
- {
- .start = RT3352_EHCI_BASE,
- .end = RT3352_EHCI_BASE + RT3352_EHCI_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = RT305X_INTC_IRQ_OTG,
- .end = RT305X_INTC_IRQ_OTG,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 rt3352_ehci_dmamask = DMA_BIT_MASK(32);
-static struct platform_device rt3352_ehci_device = {
- .name = "ehci-platform",
- .id = -1,
- .resource = rt3352_ehci_resources,
- .num_resources = ARRAY_SIZE(rt3352_ehci_resources),
- .dev = {
- .dma_mask = &rt3352_ehci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &rt3352_ehci_data,
- },
-};
-
-static struct resource rt3352_ohci_resources[] = {
- {
- .start = RT3352_OHCI_BASE,
- .end = RT3352_OHCI_BASE + RT3352_OHCI_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = RT305X_INTC_IRQ_OTG,
- .end = RT305X_INTC_IRQ_OTG,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct usb_ohci_pdata rt3352_ohci_data = {
- .power_on = rt3352_usb_power_on,
- .power_off = rt3352_usb_power_off,
-};
-
-static u64 rt3352_ohci_dmamask = DMA_BIT_MASK(32);
-static struct platform_device rt3352_ohci_device = {
- .name = "ohci-platform",
- .id = -1,
- .resource = rt3352_ohci_resources,
- .num_resources = ARRAY_SIZE(rt3352_ohci_resources),
- .dev = {
- .dma_mask = &rt3352_ohci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &rt3352_ohci_data,
- },
-};
-
-void __init rt305x_register_usb(void)
-{
- if (soc_is_rt305x() || soc_is_rt3350()) {
- platform_device_register(&rt305x_dwc_otg_device);
- } else if (soc_is_rt3352() || soc_is_rt5350()) {
- platform_device_register(&rt3352_ehci_device);
- platform_device_register(&rt3352_ohci_device);
- } else {
- BUG();
- }
-}
+++ /dev/null
-/*
- * Ralink RT305x SoC specific platform device definitions
- *
- * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __RT305X_DEVICES_H
-#define __RT305X_DEVICES_H
-
-#include <asm/mach-ralink/rt305x_esw_platform.h>
-
-struct physmap_flash_data;
-struct spi_board_info;
-
-extern struct physmap_flash_data rt305x_flash0_data;
-extern struct physmap_flash_data rt305x_flash1_data;
-
-extern struct rt305x_esw_platform_data rt305x_esw_data;
-
-void rt305x_register_flash(unsigned int id);
-void rt305x_register_ethernet(void);
-void rt305x_register_wifi(void);
-void rt305x_register_wdt(void);
-void rt305x_register_spi(struct spi_board_info *info, int n);
-void rt305x_register_usb(void);
-
-#endif /* __RT305X_DEVICES_H */
-
+++ /dev/null
-/*
- * Ralink RT305x SoC early printk support
- *
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/serial_reg.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#define UART_READ(r) \
- __raw_readl((void __iomem *)(KSEG1ADDR(RT305X_UART1_BASE) + 4 * (r)))
-
-#define UART_WRITE(r, v) \
- __raw_writel((v), (void __iomem *)(KSEG1ADDR(RT305X_UART1_BASE) + 4 * (r)))
-
-void prom_putchar(unsigned char ch)
-{
- while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0);
- UART_WRITE(UART_REG_TX, ch);
- while (((UART_READ(UART_REG_LSR)) & UART_LSR_THRE) == 0);
-}
+++ /dev/null
-/*
- * Ralink RT305x SoC specific interrupt handling
- *
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-
-#include <asm/mach-ralink/common.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-static void rt305x_intc_irq_dispatch(void)
-{
- u32 pending;
-
- pending = ramips_intc_get_status();
-
- if (pending & RT305X_INTC_INT_TIMER0)
- do_IRQ(RT305X_INTC_IRQ_TIMER0);
-
- else if (pending & RT305X_INTC_INT_TIMER1)
- do_IRQ(RT305X_INTC_IRQ_TIMER1);
-
- else if (pending & RT305X_INTC_INT_UART0)
- do_IRQ(RT305X_INTC_IRQ_UART0);
-
- else if (pending & RT305X_INTC_INT_UART1)
- do_IRQ(RT305X_INTC_IRQ_UART1);
-
- else if (pending & RT305X_INTC_INT_PERFC)
- do_IRQ(RT305X_INTC_IRQ_PERFC);
-
- else if (pending & RT305X_INTC_INT_OTG)
- do_IRQ(RT305X_INTC_IRQ_OTG);
-
- /* TODO: handle PIO interrupts as well */
-
- else
- spurious_interrupt();
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned long pending;
-
- pending = read_c0_status() & read_c0_cause() & ST0_IM;
-
- if (pending & STATUSF_IP7)
- do_IRQ(RT305X_CPU_IRQ_COUNTER);
-
- else if (pending & STATUSF_IP5)
- do_IRQ(RT305X_CPU_IRQ_FE);
-
- else if (pending & STATUSF_IP6)
- do_IRQ(RT305X_CPU_IRQ_WNIC);
-
- else if (pending & STATUSF_IP2)
- rt305x_intc_irq_dispatch();
-
- else
- spurious_interrupt();
-}
-
-void __init arch_init_irq(void)
-{
- mips_cpu_irq_init();
- ramips_intc_irq_init(RT305X_INTC_BASE, RT305X_CPU_IRQ_INTC,
- RT305X_INTC_IRQ_BASE);
-
- cp0_perfcount_irq = RT305X_INTC_IRQ_PERFC;
-}
+++ /dev/null
-/*
- * Edimax 3g-6200n board support
- *
- * Copyright (C) 2011 Andrzej Hajda <andrzej.hajda@wp.pl>
- * Copyright (C) 2012 Lukasz Golebiowski <lgolebio@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define EDIMAX_GPIO_BUTTON_WPS 12
-#define EDIMAX_GPIO_BTN_0 13 /* Wifi on/off switch button */
-
-#define EDIMAX_GPIO_LED_POWER 9
-#define EDIMAX_GPIO_LED_WLAN 14
-#define EDIMAX_GPIO_LED_3G 7
-
-#define EDIMAX_KEYS_POLL_INTERVAL 20
-#define EDIMAX_KEYS_DEBOUNCE_INTERVAL (3 * EDIMAX_KEYS_POLL_INTERVAL)
-
-static struct gpio_led edimax_leds_gpio[] __initdata = {
- {
- .name = "edimax:green:power",
- .gpio = EDIMAX_GPIO_LED_POWER,
- .active_low = 1,
- }, {
- .name = "edimax:amber:wlan",
- .gpio = EDIMAX_GPIO_LED_WLAN,
- .active_low = 1,
- }, {
- .name = "edimax:blue:3g",
- .gpio = EDIMAX_GPIO_LED_3G,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button edimax_gpio_buttons[] __initdata = {
- {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = EDIMAX_KEYS_DEBOUNCE_INTERVAL,
- .gpio = EDIMAX_GPIO_BUTTON_WPS,
- .active_low = 1,
- }, {
- .desc = "wlanswitch",
- .type = EV_KEY,
- .code = BTN_0,
- .debounce_interval = EDIMAX_KEYS_DEBOUNCE_INTERVAL,
- .gpio = EDIMAX_GPIO_BTN_0,
- .active_low = 1,
- }
-};
-
-static void __init edimax_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(edimax_leds_gpio),
- edimax_leds_gpio);
- ramips_register_gpio_buttons(-1, EDIMAX_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(edimax_gpio_buttons),
- edimax_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_3G_6200N, "3G-6200N", "Edimax 3g-6200n",
- edimax_init);
+++ /dev/null
-/*
- * Tenda 3G300M board support
- *
- * Copyright (C) 2013 Cezary Jackiewicz <cezary.jackiewicz@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define TENDA_3G300M_GPIO_BUTTON_RESET 0
-#define TENDA_3G300M_GPIO_BUTTON_MODE 10
-
-#define TENDA_3G300M_GPIO_LED_3GROUTER 11
-#define TENDA_3G300M_GPIO_LED_AP 12
-#define TENDA_3G300M_GPIO_LED_WISPROUTER 9
-#define TENDA_3G300M_GPIO_LED_WIRELESSROUTER 13
-#define TENDA_3G300M_GPIO_LED_3G 7
-#define TENDA_3G300M_GPIO_LED_WPSRESET 14
-
-#define TENDA_3G300M_KEYS_POLL_INTERVAL 20
-#define TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL (3 * TENDA_3G300M_KEYS_POLL_INTERVAL)
-
-const struct flash_platform_data tenda_3g300m_flash = {
- .type = "mx25l3205d",
-};
-
-struct spi_board_info tenda_3g300m_spi_slave_info[] __initdata = {
- {
- .modalias = "m25p80",
- .platform_data = &tenda_3g300m_flash,
- .irq = -1,
- .max_speed_hz = 10000000,
- .bus_num = 0,
- .chip_select = 0,
- }
-};
-
-static struct gpio_led tenda_3g300m_leds_gpio[] __initdata = {
- {
- .name = "tenda:blue:3grouter",
- .gpio = TENDA_3G300M_GPIO_LED_3GROUTER,
- .active_low = 1,
- },{
- .name = "tenda:blue:ap",
- .gpio = TENDA_3G300M_GPIO_LED_AP,
- .active_low = 1,
- },{
- .name = "tenda:blue:wisprouter",
- .gpio = TENDA_3G300M_GPIO_LED_WISPROUTER,
- .active_low = 1,
- },{
- .name = "tenda:blue:wirelessrouter",
- .gpio = TENDA_3G300M_GPIO_LED_WIRELESSROUTER,
- .active_low = 1,
- },{
- .name = "tenda:blue:3g",
- .gpio = TENDA_3G300M_GPIO_LED_3G,
- .active_low = 1,
- },{
- .name = "tenda:blue:wpsreset",
- .gpio = TENDA_3G300M_GPIO_LED_WPSRESET,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button tenda_3g300m_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL,
- .gpio = TENDA_3G300M_GPIO_BUTTON_RESET,
- .active_low = 1,
- },{
- .desc = "mode",
- .type = EV_KEY,
- .code = BTN_0,
- .debounce_interval = TENDA_3G300M_KEYS_DEBOUNCE_INTERVAL,
- .gpio = TENDA_3G300M_GPIO_BUTTON_MODE,
- .active_low = 1,
- }
-};
-
-static void __init tenda_3g300m_init(void)
-{
- rt305x_gpio_init((RT305X_GPIO_MODE_GPIO <<
- RT305X_GPIO_MODE_UART0_SHIFT) |
- RT305X_GPIO_MODE_JTAG);
-
- rt305x_register_spi(tenda_3g300m_spi_slave_info,
- ARRAY_SIZE(tenda_3g300m_spi_slave_info));
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(tenda_3g300m_leds_gpio),
- tenda_3g300m_leds_gpio);
-
- ramips_register_gpio_buttons(-1, TENDA_3G300M_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(tenda_3g300m_gpio_buttons),
- tenda_3g300m_gpio_buttons);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
-
- rt305x_register_wifi();
-
- rt305x_register_wdt();
-
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_3G300M, "3G300M", "Tenda 3G300M",
- tenda_3g300m_init);
+++ /dev/null
-/*
- * AirLive Air3GII board support
- *
- * Copyright (C) 2012 Cezary Jackiewicz <cezary.jackiewicz@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define AIR3GII_GPIO_BUTTON_WPS 7
-
-#define AIR3GII_GPIO_LED_WLAN 8
-#define AIR3GII_GPIO_LED_MOBILE 9
-
-#define AIR3GII_KEYS_POLL_INTERVAL 20
-#define AIR3GII_KEYS_DEBOUNCE_INTERVAL (3 * AIR3GII_KEYS_POLL_INTERVAL)
-
-const struct flash_platform_data air3gii_flash = {
- .type = "en25q32b",
-};
-
-struct spi_board_info air3gii_spi_slave_info[] __initdata = {
- {
- .modalias = "m25p80",
- .platform_data = &air3gii_flash,
- .irq = -1,
- .max_speed_hz = 10000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static struct gpio_led air3gii_leds_gpio[] __initdata = {
- {
- .name = "airlive:green:wlan",
- .gpio = AIR3GII_GPIO_LED_WLAN,
- .active_low = 0,
- }, {
- .name = "airlive:green:mobile",
- .gpio = AIR3GII_GPIO_LED_MOBILE,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button air3gii_gpio_buttons[] __initdata = {
- {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = AIR3GII_KEYS_DEBOUNCE_INTERVAL,
- .gpio = AIR3GII_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static void __init air3gii_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_spi(air3gii_spi_slave_info,
- ARRAY_SIZE(air3gii_spi_slave_info));
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(air3gii_leds_gpio),
- air3gii_leds_gpio);
-
- ramips_register_gpio_buttons(-1, AIR3GII_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(air3gii_gpio_buttons),
- air3gii_gpio_buttons);
-
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_AIR3GII, "AIR3GII", "AirLive Air3GII",
- air3gii_init);
+++ /dev/null
-/*
- * Allnet ALL0256N board support
- *
- * Copyright (C) 2012 Daniel Golle <dgolle@allnet.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define ALL0256N_GPIO_BUTTON_RESET 0
-#define ALL0256N_GPIO_LED_RSSI_LOW 14
-#define ALL0256N_GPIO_LED_RSSI_MED 12
-#define ALL0256N_GPIO_LED_RSSI_HIGH 13
-#define ALL0256N_KEYS_POLL_INTERVAL 20
-#define ALL0256N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0256N_KEYS_POLL_INTERVAL)
-
-const struct flash_platform_data all0256n_flash = {
- .type = "mx25l3205d",
-};
-
-struct spi_board_info all0256n_spi_slave_info[] __initdata = {
- {
- .modalias = "m25p80",
- .platform_data = &all0256n_flash,
- .irq = -1,
- .max_speed_hz = 10000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static struct gpio_keys_button all0256n_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = ALL0256N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ALL0256N_GPIO_BUTTON_RESET,
- .active_low = 1,
- }
-};
-
-static struct gpio_led all0256n_leds_gpio[] __initdata = {
- {
- .name = "all0256n:green:rssilow",
- .gpio = ALL0256N_GPIO_LED_RSSI_LOW,
- .active_low = 1,
- }, {
- .name = "all0256n:green:rssimed",
- .gpio = ALL0256N_GPIO_LED_RSSI_MED,
- .active_low = 1,
- }, {
- .name = "all0256n:green:rssihigh",
- .gpio = ALL0256N_GPIO_LED_RSSI_HIGH,
- .active_low = 1,
- }
-};
-
-static void __init all0256n_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
- rt305x_register_spi(all0256n_spi_slave_info,
- ARRAY_SIZE(all0256n_spi_slave_info));
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(all0256n_leds_gpio),
- all0256n_leds_gpio);
- ramips_register_gpio_buttons(-1, ALL0256N_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(all0256n_gpio_buttons),
- all0256n_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_ALL0256N, "ALL0256N", "Allnet ALL0256N",
- all0256n_init);
+++ /dev/null
-/*
- * Allnet ALL5002
- *
- * Copyright (C) 2012 Daniel Golle <dgolle@allnet.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-// #define ALL5002_GPIO_BUTTON_RESET 0
-// #define ALL5002_GPIO_LED_RSSI_LOW 14
-// #define ALL5002_GPIO_LED_RSSI_MED 12
-// #define ALL5002_GPIO_LED_RSSI_HIGH 13
-// #define ALL5002_BUTTONS_POLL_INTERVAL 20
-
-const struct flash_platform_data all5002_flash = {
- .type = "mx25l25635e",
-};
-
-struct spi_board_info all5002_spi_slave_info[] __initdata = {
- {
- .modalias = "m25p80",
- .platform_data = &all5002_flash,
- .irq = -1,
- .max_speed_hz = 10000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static void __init all5002_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
- rt305x_register_spi(all5002_spi_slave_info,
- ARRAY_SIZE(all5002_spi_slave_info));
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_ALL5002, "ALL5002", "Allnet ALL5002/ALL5003",
- all5002_init);
+++ /dev/null
-/*
- * Argus ATP-52B router support
- * http://www.argus-co.com/english/productsview.php?id=70&cid=81
- *
- * Copyright (C) 2011 Roman Yeryomin <roman@advem.lv>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define ARGUS_ATP52B_GPIO_LED_RUN 9
-#define ARGUS_ATP52B_GPIO_LED_NET 13
-#define ARGUS_ATP52B_GPIO_BUTTON_WPS 0
-#define ARGUS_ATP52B_GPIO_BUTTON_RESET 10
-#define ARGUS_ATP52B_KEYS_POLL_INTERVAL 20
-#define ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL (3 * ARGUS_ATP52B_KEYS_POLL_INTERVAL)
-
-static struct gpio_led argus_atp52b_leds_gpio[] __initdata = {
- {
- .name = "argus-atp52b:green:run",
- .gpio = ARGUS_ATP52B_GPIO_LED_RUN,
- .active_low = 1,
- },
- {
- .name = "argus-atp52b:amber:net",
- .gpio = ARGUS_ATP52B_GPIO_LED_NET,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button argus_atp52b_gpio_buttons[] __initdata = {
- {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ARGUS_ATP52B_GPIO_BUTTON_WPS,
- .active_low = 1,
- },
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = ARGUS_ATP52B_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ARGUS_ATP52B_GPIO_BUTTON_RESET,
- .active_low = 1,
- }
-};
-
-static void __init argus_atp52b_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(argus_atp52b_leds_gpio),
- argus_atp52b_leds_gpio);
- ramips_register_gpio_buttons(-1, ARGUS_ATP52B_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(argus_atp52b_gpio_buttons),
- argus_atp52b_gpio_buttons);
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_ARGUS_ATP52B, "ARGUS_ATP52B", "Argus ATP-52B",
- argus_atp52b_init);
+++ /dev/null
-/*
- * NexAira BC2 board support
- *
- * Copyright (C) 2011 Adam J. Porter <porter.adam@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define BC2_GPIO_BUTTON_RESET 17
-#define BC2_GPIO_LED_USB 20
-
-#define BC2_KEYS_POLL_INTERVAL 20
-#define BC2_KEYS_DEBOUNCE_INTERVAL (3 * BC2_KEYS_POLL_INTERVAL)
-
-static struct gpio_led bc2_leds_gpio[] __initdata = {
- {
- .name = "bc2:blue:usb",
- .gpio = BC2_GPIO_LED_USB,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button bc2_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = BC2_KEYS_DEBOUNCE_INTERVAL,
- .gpio = BC2_GPIO_BUTTON_RESET,
- .active_low = 1,
- }
-};
-
-static void __init bc2_init(void)
-{
- rt305x_gpio_init((RT305X_GPIO_MODE_GPIO <<
- RT305X_GPIO_MODE_UART0_SHIFT) |
- RT305X_GPIO_MODE_JTAG);
-
- rt305x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(bc2_leds_gpio),
- bc2_leds_gpio);
-
- ramips_register_gpio_buttons(-1, BC2_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(bc2_gpio_buttons),
- bc2_gpio_buttons);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_BC2, "BC2", "NexAira BC2",
- bc2_init);
+++ /dev/null
-/*
- * Edimax BR-6425 board support
- *
- * Copyright (C) 2012 OpenWrt.org
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define BR6425_GPIO_LED_POWER 9
-#define BR6425_GPIO_BUTTON_RESET 12
-#define BR6425_GPIO_SWITCH_RFKILL 13
-#define BR6425_GPIO_LED_WLAN 14
-#define BR6425_KEYS_POLL_INTERVAL 20
-#define BR6425_KEYS_DEBOUNCE_INTERVAL (3 * BR6425_KEYS_POLL_INTERVAL)
-
-static struct gpio_keys_button br6425_gpio_buttons[] __initdata = {
- {
- .desc = "reset_wps",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = BR6425_KEYS_DEBOUNCE_INTERVAL,
- .gpio = BR6425_GPIO_BUTTON_RESET,
- .active_low = 1,
- },
- {
- .desc = "RFKILL switch",
- .type = EV_SW,
- .code = KEY_RFKILL,
- .debounce_interval = BR6425_KEYS_DEBOUNCE_INTERVAL,
- .gpio = BR6425_GPIO_SWITCH_RFKILL,
- .active_low = 1,
- },
-};
-
-static struct gpio_led br6425_leds_gpio[] __initdata = {
- {
- .name = "edimax:green:power",
- .gpio = BR6425_GPIO_LED_POWER,
- .active_low = 1,
- }, {
- .name = "edimax:orange:wlan",
- .gpio = BR6425_GPIO_LED_WLAN,
- .active_low = 1,
- },
-};
-
-static void __init br6425_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
- rt305x_register_flash(0);
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(br6425_leds_gpio),
- br6425_leds_gpio);
- ramips_register_gpio_buttons(-1, BR6425_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(br6425_gpio_buttons),
- br6425_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_BR6425, "BR-6425", "Edimax BR-6425",
- br6425_init);
+++ /dev/null
-/*
- * Hauppauge/PCTV Broadway Support
- *
- * Copyright (C) 2012 Devin Heitmueller <dheitmueller@kernellabs.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define BROADWAY_GPIO_LED_DISKMOUNT 9
-#define BROADWAY_GPIO_LED_WPS 14
-
-#define BROADWAY_GPIO_BUTTON_WPS 0
-#define BROADWAY_GPIO_BUTTON_FACTORYRESET 13
-
-#define BROADWAY_KEYS_POLL_INTERVAL 20
-#define BROADWAY_KEYS_DEBOUNCE_INTERVAL (3 * BROADWAY_KEYS_POLL_INTERVAL)
-
-static struct gpio_led broadway_leds_gpio[] __initdata = {
- {
- .name = "red:diskmounted",
- .gpio = BROADWAY_GPIO_LED_DISKMOUNT,
- .active_low = 1,
- },
- {
- .name = "red:wps_active",
- .gpio = BROADWAY_GPIO_LED_WPS,
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_button broadway_gpio_buttons[] __initdata = {
- {
- .desc = "Factory Reset button",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = BROADWAY_KEYS_DEBOUNCE_INTERVAL,
- .gpio = BROADWAY_GPIO_BUTTON_FACTORYRESET,
- .active_low = 1,
- },
-#ifdef DJH_WPS_BUTTON_NOT_WIRED_TO_GPIO
- {
- .desc = "WPS button",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = BROADWAY_KEYS_DEBOUNCE_INTERVAL,
- .gpio = BROADWAY_GPIO_BUTTON_WPS,
- .active_low = 1,
- },
-#endif
-};
-
-static void __init broadway_init(void)
-{
- rt305x_gpio_init((RT305X_GPIO_MODE_GPIO <<
- RT305X_GPIO_MODE_UART0_SHIFT));
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL;
- rt305x_register_ethernet();
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(broadway_leds_gpio),
- broadway_leds_gpio);
- ramips_register_gpio_buttons(-1, BROADWAY_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(broadway_gpio_buttons),
- broadway_gpio_buttons);
-
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_BROADWAY, "BROADWAY", "Hauppauge Broadway",
- broadway_init);
+++ /dev/null
-/*
- * 8devices Carambola dev board support
- *
- * Copyright (C) 2012 Tobias Diedrich <ranma+openwrt@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-static void __init carambola_init(void)
-{
- /* Ugh, inverted logic...
- * This actually puts the pins into GPIO mode rather I2C, SPI, ... */
- rt305x_gpio_init(RT305X_GPIO_MODE_UART0(RT305X_GPIO_MODE_GPIO) |
- RT305X_GPIO_MODE_I2C |
- RT305X_GPIO_MODE_SPI |
- RT305X_GPIO_MODE_JTAG |
- RT305X_GPIO_MODE_MDIO);
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_CARAMBOLA, "CARAMBOLA", "8devices Carambola",
- carambola_init);
+++ /dev/null
-/*
- * D-Link DAP-1350 board support
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define DAP_1350_GPIO_LED_POWER_BLUE 8
-#define DAP_1350_GPIO_LED_POWER_RED 9
-#define DAP_1350_GPIO_LED_WPS 14
-
-#define DAP_1350_GPIO_BUTTON_WPS 0 /* active low */
-#define DAP_1350_GPIO_BUTTON_RESET 10 /* active low */
-#define DAP_1350_GPIO_SWITCH_MODE_AP 7 /* active low */
-#define DAP_1350_GPIO_SWITCH_MODE_RT 11 /* active low */
-
-#define DAP_1350_KEYS_POLL_INTERVAL 20
-#define DAP_1350_KEYS_DEBOUNCE_INTERVAL (3 * DAP_1350_KEYS_POLL_INTERVAL)
-
-static struct gpio_led dap_1350_leds_gpio[] __initdata = {
- {
- .name = "d-link:blue:power",
- .gpio = DAP_1350_GPIO_LED_POWER_BLUE,
- .active_low = 1,
- }, {
- .name = "d-link:red:power",
- .gpio = DAP_1350_GPIO_LED_POWER_RED,
- .active_low = 1,
- }, {
- .name = "d-link:blue:wps",
- .gpio = DAP_1350_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button dap_1350_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL,
- .gpio = DAP_1350_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL,
- .gpio = DAP_1350_GPIO_BUTTON_WPS,
- .active_low = 1,
- }, {
- .desc = "rt",
- .type = EV_KEY,
- .code = BTN_0,
- .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL,
- .gpio = DAP_1350_GPIO_SWITCH_MODE_RT,
- .active_low = 1,
- }, {
- .desc = "ap",
- .type = EV_KEY,
- .code = BTN_1,
- .debounce_interval = DAP_1350_KEYS_DEBOUNCE_INTERVAL,
- .gpio = DAP_1350_GPIO_SWITCH_MODE_AP,
- .active_low = 1,
- }
-};
-
-static void __init dap_1350_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(dap_1350_leds_gpio),
- dap_1350_leds_gpio);
- ramips_register_gpio_buttons(-1, DAP_1350_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(dap_1350_gpio_buttons),
- dap_1350_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_DAP_1350, "DAP-1350", "D-Link DAP-1350",
- dap_1350_init);
+++ /dev/null
-/*
- * D-Link DIR-300 rev B board support
- *
- * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define DIR_300B_GPIO_LED_STATUS_AMBER 8
-#define DIR_300B_GPIO_LED_STATUS_GREEN 9
-#define DIR_300B_GPIO_LED_WPS 13
-/*
- * NOTE: The wan led is also connected to the switch, both
- * switch and gpio must be active to make it light up
- */
-#define DIR_300B_GPIO_LED_WAN_GREEN 12
-#define DIR_300B_GPIO_LED_WAN_AMBER 14
-
-/*
- * NOTE: the WPS led in DIR-620 consists of two antiparallel leds,
- * so they can't be lit simultaneously
- */
-#define DIR_620_GPIO_LED_WPS_AMBER 11
-
-#define DIR_300B_GPIO_BUTTON_WPS 0 /* active low */
-#define DIR_300B_GPIO_BUTTON_RESET 10 /* active low */
-
-#define DIR_300B_KEYS_POLL_INTERVAL 20
-#define DIR_300B_KEYS_DEBOUNCE_INTERVAL (3 * DIR_300B_KEYS_POLL_INTERVAL)
-
-static struct gpio_led dir_300b_leds_gpio[] __initdata = {
- {
- .name = "d-link:amber:status",
- .gpio = DIR_300B_GPIO_LED_STATUS_AMBER,
- .active_low = 1,
- }, {
- .name = "d-link:green:status",
- .gpio = DIR_300B_GPIO_LED_STATUS_GREEN,
- .active_low = 1,
- }, {
- .name = "d-link:amber:wan",
- .gpio = DIR_300B_GPIO_LED_WAN_AMBER,
- .active_low = 1,
- }, {
- .name = "d-link:green:wan",
- .gpio = DIR_300B_GPIO_LED_WAN_GREEN,
- .active_low = 1,
- }, {
- .name = "d-link:blue:wps",
- .gpio = DIR_300B_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button dir_300b_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = DIR_300B_KEYS_DEBOUNCE_INTERVAL,
- .gpio = DIR_300B_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = DIR_300B_KEYS_DEBOUNCE_INTERVAL,
- .gpio = DIR_300B_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_led dir_620_leds_gpio[] __initdata = {
- {
- .name = "d-link:amber:status",
- .gpio = DIR_300B_GPIO_LED_STATUS_AMBER,
- .active_low = 1,
- }, {
- .name = "d-link:green:status",
- .gpio = DIR_300B_GPIO_LED_STATUS_GREEN,
- .active_low = 1,
- }, {
- .name = "d-link:amber:wan",
- .gpio = DIR_300B_GPIO_LED_WAN_AMBER,
- .active_low = 1,
- }, {
- .name = "d-link:green:wan",
- .gpio = DIR_300B_GPIO_LED_WAN_GREEN,
- .active_low = 1,
- }, {
- .name = "d-link:blue:wps",
- .gpio = DIR_300B_GPIO_LED_WPS,
- }, {
- .name = "d-link:amber:wps",
- .gpio = DIR_620_GPIO_LED_WPS_AMBER,
- }
-};
-
-static void __init dir_common_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_buttons(-1, DIR_300B_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(dir_300b_gpio_buttons),
- dir_300b_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-static void __init dir_300b_init(void)
-{
- dir_common_init();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_300b_leds_gpio),
- dir_300b_leds_gpio);
-}
-
-static void __init dir_620a1_init(void)
-{
- dir_common_init();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_620_leds_gpio),
- dir_620_leds_gpio);
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_DIR_300_B1, "DIR-300-B1", "D-Link DIR-300 B1",
- dir_300b_init);
-
-MIPS_MACHINE(RAMIPS_MACH_DIR_600_B1, "DIR-600-B1", "D-Link DIR-600 B1",
- dir_300b_init);
-
-MIPS_MACHINE(RAMIPS_MACH_DIR_600_B2, "DIR-600-B2", "D-Link DIR-600 B2",
- dir_300b_init);
-
-MIPS_MACHINE(RAMIPS_MACH_DIR_615_D, "DIR-615-D", "D-Link DIR-615 D",
- dir_300b_init);
-
-MIPS_MACHINE(RAMIPS_MACH_DIR_620_A1, "DIR-620-A1", "D-Link DIR-620 A1",
- dir_620a1_init);
+++ /dev/null
-/*
- * D-Link DIR-615 H1
- *
- * Copyright (C) 2012 Mikko Hissa <mikko.hissa@uta.fi>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define DIR_615_H1_GPIO_LED_WAN_AMBER 12 /* active low */
-#define DIR_615_H1_GPIO_LED_WAN_GREEN 13 /* active low */
-#define DIR_615_H1_GPIO_LED_WPS_BLUE 14 /* active low */
-
-#define DIR_615_H1_GPIO_LED_STATUS_AMBER 7
-#define DIR_615_H1_GPIO_LED_STATUS_GREEN 9
-
-#define DIR_615_H1_GPIO_BUTTON_RESET 10 /* active low */
-#define DIR_615_H1_GPIO_BUTTON_WPS 0 /* active low */
-
-#define DIR_615_H1_KEYS_POLL_INTERVAL 20
-#define DIR_615_H1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_H1_KEYS_POLL_INTERVAL)
-
-static struct gpio_led dir_615_h1_leds_gpio[] __initdata = {
- {
- .name = "d-link:amber:status",
- .gpio = DIR_615_H1_GPIO_LED_STATUS_AMBER,
- }, {
- .name = "d-link:green:status",
- .gpio = DIR_615_H1_GPIO_LED_STATUS_GREEN,
- }, {
- .name = "d-link:amber:wan",
- .gpio = DIR_615_H1_GPIO_LED_WAN_AMBER,
- .active_low = 1,
- }, {
- .name = "d-link:green:wan",
- .gpio = DIR_615_H1_GPIO_LED_WAN_GREEN,
- .active_low = 1,
- }, {
- .name = "d-link:blue:wps",
- .gpio = DIR_615_H1_GPIO_LED_WPS_BLUE,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button dir_615_h1_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = DIR_615_H1_KEYS_DEBOUNCE_INTERVAL,
- .gpio = DIR_615_H1_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = DIR_615_H1_KEYS_DEBOUNCE_INTERVAL,
- .gpio = DIR_615_H1_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-const struct flash_platform_data dir615h1_flash = {
- .type = "mx25l3205d",
-};
-
-struct spi_board_info dir615h1_spi_slave_info[] __initdata = {
- {
- .modalias = "m25p80",
- .platform_data = &dir615h1_flash,
- .irq = -1,
- .max_speed_hz = 10000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static void __init dir615h1_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
- rt305x_register_spi(dir615h1_spi_slave_info,
- ARRAY_SIZE(dir615h1_spi_slave_info));
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(dir_615_h1_leds_gpio),
- dir_615_h1_leds_gpio);
- ramips_register_gpio_buttons(-1, DIR_615_H1_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(dir_615_h1_gpio_buttons),
- dir_615_h1_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_DIR_615_H1, "DIR-615-H1", "D-Link DIR-615 H1",
- dir615h1_init);
+++ /dev/null
-/*
- * Senao / EnGenius ESR-9753 board support
- *
- * Copyright (C) 2011 Artur Wronowski <arteqw@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define ESR_9753_GPIO_LED_POWER 8
-#define ESR_9753_GPIO_LED_WPS 14
-
-#define ESR_9753_GPIO_BUTTON_WPS 0 /* active low */
-#define ESR_9753_GPIO_BUTTON_RESET 10 /* active low */
-
-#define ESR_9753_KEYS_POLL_INTERVAL 20
-#define ESR_9753_KEYS_DEBOUNCE_INTERVAL (3 * ESR_9753_KEYS_POLL_INTERVAL)
-
-static struct gpio_led esr_9753_leds_gpio[] __initdata = {
- {
- .name = "esr-9753:orange:power",
- .gpio = ESR_9753_GPIO_LED_POWER,
- .active_low = 1,
- }, {
- .name = "esr-9753:orange:wps",
- .gpio = ESR_9753_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button esr_9753_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = ESR_9753_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ESR_9753_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = ESR_9753_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ESR_9753_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static void __init esr_9753_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(esr_9753_leds_gpio),
- esr_9753_leds_gpio);
-
- ramips_register_gpio_buttons(-1, ESR_9753_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(esr_9753_gpio_buttons),
- esr_9753_gpio_buttons);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_ESR_9753, "ESR-9753", "Senao / EnGenius ESR-9753",
- esr_9753_init);
+++ /dev/null
-/*
- * Belkin F5D8235 v2 board support
- *
- * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <linux/rtl8366.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define F5D8235_V2_GPIO_LED_INTERNET_BLUE 5
-#define F5D8235_V2_GPIO_LED_INTERNET_AMBER 6
-#define F5D8235_V2_GPIO_LED_MODEM_BLUE 11
-#define F5D8235_V2_GPIO_LED_MODEM_AMBER 8
-#define F5D8235_V2_GPIO_LED_ROUTER 9
-#define F5D8235_V2_GPIO_LED_STORAGE_BLUE 23
-#define F5D8235_V2_GPIO_LED_STORAGE_AMBER 22
-#define F5D8235_V2_GPIO_LED_SECURITY_BLUE 13
-#define F5D8235_V2_GPIO_LED_SECURITY_AMBER 12
-
-static struct gpio_led f5d8235v2_leds_gpio[] __initdata = {
- {
- .name = "f5d8235v2:blue:internet",
- .gpio = F5D8235_V2_GPIO_LED_INTERNET_BLUE,
- .active_low = 1,
- }, {
- .name = "f5d8235v2:amber:internet",
- .gpio = F5D8235_V2_GPIO_LED_INTERNET_AMBER,
- .active_low = 1,
- }, {
- .name = "f5d8235v2:blue:modem",
- .gpio = F5D8235_V2_GPIO_LED_MODEM_BLUE,
- .active_low = 1,
- }, {
- .name = "f5d8235v2:amber:modem",
- .gpio = F5D8235_V2_GPIO_LED_MODEM_AMBER,
- .active_low = 1,
- }, {
- .name = "f5d8235v2:blue:router",
- .gpio = F5D8235_V2_GPIO_LED_ROUTER,
- .active_low = 1,
- }, {
- .name = "f5d8235v2:blue:storage",
- .gpio = F5D8235_V2_GPIO_LED_STORAGE_BLUE,
- .active_low = 1,
- }, {
- .name = "f5d8235v2:amber:storage",
- .gpio = F5D8235_V2_GPIO_LED_STORAGE_AMBER,
- .active_low = 1,
- }, {
- .name = "f5d8235v2:blue:security",
- .gpio = F5D8235_V2_GPIO_LED_SECURITY_BLUE,
- .active_low = 1,
- }, {
- .name = "f5d8235v2:amber:security",
- .gpio = F5D8235_V2_GPIO_LED_SECURITY_AMBER,
- .active_low = 1,
- }
-};
-
-static struct rtl8366_platform_data f5d8235v2_switch_data = {
- .gpio_sda = RT305X_GPIO_I2C_SD,
- .gpio_sck = RT305X_GPIO_I2C_SCLK,
-};
-
-static struct platform_device f5d8235v2_switch = {
- .name = RTL8366RB_DRIVER_NAME,
- .id = -1,
- .dev = {
- .platform_data = &f5d8235v2_switch_data,
- }
-};
-
-static void __init f5d8235v2_init(void)
-{
- rt305x_gpio_init((RT305X_GPIO_MODE_GPIO <<
- RT305X_GPIO_MODE_UART0_SHIFT) |
- RT305X_GPIO_MODE_I2C |
- RT305X_GPIO_MODE_SPI |
- RT305X_GPIO_MODE_MDIO);
-
- rt305x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(f5d8235v2_leds_gpio),
- f5d8235v2_leds_gpio);
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE;
- rt305x_register_ethernet();
- platform_device_register(&f5d8235v2_switch);
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_F5D8235_V2, "F5D8235_V2", "Belkin F5D8235 v2",
- f5d8235v2_init);
+++ /dev/null
-/*
- * La Fonera20N board support
- *
- * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
- * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define FONERA20N_GPIO_BUTTON_RESET 12
-#define FONERA20N_GPIO_SWITCH 13
-#define FONERA20N_GPIO_LED_WIFI 7
-#define FONERA20N_GPIO_LED_POWER 9
-#define FONERA20N_GPIO_LED_USB 14
-
-#define FONERA20N_KEYS_POLL_INTERVAL 20
-#define FONERA20N_KEYS_DEBOUNCE_INTERVAL (3 * FONERA20N_KEYS_POLL_INTERVAL)
-
-static struct gpio_led fonera20n_leds_gpio[] __initdata = {
- {
- .name = "fonera20n:orange:wifi",
- .gpio = FONERA20N_GPIO_LED_WIFI,
- .active_low = 1,
- }, {
- .name = "fonera20n:green:power",
- .gpio = FONERA20N_GPIO_LED_POWER,
- .active_low = 1,
- }, {
- .name = "fonera20n:orange:usb",
- .gpio = FONERA20N_GPIO_LED_USB,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button fonera20n_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = FONERA20N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = FONERA20N_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "switch",
- .type = EV_KEY,
- .code = BTN_1,
- .debounce_interval = FONERA20N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = FONERA20N_GPIO_SWITCH,
- .active_low = 1,
- }
-};
-
-static void __init fonera20n_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(fonera20n_leds_gpio),
- fonera20n_leds_gpio);
-
- ramips_register_gpio_buttons(-1, FONERA20N_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(fonera20n_gpio_buttons),
- fonera20n_gpio_buttons);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_FONERA20N, "FONERA20N", "La Fonera 2.0N",
- fonera20n_init);
+++ /dev/null
-/*
- * ARC FreeStation2/5 board support
- *
- * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
- * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2012 Pau Escrich <p4u@dabax.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-static void __init freestation5_init(void)
-{
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_FREESTATION5, "FREESTATION5", "ARC FreeStation5",
- freestation5_init);
+++ /dev/null
-/*
- * Aztech HW550-3G board support
- *
- * Copyright (C) 2011 Layne Edwards <ledwards76@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define HW550_3G_GPIO_LED_USB 8
-#define HW550_3G_GPIO_LED_3G 11
-#define HW550_3G_GPIO_LED_STATUS 12
-#define HW550_3G_GPIO_LED_WPS 14
-
-#define HW550_3G_GPIO_BUTTON_RESET 10
-#define HW550_3G_GPIO_BUTTON_CONNECT 7
-#define HW550_3G_GPIO_BUTTON_WPS 0
-
-#define HW550_3G_KEYS_POLL_INTERVAL 20
-#define HW550_3G_KEYS_DEBOUNCE_INTERVAL (3 * HW550_3G_KEYS_POLL_INTERVAL)
-
-static struct gpio_led hw550_3g_leds_gpio[] __initdata = {
- {
- .name = "hw550-3g:green:usb",
- .gpio = HW550_3G_GPIO_LED_USB,
- .active_low = 1,
- }, {
- .name = "hw550-3g:green:3g",
- .gpio = HW550_3G_GPIO_LED_3G,
- .active_low = 1,
- }, {
- .name = "hw550-3g:green:status",
- .gpio = HW550_3G_GPIO_LED_STATUS,
- .active_low = 1,
- }, {
- .name = "hw550-3g:green:wps",
- .gpio = HW550_3G_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button hw550_3g_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL,
- .gpio = HW550_3G_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "connect",
- .type = EV_KEY,
- .code = KEY_CONNECT,
- .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL,
- .gpio = HW550_3G_GPIO_BUTTON_CONNECT,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = HW550_3G_KEYS_DEBOUNCE_INTERVAL,
- .gpio = HW550_3G_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-#define HW550_3G_GPIO_MODE \
- ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \
- RT305X_GPIO_MODE_MDIO)
-
-static void __init hw550_3g_init(void)
-{
- rt305x_gpio_init(HW550_3G_GPIO_MODE);
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(hw550_3g_leds_gpio),
- hw550_3g_leds_gpio);
- ramips_register_gpio_buttons(-1, HW550_3G_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(hw550_3g_gpio_buttons),
- hw550_3g_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_HW550_3G, "HW550-3G", "Aztech HW550-3G",
- hw550_3g_init);
-
-MIPS_MACHINE(RAMIPS_MACH_ALL0239_3G, "ALL0239-3G", "Allnet ALL0239-3G",
- hw550_3g_init);
+++ /dev/null
-/*
- * MoFi Network MOFI3500-3GN board support
- *
- * Copyright (C) 2011 Layne Edwards <ledwards76@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define MOFI3500_3GN_GPIO_LED_USB 8
-#define MOFI3500_3GN_GPIO_LED_3G 11
-#define MOFI3500_3GN_GPIO_LED_STATUS 12
-#define MOFI3500_3GN_GPIO_LED_WPS 14
-
-#define MOFI3500_3GN_GPIO_BUTTON_RESET 10
-#define MOFI3500_3GN_GPIO_BUTTON_CONNECT 7
-#define MOFI3500_3GN_GPIO_BUTTON_WPS 0
-
-#define MOFI3500_3GN_KEYS_POLL_INTERVAL 20
-#define MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL (3 * MOFI3500_3GN_KEYS_POLL_INTERVAL)
-
-static struct gpio_led mofi3500_3gn_leds_gpio[] __initdata = {
- {
- .name = "mofi3500-3gn:green:usb",
- .gpio = MOFI3500_3GN_GPIO_LED_USB,
- .active_low = 1,
- }, {
- .name = "mofi3500-3gn:green:3g",
- .gpio = MOFI3500_3GN_GPIO_LED_3G,
- .active_low = 1,
- }, {
- .name = "mofi3500-3gn:green:status",
- .gpio = MOFI3500_3GN_GPIO_LED_STATUS,
- .active_low = 1,
- }, {
- .name = "mofi3500-3gn:green:wps",
- .gpio = MOFI3500_3GN_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button mofi3500_3gn_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL,
- .gpio = MOFI3500_3GN_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "connect",
- .type = EV_KEY,
- .code = KEY_CONNECT,
- .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL,
- .gpio = MOFI3500_3GN_GPIO_BUTTON_CONNECT,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = MOFI3500_3GN_KEYS_DEBOUNCE_INTERVAL,
- .gpio = MOFI3500_3GN_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-#define MOFI3500_3GN_GPIO_MODE \
- ((RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT) | \
- RT305X_GPIO_MODE_MDIO)
-
-static void __init mofi3500_3gn_init(void)
-{
- rt305x_gpio_init(MOFI3500_3GN_GPIO_MODE);
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(mofi3500_3gn_leds_gpio),
- mofi3500_3gn_leds_gpio);
- ramips_register_gpio_buttons(-1, MOFI3500_3GN_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(mofi3500_3gn_gpio_buttons),
- mofi3500_3gn_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_MOFI3500_3GN, "MOFI3500-3GN", "MoFi Network MOFI3500-3GN",
- mofi3500_3gn_init);
+++ /dev/null
-/*
- * Planex MZK-W300NH2 board support
- *
- * Copyright (C) 2012 Samir Ibradžić <sibradzic@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define MZKW300NH2_GPIO_BUTTON_RESET 0 /* active low */
-#define MZKW300NH2_GPIO_BUTTON_WPS 12 /* active low */
-#define MZKW300NH2_GPIO_SWITCH_MODE_RT 13 /* active low */
-
-#define MZKW300NH2_GPIO_LED_POWER 9
-#define MZKW300NH2_GPIO_LED_WLAN 14
-#define MZKW300NH2_GPIO_LED_WPS 11
-
-#define MZKW300NH2_KEYS_POLL_INTERVAL 20
-#define MZKW300NH2_KEYS_DEBOUNCE_INTERVAL (3 * MZKW300NH2_KEYS_POLL_INTERVAL)
-
-static struct gpio_led mzkw300nh2_leds_gpio[] __initdata = {
- {
- .name = "mzkw300nh2:green:power",
- .gpio = MZKW300NH2_GPIO_LED_POWER,
- .active_low = 1,
- }, {
- .name = "mzkw300nh2:amber:wlan",
- .gpio = MZKW300NH2_GPIO_LED_WLAN,
- .active_low = 1,
- }, {
- .name = "mzkw300nh2:amber:wps",
- .gpio = MZKW300NH2_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button mzkw300nh2_gpio_buttons[] __initdata = {
- {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL,
- .gpio = MZKW300NH2_GPIO_BUTTON_WPS,
- .active_low = 1,
- }, {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL,
- .gpio = MZKW300NH2_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "rt",
- .type = EV_KEY,
- .code = BTN_0,
- .debounce_interval = MZKW300NH2_KEYS_DEBOUNCE_INTERVAL,
- .gpio = MZKW300NH2_GPIO_SWITCH_MODE_RT,
- .active_low = 1,
- }
-};
-
-static void __init mzkw300nh2_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_UART0(RT305X_GPIO_MODE_GPIO) |
- RT305X_GPIO_MODE_I2C |
- RT305X_GPIO_MODE_SPI |
- RT305X_GPIO_MODE_JTAG);
-
- rt305x_register_flash(0);
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(mzkw300nh2_leds_gpio),
- mzkw300nh2_leds_gpio);
- ramips_register_gpio_buttons(-1, MZKW300NH2_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(mzkw300nh2_gpio_buttons),
- mzkw300nh2_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_MZKW300NH2, "MZK-W300NH2", "Planex MZK-W300NH2",
- mzkw300nh2_init);
+++ /dev/null
-/*
- * ZyXEL NBG-419N board support
- *
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define NBG_419N_GPIO_LED_POWER 9
-#define NBG_419N_GPIO_LED_WPS 14
-
-#define NBG_419N_GPIO_BUTTON_WPS 0 /* active low */
-#define NBG_419N_GPIO_BUTTON_RESET 10 /* active low */
-
-#define NBG_419N_KEYS_POLL_INTERVAL 20
-#define NBG_419N_KEYS_DEBOUNCE_INTERVAL (3 * NBG_419N_KEYS_POLL_INTERVAL)
-
-static struct gpio_led nbg_419n_leds_gpio[] __initdata = {
- {
- .name = "nbg-419n:green:power",
- .gpio = NBG_419N_GPIO_LED_POWER,
- .active_low = 1,
- }, {
- .name = "nbg-419n:green:wps",
- .gpio = NBG_419N_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button nbg_419n_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = NBG_419N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = NBG_419N_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = NBG_419N_KEYS_DEBOUNCE_INTERVAL,
- .gpio = NBG_419N_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static void __init nbg_419n_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(nbg_419n_leds_gpio),
- nbg_419n_leds_gpio);
- ramips_register_gpio_buttons(-1, NBG_419N_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(nbg_419n_gpio_buttons),
- nbg_419n_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_NBG_419N, "NBG-419N", "ZyXEL NBG-419N", nbg_419n_init);
+++ /dev/null
-/*
- * Netcore NW718 board support
- *
- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define NW718_GPIO_LED_USB 8
-#define NW718_GPIO_LED_CPU 13
-#define NW718_GPIO_LED_WPS 14
-
-#define NW718_GPIO_BUTTON_WPS 0
-#define NW718_GPIO_BUTTON_RESET 10
-
-#define NW718_GPIO_SPI_CS0 3
-
-#define NW718_KEYS_POLL_INTERVAL 20
-#define NW718_KEYS_DEBOUNCE_INTERVAL (3 * NW718_KEYS_POLL_INTERVAL)
-
-static struct gpio_led nw718_leds_gpio[] __initdata = {
- {
- .name = "nw718:amber:cpu",
- .gpio = NW718_GPIO_LED_CPU,
- .active_low = 1,
- }, {
- .name = "nw718:amber:usb",
- .gpio = NW718_GPIO_LED_USB,
- .active_low = 1,
- }, {
- .name = "nw718:amber:wps",
- .gpio = NW718_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button nw718_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = NW718_KEYS_DEBOUNCE_INTERVAL,
- .gpio = NW718_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = NW718_KEYS_DEBOUNCE_INTERVAL,
- .gpio = NW718_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static struct spi_board_info nw718_spi_info[] = {
- {
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 25000000,
- .modalias = "m25p80",
- }
-};
-
-static void __init nw718_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_I2C |
- RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(nw718_leds_gpio),
- nw718_leds_gpio);
- ramips_register_gpio_buttons(-1, NW718_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(nw718_gpio_buttons),
- nw718_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_spi(nw718_spi_info, ARRAY_SIZE(nw718_spi_info));
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_WHR_G300N, "NW718", "Netcore NW718", nw718_init);
+++ /dev/null
-/*
- * Omnima MiniEMBWiFi board support
- *
- * Copyright (C) 2011 Johnathan Boyce <jon.boyce@globalreach.eu.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define OMNI_EMB_GPIO_BUTTON_RESET 12 /* active low */
-
-#define OMNI_EMB_KEYS_POLL_INTERVAL 20
-#define OMNI_EMB_KEYS_DEBOUNCE_INTERVAL (3 * OMNI_EMB_KEYS_POLL_INTERVAL)
-
-#define OMNI_EMB_GPIO_LED_STATUS 9
-#define OMNI_EMB_GPIO_LED_WLAN 14
-
-static struct gpio_led omni_emb_leds_gpio[] __initdata = {
- {
- .name = "emb:green:status",
- .gpio = OMNI_EMB_GPIO_LED_STATUS,
- .active_low = 1,
- }, {
- .name = "emb:green:wlan",
- .gpio = OMNI_EMB_GPIO_LED_WLAN,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button omni_emb_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = OMNI_EMB_KEYS_DEBOUNCE_INTERVAL,
- .gpio = OMNI_EMB_GPIO_BUTTON_RESET,
- .active_low = 1,
- }
-};
-
-static void __init omni_emb_init(void)
-{
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
-
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(omni_emb_leds_gpio),
- omni_emb_leds_gpio);
- ramips_register_gpio_buttons(-1, OMNI_EMB_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(omni_emb_gpio_buttons),
- omni_emb_gpio_buttons);
-
- rt305x_register_flash(0);
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_OMNI_EMB, "OMNI-EMB", "Omnima MiniEMBWiFi",
- omni_emb_init);
+++ /dev/null
-/*
- * Petatel PSR-680W Wireless 3G Router support
- *
- * Copyright (C) 2012 Dmitry Shmygov <shmygov@rambler.ru>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define PSR_680W_GPIO_BUTTON_RESET 0 /* active low */
-
-#define PSR_680W_GPIO_LED_STATUS 19
-
-#define PSR_680W_KEYS_POLL_INTERVAL 20
-#define PSR_680W_KEYS_DEBOUNCE_INTERVAL (3 * PSR_680W_KEYS_POLL_INTERVAL)
-
-
-static struct gpio_led psr_680w_leds_gpio[] __initdata = {
- {
- .name = "psr-680w:red:wan",
- .gpio = PSR_680W_GPIO_LED_STATUS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button psr_680w_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = PSR_680W_KEYS_DEBOUNCE_INTERVAL,
- .gpio = PSR_680W_GPIO_BUTTON_RESET,
- .active_low = 1,
- }
-};
-
-static void __init psr_680w_init(void)
-{
- rt305x_gpio_init((RT305X_GPIO_MODE_I2S_UARTF << RT305X_GPIO_MODE_UART0_SHIFT) |
- RT305X_GPIO_MODE_SPI |
- RT305X_GPIO_MODE_JTAG |
- RT305X_GPIO_MODE_MDIO |
- RT305X_GPIO_MODE_RGMII);
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(psr_680w_leds_gpio),
- psr_680w_leds_gpio);
- ramips_register_gpio_buttons(-1, PSR_680W_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(psr_680w_gpio_buttons),
- psr_680w_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_PSR_680W, "PSR-680W",
- "Petatel PSR-680W Wireless 3G Router",
- psr_680w_init);
+++ /dev/null
-/*
- * Prolink PWH2004 support (or Abocom WR5205)
- *
- * Copyright (C) 2010 Esa Hyytia <esa@netlab.tkk.fi>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define PWH2004_GPIO_BUTTON_WPS 12
-#define PWH2004_GPIO_LED_POWER 9
-#define PWH2004_GPIO_LED_WIFI 14
-#define PWH2004_KEYS_POLL_INTERVAL 20
-#define PWH2004_KEYS_DEBOUNCE_INTERVAL (3 * PWH2004_KEYS_POLL_INTERVAL)
-
-static struct gpio_led pwh2004_leds_gpio[] __initdata = {
- {
- .name = "pwh2004:red:wifi",
- .gpio = PWH2004_GPIO_LED_WIFI,
- .active_low = 1,
- }, {
- .name = "pwh2004:green:power",
- .gpio = PWH2004_GPIO_LED_POWER,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button pwh2004_gpio_buttons[] __initdata = {
- {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = PWH2004_KEYS_DEBOUNCE_INTERVAL,
- .gpio = PWH2004_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static void __init pwh2004_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(pwh2004_leds_gpio),
- pwh2004_leds_gpio);
- ramips_register_gpio_buttons(-1, PWH2004_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(pwh2004_gpio_buttons),
- pwh2004_gpio_buttons);
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_PWH2004, "PWH2004", "Prolink PWH2004",
- pwh2004_init);
+++ /dev/null
-/*
- * Asus RT-G32 rev B board support
- *
- * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define RT_G32B_GPIO_BUTTON_WPS 0 /* active low */
-#define RT_G32B_GPIO_BUTTON_RESET 10 /* active low */
-
-#define RT_G32B_KEYS_POLL_INTERVAL 20
-#define RT_G32B_KEYS_DEBOUNCE_INTERVAL (3 * RT_G32B_KEYS_POLL_INTERVAL)
-
-const struct flash_platform_data rt_g32b_flash = {
- .type = "mx25l3205d",
-};
-
-struct spi_board_info __initdata rt_g32b_spi_slave_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &rt_g32b_flash,
- .irq = -1,
- .max_speed_hz = 10000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static struct gpio_keys_button rt_g32b_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = RT_G32B_KEYS_DEBOUNCE_INTERVAL,
- .gpio = RT_G32B_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = RT_G32B_KEYS_DEBOUNCE_INTERVAL,
- .gpio = RT_G32B_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static void __init rt_g32b_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
- rt305x_register_spi(rt_g32b_spi_slave_info,
- ARRAY_SIZE(rt_g32b_spi_slave_info));
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- ramips_register_gpio_buttons(-1, RT_G32B_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(rt_g32b_gpio_buttons),
- rt_g32b_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_RT_G32_B1, "RT-G32-B1", "Asus RT-G32 B1",
- rt_g32b_init);
+++ /dev/null
-/*
- * ASUS RT-N10+ board support
- *
- * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define RT_N10_PLUS_GPIO_LED_WPS 14
-
-#define RT_N10_PLUS_GPIO_BUTTON_WPS 0 /* active low */
-#define RT_N10_PLUS_GPIO_BUTTON_RESET 10 /* active low */
-
-#define RT_N10_PLUS_KEYS_POLL_INTERVAL 20
-#define RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL (3 * RT_N10_PLUS_KEYS_POLL_INTERVAL)
-
-static struct gpio_led rt_n10_plus_leds_gpio[] __initdata = {
- {
- .name = "asus:green:wps",
- .gpio = RT_N10_PLUS_GPIO_LED_WPS,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button rt_n10_plus_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL,
- .gpio = RT_N10_PLUS_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = RT_N10_PLUS_KEYS_DEBOUNCE_INTERVAL,
- .gpio = RT_N10_PLUS_GPIO_BUTTON_WPS,
- .active_low = 1,
- }
-};
-
-static void __init rt_n10_plus_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_WLLLL;
- rt305x_register_ethernet();
- ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n10_plus_leds_gpio),
- rt_n10_plus_leds_gpio);
- ramips_register_gpio_buttons(-1, RT_N10_PLUS_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(rt_n10_plus_gpio_buttons),
- rt_n10_plus_gpio_buttons);
- rt305x_register_wifi();
- rt305x_register_wdt();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_RT_N10_PLUS, "RT-N10-PLUS", "Asus RT-N10+",
- rt_n10_plus_init);
+++ /dev/null
-/*
- * ASUS RT-N13U board support
- *
- * Copyright (C) 2012 lintel<lintel.huang@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define RT_N13U_GPIO_BUTTON_RESET 10
-#define RT_N13U_GPIO_BUTTON_WPS 0
-
-#define RT_N13U_GPIO_LED_POWER 7
-#define RT_N13U_GPIO_LED_WIFI 8
-
-
-#define RT_N13U_BUTTONS_POLL_INTERVAL 10
-#define RT_N13U_BUTTONS_DEBOUNCE_INTERVAL (3 * RT_N13U_BUTTONS_POLL_INTERVAL)
-
-static struct gpio_led rt_n13u_leds_gpio[] __initdata = {
- {
- .name = "rt-n13u:power",
- .gpio = RT_N13U_GPIO_LED_POWER,
- .active_low = 1,
- }, {
- .name = "rt-n13u:wifi",
- .gpio = RT_N13U_GPIO_LED_WIFI,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button rt_n13u_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = RT_N13U_BUTTONS_DEBOUNCE_INTERVAL,
- .gpio = RT_N13U_GPIO_BUTTON_RESET,
- .active_low = 1,
- }, {
- .desc = "wps",
- .type = EV_KEY,
- .code = KEY_WPS_BUTTON,
- .debounce_interval = RT_N13U_BUTTONS_DEBOUNCE_INTERVAL,
- .gpio = RT_N13U_GPIO_BUTTON_WPS,
- .active_low = 1,
- },
-};
-
-static void __init rt_n13u_init(void)
-{
- rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
-
- rt305x_register_flash(0);
-
- ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n13u_leds_gpio),
- rt_n13u_leds_gpio);
-
- ramips_register_gpio_buttons(-1, RT_N13U_BUTTONS_POLL_INTERVAL,
- ARRAY_SIZE(rt_n13u_gpio_buttons),
- rt_n13u_gpio_buttons);
-
- rt305x_esw_data.vlan_config = RT305X_ESW_VLAN_CONFIG_LLLLW;
- rt305x_register_ethernet();
- rt305x_register_wifi();
- rt305x_register_wdt();
- rt305x_register_usb();
-}
-
-MIPS_MACHINE(RAMIPS_MACH_RT_N13U, "RT-N13U", "Asus RT-N13U",
- rt_n13u_init);
+++ /dev/null
-/*
- * Skyline SL-R7205 Wireless 3G Router support
- *
- * Copyright (C) 2012 Haipoh Teoh <hpteoh@ceedtec.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-ralink/machine.h>
-#include <asm/mach-ralink/dev-gpio-buttons.h>
-#include <asm/mach-ralink/dev-gpio-leds.h>
-#include <asm/mach-ralink/rt305x.h>
-#include <asm/mach-ralink/rt305x_regs.h>
-
-#include "devices.h"
-
-#define SL_R7205_GPIO_BUTTON_WPS 0
-#define SL_R7205_GPIO_BUTTON_RESET 10 /* active low */
-
-#define SL_R7205_GPIO_LED_WIFI 7
-
-#define SL_R7205_KEYS_POLL_INTERVAL 20
-#define SL_R7205_KEYS_DEBOUNCE_INTERVAL (3 * SL_R7205_KEYS_POLL_INTERVAL)
-
-static struct gpio_led sl_r7205_leds_gpio[] __initdata = {
- {
- .name = "sl-r7205:green:wifi",
- .gpio = SL_R7205_GPIO_LED_WIFI,
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_button sl_r7205_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- &nb
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