FEATURES:=squashfs gpio mips16
MAINTAINER:=John Crispin <blogic@openwrt.org>
-KERNEL_PATCHVER:=4.3
+KERNEL_PATCHVER:=4.4
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_STATE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-# CONFIG_ARCH_HAS_SG_CHAIN is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-# CONFIG_GPIO_MT7621 is not set
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-# CONFIG_HAVE_ARCH_BITREVERSE is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-# CONFIG_MACH_INGENIC is not set
-# CONFIG_MACH_LOONGSON32 is not set
-# CONFIG_MACH_LOONGSON64 is not set
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_NO_APPENDED_DTB=y
-# CONFIG_MIPS_RAW_APPENDED_DTB is not set
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MT7621_WDT is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_MT7620=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_MEDIATEK_GSW_MT7620=y
-CONFIG_NET_MEDIATEK_MDIO=y
-CONFIG_NET_MEDIATEK_MDIO_MT7620=y
-CONFIG_NET_MEDIATEK_MT7620=y
-# CONFIG_NET_MEDIATEK_RT3050 is not set
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-# CONFIG_NO_IOPORT_MAP is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_WDT=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCHED_INFO is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SG_SPLIT is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-# CONFIG_SUNXI_SRAM is not set
-CONFIG_SWCONFIG=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AT803X_PHY=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+# CONFIG_GPIO_MT7621 is not set
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_NO_APPENDED_DTB=y
+# CONFIG_MIPS_RAW_APPENDED_DTB is not set
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MT7621_WDT is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND_MT7620=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_MEDIATEK_GSW_MT7620=y
+CONFIG_NET_MEDIATEK_MDIO=y
+CONFIG_NET_MEDIATEK_MDIO_MT7620=y
+CONFIG_NET_MEDIATEK_MT7620=y
+# CONFIG_NET_MEDIATEK_RT3050 is not set
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_WDT=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SCHED_HRTICK=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_FSL is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_STATE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-# CONFIG_ARCH_HAS_SG_CHAIN is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-# CONFIG_HAVE_ARCH_BITREVERSE is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-# CONFIG_MACH_INGENIC is not set
-# CONFIG_MACH_LOONGSON32 is not set
-# CONFIG_MACH_LOONGSON64 is not set
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_NO_APPENDED_DTB=y
-# CONFIG_MIPS_RAW_APPENDED_DTB is not set
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_MT7620=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_MEDIATEK_ESW_RT3050=y
-# CONFIG_NET_MEDIATEK_MT7620 is not set
-CONFIG_NET_MEDIATEK_RT3050=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-# CONFIG_NO_IOPORT_MAP is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_RALINK=y
-# CONFIG_RALINK_WDT is not set
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCHED_INFO is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SG_SPLIT is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_SRCU=y
-# CONFIG_SUNXI_SRAM is not set
-CONFIG_SWCONFIG=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AT803X_PHY=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_NO_APPENDED_DTB=y
+# CONFIG_MIPS_RAW_APPENDED_DTB is not set
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND_MT7620=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_MEDIATEK_ESW_RT3050=y
+# CONFIG_NET_MEDIATEK_MT7620 is not set
+CONFIG_NET_MEDIATEK_RT3050=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_RALINK=y
+# CONFIG_RALINK_WDT is not set
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SCHED_HRTICK=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_FSL is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_STATE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-# CONFIG_ARCH_HAS_SG_CHAIN is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-# CONFIG_HAVE_ARCH_BITREVERSE is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-# CONFIG_MACH_INGENIC is not set
-# CONFIG_MACH_LOONGSON32 is not set
-# CONFIG_MACH_LOONGSON64 is not set
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-CONFIG_MIPS_FPU_EMULATOR=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_NO_APPENDED_DTB=y
-# CONFIG_MIPS_RAW_APPENDED_DTB is not set
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_MT7620=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_MEDIATEK_ESW_RT3050=y
-# CONFIG_NET_MEDIATEK_MT7620 is not set
-CONFIG_NET_MEDIATEK_RT3050=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-# CONFIG_NO_IOPORT_MAP is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RALINK=y
-# CONFIG_RALINK_WDT is not set
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCHED_INFO is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-# CONFIG_SERIAL_8250_RT288X is not set
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SG_SPLIT is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_SPI_SPIDEV=y
-CONFIG_SRCU=y
-# CONFIG_SUNXI_SRAM is not set
-CONFIG_SWCONFIG=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AT803X_PHY=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+CONFIG_MIPS_FPU_EMULATOR=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_NO_APPENDED_DTB=y
+# CONFIG_MIPS_RAW_APPENDED_DTB is not set
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND_MT7620=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_MEDIATEK_ESW_RT3050=y
+# CONFIG_NET_MEDIATEK_MT7620 is not set
+CONFIG_NET_MEDIATEK_RT3050=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RALINK=y
+# CONFIG_RALINK_WDT is not set
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SCHED_HRTICK=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_FSL is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_SPI_SPIDEV=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:08:31 +0100
-Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/irq.h | 9 +
- arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
- arch/mips/kernel/mips-cm.c | 4 +-
- arch/mips/kernel/vmlinux.lds.S | 1 +
- arch/mips/ralink/Kconfig | 18 ++
- arch/mips/ralink/Makefile | 7 +-
- arch/mips/ralink/Platform | 5 +
- arch/mips/ralink/irq-gic.c | 268 ++++++++++++++++++++++++++++
- arch/mips/ralink/malta-amon.c | 81 +++++++++
- arch/mips/ralink/mt7621.c | 209 ++++++++++++++++++++++
- 10 files changed, 638 insertions(+), 3 deletions(-)
- create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
- create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
- create mode 100644 arch/mips/ralink/irq-gic.c
- create mode 100644 arch/mips/ralink/malta-amon.c
- create mode 100644 arch/mips/ralink/mt7621.c
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/irq.h
-@@ -0,0 +1,9 @@
-+#ifndef __ASM_MACH_RALINK_IRQ_H
-+#define __ASM_MACH_RALINK_IRQ_H
-+
-+#define GIC_NUM_INTRS 64
-+#define NR_IRQS 256
-+
-+#include_next <irq.h>
-+
-+#endif
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
-@@ -0,0 +1,42 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Parts of this file are based on Ralink's 2.6.21 BSP
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#ifndef _MT7621_REGS_H_
-+#define _MT7621_REGS_H_
-+
-+#define MT7621_PALMBUS_BASE 0x1C000000
-+#define MT7621_PALMBUS_SIZE 0x03FFFFFF
-+
-+#define MT7621_SYSC_BASE 0x1E000000
-+
-+#define SYSC_REG_CHIP_NAME0 0x00
-+#define SYSC_REG_CHIP_NAME1 0x04
-+#define SYSC_REG_CHIP_REV 0x0c
-+#define SYSC_REG_SYSTEM_CONFIG0 0x10
-+#define SYSC_REG_SYSTEM_CONFIG1 0x14
-+
-+#define CHIP_REV_PKG_MASK 0x1
-+#define CHIP_REV_PKG_SHIFT 16
-+#define CHIP_REV_VER_MASK 0xf
-+#define CHIP_REV_VER_SHIFT 8
-+#define CHIP_REV_ECO_MASK 0xf
-+
-+#define MT7621_DRAM_BASE 0x0
-+#define MT7621_DDR2_SIZE_MIN 32
-+#define MT7621_DDR2_SIZE_MAX 256
-+
-+#define MT7621_CHIP_NAME0 0x3637544D
-+#define MT7621_CHIP_NAME1 0x20203132
-+
-+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
-+
-+#endif
---- a/arch/mips/kernel/vmlinux.lds.S
-+++ b/arch/mips/kernel/vmlinux.lds.S
-@@ -51,6 +51,7 @@ SECTIONS
- /* read-only */
- _text = .; /* Text and read-only data */
- .text : {
-+ /*. = . + 0x8000; */
- TEXT_TEXT
- SCHED_TEXT
- LOCK_TEXT
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -12,6 +12,11 @@ config RALINK_ILL_ACC
- depends on SOC_RT305X
- default y
-
-+config IRQ_INTC
-+ bool
-+ default y
-+ depends on !SOC_MT7621
-+
- choice
- prompt "Ralink SoC selection"
- default SOC_RT305X
-@@ -34,6 +39,16 @@ choice
- config SOC_MT7620
- bool "MT7620/8"
-
-+ config SOC_MT7621
-+ bool "MT7621"
-+ select MIPS_CPU_SCACHE
-+ select SYS_SUPPORTS_MULTITHREADING
-+ select SYS_SUPPORTS_SMP
-+ select SYS_SUPPORTS_MIPS_CPS
-+ select MIPS_GIC
-+ select COMMON_CLK
-+ select CLKSRC_MIPS_GIC
-+ select HW_HAS_PCI
- endchoice
-
- choice
-@@ -65,6 +80,10 @@ choice
- depends on SOC_MT7620
- select BUILTIN_DTB
-
-+ config DTB_MT7621_EVAL
-+ bool "MT7621 eval kit"
-+ depends on SOC_MT7621
-+
- endchoice
-
- endif
---- a/arch/mips/ralink/Makefile
-+++ b/arch/mips/ralink/Makefile
-@@ -6,16 +6,24 @@
- # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-
--obj-y := prom.o of.o reset.o clk.o irq.o timer.o
-+obj-y := prom.o of.o reset.o
-+
-+ifndef CONFIG_MIPS_GIC
-+ obj-y += clk.o timer.o
-+endif
-
- obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
-
- obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
-
-+obj-$(CONFIG_IRQ_INTC) += irq.o
-+obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o
-+
- obj-$(CONFIG_SOC_RT288X) += rt288x.o
- obj-$(CONFIG_SOC_RT305X) += rt305x.o
- obj-$(CONFIG_SOC_RT3883) += rt3883.o
- obj-$(CONFIG_SOC_MT7620) += mt7620.o
-+obj-$(CONFIG_SOC_MT7621) += mt7621.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
---- a/arch/mips/ralink/Platform
-+++ b/arch/mips/ralink/Platform
-@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
- #
- load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
- cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
-+
-+# Ralink MT7621
-+#
-+load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
-+cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
---- /dev/null
-+++ b/arch/mips/ralink/irq-gic.c
-@@ -0,0 +1,18 @@
-+#include <linux/init.h>
-+
-+#include <linux/of.h>
-+#include <linux/irqchip.h>
-+#include <linux/irqchip/mips-gic.h>
-+
-+int get_c0_perfcount_int(void)
-+{
-+ return gic_get_c0_perfcount_int();
-+}
-+EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
-+
-+void __init
-+arch_init_irq(void)
-+{
-+ irqchip_init();
-+}
-+
---- /dev/null
-+++ b/arch/mips/ralink/mt7621.c
-@@ -0,0 +1,223 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Parts of this file are based on Ralink's 2.6.21 BSP
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+
-+#include <asm/mipsregs.h>
-+#include <asm/smp-ops.h>
-+#include <asm/mips-cm.h>
-+#include <asm/mips-cpc.h>
-+#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/mach-ralink/mt7621.h>
-+
-+#include <pinmux.h>
-+
-+#include "common.h"
-+
-+#define SYSC_REG_SYSCFG 0x10
-+#define SYSC_REG_CPLL_CLKCFG0 0x2c
-+#define SYSC_REG_CUR_CLK_STS 0x44
-+#define CPU_CLK_SEL (BIT(30) | BIT(31))
-+
-+#define MT7621_GPIO_MODE_UART1 1
-+#define MT7621_GPIO_MODE_I2C 2
-+#define MT7621_GPIO_MODE_UART3_MASK 0x3
-+#define MT7621_GPIO_MODE_UART3_SHIFT 3
-+#define MT7621_GPIO_MODE_UART3_GPIO 1
-+#define MT7621_GPIO_MODE_UART2_MASK 0x3
-+#define MT7621_GPIO_MODE_UART2_SHIFT 5
-+#define MT7621_GPIO_MODE_UART2_GPIO 1
-+#define MT7621_GPIO_MODE_JTAG 7
-+#define MT7621_GPIO_MODE_WDT_MASK 0x3
-+#define MT7621_GPIO_MODE_WDT_SHIFT 8
-+#define MT7621_GPIO_MODE_WDT_GPIO 1
-+#define MT7621_GPIO_MODE_PCIE_RST 0
-+#define MT7621_GPIO_MODE_PCIE_REF 2
-+#define MT7621_GPIO_MODE_PCIE_MASK 0x3
-+#define MT7621_GPIO_MODE_PCIE_SHIFT 10
-+#define MT7621_GPIO_MODE_PCIE_GPIO 1
-+#define MT7621_GPIO_MODE_MDIO_MASK 0x3
-+#define MT7621_GPIO_MODE_MDIO_SHIFT 12
-+#define MT7621_GPIO_MODE_MDIO_GPIO 1
-+#define MT7621_GPIO_MODE_RGMII1 14
-+#define MT7621_GPIO_MODE_RGMII2 15
-+#define MT7621_GPIO_MODE_SPI_MASK 0x3
-+#define MT7621_GPIO_MODE_SPI_SHIFT 16
-+#define MT7621_GPIO_MODE_SPI_GPIO 1
-+#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
-+#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
-+#define MT7621_GPIO_MODE_SDHCI_GPIO 1
-+
-+static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
-+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
-+static struct rt2880_pmx_func uart3_grp[] = {
-+ FUNC("uart3", 0, 5, 4),
-+ FUNC("i2s", 2, 5, 4),
-+ FUNC("spdif3", 3, 5, 4),
-+};
-+static struct rt2880_pmx_func uart2_grp[] = {
-+ FUNC("uart2", 0, 9, 4),
-+ FUNC("pcm", 2, 9, 4),
-+ FUNC("spdif2", 3, 9, 4),
-+};
-+static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
-+static struct rt2880_pmx_func wdt_grp[] = {
-+ FUNC("wdt rst", 0, 18, 1),
-+ FUNC("wdt refclk", 2, 18, 1),
-+};
-+static struct rt2880_pmx_func pcie_rst_grp[] = {
-+ FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
-+ FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
-+};
-+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
-+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
-+static struct rt2880_pmx_func spi_grp[] = {
-+ FUNC("spi", 0, 34, 7),
-+ FUNC("nand1", 2, 34, 7),
-+};
-+static struct rt2880_pmx_func sdhci_grp[] = {
-+ FUNC("sdhci", 0, 41, 8),
-+ FUNC("nand2", 2, 41, 8),
-+};
-+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
-+
-+static struct rt2880_pmx_group mt7621_pinmux_data[] = {
-+ GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
-+ GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
-+ GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
-+ MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
-+ GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
-+ MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
-+ GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
-+ GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
-+ MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
-+ GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
-+ MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
-+ GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
-+ MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
-+ GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
-+ GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
-+ MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
-+ GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
-+ MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
-+ GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
-+ { 0 }
-+};
-+
-+phys_addr_t mips_cpc_default_phys_base() {
-+ panic("Cannot detect cpc address");
-+}
-+
-+void __init ralink_clk_init(void)
-+{
-+ int cpu_fdiv = 0;
-+ int cpu_ffrac = 0;
-+ int fbdiv = 0;
-+ u32 clk_sts, syscfg;
-+ u8 clk_sel = 0, xtal_mode;
-+ u32 cpu_clk;
-+
-+ if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
-+ clk_sel = 1;
-+
-+ switch (clk_sel) {
-+ case 0:
-+ clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
-+ cpu_fdiv = ((clk_sts >> 8) & 0x1F);
-+ cpu_ffrac = (clk_sts & 0x1F);
-+ cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
-+ break;
-+
-+ case 1:
-+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
-+ syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
-+ xtal_mode = (syscfg >> 6) & 0x7;
-+ if(xtal_mode >= 6) { //25Mhz Xtal
-+ cpu_clk = 25 * fbdiv * 1000 * 1000;
-+ } else if(xtal_mode >=3) { //40Mhz Xtal
-+ cpu_clk = 40 * fbdiv * 1000 * 1000;
-+ } else { // 20Mhz Xtal
-+ cpu_clk = 20 * fbdiv * 1000 * 1000;
-+ }
-+ break;
-+ }
-+}
-+
-+void __init ralink_of_remap(void)
-+{
-+ rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-+ rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
-+
-+ if (!rt_sysc_membase || !rt_memc_membase)
-+ panic("Failed to remap core resources");
-+}
-+
-+void prom_soc_init(struct ralink_soc_info *soc_info)
-+{
-+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
-+ unsigned char *name = NULL;
-+ u32 n0;
-+ u32 n1;
-+ u32 rev;
-+
-+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
-+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-+
-+ if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
-+ name = "MT7621";
-+ soc_info->compatible = "mtk,mt7621-soc";
-+ } else {
-+ panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
-+ }
-+
-+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
-+
-+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
-+ "MediaTek %s ver:%u eco:%u",
-+ name,
-+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
-+ (rev & CHIP_REV_ECO_MASK));
-+
-+ soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
-+ soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
-+ soc_info->mem_base = MT7621_DRAM_BASE;
-+
-+ rt2880_pinmux_data = mt7621_pinmux_data;
-+
-+ /* Early detection of CMP support */
-+ mips_cm_probe();
-+ mips_cpc_probe();
-+
-+ if (mips_cm_numiocu()) {
-+ /* mips_cm_probe() wipes out bootloader
-+ config for CM regions and we have to configure them
-+ again. This SoC cannot talk to pamlbus devices
-+ witout proper iocu region set up.
-+
-+ FIXME: it would be better to do this with values
-+ from DT, but we need this very early because
-+ without this we cannot talk to pretty much anything
-+ including serial.
-+ */
-+ write_gcr_reg0_base(MT7621_PALMBUS_BASE);
-+ write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-+ }
-+
-+ if (!register_cps_smp_ops())
-+ return;
-+ if (!register_cmp_smp_ops())
-+ return;
-+ if (!register_vsmp_smp_ops())
-+ return;
-+}
---- /dev/null
-+++ b/arch/mips/ralink/timer-gic.c
-@@ -0,0 +1,15 @@
-+#include <linux/init.h>
-+
-+#include <linux/of.h>
-+#include <linux/clk-provider.h>
-+#include <linux/clocksource.h>
-+
-+#include "common.h"
-+
-+void __init plat_time_init(void)
-+{
-+ ralink_of_remap();
-+
-+ of_clk_init(NULL);
-+ clocksource_of_init();
-+}
+++ /dev/null
-From c96f2cc4d5f6e1bb11f3e7e04a7e21503a214d7c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 27 Jan 2014 13:12:41 +0000
-Subject: [PATCH 02/53] MIPS: ralink: add MT7621 defconfig
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/configs/mt7621_defconfig | 197 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 197 insertions(+)
- create mode 100644 arch/mips/configs/mt7621_defconfig
-
---- /dev/null
-+++ b/arch/mips/configs/mt7621_defconfig
-@@ -0,0 +1,197 @@
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_RCU_FANOUT=32
-+CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-mipsel_24kec+dsp_uClibc-0.9.33.2/root-ramips /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
-+CONFIG_INITRAMFS_ROOT_UID=1000
-+CONFIG_INITRAMFS_ROOT_GID=1000
-+# CONFIG_RD_GZIP is not set
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+# CONFIG_AIO is not set
-+CONFIG_EMBEDDED=y
-+# CONFIG_VM_EVENT_COUNTERS is not set
-+# CONFIG_SLUB_DEBUG is not set
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_BLK_DEV_BSG is not set
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_IOSCHED_CFQ is not set
-+CONFIG_SMP=y
-+CONFIG_NR_CPUS=4
-+CONFIG_SCHED_SMT=y
-+# CONFIG_COMPACTION is not set
-+# CONFIG_CROSS_MEMORY_ATTACH is not set
-+# CONFIG_SECCOMP is not set
-+CONFIG_HZ_100=y
-+CONFIG_CMDLINE_BOOL=y
-+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_ARPD=y
-+CONFIG_SYN_COOKIES=y
-+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_BEET is not set
-+# CONFIG_INET_LRO is not set
-+# CONFIG_INET_DIAG is not set
-+CONFIG_TCP_CONG_ADVANCED=y
-+# CONFIG_TCP_CONG_BIC is not set
-+# CONFIG_TCP_CONG_WESTWOOD is not set
-+# CONFIG_TCP_CONG_HTCP is not set
-+CONFIG_IPV6_PRIVACY=y
-+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET6_XFRM_MODE_BEET is not set
-+# CONFIG_IPV6_SIT is not set
-+CONFIG_IPV6_MULTIPLE_TABLES=y
-+CONFIG_IPV6_SUBTREES=y
-+CONFIG_IPV6_MROUTE=y
-+CONFIG_NETFILTER=y
-+# CONFIG_BRIDGE_NETFILTER is not set
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NETFILTER_XT_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_LOG=m
-+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_MAC=m
-+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+CONFIG_NETFILTER_XT_MATCH_TIME=m
-+CONFIG_NF_CONNTRACK_IPV4=m
-+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_NF_NAT_IPV4=m
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_IP_NF_TARGET_REDIRECT=m
-+CONFIG_IP_NF_MANGLE=m
-+CONFIG_IP_NF_RAW=m
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_AH=m
-+CONFIG_IP6_NF_MATCH_EUI64=m
-+CONFIG_IP6_NF_MATCH_FRAG=m
-+CONFIG_IP6_NF_MATCH_OPTS=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_MATCH_MH=m
-+CONFIG_IP6_NF_MATCH_RT=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+CONFIG_IP6_NF_RAW=m
-+CONFIG_BRIDGE=m
-+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-+CONFIG_VLAN_8021Q=y
-+CONFIG_NET_SCHED=y
-+CONFIG_NET_SCH_FQ_CODEL=y
-+CONFIG_HAMRADIO=y
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+# CONFIG_FIRMWARE_IN_KERNEL is not set
-+CONFIG_MTD=y
-+CONFIG_MTD_CMDLINE_PARTS=y
-+CONFIG_MTD_BLOCK=y
-+CONFIG_MTD_CFI=y
-+CONFIG_MTD_CFI_AMDSTD=y
-+CONFIG_MTD_COMPLEX_MAPPINGS=y
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_M25P80=y
-+CONFIG_EEPROM_93CX6=m
-+CONFIG_SCSI=y
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_NETDEVICES=y
-+# CONFIG_NET_PACKET_ENGINE is not set
-+# CONFIG_NET_VENDOR_WIZNET is not set
-+CONFIG_PHYLIB=y
-+CONFIG_SWCONFIG=y
-+CONFIG_PPP=m
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_MULTILINK=y
-+CONFIG_PPPOE=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_ISDN=y
-+# CONFIG_INPUT is not set
-+# CONFIG_SERIO is not set
-+# CONFIG_VT is not set
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_8250=y
-+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-+CONFIG_SERIAL_8250_CONSOLE=y
-+# CONFIG_SERIAL_8250_PCI is not set
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-+CONFIG_SPI=y
-+CONFIG_GPIOLIB=y
-+CONFIG_GPIO_SYSFS=y
-+# CONFIG_HWMON is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_WATCHDOG_CORE=y
-+# CONFIG_VGA_ARB is not set
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_PLATFORM=y
-+CONFIG_USB_MT7621_XHCI_PLATFORM=y
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_PHY=y
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_GPIO=m
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_STAGING=y
-+CONFIG_USB_DWC2=m
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_RESET_CONTROLLER=y
-+# CONFIG_FIRMWARE_MEMMAP is not set
-+# CONFIG_DNOTIFY is not set
-+# CONFIG_PROC_PAGE_MONITOR is not set
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_XATTR=y
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_SUMMARY=y
-+CONFIG_JFFS2_FS_XATTR=y
-+# CONFIG_JFFS2_FS_POSIX_ACL is not set
-+# CONFIG_JFFS2_FS_SECURITY is not set
-+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-+# CONFIG_JFFS2_ZLIB is not set
-+CONFIG_SQUASHFS=y
-+# CONFIG_SQUASHFS_ZLIB is not set
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_PRINTK_TIME=y
-+# CONFIG_ENABLE_MUST_CHECK is not set
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+CONFIG_STRIP_ASM_SYMS=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_SCHED_DEBUG is not set
-+CONFIG_DEBUG_INFO=y
-+CONFIG_DEBUG_INFO_REDUCED=y
-+CONFIG_RCU_CPU_STALL_TIMEOUT=60
-+# CONFIG_FTRACE is not set
-+CONFIG_CRYPTO_ARC4=m
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_VIRTUALIZATION is not set
-+CONFIG_CRC_ITU_T=m
-+CONFIG_CRC32_SARWATE=y
-+# CONFIG_XZ_DEC_X86 is not set
-+CONFIG_AVERAGE=y
+++ /dev/null
-From 4d805af8246efdc330d6af9a8bd10ce892327598 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 24 Jan 2014 17:01:17 +0100
-Subject: [PATCH 03/53] MIPS: ralink: cleanup early_printk
-
-Add support for the new MT7621/8 SoC and kill ifdefs.
-Cleanup some whitespace error while we are at it.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/early_printk.c | 25 +++++++++++++++++++++++++
- 1 file changed, 25 insertions(+)
-
---- a/arch/mips/ralink/early_printk.c
-+++ b/arch/mips/ralink/early_printk.c
-@@ -25,11 +25,13 @@
- #define MT7628_CHIP_NAME1 0x20203832
-
- #define UART_REG_TX 0x04
-+#define UART_REG_LCR 0x0c
- #define UART_REG_LSR 0x14
- #define UART_REG_LSR_RT2880 0x1c
-
- static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
- static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
-+static int init_complete;
-
- static inline void uart_w32(u32 val, unsigned reg)
- {
-@@ -47,8 +49,31 @@ static inline int soc_is_mt7628(void)
- (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
- }
-
-+static inline void find_uart_base(void)
-+{
-+ int i;
-+
-+ if (!soc_is_mt7628())
-+ return;
-+
-+ for (i = 0; i < 3; i++) {
-+ u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
-+
-+ if (!reg)
-+ continue;
-+
-+ uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i));
-+ break;
-+ }
-+}
-+
- void prom_putchar(unsigned char ch)
- {
-+ if (!init_complete) {
-+ find_uart_base();
-+ init_complete = 1;
-+ }
-+
- if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
- uart_w32(ch, UART_TX);
- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+++ /dev/null
-From fec11d4e8dc5cc79bcd7c8fd55038ac21ac39965 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 16 Mar 2014 05:22:39 +0000
-Subject: [PATCH 04/53] MIPS: ralink: add MT7621 pcie driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-mt7621.c | 813 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 814 insertions(+)
- create mode 100644 arch/mips/pci/pci-mt7621.c
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
- obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
---- /dev/null
-+++ b/arch/mips/pci/pci-mt7621.c
-@@ -0,0 +1,832 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * PCI init for Ralink RT2880 solution
-+ *
-+ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2007 Bruce Chang
-+ * Initial Release
-+ *
-+ * May 2009 Bruce Chang
-+ * support RT2880/RT3883 PCIe
-+ *
-+ * May 2011 Bruce Chang
-+ * support RT6855/MT7620 PCIe
-+ *
-+ **************************************************************************
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/version.h>
-+#include <asm/pci.h>
-+#include <asm/io.h>
-+#include <asm/mips-cm.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/of.h>
-+#include <linux/of_pci.h>
-+#include <linux/platform_device.h>
-+
-+#include <ralink_regs.h>
-+
-+extern void pcie_phy_init(void);
-+extern void chk_phy_pll(void);
-+
-+/*
-+ * These functions and structures provide the BIOS scan and mapping of the PCI
-+ * devices.
-+ */
-+
-+#define CONFIG_PCIE_PORT0
-+#define CONFIG_PCIE_PORT1
-+#define CONFIG_PCIE_PORT2
-+#define RALINK_PCIE0_CLK_EN (1<<24)
-+#define RALINK_PCIE1_CLK_EN (1<<25)
-+#define RALINK_PCIE2_CLK_EN (1<<26)
-+
-+#define RALINK_PCI_CONFIG_ADDR 0x20
-+#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
-+#define SURFBOARDINT_PCIE0 11 /* PCIE0 */
-+#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
-+#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
-+#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
-+#define SURFBOARDINT_PCIE1 31 /* PCIE1 */
-+#define SURFBOARDINT_PCIE2 32 /* PCIE2 */
-+#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
-+#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
-+#define RALINK_PCIE0_RST (1<<24)
-+#define RALINK_PCIE1_RST (1<<25)
-+#define RALINK_PCIE2_RST (1<<26)
-+#define RALINK_SYSCTL_BASE 0xBE000000
-+
-+#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
-+#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
-+#define RALINK_PCI_BASE 0xBE140000
-+
-+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-+#define RT6855_PCIE0_OFFSET 0x2000
-+#define RT6855_PCIE1_OFFSET 0x3000
-+#define RT6855_PCIE2_OFFSET 0x4000
-+
-+#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
-+#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
-+#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
-+#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
-+#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
-+#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
-+#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
-+#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
-+
-+#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
-+#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
-+#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
-+#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
-+#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
-+#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
-+#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
-+#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
-+
-+#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
-+#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
-+#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
-+#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
-+#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
-+#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
-+#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
-+#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
-+
-+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-+#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
-+
-+
-+#define MV_WRITE(ofs, data) \
-+ *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
-+#define MV_READ(ofs, data) \
-+ *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-+#define MV_READ_DATA(ofs) \
-+ le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-+
-+#define MV_WRITE_16(ofs, data) \
-+ *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-+#define MV_READ_16(ofs, data) \
-+ *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-+
-+#define MV_WRITE_8(ofs, data) \
-+ *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-+#define MV_READ_8(ofs, data) \
-+ *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
-+
-+
-+
-+#define RALINK_PCI_MM_MAP_BASE 0x60000000
-+#define RALINK_PCI_IO_MAP_BASE 0x1e160000
-+
-+#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
-+#define GPIO_PERST
-+#define ASSERT_SYSRST_PCIE(val) do { \
-+ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
-+ RALINK_RSTCTRL |= val; \
-+ else \
-+ RALINK_RSTCTRL &= ~val; \
-+ } while(0)
-+#define DEASSERT_SYSRST_PCIE(val) do { \
-+ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
-+ RALINK_RSTCTRL &= ~val; \
-+ else \
-+ RALINK_RSTCTRL |= val; \
-+ } while(0)
-+#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
-+#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
-+#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
-+#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
-+#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
-+#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
-+#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
-+#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
-+//RALINK_SYSCFG1 bit
-+#define RALINK_PCI_HOST_MODE_EN (1<<7)
-+#define RALINK_PCIE_RC_MODE_EN (1<<8)
-+//RALINK_RSTCTRL bit
-+#define RALINK_PCIE_RST (1<<23)
-+#define RALINK_PCI_RST (1<<24)
-+//RALINK_CLKCFG1 bit
-+#define RALINK_PCI_CLK_EN (1<<19)
-+#define RALINK_PCIE_CLK_EN (1<<21)
-+//RALINK_GPIOMODE bit
-+#define PCI_SLOTx2 (1<<11)
-+#define PCI_SLOTx1 (2<<11)
-+//MTK PCIE PLL bit
-+#define PDRV_SW_SET (1<<31)
-+#define LC_CKDRVPD_ (1<<19)
-+
-+#define MEMORY_BASE 0x0
-+static int pcie_link_status = 0;
-+
-+#define PCI_ACCESS_READ_1 0
-+#define PCI_ACCESS_READ_2 1
-+#define PCI_ACCESS_READ_4 2
-+#define PCI_ACCESS_WRITE_1 3
-+#define PCI_ACCESS_WRITE_2 4
-+#define PCI_ACCESS_WRITE_4 5
-+
-+static int config_access(unsigned char access_type, struct pci_bus *bus,
-+ unsigned int devfn, unsigned int where, u32 * data)
-+{
-+ unsigned int slot = PCI_SLOT(devfn);
-+ u8 func = PCI_FUNC(devfn);
-+ uint32_t address_reg, data_reg;
-+ unsigned int address;
-+
-+ address_reg = RALINK_PCI_CONFIG_ADDR;
-+ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-+
-+ address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+ MV_WRITE(address_reg, address);
-+
-+ switch(access_type) {
-+ case PCI_ACCESS_WRITE_1:
-+ MV_WRITE_8(data_reg+(where&0x3), *data);
-+ break;
-+ case PCI_ACCESS_WRITE_2:
-+ MV_WRITE_16(data_reg+(where&0x3), *data);
-+ break;
-+ case PCI_ACCESS_WRITE_4:
-+ MV_WRITE(data_reg, *data);
-+ break;
-+ case PCI_ACCESS_READ_1:
-+ MV_READ_8( data_reg+(where&0x3), data);
-+ break;
-+ case PCI_ACCESS_READ_2:
-+ MV_READ_16(data_reg+(where&0x3), data);
-+ break;
-+ case PCI_ACCESS_READ_4:
-+ MV_READ(data_reg, data);
-+ break;
-+ default:
-+ printk("no specify access type\n");
-+ break;
-+ }
-+ return 0;
-+}
-+
-+static int
-+read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
-+{
-+ return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
-+}
-+
-+static int
-+read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
-+{
-+ return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
-+}
-+
-+static int
-+read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
-+{
-+ return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
-+}
-+
-+static int
-+write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-+{
-+ if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
-+ return -1;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int
-+write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
-+{
-+ if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
-+ return -1;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int
-+write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-+{
-+ if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
-+ return -1;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+
-+static int
-+pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
-+{
-+ switch (size) {
-+ case 1:
-+ return read_config_byte(bus, devfn, where, (u8 *) val);
-+ case 2:
-+ return read_config_word(bus, devfn, where, (u16 *) val);
-+ default:
-+ return read_config_dword(bus, devfn, where, val);
-+ }
-+}
-+
-+static int
-+pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-+{
-+ switch (size) {
-+ case 1:
-+ return write_config_byte(bus, devfn, where, (u8) val);
-+ case 2:
-+ return write_config_word(bus, devfn, where, (u16) val);
-+ default:
-+ return write_config_dword(bus, devfn, where, val);
-+ }
-+}
-+
-+struct pci_ops mt7621_pci_ops= {
-+ .read = pci_config_read,
-+ .write = pci_config_write,
-+};
-+
-+static struct resource mt7621_res_pci_mem1 = {
-+ .name = "PCI MEM1",
-+ .start = RALINK_PCI_MM_MAP_BASE,
-+ .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
-+ .flags = IORESOURCE_MEM,
-+};
-+static struct resource mt7621_res_pci_io1 = {
-+ .name = "PCI I/O1",
-+ .start = RALINK_PCI_IO_MAP_BASE,
-+ .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct pci_controller mt7621_controller = {
-+ .pci_ops = &mt7621_pci_ops,
-+ .mem_resource = &mt7621_res_pci_mem1,
-+ .io_resource = &mt7621_res_pci_io1,
-+ .mem_offset = 0x00000000UL,
-+ .io_offset = 0x00000000UL,
-+ .io_map_base = 0xa0000000,
-+};
-+
-+static void
-+read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
-+{
-+ unsigned int address_reg, data_reg, address;
-+
-+ address_reg = RALINK_PCI_CONFIG_ADDR;
-+ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-+ address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
-+ MV_WRITE(address_reg, address);
-+ MV_READ(data_reg, val);
-+ return;
-+}
-+
-+static void
-+write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
-+{
-+ unsigned int address_reg, data_reg, address;
-+
-+ address_reg = RALINK_PCI_CONFIG_ADDR;
-+ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-+ address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
-+ MV_WRITE(address_reg, address);
-+ MV_WRITE(data_reg, val);
-+ return;
-+}
-+
-+
-+int __init
-+pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ u16 cmd;
-+ u32 val;
-+ int irq = 0;
-+
-+ if ((dev->bus->number == 0) && (slot == 0)) {
-+ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-+ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
-+ printk("BAR0 at slot 0 = %x\n", val);
-+ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
-+ } else if((dev->bus->number == 0) && (slot == 0x1)) {
-+ write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-+ read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
-+ printk("BAR0 at slot 1 = %x\n", val);
-+ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
-+ } else if((dev->bus->number == 0) && (slot == 0x2)) {
-+ write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-+ read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
-+ printk("BAR0 at slot 2 = %x\n", val);
-+ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
-+ } else if ((dev->bus->number == 1) && (slot == 0x0)) {
-+ switch (pcie_link_status) {
-+ case 2:
-+ case 6:
-+ irq = RALINK_INT_PCIE1;
-+ break;
-+ case 4:
-+ irq = RALINK_INT_PCIE2;
-+ break;
-+ default:
-+ irq = RALINK_INT_PCIE0;
-+ }
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number == 2) && (slot == 0x0)) {
-+ switch (pcie_link_status) {
-+ case 5:
-+ case 6:
-+ irq = RALINK_INT_PCIE2;
-+ break;
-+ default:
-+ irq = RALINK_INT_PCIE1;
-+ }
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number == 2) && (slot == 0x1)) {
-+ switch (pcie_link_status) {
-+ case 5:
-+ case 6:
-+ irq = RALINK_INT_PCIE2;
-+ break;
-+ default:
-+ irq = RALINK_INT_PCIE1;
-+ }
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number ==3) && (slot == 0x0)) {
-+ irq = RALINK_INT_PCIE2;
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number ==3) && (slot == 0x1)) {
-+ irq = RALINK_INT_PCIE2;
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else if ((dev->bus->number ==3) && (slot == 0x2)) {
-+ irq = RALINK_INT_PCIE2;
-+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
-+ } else {
-+ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
-+ return 0;
-+ }
-+
-+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
-+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
-+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
-+ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-+ pci_write_config_word(dev, PCI_COMMAND, cmd);
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-+ return irq;
-+}
-+
-+void
-+set_pcie_phy(u32 *addr, int start_b, int bits, int val)
-+{
-+// printk("0x%p:", addr);
-+// printk(" %x", *addr);
-+ *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
-+ *(unsigned int *)(addr) |= val << start_b;
-+// printk(" -> %x\n", *addr);
-+}
-+
-+void
-+bypass_pipe_rst(void)
-+{
-+#if defined (CONFIG_PCIE_PORT0)
-+ /* PCIe Port 0 */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ /* PCIe Port 1 */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ /* PCIe Port 2 */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
-+#endif
-+}
-+
-+void
-+set_phy_for_ssc(void)
-+{
-+ unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
-+
-+ reg = (reg >> 6) & 0x7;
-+#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
-+ /* Set PCIe Port0 & Port1 PHY to disable SSC */
-+ /* Debug Xtal Type */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
-+ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
-+ printk("***** Xtal 40MHz *****\n");
-+ } else { // 25MHz | 20MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
-+ if (reg >= 6) {
-+ printk("***** Xtal 25MHz *****\n");
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
-+ } else {
-+ printk("***** Xtal 20MHz *****\n");
-+ }
-+ }
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
-+ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
-+ }
-+ /* Enable PHY and disable force mode */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ /* Set PCIe Port2 PHY to disable SSC */
-+ /* Debug Xtal Type */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
-+ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
-+ } else { // 25MHz | 20MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
-+ if (reg >= 6) { // 25MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
-+ }
-+ }
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
-+ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
-+ }
-+ /* Enable PHY and disable force mode */
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
-+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
-+#endif
-+}
-+
-+void setup_cm_memory_region(struct resource *mem_resource)
-+{
-+ resource_size_t mask;
-+ if (mips_cm_numiocu()) {
-+ /* FIXME: hardware doesn't accept mask values with 1s after
-+ 0s (e.g. 0xffef), so it would be great to warn if that's
-+ about to happen */
-+ mask = ~(mem_resource->end - mem_resource->start);
-+
-+ write_gcr_reg1_base(mem_resource->start);
-+ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-+ printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
-+ read_gcr_reg1_base(),
-+ read_gcr_reg1_mask());
-+ }
-+}
-+
-+static int mt7621_pci_probe(struct platform_device *pdev)
-+{
-+ unsigned long val = 0;
-+
-+ iomem_resource.start = 0;
-+ iomem_resource.end= ~0;
-+ ioport_resource.start= 0;
-+ ioport_resource.end = ~0;
-+
-+#if defined (CONFIG_PCIE_PORT0)
-+ val = RALINK_PCIE0_RST;
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ val |= RALINK_PCIE1_RST;
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ val |= RALINK_PCIE2_RST;
-+#endif
-+ ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
-+ printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
-+#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
-+ *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
-+ *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
-+ mdelay(100);
-+ *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
-+ mdelay(100);
-+ *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
-+
-+ mdelay(100);
-+#else
-+ *(unsigned int *)(0xbe000060) &= ~0x00000c00;
-+#endif
-+#if defined (CONFIG_PCIE_PORT0)
-+ val = RALINK_PCIE0_RST;
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ val |= RALINK_PCIE1_RST;
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ val |= RALINK_PCIE2_RST;
-+#endif
-+ DEASSERT_SYSRST_PCIE(val);
-+ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
-+
-+ if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
-+ bypass_pipe_rst();
-+ set_phy_for_ssc();
-+ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
-+
-+#if defined (CONFIG_PCIE_PORT0)
-+ read_config(0, 0, 0, 0x70c, &val);
-+ printk("Port 0 N_FTS = %x\n", (unsigned int)val);
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ read_config(0, 1, 0, 0x70c, &val);
-+ printk("Port 1 N_FTS = %x\n", (unsigned int)val);
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ read_config(0, 2, 0, 0x70c, &val);
-+ printk("Port 2 N_FTS = %x\n", (unsigned int)val);
-+#endif
-+
-+ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
-+ RALINK_SYSCFG1 &= ~(0x30);
-+ RALINK_SYSCFG1 |= (2<<4);
-+ RALINK_PCIE_CLK_GEN &= 0x7fffffff;
-+ RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
-+ RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
-+ RALINK_PCIE_CLK_GEN |= 0x80000000;
-+ mdelay(50);
-+ RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
-+
-+
-+#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
-+ *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
-+ mdelay(100);
-+#else
-+ RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
-+#endif
-+ mdelay(500);
-+
-+
-+ mdelay(500);
-+#if defined (CONFIG_PCIE_PORT0)
-+ if(( RALINK_PCI0_STATUS & 0x1) == 0)
-+ {
-+ printk("PCIE0 no card, disable it(RST&CLK)\n");
-+ ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
-+ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
-+ pcie_link_status &= ~(1<<0);
-+ } else {
-+ pcie_link_status |= 1<<0;
-+ RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
-+ }
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ if(( RALINK_PCI1_STATUS & 0x1) == 0)
-+ {
-+ printk("PCIE1 no card, disable it(RST&CLK)\n");
-+ ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
-+ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
-+ pcie_link_status &= ~(1<<1);
-+ } else {
-+ pcie_link_status |= 1<<1;
-+ RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
-+ }
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ if (( RALINK_PCI2_STATUS & 0x1) == 0) {
-+ printk("PCIE2 no card, disable it(RST&CLK)\n");
-+ ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
-+ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
-+ pcie_link_status &= ~(1<<2);
-+ } else {
-+ pcie_link_status |= 1<<2;
-+ RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
-+ }
-+#endif
-+ if (pcie_link_status == 0)
-+ return 0;
-+
-+/*
-+pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
-+3'b000 x x x
-+3'b001 x x 0
-+3'b010 x 0 x
-+3'b011 x 1 0
-+3'b100 0 x x
-+3'b101 1 x 0
-+3'b110 1 0 x
-+3'b111 2 1 0
-+*/
-+ switch(pcie_link_status) {
-+ case 2:
-+ RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
-+ RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
-+ RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
-+ break;
-+ case 4:
-+ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-+ RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
-+ RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
-+ RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
-+ break;
-+ case 5:
-+ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-+ RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
-+ RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
-+ RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
-+ break;
-+ case 6:
-+ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-+ RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
-+ RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
-+ RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
-+ break;
-+ }
-+ printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
-+ //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
-+
-+/*
-+ ioport_resource.start = mt7621_res_pci_io1.start;
-+ ioport_resource.end = mt7621_res_pci_io1.end;
-+*/
-+
-+ RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
-+ RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
-+
-+#if defined (CONFIG_PCIE_PORT0)
-+ //PCIe0
-+ if((pcie_link_status & 0x1) != 0) {
-+ RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
-+ RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
-+ RALINK_PCI0_CLASS = 0x06040001;
-+ printk("PCIE0 enabled\n");
-+ }
-+#endif
-+#if defined (CONFIG_PCIE_PORT1)
-+ //PCIe1
-+ if ((pcie_link_status & 0x2) != 0) {
-+ RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
-+ RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
-+ RALINK_PCI1_CLASS = 0x06040001;
-+ printk("PCIE1 enabled\n");
-+ }
-+#endif
-+#if defined (CONFIG_PCIE_PORT2)
-+ //PCIe2
-+ if ((pcie_link_status & 0x4) != 0) {
-+ RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
-+ RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
-+ RALINK_PCI2_CLASS = 0x06040001;
-+ printk("PCIE2 enabled\n");
-+ }
-+#endif
-+
-+
-+ switch(pcie_link_status) {
-+ case 7:
-+ read_config(0, 2, 0, 0x4, &val);
-+ write_config(0, 2, 0, 0x4, val|0x4);
-+ // write_config(0, 1, 0, 0x4, val|0x7);
-+ read_config(0, 2, 0, 0x70c, &val);
-+ val &= ~(0xff)<<8;
-+ val |= 0x50<<8;
-+ write_config(0, 2, 0, 0x70c, val);
-+ case 3:
-+ case 5:
-+ case 6:
-+ read_config(0, 1, 0, 0x4, &val);
-+ write_config(0, 1, 0, 0x4, val|0x4);
-+ // write_config(0, 1, 0, 0x4, val|0x7);
-+ read_config(0, 1, 0, 0x70c, &val);
-+ val &= ~(0xff)<<8;
-+ val |= 0x50<<8;
-+ write_config(0, 1, 0, 0x70c, val);
-+ default:
-+ read_config(0, 0, 0, 0x4, &val);
-+ write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
-+ // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
-+ read_config(0, 0, 0, 0x70c, &val);
-+ val &= ~(0xff)<<8;
-+ val |= 0x50<<8;
-+ write_config(0, 0, 0, 0x70c, val);
-+ }
-+
-+ pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
-+ setup_cm_memory_region(mt7621_controller.mem_resource);
-+ register_pci_controller(&mt7621_controller);
-+ return 0;
-+
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+static const struct of_device_id mt7621_pci_ids[] = {
-+ { .compatible = "mediatek,mt7621-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
-+
-+static struct platform_driver mt7621_pci_driver = {
-+ .probe = mt7621_pci_probe,
-+ .driver = {
-+ .name = "mt7621-pci",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(mt7621_pci_ids),
-+ },
-+};
-+
-+static int __init mt7621_pci_init(void)
-+{
-+ return platform_driver_register(&mt7621_pci_driver);
-+}
-+
-+arch_initcall(mt7621_pci_init);
+++ /dev/null
-From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:08:11 +0200
-Subject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k
- irq
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -1,11 +1,16 @@
- if RALINK
-
-+config CEVT_SYSTICK_QUIRK
-+ bool
-+ default n
-+
- config CLKEVT_RT3352
- bool
- depends on SOC_RT305X || SOC_MT7620
- default y
- select CLKSRC_OF
- select CLKSRC_MMIO
-+ select CEVT_SYSTICK_QUIRK
-
- config RALINK_ILL_ACC
- bool
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -15,6 +15,26 @@
- #include <asm/time.h>
- #include <asm/cevt-r4k.h>
-
-+static int mips_state_oneshot(struct clock_event_device *evt)
-+{
-+ if (!cp0_timer_irq_installed) {
-+ cp0_timer_irq_installed = 1;
-+ setup_irq(evt->irq, &c0_compare_irqaction);
-+ }
-+
-+ return 0;
-+}
-+
-+static int mips_state_shutdown(struct clock_event_device *evt)
-+{
-+ if (cp0_timer_irq_installed) {
-+ cp0_timer_irq_installed = 0;
-+ remove_irq(evt->irq, &c0_compare_irqaction);
-+ }
-+
-+ return 0;
-+}
-+
- static int mips_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
-@@ -208,18 +228,21 @@ int r4k_clockevent_init(void)
- cd->rating = 300;
- cd->irq = irq;
- cd->cpumask = cpumask_of(cpu);
-+ cd->set_state_shutdown = mips_state_shutdown;
-+ cd->set_state_oneshot = mips_state_oneshot;
- cd->set_next_event = mips_next_event;
- cd->event_handler = mips_event_handler;
-
- clockevents_register_device(cd);
-
-+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
- if (cp0_timer_irq_installed)
- return 0;
-
- cp0_timer_irq_installed = 1;
-
- setup_irq(irq, &c0_compare_irqaction);
--
-+#endif
- return 0;
- }
-
+++ /dev/null
-From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 16:26:41 +0200
-Subject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling
-
-This feature will break udelay() and cause the delay loop to have longer delays
-when the frequency is scaled causing a performance hit.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/cevt-rt3352.c | 38 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 38 insertions(+)
-
---- a/arch/mips/ralink/cevt-rt3352.c
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -29,6 +29,10 @@
- /* enable the counter */
- #define CFG_CNT_EN 0x1
-
-+/* mt7620 frequency scaling defines */
-+#define CLK_LUT_CFG 0x40
-+#define SLEEP_EN BIT(31)
-+
- struct systick_device {
- void __iomem *membase;
- struct clock_event_device dev;
-@@ -36,9 +40,26 @@ struct systick_device {
- int freq_scale;
- };
-
-+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
-+
- static int systick_set_oneshot(struct clock_event_device *evt);
- static int systick_shutdown(struct clock_event_device *evt);
-
-+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
-+{
-+ if (sdev->freq_scale == status)
-+ return;
-+
-+ sdev->freq_scale = status;
-+
-+ pr_info("%s: %s autosleep mode\n", systick.dev.name,
-+ (status) ? ("enable") : ("disable"));
-+ if (status)
-+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
-+ else
-+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
-+}
-+
- static int systick_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
-@@ -99,6 +120,9 @@ static int systick_shutdown(struct clock
- sdev->irq_requested = 0;
- iowrite32(0, systick.membase + SYSTICK_CONFIG);
-
-+ if (systick_freq_scaling)
-+ systick_freq_scaling(sdev, 0);
-+
- return 0;
- }
-
-@@ -114,15 +138,29 @@ static int systick_set_oneshot(struct cl
- iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
- systick.membase + SYSTICK_CONFIG);
-
-+ if (systick_freq_scaling)
-+ systick_freq_scaling(sdev, 1);
-+
- return 0;
- }
-
-+static const struct of_device_id systick_match[] = {
-+ { .compatible = "ralink,mt7620-systick", .data = mt7620_freq_scaling},
-+ {},
-+};
-+
- static void __init ralink_systick_init(struct device_node *np)
- {
-+ const struct of_device_id *match;
-+
- systick.membase = of_iomap(np, 0);
- if (!systick.membase)
- return;
-
-+ match = of_match_node(systick_match, np);
-+ if (match)
-+ systick_freq_scaling = match->data;
-+
- systick_irqaction.name = np->name;
- systick.dev.name = np->name;
- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
+++ /dev/null
-From 67b7bff0fd364c194e653f69baa623ba2141bd4c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Aug 2014 18:46:02 +0200
-Subject: [PATCH 07/53] MIPS: ralink: copy the commandline from the devicetree
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -76,6 +76,8 @@ void __init plat_mem_setup(void)
-
- strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
-
-+ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
-+
- of_scan_flat_dt(early_init_dt_find_memory, NULL);
- if (memory_dtb)
- of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+++ /dev/null
-From 0fd52df8bce3be9edbc195b120bc9a68f970d9e5 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Aug 2014 20:43:25 +0200
-Subject: [PATCH 08/53] MIPS: ralink: mt7620: fix usb issue during frequency
- scaling
-
- If the USB HCD is running and the cpu is scaled too low, then the USB stops
- working. Increase the idle speed of the core to fix this if the kernel is
- built with USB support.
-
- The values are taken from the Ralink SDK Kernel.
-
- Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -40,6 +40,12 @@
- /* is this a MT7620 or a MT7628 */
- enum mt762x_soc_type mt762x_soc;
-
-+/* clock scaling */
-+#define CLKCFG_FDIV_MASK 0x1f00
-+#define CLKCFG_FDIV_USB_VAL 0x0300
-+#define CLKCFG_FFRAC_MASK 0x001f
-+#define CLKCFG_FFRAC_USB_VAL 0x0003
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-
-@@ -423,6 +429,19 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000b00.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", periph_rate);
- ralink_clk_add("10180000.wmac", xtal_rate);
-+
-+ if (IS_ENABLED(CONFIG_USB)) {
-+ /*
-+ * When the CPU goes into sleep mode, the BUS clock will be too low for
-+ * USB to function properly
-+ */
-+ u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
-+
-+ val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
-+ val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
-+
-+ rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
-+ }
- }
-
- void __init ralink_of_remap(void)
+++ /dev/null
-From 41aa7fc236fdb1f4c9b8b10df9b71f0d248cb36b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:11:12 +0100
-Subject: [PATCH 09/53] PCI: MIPS: adds mt7620a pcie driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/pci-mt7620.c | 396 ++++++++++++++++++++++++++++
- arch/mips/ralink/Kconfig | 1 +
- 4 files changed, 399 insertions(+)
- create mode 100644 arch/mips/pci/pci-mt7620.c
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -19,6 +19,7 @@ enum mt762x_soc_type {
- MT762X_SOC_MT7620N,
- MT762X_SOC_MT7628AN,
- };
-+extern enum mt762x_soc_type mt762x_soc;
-
- #define MT7620_SYSC_BASE 0x10000000
-
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
- obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
- obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
---- /dev/null
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -0,0 +1,396 @@
-+/*
-+ * Ralink MT7620A SoC PCI support
-+ *
-+ * Copyright (C) 2007-2013 Bruce Chang
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+#include <linux/reset.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/mach-ralink/mt7620.h>
-+
-+#define RALINK_PCI_MM_MAP_BASE 0x20000000
-+#define RALINK_PCI_IO_MAP_BASE 0x10160000
-+
-+#define RALINK_INT_PCIE0 4
-+#define RALINK_SYSCFG1 0x14
-+#define RALINK_CLKCFG1 0x30
-+#define RALINK_GPIOMODE 0x60
-+#define RALINK_PCIE_CLK_GEN 0x7c
-+#define RALINK_PCIE_CLK_GEN1 0x80
-+#define PCIEPHY0_CFG 0x90
-+#define PPLL_CFG1 0x9c
-+#define PPLL_DRV 0xa0
-+#define PDRV_SW_SET (1<<31)
-+#define LC_CKDRVPD_ (1<<19)
-+
-+#define RALINK_PCI_CONFIG_ADDR 0x20
-+#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
-+#define MEMORY_BASE 0x0
-+#define RALINK_PCIE0_RST (1<<26)
-+#define RALINK_PCI_BASE 0xB0140000
-+#define RALINK_PCI_MEMBASE 0x28
-+#define RALINK_PCI_IOBASE 0x2C
-+
-+#define RT6855_PCIE0_OFFSET 0x2000
-+
-+#define RALINK_PCI_PCICFG_ADDR 0x00
-+#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
-+#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
-+#define RALINK_PCI0_ID 0x30
-+#define RALINK_PCI0_CLASS 0x34
-+#define RALINK_PCI0_SUBID 0x38
-+#define RALINK_PCI0_STATUS 0x50
-+#define RALINK_PCI_PCIMSK_ADDR 0x0C
-+
-+#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
-+#define RALINK_PCIE0_CLK_EN (1 << 26)
-+
-+#define BUSY 0x80000000
-+#define WAITRETRY_MAX 10
-+#define WRITE_MODE (1UL << 23)
-+#define DATA_SHIFT 0
-+#define ADDR_SHIFT 8
-+
-+static void __iomem *bridge_base;
-+static void __iomem *pcie_base;
-+
-+static struct reset_control *rstpcie0;
-+
-+static inline void bridge_w32(u32 val, unsigned reg)
-+{
-+ iowrite32(val, bridge_base + reg);
-+}
-+
-+static inline u32 bridge_r32(unsigned reg)
-+{
-+ return ioread32(bridge_base + reg);
-+}
-+
-+static inline void pcie_w32(u32 val, unsigned reg)
-+{
-+ iowrite32(val, pcie_base + reg);
-+}
-+
-+static inline u32 pcie_r32(unsigned reg)
-+{
-+ return ioread32(pcie_base + reg);
-+}
-+
-+static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
-+{
-+ u32 val = pcie_r32(reg);
-+
-+ val &= ~clr;
-+ val |= set;
-+ pcie_w32(val, reg);
-+}
-+
-+static int wait_pciephy_busy(void)
-+{
-+ unsigned long reg_value = 0x0, retry = 0;
-+
-+ while (1) {
-+ reg_value = pcie_r32(PCIEPHY0_CFG);
-+
-+ if (reg_value & BUSY)
-+ mdelay(100);
-+ else
-+ break;
-+ if (retry++ > WAITRETRY_MAX){
-+ printk("PCIE-PHY retry failed.\n");
-+ return -1;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static void pcie_phy(unsigned long addr, unsigned long val)
-+{
-+ wait_pciephy_busy();
-+ pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
-+ mdelay(1);
-+ wait_pciephy_busy();
-+}
-+
-+static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
-+{
-+ unsigned int slot = PCI_SLOT(devfn);
-+ u8 func = PCI_FUNC(devfn);
-+ u32 address;
-+ u32 data;
-+ u32 num = 0;
-+
-+ if (bus)
-+ num = bus->number;
-+
-+ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
-+
-+ switch (size) {
-+ case 1:
-+ *val = (data >> ((where & 3) << 3)) & 0xff;
-+ break;
-+ case 2:
-+ *val = (data >> ((where & 3) << 3)) & 0xffff;
-+ break;
-+ case 4:
-+ *val = data;
-+ break;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-+{
-+ unsigned int slot = PCI_SLOT(devfn);
-+ u8 func = PCI_FUNC(devfn);
-+ u32 address;
-+ u32 data;
-+ u32 num = 0;
-+
-+ if (bus)
-+ num = bus->number;
-+
-+ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
-+ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
-+
-+ switch (size) {
-+ case 1:
-+ data = (data & ~(0xff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 2:
-+ data = (data & ~(0xffff << ((where & 3) << 3))) |
-+ (val << ((where & 3) << 3));
-+ break;
-+ case 4:
-+ data = val;
-+ break;
-+ }
-+
-+ bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+struct pci_ops mt7620_pci_ops= {
-+ .read = pci_config_read,
-+ .write = pci_config_write,
-+};
-+
-+static struct resource mt7620_res_pci_mem1;
-+static struct resource mt7620_res_pci_io1;
-+struct pci_controller mt7620_controller = {
-+ .pci_ops = &mt7620_pci_ops,
-+ .mem_resource = &mt7620_res_pci_mem1,
-+ .mem_offset = 0x00000000UL,
-+ .io_resource = &mt7620_res_pci_io1,
-+ .io_offset = 0x00000000UL,
-+ .io_map_base = 0xa0000000,
-+};
-+
-+static int mt7620_pci_hw_init(struct platform_device *pdev) {
-+ /* PCIE: bypass PCIe DLL */
-+ pcie_phy(0x0, 0x80);
-+ pcie_phy(0x1, 0x04);
-+
-+ /* PCIE: Elastic buffer control */
-+ pcie_phy(0x68, 0xB4);
-+
-+ pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
-+
-+ reset_control_assert(rstpcie0);
-+
-+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+ rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
-+
-+ reset_control_deassert(rstpcie0);
-+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
-+
-+ mdelay(100);
-+
-+ if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
-+ dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
-+ reset_control_assert(rstpcie0);
-+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+ return -1;
-+ }
-+ rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
-+
-+ return 0;
-+}
-+
-+static int mt7628_pci_hw_init(struct platform_device *pdev) {
-+ u32 val = 0;
-+
-+ rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
-+ reset_control_deassert(rstpcie0);
-+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
-+ mdelay(100);
-+
-+ pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
-+
-+ pci_config_read(NULL, 0, 0x70c, 4, &val);
-+ val &= ~(0xff) << 8;
-+ val |= 0x50 << 8;
-+ pci_config_write(NULL, 0, 0x70c, 4, val);
-+
-+ pci_config_read(NULL, 0, 0x70c, 4, &val);
-+ dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
-+
-+ return 0;
-+}
-+
-+static int mt7620_pci_probe(struct platform_device *pdev)
-+{
-+ struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+ u32 val = 0;
-+
-+ rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
-+ if (IS_ERR(rstpcie0))
-+ return PTR_ERR(rstpcie0);
-+
-+ bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
-+ if (!bridge_base)
-+ return -ENOMEM;
-+
-+ pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
-+ if (!pcie_base)
-+ return -ENOMEM;
-+
-+ iomem_resource.start = 0;
-+ iomem_resource.end = ~0;
-+ ioport_resource.start = 0;
-+ ioport_resource.end = ~0;
-+
-+ /* bring up the pci core */
-+ switch (ralink_soc) {
-+ case MT762X_SOC_MT7620A:
-+ if (mt7620_pci_hw_init(pdev))
-+ return -1;
-+ break;
-+
-+ case MT762X_SOC_MT7628AN:
-+ if (mt7628_pci_hw_init(pdev))
-+ return -1;
-+ break;
-+
-+ default:
-+ dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
-+ return -1;
-+ }
-+ mdelay(50);
-+
-+ /* enable write access */
-+ pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
-+ mdelay(100);
-+
-+ /* check if there is a card present */
-+ if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
-+ reset_control_assert(rstpcie0);
-+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+ if (ralink_soc == MT762X_SOC_MT7620A)
-+ rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
-+ dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
-+ return -1;
-+ }
-+
-+ /* setup ranges */
-+ bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
-+ bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
-+
-+ pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
-+ pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
-+ pcie_w32(0x06040001, RALINK_PCI0_CLASS);
-+
-+ /* enable interrupts */
-+ pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
-+
-+ /* voodoo from the SDK driver */
-+ pci_config_read(NULL, 0, 4, 4, &val);
-+ pci_config_write(NULL, 0, 4, 4, val | 0x7);
-+
-+ pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
-+ register_pci_controller(&mt7620_controller);
-+
-+ return 0;
-+}
-+
-+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ u16 cmd;
-+ u32 val;
-+ int irq = 0;
-+
-+ if ((dev->bus->number == 0) && (slot == 0)) {
-+ pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
-+ pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
-+ pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
-+ } else if ((dev->bus->number == 1) && (slot == 0x0)) {
-+ irq = RALINK_INT_PCIE0;
-+ } else {
-+ dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
-+ return 0;
-+ }
-+ dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
-+
-+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
-+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
-+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
-+
-+ // FIXME
-+ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-+ pci_write_config_word(dev, PCI_COMMAND, cmd);
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-+ //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
-+
-+ return irq;
-+}
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return 0;
-+}
-+
-+static const struct of_device_id mt7620_pci_ids[] = {
-+ { .compatible = "mediatek,mt7620-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
-+
-+static struct platform_driver mt7620_pci_driver = {
-+ .probe = mt7620_pci_probe,
-+ .driver = {
-+ .name = "mt7620-pci",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(mt7620_pci_ids),
-+ },
-+};
-+
-+static int __init mt7620_pci_init(void)
-+{
-+ return platform_driver_register(&mt7620_pci_driver);
-+}
-+
-+arch_initcall(mt7620_pci_init);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -43,6 +43,7 @@ choice
-
- config SOC_MT7620
- bool "MT7620/8"
-+ select HW_HAS_PCI
-
- config SOC_MT7621
- bool "MT7621"
+++ /dev/null
-From 39ce22c870f4503bed5e451acfcab21eba3b6239 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:49:07 +0100
-Subject: [PATCH 10/53] arch: mips: ralink: add spi1 clocks
-
-based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 1 +
- arch/mips/ralink/rt305x.c | 1 +
- arch/mips/ralink/rt3883.c | 1 +
- 3 files changed, 3 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -427,6 +427,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000100.timer", periph_rate);
- ralink_clk_add("10000120.watchdog", periph_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
-+ ralink_clk_add("10000b40.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", periph_rate);
- ralink_clk_add("10180000.wmac", xtal_rate);
-
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -202,6 +202,7 @@ void __init ralink_clk_init(void)
-
- ralink_clk_add("cpu", cpu_rate);
- ralink_clk_add("10000b00.spi", sys_rate);
-+ ralink_clk_add("10000b40.spi", sys_rate);
- ralink_clk_add("10000100.timer", wdt_rate);
- ralink_clk_add("10000120.watchdog", wdt_rate);
- ralink_clk_add("10000500.uart", uart_rate);
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -109,6 +109,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000120.watchdog", sys_rate);
- ralink_clk_add("10000500.uart", 40000000);
- ralink_clk_add("10000b00.spi", sys_rate);
-+ ralink_clk_add("10000b40.spi", sys_rate);
- ralink_clk_add("10000c00.uartlite", 40000000);
- ralink_clk_add("10100000.ethernet", sys_rate);
- ralink_clk_add("10180000.wmac", 40000000);
+++ /dev/null
-From 22ee5168a5dfeda748cabd0bbf728d6bdc6b925b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:12:38 +0100
-Subject: [PATCH 11/53] arch: mips: ralink: unify soc detection
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 8 --------
- arch/mips/include/asm/mach-ralink/ralink_regs.h | 14 ++++++++++++++
- arch/mips/include/asm/mach-ralink/rt305x.h | 21 ++++++---------------
- arch/mips/ralink/prom.c | 5 ++++-
- arch/mips/ralink/rt305x.c | 12 +++++-------
- 5 files changed, 29 insertions(+), 31 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -13,14 +13,6 @@
- #ifndef _MT7620_REGS_H_
- #define _MT7620_REGS_H_
-
--enum mt762x_soc_type {
-- MT762X_SOC_UNKNOWN = 0,
-- MT762X_SOC_MT7620A,
-- MT762X_SOC_MT7620N,
-- MT762X_SOC_MT7628AN,
--};
--extern enum mt762x_soc_type mt762x_soc;
--
- #define MT7620_SYSC_BASE 0x10000000
-
- #define SYSC_REG_CHIP_NAME0 0x00
---- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
-+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
-@@ -13,6 +13,20 @@
- #ifndef _RALINK_REGS_H_
- #define _RALINK_REGS_H_
-
-+enum ralink_soc_type {
-+ RALINK_UNKNOWN = 0,
-+ RT305X_SOC_RT3050,
-+ RT305X_SOC_RT3052,
-+ RT305X_SOC_RT3350,
-+ RT305X_SOC_RT3352,
-+ RT305X_SOC_RT5350,
-+ MT762X_SOC_MT7620A,
-+ MT762X_SOC_MT7620N,
-+ MT762X_SOC_MT7621AT,
-+ MT762X_SOC_MT7628AN,
-+};
-+extern enum ralink_soc_type ralink_soc;
-+
- extern __iomem void *rt_sysc_membase;
- extern __iomem void *rt_memc_membase;
-
---- a/arch/mips/include/asm/mach-ralink/rt305x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
-@@ -13,25 +13,16 @@
- #ifndef _RT305X_REGS_H_
- #define _RT305X_REGS_H_
-
--enum rt305x_soc_type {
-- RT305X_SOC_UNKNOWN = 0,
-- RT305X_SOC_RT3050,
-- RT305X_SOC_RT3052,
-- RT305X_SOC_RT3350,
-- RT305X_SOC_RT3352,
-- RT305X_SOC_RT5350,
--};
--
--extern enum rt305x_soc_type rt305x_soc;
-+extern enum ralink_soc_type ralink_soc;
-
- static inline int soc_is_rt3050(void)
- {
-- return rt305x_soc == RT305X_SOC_RT3050;
-+ return ralink_soc == RT305X_SOC_RT3050;
- }
-
- static inline int soc_is_rt3052(void)
- {
-- return rt305x_soc == RT305X_SOC_RT3052;
-+ return ralink_soc == RT305X_SOC_RT3052;
- }
-
- static inline int soc_is_rt305x(void)
-@@ -41,17 +32,17 @@ static inline int soc_is_rt305x(void)
-
- static inline int soc_is_rt3350(void)
- {
-- return rt305x_soc == RT305X_SOC_RT3350;
-+ return ralink_soc == RT305X_SOC_RT3350;
- }
-
- static inline int soc_is_rt3352(void)
- {
-- return rt305x_soc == RT305X_SOC_RT3352;
-+ return ralink_soc == RT305X_SOC_RT3352;
- }
-
- static inline int soc_is_rt5350(void)
- {
-- return rt305x_soc == RT305X_SOC_RT5350;
-+ return ralink_soc == RT305X_SOC_RT5350;
- }
-
- #define RT305X_SYSC_BASE 0x10000000
---- a/arch/mips/ralink/prom.c
-+++ b/arch/mips/ralink/prom.c
-@@ -15,10 +15,13 @@
- #include <asm/bootinfo.h>
- #include <asm/addrspace.h>
-
-+#include <asm/mach-ralink/ralink_regs.h>
-+
- #include "common.h"
-
- struct ralink_soc_info soc_info;
--struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
-+enum ralink_soc_type ralink_soc;
-+EXPORT_SYMBOL_GPL(ralink_soc);
-
- const char *get_system_type(void)
- {
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -21,8 +21,6 @@
-
- #include "common.h"
-
--enum rt305x_soc_type rt305x_soc;
--
- static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
- static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
- static struct rt2880_pmx_func uartf_func[] = {
-@@ -236,24 +234,24 @@ void prom_soc_init(struct ralink_soc_inf
-
- icache_sets = (read_c0_config1() >> 22) & 7;
- if (icache_sets == 1) {
-- rt305x_soc = RT305X_SOC_RT3050;
-+ ralink_soc = RT305X_SOC_RT3050;
- name = "RT3050";
- soc_info->compatible = "ralink,rt3050-soc";
- } else {
-- rt305x_soc = RT305X_SOC_RT3052;
-+ ralink_soc = RT305X_SOC_RT3052;
- name = "RT3052";
- soc_info->compatible = "ralink,rt3052-soc";
- }
- } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
-- rt305x_soc = RT305X_SOC_RT3350;
-+ ralink_soc = RT305X_SOC_RT3350;
- name = "RT3350";
- soc_info->compatible = "ralink,rt3350-soc";
- } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
-- rt305x_soc = RT305X_SOC_RT3352;
-+ ralink_soc = RT305X_SOC_RT3352;
- name = "RT3352";
- soc_info->compatible = "ralink,rt3352-soc";
- } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
-- rt305x_soc = RT305X_SOC_RT5350;
-+ ralink_soc = RT305X_SOC_RT5350;
- name = "RT5350";
- soc_info->compatible = "ralink,rt5350-soc";
- } else {
+++ /dev/null
-From 2a7f11a3a569159e97b7c5134c4d1f3f5b253637 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:14:42 +0100
-Subject: [PATCH 12/53] arch: mips: fix clock jitter
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/cevt-rt3352.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/cevt-rt3352.c
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -69,7 +69,7 @@ static int systick_next_event(unsigned l
- sdev = container_of(evt, struct systick_device, dev);
- count = ioread32(sdev->membase + SYSTICK_COUNT);
- count = (count + delta) % SYSTICK_FREQ;
-- iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
-+ iowrite32(count, sdev->membase + SYSTICK_COMPARE);
-
- return 0;
- }
+++ /dev/null
-From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:15:32 +0100
-Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/kernel/setup.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/kernel/setup.c
-+++ b/arch/mips/kernel/setup.c
-@@ -681,7 +681,6 @@ static void __init arch_mem_init(char **
- crashk_res.end - crashk_res.start + 1,
- BOOTMEM_DEFAULT);
- #endif
-- device_tree_init();
- sparse_init();
- plat_swiotlb_setup();
- paging_init();
-@@ -791,6 +790,7 @@ void __init setup_arch(char **cmdline_p)
- prefill_possible_map();
-
- cpu_cache_init();
-+ device_tree_init();
- }
-
- unsigned long kernelsp[NR_CPUS];
+++ /dev/null
-From e6ed424c36458aff8738fb1fbb0141196678058a Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:17:23 +0100
-Subject: [PATCH 14/53] arch: mips: cleanup cevt-rt3352
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/cevt-rt3352.c | 85 ++++++++++++++++++++++++++--------------
- 1 file changed, 56 insertions(+), 29 deletions(-)
-
---- a/arch/mips/ralink/cevt-rt3352.c
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -52,7 +52,7 @@ static inline void mt7620_freq_scaling(s
-
- sdev->freq_scale = status;
-
-- pr_info("%s: %s autosleep mode\n", systick.dev.name,
-+ pr_info("%s: %s autosleep mode\n", sdev->dev.name,
- (status) ? ("enable") : ("disable"));
- if (status)
- rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
-@@ -60,18 +60,33 @@ static inline void mt7620_freq_scaling(s
- rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
- }
-
-+static inline unsigned int read_count(struct systick_device *sdev)
-+{
-+ return ioread32(sdev->membase + SYSTICK_COUNT);
-+}
-+
-+static inline unsigned int read_compare(struct systick_device *sdev)
-+{
-+ return ioread32(sdev->membase + SYSTICK_COMPARE);
-+}
-+
-+static inline void write_compare(struct systick_device *sdev, unsigned int val)
-+{
-+ iowrite32(val, sdev->membase + SYSTICK_COMPARE);
-+}
-+
- static int systick_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
- struct systick_device *sdev;
-- u32 count;
-+ int res;
-
- sdev = container_of(evt, struct systick_device, dev);
-- count = ioread32(sdev->membase + SYSTICK_COUNT);
-- count = (count + delta) % SYSTICK_FREQ;
-- iowrite32(count, sdev->membase + SYSTICK_COMPARE);
-+ delta += read_count(sdev);
-+ write_compare(sdev, delta);
-+ res = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0;
-
-- return 0;
-+ return res;
- }
-
- static void systick_event_handler(struct clock_event_device *dev)
-@@ -81,20 +96,25 @@ static void systick_event_handler(struct
-
- static irqreturn_t systick_interrupt(int irq, void *dev_id)
- {
-- struct clock_event_device *dev = (struct clock_event_device *) dev_id;
-+ int ret = 0;
-+ struct clock_event_device *cdev;
-+ struct systick_device *sdev;
-
-- dev->event_handler(dev);
-+ if (read_c0_cause() & STATUSF_IP7) {
-+ cdev = (struct clock_event_device *) dev_id;
-+ sdev = container_of(cdev, struct systick_device, dev);
-+
-+ /* Clear Count/Compare Interrupt */
-+ write_compare(sdev, read_compare(sdev));
-+ cdev->event_handler(cdev);
-+ ret = 1;
-+ }
-
-- return IRQ_HANDLED;
-+ return IRQ_RETVAL(ret);
- }
-
- static struct systick_device systick = {
- .dev = {
-- /*
-- * cevt-r4k uses 300, make sure systick
-- * gets used if available
-- */
-- .rating = 310,
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = systick_next_event,
- .set_state_shutdown = systick_shutdown,
-@@ -116,9 +136,9 @@ static int systick_shutdown(struct clock
- sdev = container_of(evt, struct systick_device, dev);
-
- if (sdev->irq_requested)
-- free_irq(systick.dev.irq, &systick_irqaction);
-+ remove_irq(systick.dev.irq, &systick_irqaction);
- sdev->irq_requested = 0;
-- iowrite32(0, systick.membase + SYSTICK_CONFIG);
-+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
-
- if (systick_freq_scaling)
- systick_freq_scaling(sdev, 0);
-@@ -145,38 +165,45 @@ static int systick_set_oneshot(struct cl
- }
-
- static const struct of_device_id systick_match[] = {
-- { .compatible = "ralink,mt7620-systick", .data = mt7620_freq_scaling},
-+ { .compatible = "ralink,mt7620a-systick", .data = mt7620_freq_scaling},
- {},
- };
-
- static void __init ralink_systick_init(struct device_node *np)
- {
- const struct of_device_id *match;
-+ int rating = 200;
-
- systick.membase = of_iomap(np, 0);
- if (!systick.membase)
- return;
-
- match = of_match_node(systick_match, np);
-- if (match)
-+ if (match) {
- systick_freq_scaling = match->data;
-+ /*
-+ * cevt-r4k uses 300, make sure systick
-+ * gets used if available
-+ */
-+ rating = 310;
-+ }
-
-- systick_irqaction.name = np->name;
-- systick.dev.name = np->name;
-- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
-- systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
-- systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
-+ /* enable counter than register clock source */
-+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
-+ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
-+ SYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up);
-+
-+ /* register clock event */
- systick.dev.irq = irq_of_parse_and_map(np, 0);
- if (!systick.dev.irq) {
- pr_err("%s: request_irq failed", np->name);
- return;
- }
--
-- clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
-- SYSTICK_FREQ, 301, 16, clocksource_mmio_readl_up);
--
-- clockevents_register_device(&systick.dev);
--
-+ systick_irqaction.name = np->name;
-+ systick.dev.name = np->name;
-+ systick.dev.rating = rating;
-+ systick.dev.cpumask = cpumask_of(0);
-+ clockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff);
- pr_info("%s: running - mult: %d, shift: %d\n",
- np->name, systick.dev.mult, systick.dev.shift);
- }
+++ /dev/null
-From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:18:05 +0100
-Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by
- default
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -13,9 +13,9 @@ config CLKEVT_RT3352
- select CEVT_SYSTICK_QUIRK
-
- config RALINK_ILL_ACC
-- bool
-+ bool "illegal access irq"
- depends on SOC_RT305X
-- default y
-+ default n
-
- config IRQ_INTC
- bool
+++ /dev/null
-From 3c146f6123a73cb6c7d21269b5ada8ccb272a988 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:18:41 +0100
-Subject: [PATCH 16/53] arch: mips: ralink: remove non-PCI check
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 3 ---
- 1 file changed, 3 deletions(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -526,9 +526,6 @@ void prom_soc_init(struct ralink_soc_inf
- mt762x_soc = MT762X_SOC_MT7620N;
- name = "MT7620N";
- soc_info->compatible = "ralink,mt7620n-soc";
--#ifdef CONFIG_PCI
-- panic("mt7620n is only supported for non pci kernels");
--#endif
- }
- } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
- mt762x_soc = MT762X_SOC_MT7628AN;
+++ /dev/null
-From 145fcd145e0adb10531bb2e8c9f919b0606dff4d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:19:15 +0100
-Subject: [PATCH 17/53] arch: mips: ralink: do not set pm_poweroff
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/reset.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -98,7 +98,6 @@ static int __init mips_reboot_setup(void
- {
- _machine_restart = ralink_restart;
- _machine_halt = ralink_halt;
-- pm_power_off = ralink_halt;
-
- return 0;
- }
+++ /dev/null
-From d3c1e72c755cf67427b5d410039a096520d6537f Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:19:55 +0100
-Subject: [PATCH 18/53] arch: mips: ralink: reset pci prior to reboot
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/reset.c | 12 ++++++++++--
- 1 file changed, 10 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -11,6 +11,7 @@
- #include <linux/pm.h>
- #include <linux/io.h>
- #include <linux/of.h>
-+#include <linux/delay.h>
- #include <linux/reset-controller.h>
-
- #include <asm/reboot.h>
-@@ -18,8 +19,10 @@
- #include <asm/mach-ralink/ralink_regs.h>
-
- /* Reset Control */
--#define SYSC_REG_RESET_CTRL 0x034
--#define RSTCTL_RESET_SYSTEM BIT(0)
-+#define SYSC_REG_RESET_CTRL 0x034
-+
-+#define RSTCTL_RESET_PCI BIT(26)
-+#define RSTCTL_RESET_SYSTEM BIT(0)
-
- static int ralink_assert_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-@@ -83,6 +86,11 @@ void ralink_rst_init(void)
-
- static void ralink_restart(char *command)
- {
-+ if (IS_ENABLED(CONFIG_PCI)) {
-+ rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
-+ mdelay(50);
-+ }
-+
- local_irq_disable();
- rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
- unreachable();
+++ /dev/null
-From 43372c2be9fcf68bc40c322039c75893ce4e982c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:20:47 +0100
-Subject: [PATCH 19/53] arch: mips: ralink: add mt7621 cpu-feature-overrides
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../asm/mach-ralink/mt7621/cpu-feature-overrides.h | 65 ++++++++++++++++++++
- 1 file changed, 65 insertions(+)
- create mode 100644 arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
-@@ -0,0 +1,65 @@
-+/*
-+ * Ralink MT7621 specific CPU feature overrides
-+ *
-+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * This file was derived from: include/asm-mips/cpu-features.h
-+ * Copyright (C) 2003, 2004 Ralf Baechle
-+ * Copyright (C) 2004 Maciej W. Rozycki
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
-+#define _MT7621_CPU_FEATURE_OVERRIDES_H
-+
-+#define cpu_has_tlb 1
-+#define cpu_has_4kex 1
-+#define cpu_has_3k_cache 0
-+#define cpu_has_4k_cache 1
-+#define cpu_has_tx39_cache 0
-+#define cpu_has_sb1_cache 0
-+#define cpu_has_fpu 0
-+#define cpu_has_32fpr 0
-+#define cpu_has_counter 1
-+#define cpu_has_watch 1
-+#define cpu_has_divec 1
-+
-+#define cpu_has_prefetch 1
-+#define cpu_has_ejtag 1
-+#define cpu_has_llsc 1
-+
-+#define cpu_has_mips16 1
-+#define cpu_has_mdmx 0
-+#define cpu_has_mips3d 0
-+#define cpu_has_smartmips 0
-+
-+#define cpu_has_mips32r1 1
-+#define cpu_has_mips32r2 1
-+#define cpu_has_mips64r1 0
-+#define cpu_has_mips64r2 0
-+
-+#define cpu_has_dsp 1
-+#define cpu_has_dsp2 0
-+#define cpu_has_mipsmt 1
-+
-+#define cpu_has_64bits 0
-+#define cpu_has_64bit_zero_reg 0
-+#define cpu_has_64bit_gp_regs 0
-+#define cpu_has_64bit_addresses 0
-+
-+#define cpu_dcache_line_size() 32
-+#define cpu_icache_line_size() 32
-+
-+#define cpu_has_dc_aliases 0
-+#define cpu_has_vtag_icache 0
-+
-+#define cpu_has_rixi 0
-+#define cpu_has_tlbinv 0
-+#define cpu_has_userlocal 1
-+
-+#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */
+++ /dev/null
-From 0315355131c46c42164a4b180363bc79728f7015 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:27:15 +0100
-Subject: [PATCH 20/53] arch: mips: ralink: mt7628 fixes
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 76 +++++++++++++++++++++++++++++----------------
- 1 file changed, 50 insertions(+), 26 deletions(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -104,28 +104,28 @@ static struct rt2880_pmx_group mt7620a_p
- };
-
- static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
-- FUNC("sdcx", 3, 19, 1),
-+ FUNC("sdcx d6", 3, 19, 1),
- FUNC("utif", 2, 19, 1),
- FUNC("gpio", 1, 19, 1),
-- FUNC("pwm", 0, 19, 1),
-+ FUNC("pwm1", 0, 19, 1),
- };
-
- static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
-- FUNC("sdcx", 3, 18, 1),
-+ FUNC("sdcx d7", 3, 18, 1),
- FUNC("utif", 2, 18, 1),
- FUNC("gpio", 1, 18, 1),
-- FUNC("pwm", 0, 18, 1),
-+ FUNC("pwm0", 0, 18, 1),
- };
-
- static struct rt2880_pmx_func uart2_grp_mt7628[] = {
-- FUNC("sdcx", 3, 20, 2),
-+ FUNC("sdcx d5 d4", 3, 20, 2),
- FUNC("pwm", 2, 20, 2),
- FUNC("gpio", 1, 20, 2),
- FUNC("uart", 0, 20, 2),
- };
-
- static struct rt2880_pmx_func uart1_grp_mt7628[] = {
-- FUNC("sdcx", 3, 45, 2),
-+ FUNC("sw_r", 3, 45, 2),
- FUNC("pwm", 2, 45, 2),
- FUNC("gpio", 1, 45, 2),
- FUNC("uart", 0, 45, 2),
-@@ -168,7 +168,7 @@ static struct rt2880_pmx_func spi_cs1_gr
- FUNC("-", 3, 6, 1),
- FUNC("refclk", 2, 6, 1),
- FUNC("gpio", 1, 6, 1),
-- FUNC("spi", 0, 6, 1),
-+ FUNC("spi cs1", 0, 6, 1),
- };
-
- static struct rt2880_pmx_func spis_grp_mt7628[] = {
-@@ -185,28 +185,44 @@ static struct rt2880_pmx_func gpio_grp_m
- FUNC("gpio", 0, 11, 1),
- };
-
--#define MT7628_GPIO_MODE_MASK 0x3
--
--#define MT7628_GPIO_MODE_PWM1 30
--#define MT7628_GPIO_MODE_PWM0 28
--#define MT7628_GPIO_MODE_UART2 26
--#define MT7628_GPIO_MODE_UART1 24
--#define MT7628_GPIO_MODE_I2C 20
--#define MT7628_GPIO_MODE_REFCLK 18
--#define MT7628_GPIO_MODE_PERST 16
--#define MT7628_GPIO_MODE_WDT 14
--#define MT7628_GPIO_MODE_SPI 12
--#define MT7628_GPIO_MODE_SDMODE 10
--#define MT7628_GPIO_MODE_UART0 8
--#define MT7628_GPIO_MODE_I2S 6
--#define MT7628_GPIO_MODE_CS1 4
--#define MT7628_GPIO_MODE_SPIS 2
--#define MT7628_GPIO_MODE_GPIO 0
-+static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
-+ FUNC("rsvd", 3, 35, 1),
-+ FUNC("rsvd", 2, 35, 1),
-+ FUNC("gpio", 1, 35, 1),
-+ FUNC("wled_kn", 0, 35, 1),
-+};
-+
-+static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
-+ FUNC("rsvd", 3, 35, 1),
-+ FUNC("rsvd", 2, 35, 1),
-+ FUNC("gpio", 1, 35, 1),
-+ FUNC("wled_an", 0, 35, 1),
-+};
-+
-+#define MT7628_GPIO_MODE_MASK 0x3
-+
-+#define MT7628_GPIO_MODE_WLED_KN 48
-+#define MT7628_GPIO_MODE_WLED_AN 32
-+#define MT7628_GPIO_MODE_PWM1 30
-+#define MT7628_GPIO_MODE_PWM0 28
-+#define MT7628_GPIO_MODE_UART2 26
-+#define MT7628_GPIO_MODE_UART1 24
-+#define MT7628_GPIO_MODE_I2C 20
-+#define MT7628_GPIO_MODE_REFCLK 18
-+#define MT7628_GPIO_MODE_PERST 16
-+#define MT7628_GPIO_MODE_WDT 14
-+#define MT7628_GPIO_MODE_SPI 12
-+#define MT7628_GPIO_MODE_SDMODE 10
-+#define MT7628_GPIO_MODE_UART0 8
-+#define MT7628_GPIO_MODE_I2S 6
-+#define MT7628_GPIO_MODE_CS1 4
-+#define MT7628_GPIO_MODE_SPIS 2
-+#define MT7628_GPIO_MODE_GPIO 0
-
- static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
- GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 1, MT7628_GPIO_MODE_PWM1),
-- GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
-+ GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 1, MT7628_GPIO_MODE_PWM0),
- GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 1, MT7628_GPIO_MODE_UART2),
-@@ -230,6 +246,10 @@ static struct rt2880_pmx_group mt7628an_
- 1, MT7628_GPIO_MODE_SPIS),
- GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
- 1, MT7628_GPIO_MODE_GPIO),
-+ GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
-+ 1, MT7628_GPIO_MODE_WLED_AN),
-+ GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
-+ 1, MT7628_GPIO_MODE_WLED_KN),
- { 0 }
- };
-
-@@ -542,7 +562,11 @@ void prom_soc_init(struct ralink_soc_inf
- (rev & CHIP_REV_ECO_MASK));
-
- cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
-- dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
-+
-+ if (ralink_soc == MT762X_SOC_MT7628AN)
-+ dram_type = ((cfg0&0x00000001) == 0x00000001)?SYSCFG0_DRAM_TYPE_DDR1_MT7628:SYSCFG0_DRAM_TYPE_DDR2_MT7628;
-+ else
-+ dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
-
- soc_info->mem_base = MT7620_DRAM_BASE;
- if (mt762x_soc == MT762X_SOC_MT7628AN)
+++ /dev/null
-From 14ef339843c24bf449d0f6d8bc176368c331c2c8 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:29:00 +0100
-Subject: [PATCH 21/53] arch: mips: ralink: add mt7688 detection
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
- arch/mips/include/asm/mach-ralink/ralink_regs.h | 1 +
- arch/mips/ralink/mt7620.c | 21 ++++++++++++++++-----
- 3 files changed, 18 insertions(+), 5 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -17,6 +17,7 @@
-
- #define SYSC_REG_CHIP_NAME0 0x00
- #define SYSC_REG_CHIP_NAME1 0x04
-+#define SYSC_REG_EFUSE_CFG 0x08
- #define SYSC_REG_CHIP_REV 0x0c
- #define SYSC_REG_SYSTEM_CONFIG0 0x10
- #define SYSC_REG_SYSTEM_CONFIG1 0x14
---- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
-+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
-@@ -24,6 +24,7 @@ enum ralink_soc_type {
- MT762X_SOC_MT7620N,
- MT762X_SOC_MT7621AT,
- MT762X_SOC_MT7628AN,
-+ MT762X_SOC_MT7688,
- };
- extern enum ralink_soc_type ralink_soc;
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -46,6 +46,9 @@ enum mt762x_soc_type mt762x_soc;
- #define CLKCFG_FFRAC_MASK 0x001f
- #define CLKCFG_FFRAC_USB_VAL 0x0003
-
-+/* EFUSE bits */
-+#define EFUSE_MT7688 0x100000
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-
-@@ -407,7 +410,7 @@ void __init ralink_clk_init(void)
- #define RINT(x) ((x) / 1000000)
- #define RFRAC(x) (((x) / 1000) % 1000)
-
-- if (mt762x_soc == MT762X_SOC_MT7628AN) {
-+ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
- if (xtal_rate == MHZ(40))
- cpu_rate = MHZ(580);
- else
-@@ -451,7 +454,8 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10000c00.uartlite", periph_rate);
- ralink_clk_add("10180000.wmac", xtal_rate);
-
-- if (IS_ENABLED(CONFIG_USB)) {
-+ if (IS_ENABLED(CONFIG_USB) &&
-+ (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
- /*
- * When the CPU goes into sleep mode, the BUS clock will be too low for
- * USB to function properly
-@@ -548,8 +552,15 @@ void prom_soc_init(struct ralink_soc_inf
- soc_info->compatible = "ralink,mt7620n-soc";
- }
- } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
-- mt762x_soc = MT762X_SOC_MT7628AN;
-- name = "MT7628AN";
-+ u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
-+
-+ if (efuse & EFUSE_MT7688) {
-+ mt762x_soc = MT762X_SOC_MT7688;
-+ name = "MT7688";
-+ } else {
-+ mt762x_soc = MT762X_SOC_MT7628AN;
-+ name = "MT7628AN";
-+ }
- soc_info->compatible = "ralink,mt7628an-soc";
- } else {
- panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
-@@ -582,7 +593,7 @@ void prom_soc_init(struct ralink_soc_inf
- pr_info("Digital PMU set to %s control\n",
- (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
-
-- if (mt762x_soc == MT762X_SOC_MT7628AN)
-+ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
- rt2880_pinmux_data = mt7628an_pinmux_data;
- else
- rt2880_pinmux_data = mt7620a_pinmux_data;
+++ /dev/null
-From 2e5d90398aacde3e46dfd87e6f716b00a0ffcd83 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:30:11 +0100
-Subject: [PATCH 22/53] arch: mips: ralink: proper vendor id srtring
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -567,7 +567,7 @@ void prom_soc_init(struct ralink_soc_inf
- }
-
- snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
-- "Ralink %s ver:%u eco:%u",
-+ "MediaTek %s ver:%u eco:%u",
- name,
- (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
- (rev & CHIP_REV_ECO_MASK));
+++ /dev/null
-From 4ede4fbb485d0a88839df1f02371fc00755db636 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:31:41 +0100
-Subject: [PATCH 23/53] arch: mips: ralink: unify soc id
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 19 ++++++++-----------
- 1 file changed, 8 insertions(+), 11 deletions(-)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -37,9 +37,6 @@
- #define PMU1_CFG 0x8C
- #define DIG_SW_SEL BIT(25)
-
--/* is this a MT7620 or a MT7628 */
--enum mt762x_soc_type mt762x_soc;
--
- /* clock scaling */
- #define CLKCFG_FDIV_MASK 0x1f00
- #define CLKCFG_FDIV_USB_VAL 0x0300
-@@ -410,7 +407,7 @@ void __init ralink_clk_init(void)
- #define RINT(x) ((x) / 1000000)
- #define RFRAC(x) (((x) / 1000) % 1000)
-
-- if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
-+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
- if (xtal_rate == MHZ(40))
- cpu_rate = MHZ(580);
- else
-@@ -455,7 +452,7 @@ void __init ralink_clk_init(void)
- ralink_clk_add("10180000.wmac", xtal_rate);
-
- if (IS_ENABLED(CONFIG_USB) &&
-- (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
-+ (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7620N)) {
- /*
- * When the CPU goes into sleep mode, the BUS clock will be too low for
- * USB to function properly
-@@ -543,11 +540,11 @@ void prom_soc_init(struct ralink_soc_inf
-
- if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
- if (bga) {
-- mt762x_soc = MT762X_SOC_MT7620A;
-+ ralink_soc = MT762X_SOC_MT7620A;
- name = "MT7620A";
- soc_info->compatible = "ralink,mt7620a-soc";
- } else {
-- mt762x_soc = MT762X_SOC_MT7620N;
-+ ralink_soc = MT762X_SOC_MT7620N;
- name = "MT7620N";
- soc_info->compatible = "ralink,mt7620n-soc";
- }
-@@ -555,10 +552,10 @@ void prom_soc_init(struct ralink_soc_inf
- u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
-
- if (efuse & EFUSE_MT7688) {
-- mt762x_soc = MT762X_SOC_MT7688;
-+ ralink_soc = MT762X_SOC_MT7688;
- name = "MT7688";
- } else {
-- mt762x_soc = MT762X_SOC_MT7628AN;
-+ ralink_soc = MT762X_SOC_MT7628AN;
- name = "MT7628AN";
- }
- soc_info->compatible = "ralink,mt7628an-soc";
-@@ -580,7 +577,7 @@ void prom_soc_init(struct ralink_soc_inf
- dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
-
- soc_info->mem_base = MT7620_DRAM_BASE;
-- if (mt762x_soc == MT762X_SOC_MT7628AN)
-+ if (ralink_soc == MT762X_SOC_MT7628AN)
- mt7628_dram_init(soc_info);
- else
- mt7620_dram_init(soc_info);
-@@ -593,7 +590,7 @@ void prom_soc_init(struct ralink_soc_inf
- pr_info("Digital PMU set to %s control\n",
- (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
-
-- if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
-+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688)
- rt2880_pinmux_data = mt7628an_pinmux_data;
- else
- rt2880_pinmux_data = mt7620a_pinmux_data;
+++ /dev/null
-From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 12 Aug 2014 20:49:27 +0200
-Subject: [PATCH 24/53] GPIO: add named gpio exports
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
- drivers/gpio/gpiolib-sysfs.c | 10 +++++-
- include/asm-generic/gpio.h | 6 ++++
- include/linux/gpio/consumer.h | 8 +++++
- 4 files changed, 91 insertions(+), 1 deletion(-)
-
---- a/drivers/gpio/gpiolib-of.c
-+++ b/drivers/gpio/gpiolib-of.c
-@@ -23,6 +23,8 @@
- #include <linux/pinctrl/pinctrl.h>
- #include <linux/slab.h>
- #include <linux/gpio/machine.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-
- #include "gpiolib.h"
-
-@@ -450,3 +452,69 @@ void of_gpiochip_remove(struct gpio_chip
- gpiochip_remove_pin_ranges(chip);
- of_node_put(chip->of_node);
- }
-+
-+static struct of_device_id gpio_export_ids[] = {
-+ { .compatible = "gpio-export" },
-+ { /* sentinel */ }
-+};
-+
-+static int __init of_gpio_export_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct device_node *cnp;
-+ u32 val;
-+ int nb = 0;
-+
-+ for_each_child_of_node(np, cnp) {
-+ const char *name = NULL;
-+ int gpio;
-+ bool dmc;
-+ int max_gpio = 1;
-+ int i;
-+
-+ of_property_read_string(cnp, "gpio-export,name", &name);
-+
-+ if (!name)
-+ max_gpio = of_gpio_count(cnp);
-+
-+ for (i = 0; i < max_gpio; i++) {
-+ unsigned flags = 0;
-+ enum of_gpio_flags of_flags;
-+
-+ gpio = of_get_gpio_flags(cnp, i, &of_flags);
-+
-+ if (of_flags == OF_GPIO_ACTIVE_LOW)
-+ flags |= GPIOF_ACTIVE_LOW;
-+
-+ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
-+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
-+ else
-+ flags |= GPIOF_IN;
-+
-+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
-+ continue;
-+
-+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
-+ gpio_export_with_name(gpio, dmc, name);
-+ nb++;
-+ }
-+ }
-+
-+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver gpio_export_driver = {
-+ .driver = {
-+ .name = "gpio-export",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(gpio_export_ids),
-+ },
-+};
-+
-+static int __init of_gpio_export_init(void)
-+{
-+ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe);
-+}
-+device_initcall(of_gpio_export_init);
---- a/drivers/gpio/gpiolib-sysfs.c
-+++ b/drivers/gpio/gpiolib-sysfs.c
-@@ -544,7 +544,7 @@ static struct class gpio_class = {
- *
- * Returns zero on success, else an error.
- */
--int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
- {
- struct gpio_chip *chip;
- struct gpiod_data *data;
-@@ -604,6 +604,8 @@ int gpiod_export(struct gpio_desc *desc,
- offset = gpio_chip_hwgpio(desc);
- if (chip->names && chip->names[offset])
- ioname = chip->names[offset];
-+ if (name)
-+ ioname = name;
-
- dev = device_create_with_groups(&gpio_class, chip->dev,
- MKDEV(0, 0), data, gpio_groups,
-@@ -625,6 +627,12 @@ err_unlock:
- gpiod_dbg(desc, "%s: status %d\n", __func__, status);
- return status;
- }
-+EXPORT_SYMBOL_GPL(__gpiod_export);
-+
-+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+{
-+ return __gpiod_export(desc, direction_may_change, NULL);
-+}
- EXPORT_SYMBOL_GPL(gpiod_export);
-
- static int match_export(struct device *dev, const void *desc)
---- a/include/asm-generic/gpio.h
-+++ b/include/asm-generic/gpio.h
-@@ -122,6 +122,12 @@ static inline int gpio_export(unsigned g
- return gpiod_export(gpio_to_desc(gpio), direction_may_change);
- }
-
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
-+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
-+{
-+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
-+}
-+
- static inline int gpio_export_link(struct device *dev, const char *name,
- unsigned gpio)
- {
---- a/include/linux/gpio/consumer.h
-+++ b/include/linux/gpio/consumer.h
-@@ -426,6 +426,7 @@ static inline struct gpio_desc *devm_get
-
- #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
-
-+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
- int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
- int gpiod_export_link(struct device *dev, const char *name,
- struct gpio_desc *desc);
-@@ -433,6 +434,13 @@ void gpiod_unexport(struct gpio_desc *de
-
- #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
-
-+static inline int _gpiod_export(struct gpio_desc *desc,
-+ bool direction_may_change,
-+ const char *name)
-+{
-+ return -ENOSYS;
-+}
-+
- static inline int gpiod_export(struct gpio_desc *desc,
- bool direction_may_change)
- {
+++ /dev/null
-From 7adbe9a88c33c6e362a10b109d963b5500a21f00 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:34:05 +0100
-Subject: [PATCH 25/53] pinctrl: ralink: add pinctrl driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/Kconfig | 2 +
- drivers/pinctrl/Kconfig | 5 +
- drivers/pinctrl/Makefile | 1 +
- drivers/pinctrl/pinctrl-rt2880.c | 474 ++++++++++++++++++++++++++++++++++++++
- 4 files changed, 482 insertions(+)
- create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -557,6 +557,8 @@ config RALINK
- select CLKDEV_LOOKUP
- select ARCH_HAS_RESET_CONTROLLER
- select RESET_CONTROLLER
-+ select PINCTRL
-+ select PINCTRL_RT2880
-
- config SGI_IP22
- bool "SGI IP22 (Indy/Indigo2)"
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -103,6 +103,11 @@ config PINCTRL_LPC18XX
- help
- Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
-
-+config PINCTRL_RT2880
-+ bool
-+ depends on RALINK
-+ select PINMUX
-+
- config PINCTRL_FALCON
- bool
- depends on SOC_FALCON
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MESON) += meson/
- obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
- obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
- obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
-+obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
- obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
- obj-$(CONFIG_PINCTRL_SIRF) += sirf/
- obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-rt2880.c
-@@ -0,0 +1,474 @@
-+/*
-+ * linux/drivers/pinctrl/pinctrl-rt2880.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinconf.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/pinctrl/machine.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/mach-ralink/pinmux.h>
-+#include <asm/mach-ralink/mt7620.h>
-+
-+#include "core.h"
-+
-+#define SYSC_REG_GPIO_MODE 0x60
-+#define SYSC_REG_GPIO_MODE2 0x64
-+
-+struct rt2880_priv {
-+ struct device *dev;
-+
-+ struct pinctrl_pin_desc *pads;
-+ struct pinctrl_desc *desc;
-+
-+ struct rt2880_pmx_func **func;
-+ int func_count;
-+
-+ struct rt2880_pmx_group *groups;
-+ const char **group_names;
-+ int group_count;
-+
-+ uint8_t *gpio;
-+ int max_pins;
-+};
-+
-+struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
-+
-+static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->group_count;
-+}
-+
-+static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
-+ unsigned group)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (group >= p->group_count)
-+ return NULL;
-+
-+ return p->group_names[group];
-+}
-+
-+static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
-+ unsigned group,
-+ const unsigned **pins,
-+ unsigned *num_pins)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (group >= p->group_count)
-+ return -EINVAL;
-+
-+ *pins = p->groups[group].func[0].pins;
-+ *num_pins = p->groups[group].func[0].pin_count;
-+
-+ return 0;
-+}
-+
-+static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_map *map, unsigned num_maps)
-+{
-+ int i;
-+
-+ for (i = 0; i < num_maps; i++)
-+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
-+ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
-+ kfree(map[i].data.configs.configs);
-+ kfree(map);
-+}
-+
-+static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
-+ struct seq_file *s,
-+ unsigned offset)
-+{
-+ seq_printf(s, "ralink pio");
-+}
-+
-+static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
-+ struct device_node *np,
-+ struct pinctrl_map **map)
-+{
-+ const char *function;
-+ int func = of_property_read_string(np, "ralink,function", &function);
-+ int grps = of_property_count_strings(np, "ralink,group");
-+ int i;
-+
-+ if (func || !grps)
-+ return;
-+
-+ for (i = 0; i < grps; i++) {
-+ const char *group;
-+
-+ of_property_read_string_index(np, "ralink,group", i, &group);
-+
-+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
-+ (*map)->name = function;
-+ (*map)->data.mux.group = group;
-+ (*map)->data.mux.function = function;
-+ (*map)++;
-+ }
-+}
-+
-+static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
-+ struct device_node *np_config,
-+ struct pinctrl_map **map,
-+ unsigned *num_maps)
-+{
-+ int max_maps = 0;
-+ struct pinctrl_map *tmp;
-+ struct device_node *np;
-+
-+ for_each_child_of_node(np_config, np) {
-+ int ret = of_property_count_strings(np, "ralink,group");
-+
-+ if (ret >= 0)
-+ max_maps += ret;
-+ }
-+
-+ if (!max_maps)
-+ return max_maps;
-+
-+ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
-+ if (!*map)
-+ return -ENOMEM;
-+
-+ tmp = *map;
-+
-+ for_each_child_of_node(np_config, np)
-+ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
-+ *num_maps = max_maps;
-+
-+ return 0;
-+}
-+
-+static const struct pinctrl_ops rt2880_pctrl_ops = {
-+ .get_groups_count = rt2880_get_group_count,
-+ .get_group_name = rt2880_get_group_name,
-+ .get_group_pins = rt2880_get_group_pins,
-+ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
-+ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
-+ .dt_free_map = rt2880_pinctrl_dt_free_map,
-+};
-+
-+static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->func_count;
-+}
-+
-+static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
-+ unsigned func)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->func[func]->name;
-+}
-+
-+static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ const char * const **groups,
-+ unsigned * const num_groups)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (p->func[func]->group_count == 1)
-+ *groups = &p->group_names[p->func[func]->groups[0]];
-+ else
-+ *groups = p->group_names;
-+
-+ *num_groups = p->func[func]->group_count;
-+
-+ return 0;
-+}
-+
-+static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ unsigned group)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+ u32 mode = 0;
-+ u32 reg = SYSC_REG_GPIO_MODE;
-+ int i;
-+ int shift;
-+
-+ /* dont allow double use */
-+ if (p->groups[group].enabled) {
-+ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
-+ return -EBUSY;
-+ }
-+
-+ p->groups[group].enabled = 1;
-+ p->func[func]->enabled = 1;
-+
-+ shift = p->groups[group].shift;
-+ if (shift >= 32) {
-+ shift -= 32;
-+ reg = SYSC_REG_GPIO_MODE2;
-+ }
-+ mode = rt_sysc_r32(reg);
-+ mode &= ~(p->groups[group].mask << shift);
-+
-+ /* mark the pins as gpio */
-+ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
-+ p->gpio[p->groups[group].func[0].pins[i]] = 1;
-+
-+ /* function 0 is gpio and needs special handling */
-+ if (func == 0) {
-+ mode |= p->groups[group].gpio << shift;
-+ } else {
-+ for (i = 0; i < p->func[func]->pin_count; i++)
-+ p->gpio[p->func[func]->pins[i]] = 0;
-+ mode |= p->func[func]->value << shift;
-+ }
-+ rt_sysc_w32(mode, reg);
-+
-+ return 0;
-+}
-+
-+static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_gpio_range *range,
-+ unsigned pin)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (!p->gpio[pin]) {
-+ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct pinmux_ops rt2880_pmx_group_ops = {
-+ .get_functions_count = rt2880_pmx_func_count,
-+ .get_function_name = rt2880_pmx_func_name,
-+ .get_function_groups = rt2880_pmx_group_get_groups,
-+ .set_mux = rt2880_pmx_group_enable,
-+ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
-+};
-+
-+static struct pinctrl_desc rt2880_pctrl_desc = {
-+ .owner = THIS_MODULE,
-+ .name = "rt2880-pinmux",
-+ .pctlops = &rt2880_pctrl_ops,
-+ .pmxops = &rt2880_pmx_group_ops,
-+};
-+
-+static struct rt2880_pmx_func gpio_func = {
-+ .name = "gpio",
-+};
-+
-+static int rt2880_pinmux_index(struct rt2880_priv *p)
-+{
-+ struct rt2880_pmx_func **f;
-+ struct rt2880_pmx_group *mux = p->groups;
-+ int i, j, c = 0;
-+
-+ /* count the mux functions */
-+ while (mux->name) {
-+ p->group_count++;
-+ mux++;
-+ }
-+
-+ /* allocate the group names array needed by the gpio function */
-+ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
-+ if (!p->group_names)
-+ return -1;
-+
-+ for (i = 0; i < p->group_count; i++) {
-+ p->group_names[i] = p->groups[i].name;
-+ p->func_count += p->groups[i].func_count;
-+ }
-+
-+ /* we have a dummy function[0] for gpio */
-+ p->func_count++;
-+
-+ /* allocate our function and group mapping index buffers */
-+ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
-+ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
-+ if (!f || !gpio_func.groups)
-+ return -1;
-+
-+ /* add a backpointer to the function so it knows its group */
-+ gpio_func.group_count = p->group_count;
-+ for (i = 0; i < gpio_func.group_count; i++)
-+ gpio_func.groups[i] = i;
-+
-+ f[c] = &gpio_func;
-+ c++;
-+
-+ /* add remaining functions */
-+ for (i = 0; i < p->group_count; i++) {
-+ for (j = 0; j < p->groups[i].func_count; j++) {
-+ f[c] = &p->groups[i].func[j];
-+ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
-+ f[c]->groups[0] = i;
-+ f[c]->group_count = 1;
-+ c++;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static int rt2880_pinmux_pins(struct rt2880_priv *p)
-+{
-+ int i, j;
-+
-+ /* loop over the functions and initialize the pins array. also work out the highest pin used */
-+ for (i = 0; i < p->func_count; i++) {
-+ int pin;
-+
-+ if (!p->func[i]->pin_count)
-+ continue;
-+
-+ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
-+ for (j = 0; j < p->func[i]->pin_count; j++)
-+ p->func[i]->pins[j] = p->func[i]->pin_first + j;
-+
-+ pin = p->func[i]->pin_first + p->func[i]->pin_count;
-+ if (pin > p->max_pins)
-+ p->max_pins = pin;
-+ }
-+
-+ /* the buffer that tells us which pins are gpio */
-+ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
-+ GFP_KERNEL);
-+ /* the pads needed to tell pinctrl about our pins */
-+ p->pads = devm_kzalloc(p->dev,
-+ sizeof(struct pinctrl_pin_desc) * p->max_pins,
-+ GFP_KERNEL);
-+ if (!p->pads || !p->gpio ) {
-+ dev_err(p->dev, "Failed to allocate gpio data\n");
-+ return -ENOMEM;
-+ }
-+
-+ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
-+ for (i = 0; i < p->func_count; i++) {
-+ if (!p->func[i]->pin_count)
-+ continue;
-+
-+ for (j = 0; j < p->func[i]->pin_count; j++)
-+ p->gpio[p->func[i]->pins[j]] = 0;
-+ }
-+
-+ /* pin 0 is always a gpio */
-+ p->gpio[0] = 1;
-+
-+ /* set the pads */
-+ for (i = 0; i < p->max_pins; i++) {
-+ /* strlen("ioXY") + 1 = 5 */
-+ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
-+
-+ if (!name) {
-+ dev_err(p->dev, "Failed to allocate pad name\n");
-+ return -ENOMEM;
-+ }
-+ snprintf(name, 5, "io%d", i);
-+ p->pads[i].number = i;
-+ p->pads[i].name = name;
-+ }
-+ p->desc->pins = p->pads;
-+ p->desc->npins = p->max_pins;
-+
-+ return 0;
-+}
-+
-+static int rt2880_pinmux_probe(struct platform_device *pdev)
-+{
-+ struct rt2880_priv *p;
-+ struct pinctrl_dev *dev;
-+ struct device_node *np;
-+
-+ if (!rt2880_pinmux_data)
-+ return -ENOSYS;
-+
-+ /* setup the private data */
-+ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
-+ if (!p)
-+ return -ENOMEM;
-+
-+ p->dev = &pdev->dev;
-+ p->desc = &rt2880_pctrl_desc;
-+ p->groups = rt2880_pinmux_data;
-+ platform_set_drvdata(pdev, p);
-+
-+ /* init the device */
-+ if (rt2880_pinmux_index(p)) {
-+ dev_err(&pdev->dev, "failed to load index\n");
-+ return -EINVAL;
-+ }
-+ if (rt2880_pinmux_pins(p)) {
-+ dev_err(&pdev->dev, "failed to load pins\n");
-+ return -EINVAL;
-+ }
-+ dev = pinctrl_register(p->desc, &pdev->dev, p);
-+ if (IS_ERR(dev))
-+ return PTR_ERR(dev);
-+
-+ /* finalize by adding gpio ranges for enables gpio controllers */
-+ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
-+ const __be32 *ngpio, *gpiobase;
-+ struct pinctrl_gpio_range *range;
-+ char *name;
-+
-+ if (!of_device_is_available(np))
-+ continue;
-+
-+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
-+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
-+ if (!ngpio || !gpiobase) {
-+ dev_err(&pdev->dev, "failed to load chip info\n");
-+ return -EINVAL;
-+ }
-+
-+ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
-+ range->name = name = (char *) &range[1];
-+ sprintf(name, "pio");
-+ range->npins = __be32_to_cpu(*ngpio);
-+ range->base = __be32_to_cpu(*gpiobase);
-+ range->pin_base = range->base;
-+ pinctrl_add_gpio_range(dev, range);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id rt2880_pinmux_match[] = {
-+ { .compatible = "ralink,rt2880-pinmux" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
-+
-+static struct platform_driver rt2880_pinmux_driver = {
-+ .probe = rt2880_pinmux_probe,
-+ .driver = {
-+ .name = "rt2880-pinmux",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt2880_pinmux_match,
-+ },
-+};
-+
-+int __init rt2880_pinmux_init(void)
-+{
-+ return platform_driver_register(&rt2880_pinmux_driver);
-+}
-+
-+core_initcall_sync(rt2880_pinmux_init);
+++ /dev/null
-From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 19:45:30 +0200
-Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink
-
-Describe gpio-ralink binding.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: devicetree@vger.kernel.org
-Cc: linux-gpio@vger.kernel.org
----
- .../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++
- 1 file changed, 40 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-@@ -0,0 +1,40 @@
-+Ralink SoC GPIO controller bindings
-+
-+Required properties:
-+- compatible:
-+ - "ralink,rt2880-gpio" for Ralink controllers
-+- #gpio-cells : Should be two.
-+ - first cell is the pin number
-+ - second cell is used to specify optional parameters (unused)
-+- gpio-controller : Marks the device node as a GPIO controller
-+- reg : Physical base address and length of the controller's registers
-+- interrupt-parent: phandle to the INTC device node
-+- interrupts : Specify the INTC interrupt number
-+- ralink,num-gpios : Specify the number of GPIOs
-+- ralink,register-map : The register layout depends on the GPIO bank and actual
-+ SoC type. Register offsets need to be in this order.
-+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
-+
-+Optional properties:
-+- ralink,gpio-base : Specify the GPIO chips base number
-+
-+Example:
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
-+
-+ #gpio-cells = <2>;
-+ gpio-controller;
-+
-+ reg = <0x600 0x34>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ ralink,gpio-base = <0>;
-+ ralink,num-gpios = <24>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ };
+++ /dev/null
-From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Aug 2014 20:36:29 +0200
-Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
-
-Add gpio driver for Ralink SoC. This driver makes the gpio core on
-RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: linux-gpio@vger.kernel.org
----
- arch/mips/include/asm/mach-ralink/gpio.h | 24 ++
- drivers/gpio/Kconfig | 6 +
- drivers/gpio/Makefile | 1 +
- drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++
- 4 files changed, 386 insertions(+)
- create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
- create mode 100644 drivers/gpio/gpio-ralink.c
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/gpio.h
-@@ -0,0 +1,24 @@
-+/*
-+ * Ralink SoC GPIO API support
-+ *
-+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef __ASM_MACH_RALINK_GPIO_H
-+#define __ASM_MACH_RALINK_GPIO_H
-+
-+#define ARCH_NR_GPIOS 128
-+#include <asm-generic/gpio.h>
-+
-+#define gpio_get_value __gpio_get_value
-+#define gpio_set_value __gpio_set_value
-+#define gpio_cansleep __gpio_cansleep
-+#define gpio_to_irq __gpio_to_irq
-+
-+#endif /* __ASM_MACH_RALINK_GPIO_H */
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -404,6 +404,12 @@ config GPIO_SCH311X
- To compile this driver as a module, choose M here: the module will
- be called gpio-sch311x.
-
-+config GPIO_RALINK
-+ bool "Ralink GPIO Support"
-+ depends on RALINK
-+ help
-+ Say yes here to support the Ralink SoC GPIO device
-+
- config GPIO_SPEAR_SPICS
- bool "ST SPEAr13xx SPI Chip Select as GPIO support"
- depends on PLAT_SPEAR
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -75,6 +75,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
- obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
- obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
- obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
-+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
- obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
- obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
- obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
---- /dev/null
-+++ b/drivers/gpio/gpio-ralink.c
-@@ -0,0 +1,355 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/spinlock.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_irq.h>
-+#include <linux/irqdomain.h>
-+#include <linux/interrupt.h>
-+
-+enum ralink_gpio_reg {
-+ GPIO_REG_INT = 0,
-+ GPIO_REG_EDGE,
-+ GPIO_REG_RENA,
-+ GPIO_REG_FENA,
-+ GPIO_REG_DATA,
-+ GPIO_REG_DIR,
-+ GPIO_REG_POL,
-+ GPIO_REG_SET,
-+ GPIO_REG_RESET,
-+ GPIO_REG_TOGGLE,
-+ GPIO_REG_MAX
-+};
-+
-+struct ralink_gpio_chip {
-+ struct gpio_chip chip;
-+ u8 regs[GPIO_REG_MAX];
-+
-+ spinlock_t lock;
-+ void __iomem *membase;
-+ struct irq_domain *domain;
-+ int irq;
-+
-+ u32 rising;
-+ u32 falling;
-+};
-+
-+#define MAP_MAX 4
-+static struct irq_domain *irq_map[MAP_MAX];
-+static int irq_map_count;
-+static atomic_t irq_refcount = ATOMIC_INIT(0);
-+
-+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
-+{
-+ struct ralink_gpio_chip *rg;
-+
-+ rg = container_of(chip, struct ralink_gpio_chip, chip);
-+
-+ return rg;
-+}
-+
-+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
-+{
-+ iowrite32(val, rg->membase + rg->regs[reg]);
-+}
-+
-+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
-+{
-+ return ioread32(rg->membase + rg->regs[reg]);
-+}
-+
-+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
-+}
-+
-+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
-+}
-+
-+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
-+ t &= ~BIT(offset);
-+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int ralink_gpio_direction_output(struct gpio_chip *chip,
-+ unsigned offset, int value)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ ralink_gpio_set(chip, offset, value);
-+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
-+ t |= BIT(offset);
-+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ if (rg->irq < 1)
-+ return -1;
-+
-+ return irq_create_mapping(rg->domain, pin);
-+}
-+
-+static void ralink_gpio_irq_handler(struct irq_desc *desc)
-+{
-+ int i;
-+
-+ for (i = 0; i < irq_map_count; i++) {
-+ struct irq_domain *domain = irq_map[i];
-+ struct ralink_gpio_chip *rg;
-+ unsigned long pending;
-+ int bit;
-+
-+ rg = (struct ralink_gpio_chip *) domain->host_data;
-+ pending = rt_gpio_r32(rg, GPIO_REG_INT);
-+
-+ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
-+ u32 map = irq_find_mapping(domain, bit);
-+ generic_handle_irq(map);
-+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
-+ }
-+ }
-+}
-+
-+static void ralink_gpio_irq_unmask(struct irq_data *d)
-+{
-+ struct ralink_gpio_chip *rg;
-+ unsigned long flags;
-+ u32 rise, fall;
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
-+ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
-+ rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static void ralink_gpio_irq_mask(struct irq_data *d)
-+{
-+ struct ralink_gpio_chip *rg;
-+ unsigned long flags;
-+ u32 rise, fall;
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
-+ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
-+ rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
-+{
-+ struct ralink_gpio_chip *rg;
-+ u32 mask = BIT(d->hwirq);
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+
-+ if (type == IRQ_TYPE_PROBE) {
-+ if ((rg->rising | rg->falling) & mask)
-+ return 0;
-+
-+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-+ }
-+
-+ if (type & IRQ_TYPE_EDGE_RISING)
-+ rg->rising |= mask;
-+ else
-+ rg->rising &= ~mask;
-+
-+ if (type & IRQ_TYPE_EDGE_FALLING)
-+ rg->falling |= mask;
-+ else
-+ rg->falling &= ~mask;
-+
-+ return 0;
-+}
-+
-+static struct irq_chip ralink_gpio_irq_chip = {
-+ .name = "GPIO",
-+ .irq_unmask = ralink_gpio_irq_unmask,
-+ .irq_mask = ralink_gpio_irq_mask,
-+ .irq_mask_ack = ralink_gpio_irq_mask,
-+ .irq_set_type = ralink_gpio_irq_type,
-+};
-+
-+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
-+ irq_set_handler_data(irq, d);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = gpio_map,
-+};
-+
-+static void ralink_gpio_irq_init(struct device_node *np,
-+ struct ralink_gpio_chip *rg)
-+{
-+ if (irq_map_count >= MAP_MAX)
-+ return;
-+
-+ rg->irq = irq_of_parse_and_map(np, 0);
-+ if (!rg->irq)
-+ return;
-+
-+ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
-+ &irq_domain_ops, rg);
-+ if (!rg->domain) {
-+ dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
-+ return;
-+ }
-+
-+ irq_map[irq_map_count++] = rg->domain;
-+
-+ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
-+ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
-+
-+ if (!atomic_read(&irq_refcount))
-+ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
-+ atomic_inc(&irq_refcount);
-+
-+ dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
-+}
-+
-+static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
-+{
-+ int gpio = chip->base + offset;
-+
-+ return pinctrl_request_gpio(gpio);
-+}
-+
-+static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset)
-+{
-+ int gpio = chip->base + offset;
-+
-+ pinctrl_free_gpio(gpio);
-+}
-+
-+static int ralink_gpio_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ struct ralink_gpio_chip *rg;
-+ const __be32 *ngpio, *gpiobase;
-+
-+ if (!res) {
-+ dev_err(&pdev->dev, "failed to find resource\n");
-+ return -ENOMEM;
-+ }
-+
-+ rg = devm_kzalloc(&pdev->dev,
-+ sizeof(struct ralink_gpio_chip), GFP_KERNEL);
-+ if (!rg)
-+ return -ENOMEM;
-+
-+ rg->membase = devm_ioremap_resource(&pdev->dev, res);
-+ if (!rg->membase) {
-+ dev_err(&pdev->dev, "cannot remap I/O memory region\n");
-+ return -ENOMEM;
-+ }
-+
-+ if (of_property_read_u8_array(np, "ralink,register-map",
-+ rg->regs, GPIO_REG_MAX)) {
-+ dev_err(&pdev->dev, "failed to read register definition\n");
-+ return -EINVAL;
-+ }
-+
-+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
-+ if (!ngpio) {
-+ dev_err(&pdev->dev, "failed to read number of pins\n");
-+ return -EINVAL;
-+ }
-+
-+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
-+ if (gpiobase)
-+ rg->chip.base = be32_to_cpu(*gpiobase);
-+ else
-+ rg->chip.base = -1;
-+
-+ spin_lock_init(&rg->lock);
-+
-+ rg->chip.dev = &pdev->dev;
-+ rg->chip.label = dev_name(&pdev->dev);
-+ rg->chip.of_node = np;
-+ rg->chip.ngpio = be32_to_cpu(*ngpio);
-+ rg->chip.direction_input = ralink_gpio_direction_input;
-+ rg->chip.direction_output = ralink_gpio_direction_output;
-+ rg->chip.get = ralink_gpio_get;
-+ rg->chip.set = ralink_gpio_set;
-+ rg->chip.request = ralink_gpio_request;
-+ rg->chip.to_irq = ralink_gpio_to_irq;
-+ rg->chip.free = ralink_gpio_free;
-+
-+ /* set polarity to low for all lines */
-+ rt_gpio_w32(rg, GPIO_REG_POL, 0);
-+
-+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
-+
-+ ralink_gpio_irq_init(np, rg);
-+
-+ return gpiochip_add(&rg->chip);
-+}
-+
-+static const struct of_device_id ralink_gpio_match[] = {
-+ { .compatible = "ralink,rt2880-gpio" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, ralink_gpio_match);
-+
-+static struct platform_driver ralink_gpio_driver = {
-+ .probe = ralink_gpio_probe,
-+ .driver = {
-+ .name = "rt2880_gpio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = ralink_gpio_match,
-+ },
-+};
-+
-+static int __init ralink_gpio_init(void)
-+{
-+ return platform_driver_register(&ralink_gpio_driver);
-+}
-+
-+subsys_initcall(ralink_gpio_init);
+++ /dev/null
-From 61ac7d9b4228de8c332900902c2b93189b042eab Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 11:00:32 +0100
-Subject: [PATCH 28/53] GPIO: ralink: add mt7621 gpio controller
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/Kconfig | 3 +
- drivers/gpio/Kconfig | 6 +
- drivers/gpio/Makefile | 1 +
- drivers/gpio/gpio-mt7621.c | 354 ++++++++++++++++++++++++++++++++++++++++++++
- 4 files changed, 364 insertions(+)
- create mode 100644 drivers/gpio/gpio-mt7621.c
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -559,6 +559,9 @@ config RALINK
- select RESET_CONTROLLER
- select PINCTRL
- select PINCTRL_RT2880
-+ select ARCH_HAS_RESET_CONTROLLER
-+ select RESET_CONTROLLER
-+ select ARCH_REQUIRE_GPIOLIB
-
- config SGI_IP22
- bool "SGI IP22 (Indy/Indigo2)"
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -269,6 +269,12 @@ config GPIO_MB86S7X
- help
- Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs.
-
-+config GPIO_MT7621
-+ bool "Mediatek GPIO Support"
-+ depends on SOC_MT7620 || SOC_MT7621
-+ help
-+ Say yes here to support the Mediatek SoC GPIO device
-+
- config GPIO_MM_LANTIQ
- bool "Lantiq Memory mapped GPIOs"
- depends on LANTIQ && SOC_XWAY
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -119,3 +119,4 @@ obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa
- obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
- obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
- obj-$(CONFIG_GPIO_ZX) += gpio-zx.o
-+obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
---- /dev/null
-+++ b/drivers/gpio/gpio-mt7621.c
-@@ -0,0 +1,354 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/io.h>
-+#include <linux/err.h>
-+#include <linux/gpio.h>
-+#include <linux/module.h>
-+#include <linux/of_irq.h>
-+#include <linux/spinlock.h>
-+#include <linux/irqdomain.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+
-+#define MTK_MAX_BANK 3
-+#define MTK_BANK_WIDTH 32
-+
-+enum mediatek_gpio_reg {
-+ GPIO_REG_CTRL = 0,
-+ GPIO_REG_POL,
-+ GPIO_REG_DATA,
-+ GPIO_REG_DSET,
-+ GPIO_REG_DCLR,
-+ GPIO_REG_REDGE,
-+ GPIO_REG_FEDGE,
-+ GPIO_REG_HLVL,
-+ GPIO_REG_LLVL,
-+ GPIO_REG_STAT,
-+ GPIO_REG_EDGE,
-+};
-+
-+static void __iomem *mediatek_gpio_membase;
-+static int mediatek_gpio_irq;
-+static struct irq_domain *mediatek_gpio_irq_domain;
-+static atomic_t irq_refcount = ATOMIC_INIT(0);
-+
-+struct mtk_gc {
-+ struct gpio_chip chip;
-+ spinlock_t lock;
-+ int bank;
-+ u32 rising;
-+ u32 falling;
-+} *gc_map[MTK_MAX_BANK];
-+
-+static inline struct mtk_gc
-+*to_mediatek_gpio(struct gpio_chip *chip)
-+{
-+ struct mtk_gc *mgc;
-+
-+ mgc = container_of(chip, struct mtk_gc, chip);
-+
-+ return mgc;
-+}
-+
-+static inline void
-+mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
-+{
-+ iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
-+}
-+
-+static inline u32
-+mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
-+{
-+ return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
-+}
-+
-+static void
-+mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+
-+ mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
-+}
-+
-+static int
-+mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+
-+ return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
-+}
-+
-+static int
-+mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
-+ t &= ~BIT(offset);
-+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int
-+mediatek_gpio_direction_output(struct gpio_chip *chip,
-+ unsigned offset, int value)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
-+ t |= BIT(offset);
-+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
-+ mediatek_gpio_set(chip, offset, value);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int
-+mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ if (t & BIT(offset))
-+ return 0;
-+
-+ return 1;
-+}
-+
-+static int
-+mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct mtk_gc *rg = to_mediatek_gpio(chip);
-+
-+ return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH));
-+}
-+
-+static int
-+mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
-+{
-+ const __be32 *id = of_get_property(bank, "reg", NULL);
-+ struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
-+ sizeof(struct mtk_gc), GFP_KERNEL);
-+
-+ if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK)
-+ return -ENOMEM;
-+
-+ gc_map[be32_to_cpu(*id)] = rg;
-+
-+ memset(rg, 0, sizeof(struct mtk_gc));
-+
-+ spin_lock_init(&rg->lock);
-+
-+ rg->chip.dev = &pdev->dev;
-+ rg->chip.label = dev_name(&pdev->dev);
-+ rg->chip.of_node = bank;
-+ rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
-+ rg->chip.ngpio = MTK_BANK_WIDTH;
-+ rg->chip.direction_input = mediatek_gpio_direction_input;
-+ rg->chip.direction_output = mediatek_gpio_direction_output;
-+ rg->chip.get_direction = mediatek_gpio_get_direction;
-+ rg->chip.get = mediatek_gpio_get;
-+ rg->chip.set = mediatek_gpio_set;
-+ if (mediatek_gpio_irq_domain)
-+ rg->chip.to_irq = mediatek_gpio_to_irq;
-+ rg->bank = be32_to_cpu(*id);
-+
-+ /* set polarity to low for all gpios */
-+ mtk_gpio_w32(rg, GPIO_REG_POL, 0);
-+
-+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
-+
-+ return gpiochip_add(&rg->chip);
-+}
-+
-+static void
-+mediatek_gpio_irq_handler(struct irq_desc *desc)
-+{
-+ int i;
-+
-+ for (i = 0; i < MTK_MAX_BANK; i++) {
-+ struct mtk_gc *rg = gc_map[i];
-+ unsigned long pending;
-+ int bit;
-+
-+ if (!rg)
-+ continue;
-+
-+ pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
-+
-+ for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
-+ u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit);
-+
-+ generic_handle_irq(map);
-+ mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
-+ }
-+ }
-+}
-+
-+static void
-+mediatek_gpio_irq_unmask(struct irq_data *d)
-+{
-+ int pin = d->hwirq;
-+ int bank = pin / 32;
-+ struct mtk_gc *rg = gc_map[bank];
-+ unsigned long flags;
-+ u32 rise, fall;
-+
-+ if (!rg)
-+ return;
-+
-+ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
-+ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising));
-+ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static void
-+mediatek_gpio_irq_mask(struct irq_data *d)
-+{
-+ int pin = d->hwirq;
-+ int bank = pin / 32;
-+ struct mtk_gc *rg = gc_map[bank];
-+ unsigned long flags;
-+ u32 rise, fall;
-+
-+ if (!rg)
-+ return;
-+
-+ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
-+ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq));
-+ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static int
-+mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
-+{
-+ int pin = d->hwirq;
-+ int bank = pin / 32;
-+ struct mtk_gc *rg = gc_map[bank];
-+ u32 mask = BIT(d->hwirq);
-+
-+ if (!rg)
-+ return -1;
-+
-+ if (type == IRQ_TYPE_PROBE) {
-+ if ((rg->rising | rg->falling) & mask)
-+ return 0;
-+
-+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-+ }
-+
-+ if (type & IRQ_TYPE_EDGE_RISING)
-+ rg->rising |= mask;
-+ else
-+ rg->rising &= ~mask;
-+
-+ if (type & IRQ_TYPE_EDGE_FALLING)
-+ rg->falling |= mask;
-+ else
-+ rg->falling &= ~mask;
-+
-+ return 0;
-+}
-+
-+static struct irq_chip mediatek_gpio_irq_chip = {
-+ .name = "GPIO",
-+ .irq_unmask = mediatek_gpio_irq_unmask,
-+ .irq_mask = mediatek_gpio_irq_mask,
-+ .irq_mask_ack = mediatek_gpio_irq_mask,
-+ .irq_set_type = mediatek_gpio_irq_type,
-+};
-+
-+static int
-+mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq);
-+ irq_set_handler_data(irq, d);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = mediatek_gpio_gpio_map,
-+};
-+
-+static int
-+mediatek_gpio_probe(struct platform_device *pdev)
-+{
-+ struct device_node *bank, *np = pdev->dev.of_node;
-+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+ mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(mediatek_gpio_membase))
-+ return PTR_ERR(mediatek_gpio_membase);
-+
-+ mediatek_gpio_irq = irq_of_parse_and_map(np, 0);
-+ if (mediatek_gpio_irq) {
-+ mediatek_gpio_irq_domain = irq_domain_add_linear(np,
-+ MTK_MAX_BANK * MTK_BANK_WIDTH,
-+ &irq_domain_ops, NULL);
-+ if (!mediatek_gpio_irq_domain)
-+ dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
-+ }
-+
-+ for_each_child_of_node(np, bank)
-+ if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
-+ mediatek_gpio_bank_probe(pdev, bank);
-+
-+ if (mediatek_gpio_irq_domain)
-+ irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mediatek_gpio_match[] = {
-+ { .compatible = "mtk,mt7621-gpio" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
-+
-+static struct platform_driver mediatek_gpio_driver = {
-+ .probe = mediatek_gpio_probe,
-+ .driver = {
-+ .name = "mt7621_gpio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mediatek_gpio_match,
-+ },
-+};
-+
-+static int __init
-+mediatek_gpio_init(void)
-+{
-+ return platform_driver_register(&mediatek_gpio_driver);
-+}
-+
-+subsys_initcall(mediatek_gpio_init);
+++ /dev/null
-From b00b5eafa7e8d059bd0ce844e66f648916953270 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 3 Jan 2016 19:11:22 +0100
-Subject: [PATCH 2/3] phy: ralink-usb: add driver for Mediatek/Ralink
-
-Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
-The driver is trivial and only sets up power and host mode.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../devicetree/bindings/phy/ralink-usb-phy.txt | 17 ++
- drivers/phy/Kconfig | 8 +
- drivers/phy/Makefile | 1 +
- drivers/phy/phy-ralink-usb.c | 171 ++++++++++++++++++++
- 4 files changed, 197 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
- create mode 100644 drivers/phy/phy-ralink-usb.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
-@@ -0,0 +1,17 @@
-+Mediatek/Ralink USB PHY
-+
-+Required properties:
-+ - compatible: ralink,rt3352-usbphy or mediatek,mt7620-usbphy
-+ - #phy-cells: should be 0
-+ - resets: the two reset controllers for host and device
-+ - reset-names: the names of the 2 reset controllers
-+
-+Example:
-+
-+usbphy: phy {
-+ compatible = "mediatek,mt7620-usbphy";
-+ #phy-cells = <0>;
-+
-+ resets = <&rstctrl 22 &rstctrl 25>;
-+ reset-names = "host", "device";
-+};
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -331,6 +331,14 @@
- help
- This option enables support for APM X-Gene SoC multi-purpose PHY.
-
-+config PHY_RALINK_USB
-+ tristate "Ralink USB PHY driver"
-+ select GENERIC_PHY
-+ depends on RALINK
-+ help
-+ This option enables support for the Ralink USB PHY found inside
-+ RT3352 and MT7620.
-+
- config PHY_STIH407_USB
- tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
- depends on RESET_CONTROLLER
---- a/drivers/phy/Makefile
-+++ b/drivers/phy/Makefile
-@@ -46,3 +46,4 @@
- obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
- obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
- obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
-+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
---- /dev/null
-+++ b/drivers/phy/phy-ralink-usb.c
-@@ -0,0 +1,228 @@
-+/*
-+ * Allwinner ralink USB phy driver
-+ *
-+ * Copyright (C) 2016 John Crispin <blogic@openwrt.org>
-+ *
-+ * Based on code from
-+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+#include <linux/of_platform.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define RT_SYSC_REG_SYSCFG1 0x014
-+#define RT_SYSC_REG_CLKCFG1 0x030
-+#define RT_SYSC_REG_USB_PHY_CFG 0x05c
-+
-+#define OFS_U2_PHY_AC0 0x00
-+#define OFS_U2_PHY_AC1 0x04
-+#define OFS_U2_PHY_AC2 0x08
-+#define OFS_U2_PHY_ACR0 0x10
-+#define OFS_U2_PHY_ACR1 0x14
-+#define OFS_U2_PHY_ACR2 0x18
-+#define OFS_U2_PHY_ACR3 0x1C
-+#define OFS_U2_PHY_ACR4 0x20
-+#define OFS_U2_PHY_AMON0 0x24
-+#define OFS_U2_PHY_DCR0 0x60
-+#define OFS_U2_PHY_DCR1 0x64
-+#define OFS_U2_PHY_DTM0 0x68
-+#define OFS_U2_PHY_DTM1 0x6C
-+
-+#define RT_RSTCTRL_UDEV BIT(25)
-+#define RT_RSTCTRL_UHST BIT(22)
-+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
-+
-+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
-+#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
-+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
-+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
-+
-+#define USB_PHY_UTMI_8B60M BIT(1)
-+#define UDEV_WAKEUP BIT(0)
-+
-+struct ralink_usb_phy {
-+ struct reset_control *rstdev;
-+ struct reset_control *rsthost;
-+ u32 clk;
-+ struct phy *phy;
-+ void __iomem *base;
-+};
-+
-+static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
-+{
-+ iowrite32(val, phy->base + reg);
-+}
-+
-+static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
-+{
-+ return ioread32(phy->base + reg);
-+}
-+
-+static void
-+u2_phy_init(struct ralink_usb_phy *phy)
-+{
-+ u2_phy_r32(phy, OFS_U2_PHY_AC2);
-+ u2_phy_r32(phy, OFS_U2_PHY_ACR0);
-+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
-+
-+ u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
-+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
-+ u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
-+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
-+ u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
-+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
-+ u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
-+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
-+ u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
-+ u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
-+ u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
-+ u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
-+}
-+
-+static int ralink_usb_phy_power_on(struct phy *_phy)
-+{
-+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
-+ u32 t;
-+
-+ /* enable the phy */
-+ rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
-+
-+ /* setup host mode */
-+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
-+
-+ /* deassert the reset lines */
-+ reset_control_deassert(phy->rsthost);
-+ reset_control_deassert(phy->rstdev);
-+
-+ /*
-+ * The SDK kernel had a delay of 100ms. however on device
-+ * testing showed that 10ms is enough
-+ */
-+ mdelay(10);
-+
-+ if (!IS_ERR(phy->base))
-+ u2_phy_init(phy);
-+
-+ /* print some status info */
-+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
-+ dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
-+ (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
-+ if (t & USB_PHY_UTMI_8B60M)
-+ dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
-+ else
-+ dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
-+
-+ return 0;
-+}
-+
-+static int ralink_usb_phy_power_off(struct phy *_phy)
-+{
-+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
-+
-+ /* assert the reset lines */
-+ reset_control_assert(phy->rstdev);
-+ reset_control_assert(phy->rsthost);
-+
-+ /* disable the phy */
-+ rt_sysc_m32(phy->clk, 0, RT_SYSC_REG_CLKCFG1);
-+
-+ return 0;
-+}
-+
-+static struct phy_ops ralink_usb_phy_ops = {
-+ .power_on = ralink_usb_phy_power_on,
-+ .power_off = ralink_usb_phy_power_off,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct of_device_id ralink_usb_phy_of_match[] = {
-+ {
-+ .compatible = "ralink,rt3352-usbphy",
-+ .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
-+ RT_CLKCFG1_UPHY0_CLK_EN)
-+ },
-+ {
-+ .compatible = "mediatek,mt7620-usbphy",
-+ .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
-+ MT7620_CLKCFG1_UPHY0_CLK_EN) },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
-+
-+static int ralink_usb_phy_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ struct device *dev = &pdev->dev;
-+ struct phy_provider *phy_provider;
-+ const struct of_device_id *match;
-+ struct ralink_usb_phy *phy;
-+
-+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
-+ if (!phy)
-+ return -ENOMEM;
-+
-+ match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
-+ if (!match)
-+ return -ENODEV;
-+
-+ phy->clk = (int) match->data;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ phy->base = devm_ioremap_resource(&pdev->dev, res);
-+
-+ phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
-+ if (IS_ERR(phy->rsthost)) {
-+ dev_err(dev, "host reset is missing\n");
-+ return PTR_ERR(phy->rsthost);
-+ }
-+
-+ phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
-+ if (IS_ERR(phy->rstdev)) {
-+ dev_err(dev, "device reset is missing\n");
-+ return PTR_ERR(phy->rstdev);
-+ }
-+
-+ phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
-+ if (IS_ERR(phy->phy)) {
-+ dev_err(dev, "failed to create PHY\n");
-+ return PTR_ERR(phy->phy);
-+ }
-+ phy_set_drvdata(phy->phy, phy);
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+}
-+
-+static struct platform_driver ralink_usb_phy_driver = {
-+ .probe = ralink_usb_phy_probe,
-+ .driver = {
-+ .of_match_table = ralink_usb_phy_of_match,
-+ .name = "ralink-usb-phy",
-+ }
-+};
-+module_platform_driver(ralink_usb_phy_driver);
-+
-+MODULE_DESCRIPTION("Ralink USB phy driver");
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 19 Sep 2013 01:50:59 +0200
-Subject: [PATCH 31/53] uvc: add iPassion iP2970 support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/media/usb/uvc/uvc_driver.c | 12 +++
- drivers/media/usb/uvc/uvc_status.c | 2 +
- drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++
- drivers/media/usb/uvc/uvcvideo.h | 5 +-
- 4 files changed, 165 insertions(+), 1 deletion(-)
-
---- a/drivers/media/usb/uvc/uvc_driver.c
-+++ b/drivers/media/usb/uvc/uvc_driver.c
-@@ -2536,6 +2536,18 @@ static struct usb_device_id uvc_ids[] =
- .bInterfaceSubClass = 1,
- .bInterfaceProtocol = 0,
- .driver_info = UVC_QUIRK_FORCE_Y8 },
-+ /* iPassion iP2970 */
-+ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE
-+ | USB_DEVICE_ID_MATCH_INT_INFO,
-+ .idVendor = 0x1B3B,
-+ .idProduct = 0x2970,
-+ .bInterfaceClass = USB_CLASS_VIDEO,
-+ .bInterfaceSubClass = 1,
-+ .bInterfaceProtocol = 0,
-+ .driver_info = UVC_QUIRK_PROBE_MINMAX
-+ | UVC_QUIRK_STREAM_NO_FID
-+ | UVC_QUIRK_MOTION
-+ | UVC_QUIRK_SINGLE_ISO },
- /* Generic USB Video Class */
- { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) },
- {}
---- a/drivers/media/usb/uvc/uvc_status.c
-+++ b/drivers/media/usb/uvc/uvc_status.c
-@@ -139,6 +139,7 @@ static void uvc_status_complete(struct u
- switch (dev->status[0] & 0x0f) {
- case UVC_STATUS_TYPE_CONTROL:
- uvc_event_control(dev, dev->status, len);
-+ dev->motion = 1;
- break;
-
- case UVC_STATUS_TYPE_STREAMING:
-@@ -182,6 +183,7 @@ int uvc_status_init(struct uvc_device *d
- }
-
- pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
-+ dev->motion = 0;
-
- /* For high-speed interrupt endpoints, the bInterval value is used as
- * an exponent of two. Some developers forgot about it.
---- a/drivers/media/usb/uvc/uvc_video.c
-+++ b/drivers/media/usb/uvc/uvc_video.c
-@@ -21,6 +21,11 @@
- #include <linux/wait.h>
- #include <linux/atomic.h>
- #include <asm/unaligned.h>
-+#include <linux/skbuff.h>
-+#include <linux/kobject.h>
-+#include <linux/netlink.h>
-+#include <linux/kobject.h>
-+#include <linux/workqueue.h>
-
- #include <media/v4l2-common.h>
-
-@@ -1089,9 +1094,149 @@ static void uvc_video_decode_data(struct
- }
- }
-
-+struct bh_priv {
-+ unsigned long seen;
-+};
-+
-+struct bh_event {
-+ const char *name;
-+ struct sk_buff *skb;
-+ struct work_struct work;
-+};
-+
-+#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args )
-+#define BH_DBG(fmt, args...) do {} while (0)
-+#define BH_SKB_SIZE 2048
-+
-+extern u64 uevent_next_seqnum(void);
-+static int seen = 0;
-+
-+static int bh_event_add_var(struct bh_event *event, int argv,
-+ const char *format, ...)
-+{
-+ static char buf[128];
-+ char *s;
-+ va_list args;
-+ int len;
-+
-+ if (argv)
-+ return 0;
-+
-+ va_start(args, format);
-+ len = vsnprintf(buf, sizeof(buf), format, args);
-+ va_end(args);
-+
-+ if (len >= sizeof(buf)) {
-+ BH_ERR("buffer size too small\n");
-+ WARN_ON(1);
-+ return -ENOMEM;
-+ }
-+
-+ s = skb_put(event->skb, len + 1);
-+ strcpy(s, buf);
-+
-+ BH_DBG("added variable '%s'\n", s);
-+
-+ return 0;
-+}
-+
-+static int motion_hotplug_fill_event(struct bh_event *event)
-+{
-+ int s = jiffies;
-+ int ret;
-+
-+ if (!seen)
-+ seen = jiffies;
-+
-+ ret = bh_event_add_var(event, 0, "HOME=%s", "/");
-+ if (ret)
-+ return ret;
-+
-+ ret = bh_event_add_var(event, 0, "PATH=%s",
-+ "/sbin:/bin:/usr/sbin:/usr/bin");
-+ if (ret)
-+ return ret;
-+
-+ ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb");
-+ if (ret)
-+ return ret;
-+
-+ ret = bh_event_add_var(event, 0, "ACTION=motion");
-+ if (ret)
-+ return ret;
-+
-+ ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen);
-+ if (ret)
-+ return ret;
-+ seen = s;
-+
-+ ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum());
-+
-+ return ret;
-+}
-+
-+static void motion_hotplug_work(struct work_struct *work)
-+{
-+ struct bh_event *event = container_of(work, struct bh_event, work);
-+ int ret = 0;
-+
-+ event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);
-+ if (!event->skb)
-+ goto out_free_event;
-+
-+ ret = bh_event_add_var(event, 0, "%s@", "add");
-+ if (ret)
-+ goto out_free_skb;
-+
-+ ret = motion_hotplug_fill_event(event);
-+ if (ret)
-+ goto out_free_skb;
-+
-+ NETLINK_CB(event->skb).dst_group = 1;
-+ broadcast_uevent(event->skb, 0, 1, GFP_KERNEL);
-+
-+out_free_skb:
-+ if (ret) {
-+ BH_ERR("work error %d\n", ret);
-+ kfree_skb(event->skb);
-+ }
-+out_free_event:
-+ kfree(event);
-+}
-+
-+static int motion_hotplug_create_event(void)
-+{
-+ struct bh_event *event;
-+
-+ event = kzalloc(sizeof(*event), GFP_KERNEL);
-+ if (!event)
-+ return -ENOMEM;
-+
-+ event->name = "motion";
-+
-+ INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work);
-+ schedule_work(&event->work);
-+
-+ return 0;
-+}
-+
-+#define MOTION_FLAG_OFFSET 4
- static void uvc_video_decode_end(struct uvc_streaming *stream,
- struct uvc_buffer *buf, const __u8 *data, int len)
- {
-+ if ((stream->dev->quirks & UVC_QUIRK_MOTION) &&
-+ (data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {
-+ u8 *mem;
-+ buf->state = UVC_BUF_STATE_READY;
-+ mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET);
-+ if ( stream->dev->motion ) {
-+ stream->dev->motion = 0;
-+ motion_hotplug_create_event();
-+ } else {
-+ *mem &= 0x7f;
-+ }
-+ }
-+
- /* Mark the buffer as done if the EOF marker is set. */
- if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
- uvc_trace(UVC_TRACE_FRAME, "Frame complete (EOF found).\n");
-@@ -1504,6 +1649,8 @@ static int uvc_init_video_isoc(struct uv
- if (npackets == 0)
- return -ENOMEM;
-
-+ if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO)
-+ npackets = 1;
- size = npackets * psize;
-
- for (i = 0; i < UVC_URBS; ++i) {
---- a/drivers/media/usb/uvc/uvcvideo.h
-+++ b/drivers/media/usb/uvc/uvcvideo.h
-@@ -152,7 +152,9 @@
- #define UVC_QUIRK_RESTRICT_FRAME_RATE 0x00000200
- #define UVC_QUIRK_RESTORE_CTRLS_ON_INIT 0x00000400
- #define UVC_QUIRK_FORCE_Y8 0x00000800
--
-+#define UVC_QUIRK_MOTION 0x00001000
-+#define UVC_QUIRK_SINGLE_ISO 0x00002000
-+
- /* Format flags */
- #define UVC_FMT_FLAG_COMPRESSED 0x00000001
- #define UVC_FMT_FLAG_STREAM 0x00000002
-@@ -550,6 +552,7 @@ struct uvc_device {
- __u8 *status;
- struct input_dev *input;
- char input_phys[64];
-+ int motion;
- };
-
- enum uvc_handle_state {
+++ /dev/null
-From a758e0870c6d1e4b0272f6e7f9efa9face5534bb Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:49:07 +0100
-Subject: [PATCH 32/53] USB: dwc2: add device_reset()
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/usb/dwc2/hcd.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/usb/dwc2/hcd.c
-+++ b/drivers/usb/dwc2/hcd.c
-@@ -47,6 +47,7 @@
- #include <linux/io.h>
- #include <linux/slab.h>
- #include <linux/usb.h>
-+#include <linux/reset.h>
-
- #include <linux/usb/hcd.h>
- #include <linux/usb/ch11.h>
-@@ -2841,6 +2842,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
-
- retval = -ENOMEM;
-
-+ device_reset(hsotg->dev);
-+
- hcfg = readl(hsotg->regs + HCFG);
- dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
-
+++ /dev/null
-From 71fbde37e60c11f5a715c105d25b9c6cee8dae6c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:14:03 +0100
-Subject: [PATCH 33/53] USB: add xhci hooks
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/usb/core/hcd-pci.c | 5 +
- drivers/usb/core/hub.c | 2 +-
- drivers/usb/core/port.c | 10 +-
- drivers/usb/host/Kconfig | 9 +-
- drivers/usb/host/Makefile | 10 +-
- drivers/usb/host/mtk-phy-7621.c | 445 +++++
- drivers/usb/host/mtk-phy-7621.h | 2871 +++++++++++++++++++++++++++++++++
- drivers/usb/host/mtk-phy-ahb.c | 58 +
- drivers/usb/host/mtk-phy.c | 102 ++
- drivers/usb/host/mtk-phy.h | 179 ++
- drivers/usb/host/pci-quirks.h | 2 +-
- drivers/usb/host/xhci-dbg.c | 3 +
- drivers/usb/host/xhci-mem.c | 11 +
- drivers/usb/host/xhci-mtk-power.c | 115 ++
- drivers/usb/host/xhci-mtk-power.h | 13 +
- drivers/usb/host/xhci-mtk-scheduler.c | 608 +++++++
- drivers/usb/host/xhci-mtk-scheduler.h | 77 +
- drivers/usb/host/xhci-mtk.c | 265 +++
- drivers/usb/host/xhci-mtk.h | 120 ++
- drivers/usb/host/xhci-plat.c | 11 +
- drivers/usb/host/xhci-ring.c | 104 ++
- drivers/usb/host/xhci.c | 209 ++-
- drivers/usb/host/xhci.h | 39 +
- 23 files changed, 5257 insertions(+), 11 deletions(-)
- create mode 100644 drivers/usb/host/mtk-phy-7621.c
- create mode 100644 drivers/usb/host/mtk-phy-7621.h
- create mode 100644 drivers/usb/host/mtk-phy-ahb.c
- create mode 100644 drivers/usb/host/mtk-phy.c
- create mode 100644 drivers/usb/host/mtk-phy.h
- create mode 100644 drivers/usb/host/xhci-mtk-power.c
- create mode 100644 drivers/usb/host/xhci-mtk-power.h
- create mode 100644 drivers/usb/host/xhci-mtk-scheduler.c
- create mode 100644 drivers/usb/host/xhci-mtk-scheduler.h
- create mode 100644 drivers/usb/host/xhci-mtk.c
- create mode 100644 drivers/usb/host/xhci-mtk.h
-
---- a/drivers/usb/core/hcd-pci.c
-+++ b/drivers/usb/core/hcd-pci.c
-@@ -214,8 +214,13 @@ int usb_hcd_pci_probe(struct pci_dev *de
- goto disable_pci;
- }
-
-+
-+#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
-+ hcd->amd_resume_bug = 0;
-+#else
- hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
- driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
-+#endif
-
- if (driver->flags & HCD_MEMORY) {
- /* EHCI, OHCI */
---- a/drivers/usb/core/hub.c
-+++ b/drivers/usb/core/hub.c
-@@ -1291,7 +1291,7 @@ static void hub_quiesce(struct usb_hub *
- if (type != HUB_SUSPEND) {
- /* Disconnect all the children */
- for (i = 0; i < hdev->maxchild; ++i) {
-- if (hub->ports[i]->child)
-+ if (hub->ports[i] && hub->ports[i]->child)
- usb_disconnect(&hub->ports[i]->child);
- }
- }
---- a/drivers/usb/core/port.c
-+++ b/drivers/usb/core/port.c
-@@ -480,8 +480,10 @@ void usb_hub_remove_port_device(struct u
- struct usb_port *port_dev = hub->ports[port1 - 1];
- struct usb_port *peer;
-
-- peer = port_dev->peer;
-- if (peer)
-- unlink_peers(port_dev, peer);
-- device_unregister(&port_dev->dev);
-+ if(port_dev) {
-+ peer = port_dev->peer;
-+ if (peer)
-+ unlink_peers(port_dev, peer);
-+ device_unregister(&port_dev->dev);
-+ }
- }
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -41,6 +41,13 @@ config USB_XHCI_PLATFORM
-
- If unsure, say N.
-
-+config USB_MT7621_XHCI_PLATFORM
-+ bool
-+ depends on USB_XHCI_PLATFORM
-+ depends on SOC_MT7621
-+ select USB_PHY
-+ default y
-+
- config USB_XHCI_MVEBU
- tristate "xHCI support for Marvell Armada 375/38x"
- select USB_XHCI_PLATFORM
-@@ -590,7 +597,7 @@ endif # USB_OHCI_HCD
-
- config USB_UHCI_HCD
- tristate "UHCI HCD (most Intel and VIA) support"
-- depends on PCI || USB_UHCI_SUPPORT_NON_PCI_HC
-+ depends on BROKEN && (PCI || USB_UHCI_SUPPORT_NON_PCI_HC)
- ---help---
- The Universal Host Controller Interface is a standard by Intel for
- accessing the USB hardware in the PC (which is also called the USB
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -14,7 +14,12 @@ xhci-hcd-y := xhci.o xhci-mem.o
- xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
- xhci-hcd-y += xhci-trace.o
-
-+ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
-+xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
-+endif
-+
- xhci-plat-hcd-y := xhci-plat.o
-+
- ifneq ($(CONFIG_USB_XHCI_MVEBU), )
- xhci-plat-hcd-y += xhci-mvebu.o
- endif
-@@ -24,11 +29,10 @@ endif
-
- obj-$(CONFIG_USB_WHCI_HCD) += whci/
-
--ifneq ($(CONFIG_USB), )
-+ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
- obj-$(CONFIG_PCI) += pci-quirks.o
-+ obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
- endif
--
--obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
- obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
-
- obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
---- /dev/null
-+++ b/drivers/usb/host/mtk-phy-7621.c
-@@ -0,0 +1,445 @@
-+#include "mtk-phy.h"
-+
-+#ifdef CONFIG_PROJECT_7621
-+#include "mtk-phy-7621.h"
-+
-+//not used on SoC
-+PHY_INT32 phy_init(struct u3phy_info *info){
-+ return PHY_TRUE;
-+}
-+
-+//not used on SoC
-+PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
-+ return PHY_TRUE;
-+}
-+
-+//--------------------------------------------------------
-+// Function : fgEyeScanHelper_CheckPtInRegion()
-+// Description : Check if the test point is in a rectangle region.
-+// If it is in the rectangle, also check if this point
-+// is on the multiple of deltaX and deltaY.
-+// Parameter : strucScanRegion * prEye - the region
-+// BYTE bX
-+// BYTE bY
-+// Return : BYTE - TRUE : This point needs to be tested
-+// FALSE: This point will be omitted
-+// Note : First check within the rectangle.
-+// Secondly, use modulous to check if the point will be tested.
-+//--------------------------------------------------------
-+static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
-+{
-+ PHY_INT8 fgValid = true;
-+
-+
-+ /// Be careful, the axis origin is on the TOP-LEFT corner.
-+ /// Therefore the top-left point has the minimum X and Y
-+ /// Botton-right point is the maximum X and Y
-+ if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
-+ && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
-+ {
-+ // With the region, now check whether or not the input test point is
-+ // on the multiples of X and Y
-+ // Do not have to worry about negative value, because we have already
-+ // check the input bX, and bY is within the region.
-+ if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
-+ || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
-+ {
-+ // if the division will have remainder, that means
-+ // the input test point is on the multiples of X and Y
-+ fgValid = false;
-+ }
-+ else
-+ {
-+ }
-+ }
-+ else
-+ {
-+
-+ fgValid = false;
-+ }
-+ return fgValid;
-+}
-+
-+//--------------------------------------------------------
-+// Function : EyeScanHelper_RunTest()
-+// Description : Enable the test, and wait til it is completed
-+// Parameter : None
-+// Return : None
-+// Note : None
-+//--------------------------------------------------------
-+static void EyeScanHelper_RunTest(struct u3phy_info *info)
-+{
-+ DRV_UDELAY(100);
-+ // Disable the test
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
-+ DRV_UDELAY(100);
-+ // Run the test
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
-+ DRV_UDELAY(100);
-+ // Wait til it's done
-+ //RGS_SSUSB_RX_EYE_CNT_RDY
-+ while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
-+ , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
-+}
-+
-+//--------------------------------------------------------
-+// Function : fgEyeScanHelper_CalNextPoint()
-+// Description : Calcualte the test point for the measurement
-+// Parameter : None
-+// Return : BOOL - TRUE : the next point is within the
-+// boundaryof HW limit
-+// FALSE: the next point is out of the HW limit
-+// Note : The next point is obtained by calculating
-+// from the bottom left of the region rectangle
-+// and then scanning up until it reaches the upper
-+// limit. At this time, the x will increment, and
-+// start scanning downwards until the y hits the
-+// zero.
-+//--------------------------------------------------------
-+static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
-+{
-+ if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
-+ || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
-+ )
-+ {
-+ /// Reaches the limit of Y axis
-+ /// Increment X
-+ _bXcurr++;
-+ _fgXChged = true;
-+ _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
-+
-+ if (_bXcurr > MAX_X)
-+ {
-+ return false;
-+ }
-+ }
-+ else
-+ {
-+ _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
-+ _fgXChged = false;
-+ }
-+ return PHY_TRUE;
-+}
-+
-+PHY_INT32 eyescan_init(struct u3phy_info *info){
-+ //initial PHY setting
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
-+ , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
-+ , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
-+ return PHY_TRUE;
-+}
-+
-+PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
-+ , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
-+ PHY_INT32 cOfst = 0;
-+ PHY_UINT8 bIdxX = 0;
-+ PHY_UINT8 bIdxY = 0;
-+ //PHY_INT8 bCnt = 0;
-+ PHY_UINT8 bIdxCycCnt = 0;
-+ PHY_INT8 fgValid;
-+ PHY_INT8 cX;
-+ PHY_INT8 cY;
-+ PHY_UINT8 bExtendCnt;
-+ PHY_INT8 isContinue;
-+ //PHY_INT8 isBreak;
-+ PHY_UINT32 wErr0 = 0, wErr1 = 0;
-+ //PHY_UINT32 temp;
-+
-+ PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-+ PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-+
-+ _rEye1.bX_tl = x_t1;
-+ _rEye1.bY_tl = y_t1;
-+ _rEye1.bX_br = x_br;
-+ _rEye1.bY_br = y_br;
-+ _rEye1.bDeltaX = delta_x;
-+ _rEye1.bDeltaY = delta_y;
-+
-+ _rEye2.bX_tl = x_t1;
-+ _rEye2.bY_tl = y_t1;
-+ _rEye2.bX_br = x_br;
-+ _rEye2.bY_br = y_br;
-+ _rEye2.bDeltaX = delta_x;
-+ _rEye2.bDeltaY = delta_y;
-+
-+ _rTestCycle.wEyeCnt = eye_cnt;
-+ _rTestCycle.bNumOfEyeCnt = num_cnt;
-+ _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
-+ _rTestCycle.bPICalEn = PI_cal_en;
-+
-+ _bXcurr = 0;
-+ _bYcurr = 0;
-+ _eScanDir = SCAN_DN;
-+ _fgXChged = false;
-+
-+ printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
-+ eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
-+ x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
-+
-+ //force SIGDET to OFF
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
-+ , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
-+
-+ // RX_TRI_DET_EN to Disable
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
-+ , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
-+
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
-+
-+
-+ if (PI_cal_en){
-+ // PI Calibration
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
-+
-+ DRV_UDELAY(20);
-+
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
-+ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
-+ _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
-+ , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
-+
-+ printk(KERN_ERR "PI result: %d\n", _bPIResult);
-+ }
-+ // Read Initial DAC
-+ // Set CYCLE
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
-+ ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
-+
-+ // Eye Monitor Feature
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
-+ , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
-+
-+ // Move X,Y to the top-left corner
-+ for (cOfst = 0; cOfst >= -64; cOfst--)
-+ {
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
-+ }
-+ for (cOfst = 0; cOfst < 64; cOfst++)
-+ {
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
-+ }
-+ //ClearErrorResult
-+ for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
-+ for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
-+ {
-+ for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
-+ pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
-+ pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
-+ }
-+ }
-+ }
-+ isContinue = true;
-+ while(isContinue){
-+ //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
-+ // The point is within the boundary, then let's check if it is within
-+ // the testing region.
-+ // The point is only test-able if one of the eye region
-+ // includes this point.
-+ fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
-+ || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
-+ // Translate bX and bY to 2's complement from where the origin was on the
-+ // top left corner.
-+ // 0x40 and 0x3F needs a bit of thinking!!!! >"<
-+ cX = (_bXcurr ^ 0x40);
-+ cY = (_bYcurr ^ 0x3F);
-+
-+ // Set X if necessary
-+ if (_fgXChged == true)
-+ {
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
-+ }
-+ // Set Y
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
-+
-+ /// Test this point!
-+ if (fgValid){
-+ for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
-+ {
-+ //run test
-+ EyeScanHelper_RunTest(info);
-+ }
-+ for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
-+ {
-+ EyeScanHelper_RunTest(info);
-+ wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
-+ , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
-+ wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
-+ , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
-+
-+ pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
-+ pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
-+
-+ //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
-+// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
-+// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
-+ }
-+ //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
-+ }
-+ else{
-+
-+ }
-+ if (fgEyeScanHelper_CalNextPoint() == false){
-+#if 0
-+ printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
-+ printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
-+#endif
-+ printk(KERN_ERR "end of eye scan\n");
-+ isContinue = false;
-+ }
-+ }
-+ printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
-+ , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
-+ , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
-+
-+ // Move X,Y to the top-left corner
-+ for (cOfst = 63; cOfst >= 0; cOfst--)
-+ {
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
-+ }
-+ for (cOfst = 63; cOfst >= 0; cOfst--)
-+ {
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
-+ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
-+ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
-+
-+ }
-+ printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
-+ , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
-+ , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
-+
-+ printk(KERN_ERR "PI result: %d\n", _bPIResult);
-+ printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
-+ printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
-+
-+ return PHY_TRUE;
-+}
-+
-+//not used on SoC
-+PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
-+ return PHY_TRUE;
-+}
-+
-+//not used on SoC
-+PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
-+ return PHY_TRUE;
-+}
-+
-+PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
-+ PHY_INT32 i=0;
-+ //PHY_INT32 j=0;
-+ //PHY_INT8 u1SrCalVal = 0;
-+ //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
-+ PHY_INT32 fgRet = 0;
-+ PHY_INT32 u4FmOut = 0;
-+ PHY_INT32 u4Tmp = 0;
-+ //PHY_INT32 temp;
-+
-+ // => RG_USB20_HSTX_SRCAL_EN = 1
-+ // enable HS TX SR calibration
-+ U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
-+ , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
-+ DRV_MSLEEP(1);
-+
-+ // => RG_FRCK_EN = 1
-+ // Enable free run clock
-+ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
-+ , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
-+
-+ // MT6290 HS signal quality patch
-+ // => RG_CYCLECNT = 400
-+ // Setting cyclecnt =400
-+ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
-+ , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
-+
-+ // => RG_FREQDET_EN = 1
-+ // Enable frequency meter
-+ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
-+ , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
-+
-+ // wait for FM detection done, set 10ms timeout
-+ for(i=0; i<10; i++){
-+ // => u4FmOut = USB_FM_OUT
-+ // read FM_OUT
-+ u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
-+ printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
-+
-+ // check if FM detection done
-+ if (u4FmOut != 0)
-+ {
-+ fgRet = 0;
-+ printk("FM detection done! loop = %d\n", i);
-+
-+ break;
-+ }
-+
-+ fgRet = 1;
-+ DRV_MSLEEP(1);
-+ }
-+ // => RG_FREQDET_EN = 0
-+ // disable frequency meter
-+ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
-+ , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
-+
-+ // => RG_FRCK_EN = 0
-+ // disable free run clock
-+ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
-+ , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
-+
-+ // => RG_USB20_HSTX_SRCAL_EN = 0
-+ // disable HS TX SR calibration
-+ U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
-+ , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
-+ DRV_MSLEEP(1);
-+
-+ if(u4FmOut == 0){
-+ U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
-+ , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
-+
-+ fgRet = 1;
-+ }
-+ else{
-+ // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
-+ u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
-+ printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
-+ U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
-+ , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
-+ }
-+ return fgRet;
-+}
-+
-+#endif
---- /dev/null
-+++ b/drivers/usb/host/mtk-phy-7621.h
-@@ -0,0 +1,2871 @@
-+#ifdef CONFIG_PROJECT_7621
-+#ifndef __MTK_PHY_7621_H
-+#define __MTK_PHY_7621_H
-+
-+#define U2_SR_COEF_7621 28
-+
-+///////////////////////////////////////////////////////////////////////////////
-+
-+struct u2phy_reg {
-+ //0x0
-+ PHY_LE32 u2phyac0;
-+ PHY_LE32 u2phyac1;
-+ PHY_LE32 u2phyac2;
-+ PHY_LE32 reserve0;
-+ //0x10
-+ PHY_LE32 u2phyacr0;
-+ PHY_LE32 u2phyacr1;
-+ PHY_LE32 u2phyacr2;
-+ PHY_LE32 u2phyacr3;
-+ //0x20
-+ PHY_LE32 u2phyacr4;
-+ PHY_LE32 u2phyamon0;
-+ PHY_LE32 reserve1[2];
-+ //0x30~0x50
-+ PHY_LE32 reserve2[12];
-+ //0x60
-+ PHY_LE32 u2phydcr0;
-+ PHY_LE32 u2phydcr1;
-+ PHY_LE32 u2phydtm0;
-+ PHY_LE32 u2phydtm1;
-+ //0x70
-+ PHY_LE32 u2phydmon0;
-+ PHY_LE32 u2phydmon1;
-+ PHY_LE32 u2phydmon2;
-+ PHY_LE32 u2phydmon3;
-+ //0x80
-+ PHY_LE32 u2phybc12c;
-+ PHY_LE32 u2phybc12c1;
-+ PHY_LE32 reserve3[2];
-+ //0x90~0xe0
-+ PHY_LE32 reserve4[24];
-+ //0xf0
-+ PHY_LE32 reserve6[3];
-+ PHY_LE32 regfcom;
-+};
-+
-+//U3D_U2PHYAC0
-+#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
-+#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
-+#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
-+#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
-+#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
-+#define RG_USB20_REF_EN (0x1<<15) //15:15
-+#define RG_USB20_INTR_EN (0x1<<14) //14:14
-+#define RG_USB20_BG_TRIM (0xf<<8) //11:8
-+#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
-+#define RG_USB20_BG_RASEL (0x3<<4) //5:4
-+#define RG_USB20_BGR_DIV (0x3<<2) //3:2
-+#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
-+#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
-+
-+//U3D_U2PHYAC1
-+#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
-+#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
-+#define RG_USB20_MPX_SEL (0xff<<16) //23:16
-+#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
-+#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
-+#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
-+#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
-+#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
-+#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
-+
-+//U3D_U2PHYAC2
-+#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
-+#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
-+#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
-+
-+//U3D_U2PHYACR0
-+#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
-+#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
-+#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
-+#define RG_USB20_LS_CR (0x7<<12) //14:12
-+#define RG_USB20_FS_CR (0x7<<8) //10:8
-+#define RG_USB20_LS_SR (0x7<<4) //6:4
-+#define RG_USB20_FS_SR (0x7<<0) //2:0
-+
-+//U3D_U2PHYACR1
-+#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
-+#define RG_USB20_SQD (0x3<<24) //25:24
-+#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
-+#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
-+#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
-+#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
-+#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
-+#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
-+#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
-+#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
-+#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
-+
-+//U3D_U2PHYACR2
-+#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
-+#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
-+#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
-+#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
-+#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
-+#define RG_USB20_DISCD (0x3<<20) //21:20
-+#define RG_USB20_DISCTH (0xf<<16) //19:16
-+#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
-+#define RG_USB20_SQCAL (0xf<<8) //11:8
-+#define RG_USB20_SQTH (0xf<<0) //3:0
-+
-+//U3D_U2PHYACR3
-+#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
-+#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
-+#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
-+#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
-+#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
-+#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
-+#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
-+#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
-+#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
-+#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
-+#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
-+#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
-+#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
-+#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
-+#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
-+#define RG_USB20_PHY_REV (0xff<<0) //7:0
-+
-+//U3D_U2PHYACR4
-+#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
-+#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
-+#define USB20_DP_100K_EN (0x1<<16) //16:16
-+#define USB20_GPIO_DM_I (0x1<<15) //15:15
-+#define USB20_GPIO_DP_I (0x1<<14) //14:14
-+#define USB20_GPIO_DM_OE (0x1<<13) //13:13
-+#define USB20_GPIO_DP_OE (0x1<<12) //12:12
-+#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
-+#define USB20_GPIO_MODE (0x1<<8) //8:8
-+#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
-+#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
-+#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
-+#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
-+
-+//U3D_U2PHYAMON0
-+#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
-+#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
-+
-+//U3D_U2PHYDCR0
-+#define RG_USB20_CDR_TST (0x3<<30) //31:30
-+#define RG_USB20_GATED_ENB (0x1<<29) //29:29
-+#define RG_USB20_TESTMODE (0x3<<26) //27:26
-+#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
-+#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
-+#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
-+#define RG_USB20_EBTHRLD (0x1<<7) //7:7
-+#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
-+#define RG_USB20_TX_TST (0x1<<5) //5:5
-+#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
-+#define RG_USB20_CDR_FILT (0xf<<0) //3:0
-+
-+//U3D_U2PHYDCR1
-+#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
-+#define RG_USB20_DRVVBUS (0x1<<23) //23:23
-+#define RG_DEBUG_EN (0x1<<22) //22:22
-+#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
-+#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
-+#define RG_USB20_BERTH (0x3<<16) //17:16
-+#define RG_USB20_LBMODE (0x3<<13) //14:13
-+#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
-+#define RG_USB20_TAPSEL (0xfff<<0) //11:0
-+
-+//U3D_U2PHYDTM0
-+#define RG_UART_MODE (0x3<<30) //31:30
-+#define FORCE_UART_I (0x1<<29) //29:29
-+#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
-+#define FORCE_UART_TX_OE (0x1<<27) //27:27
-+#define FORCE_UART_EN (0x1<<26) //26:26
-+#define FORCE_USB_CLKEN (0x1<<25) //25:25
-+#define FORCE_DRVVBUS (0x1<<24) //24:24
-+#define FORCE_DATAIN (0x1<<23) //23:23
-+#define FORCE_TXVALID (0x1<<22) //22:22
-+#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
-+#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
-+#define FORCE_XCVRSEL (0x1<<19) //19:19
-+#define FORCE_SUSPENDM (0x1<<18) //18:18
-+#define FORCE_TERMSEL (0x1<<17) //17:17
-+#define FORCE_OPMODE (0x1<<16) //16:16
-+#define UTMI_MUXSEL (0x1<<15) //15:15
-+#define RG_RESET (0x1<<14) //14:14
-+#define RG_DATAIN (0xf<<10) //13:10
-+#define RG_TXVALIDH (0x1<<9) //9:9
-+#define RG_TXVALID (0x1<<8) //8:8
-+#define RG_DMPULLDOWN (0x1<<7) //7:7
-+#define RG_DPPULLDOWN (0x1<<6) //6:6
-+#define RG_XCVRSEL (0x3<<4) //5:4
-+#define RG_SUSPENDM (0x1<<3) //3:3
-+#define RG_TERMSEL (0x1<<2) //2:2
-+#define RG_OPMODE (0x3<<0) //1:0
-+
-+//U3D_U2PHYDTM1
-+#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
-+#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
-+#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
-+#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
-+#define RG_UART_I (0x1<<19) //19:19
-+#define RG_UART_BIAS_EN (0x1<<18) //18:18
-+#define RG_UART_TX_OE (0x1<<17) //17:17
-+#define RG_UART_EN (0x1<<16) //16:16
-+#define FORCE_VBUSVALID (0x1<<13) //13:13
-+#define FORCE_SESSEND (0x1<<12) //12:12
-+#define FORCE_BVALID (0x1<<11) //11:11
-+#define FORCE_AVALID (0x1<<10) //10:10
-+#define FORCE_IDDIG (0x1<<9) //9:9
-+#define FORCE_IDPULLUP (0x1<<8) //8:8
-+#define RG_VBUSVALID (0x1<<5) //5:5
-+#define RG_SESSEND (0x1<<4) //4:4
-+#define RG_BVALID (0x1<<3) //3:3
-+#define RG_AVALID (0x1<<2) //2:2
-+#define RG_IDDIG (0x1<<1) //1:1
-+#define RG_IDPULLUP (0x1<<0) //0:0
-+
-+//U3D_U2PHYDMON0
-+#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
-+
-+//U3D_U2PHYDMON1
-+#define USB20_UART_O (0x1<<31) //31:31
-+#define RGO_USB20_LB_PASS (0x1<<30) //30:30
-+#define RGO_USB20_LB_DONE (0x1<<29) //29:29
-+#define AD_USB20_BVALID (0x1<<28) //28:28
-+#define USB20_IDDIG (0x1<<27) //27:27
-+#define AD_USB20_VBUSVALID (0x1<<26) //26:26
-+#define AD_USB20_SESSEND (0x1<<25) //25:25
-+#define AD_USB20_AVALID (0x1<<24) //24:24
-+#define USB20_LINE_STATE (0x3<<22) //23:22
-+#define USB20_HST_DISCON (0x1<<21) //21:21
-+#define USB20_TX_READY (0x1<<20) //20:20
-+#define USB20_RX_ERROR (0x1<<19) //19:19
-+#define USB20_RX_ACTIVE (0x1<<18) //18:18
-+#define USB20_RX_VALIDH (0x1<<17) //17:17
-+#define USB20_RX_VALID (0x1<<16) //16:16
-+#define USB20_DATA_OUT (0xffff<<0) //15:0
-+
-+//U3D_U2PHYDMON2
-+#define RGO_TXVALID_CNT (0xff<<24) //31:24
-+#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
-+#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
-+#define USB20_PROBE_OUT (0xff<<0) //7:0
-+
-+//U3D_U2PHYDMON3
-+#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
-+#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
-+#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
-+#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
-+#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
-+
-+//U3D_U2PHYBC12C
-+#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
-+#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
-+#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
-+#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
-+#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
-+#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
-+#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
-+#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
-+#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
-+#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
-+#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
-+#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
-+#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
-+#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
-+#define RG_CHGDT_EN (0x1<<0) //0:0
-+
-+//U3D_U2PHYBC12C1
-+#define RG_CHGDT_REV (0xff<<0) //7:0
-+
-+//U3D_REGFCOM
-+#define RG_PAGE (0xff<<24) //31:24
-+#define I2C_MODE (0x1<<16) //16:16
-+
-+
-+/* OFFSET */
-+
-+//U3D_U2PHYAC0
-+#define RG_USB20_USBPLL_DIVEN_OFST (28)
-+#define RG_USB20_USBPLL_CKCTRL_OFST (26)
-+#define RG_USB20_USBPLL_PREDIV_OFST (24)
-+#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
-+#define RG_USB20_USBPLL_FBDIV_OFST (16)
-+#define RG_USB20_REF_EN_OFST (15)
-+#define RG_USB20_INTR_EN_OFST (14)
-+#define RG_USB20_BG_TRIM_OFST (8)
-+#define RG_USB20_BG_RBSEL_OFST (6)
-+#define RG_USB20_BG_RASEL_OFST (4)
-+#define RG_USB20_BGR_DIV_OFST (2)
-+#define RG_SIFSLV_CHP_EN_OFST (1)
-+#define RG_SIFSLV_BGR_EN_OFST (0)
-+
-+//U3D_U2PHYAC1
-+#define RG_USB20_VRT_VREF_SEL_OFST (28)
-+#define RG_USB20_TERM_VREF_SEL_OFST (24)
-+#define RG_USB20_MPX_SEL_OFST (16)
-+#define RG_USB20_MPX_OUT_SEL_OFST (12)
-+#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
-+#define RG_USB20_USBPLL_ACCEN_OFST (3)
-+#define RG_USB20_USBPLL_LF_OFST (2)
-+#define RG_USB20_USBPLL_BR_OFST (1)
-+#define RG_USB20_USBPLL_BP_OFST (0)
-+
-+//U3D_U2PHYAC2
-+#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
-+#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
-+#define RG_USB20_CLKREF_REV_OFST (0)
-+
-+//U3D_U2PHYACR0
-+#define RG_USB20_ICUSB_EN_OFST (24)
-+#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
-+#define RG_USB20_HSTX_SRCTRL_OFST (16)
-+#define RG_USB20_LS_CR_OFST (12)
-+#define RG_USB20_FS_CR_OFST (8)
-+#define RG_USB20_LS_SR_OFST (4)
-+#define RG_USB20_FS_SR_OFST (0)
-+
-+//U3D_U2PHYACR1
-+#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
-+#define RG_USB20_SQD_OFST (24)
-+#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
-+#define RG_USB20_HSTX_TMODE_EN_OFST (19)
-+#define RG_USB20_PHYD_MONEN_OFST (18)
-+#define RG_USB20_INLPBK_EN_OFST (17)
-+#define RG_USB20_CHIRP_EN_OFST (16)
-+#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
-+#define RG_USB20_DM_ABIST_SELE_OFST (8)
-+#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
-+#define RG_USB20_DP_ABIST_SELE_OFST (0)
-+
-+//U3D_U2PHYACR2
-+#define RG_USB20_OTG_ABIST_SELE_OFST (29)
-+#define RG_USB20_OTG_ABIST_EN_OFST (28)
-+#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
-+#define RG_USB20_OTG_VBUSTH_OFST (24)
-+#define RG_USB20_DISC_FIT_EN_OFST (22)
-+#define RG_USB20_DISCD_OFST (20)
-+#define RG_USB20_DISCTH_OFST (16)
-+#define RG_USB20_SQCAL_EN_OFST (15)
-+#define RG_USB20_SQCAL_OFST (8)
-+#define RG_USB20_SQTH_OFST (0)
-+
-+//U3D_U2PHYACR3
-+#define RG_USB20_HSTX_DBIST_OFST (28)
-+#define RG_USB20_HSTX_BIST_EN_OFST (26)
-+#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
-+#define RG_USB20_HSRX_TMODE_EN_OFST (23)
-+#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
-+#define RG_USB20_USB11_TMODE_EN_OFST (19)
-+#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
-+#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
-+#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
-+#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
-+#define RG_USB20_PUPD_BIST_EN_OFST (12)
-+#define RG_USB20_EN_PU_DM_OFST (11)
-+#define RG_USB20_EN_PD_DM_OFST (10)
-+#define RG_USB20_EN_PU_DP_OFST (9)
-+#define RG_USB20_EN_PD_DP_OFST (8)
-+#define RG_USB20_PHY_REV_OFST (0)
-+
-+//U3D_U2PHYACR4
-+#define RG_USB20_DP_100K_MODE_OFST (18)
-+#define RG_USB20_DM_100K_EN_OFST (17)
-+#define USB20_DP_100K_EN_OFST (16)
-+#define USB20_GPIO_DM_I_OFST (15)
-+#define USB20_GPIO_DP_I_OFST (14)
-+#define USB20_GPIO_DM_OE_OFST (13)
-+#define USB20_GPIO_DP_OE_OFST (12)
-+#define RG_USB20_GPIO_CTL_OFST (9)
-+#define USB20_GPIO_MODE_OFST (8)
-+#define RG_USB20_TX_BIAS_EN_OFST (5)
-+#define RG_USB20_TX_VCMPDN_EN_OFST (4)
-+#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
-+#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
-+
-+//U3D_U2PHYAMON0
-+#define RGO_USB20_GPIO_DM_O_OFST (1)
-+#define RGO_USB20_GPIO_DP_O_OFST (0)
-+
-+//U3D_U2PHYDCR0
-+#define RG_USB20_CDR_TST_OFST (30)
-+#define RG_USB20_GATED_ENB_OFST (29)
-+#define RG_USB20_TESTMODE_OFST (26)
-+#define RG_USB20_PLL_STABLE_OFST (25)
-+#define RG_USB20_PLL_FORCE_ON_OFST (24)
-+#define RG_USB20_PHYD_RESERVE_OFST (8)
-+#define RG_USB20_EBTHRLD_OFST (7)
-+#define RG_USB20_EARLY_HSTX_I_OFST (6)
-+#define RG_USB20_TX_TST_OFST (5)
-+#define RG_USB20_NEGEDGE_ENB_OFST (4)
-+#define RG_USB20_CDR_FILT_OFST (0)
-+
-+//U3D_U2PHYDCR1
-+#define RG_USB20_PROBE_SEL_OFST (24)
-+#define RG_USB20_DRVVBUS_OFST (23)
-+#define RG_DEBUG_EN_OFST (22)
-+#define RG_USB20_OTG_PROBE_OFST (20)
-+#define RG_USB20_SW_PLLMODE_OFST (18)
-+#define RG_USB20_BERTH_OFST (16)
-+#define RG_USB20_LBMODE_OFST (13)
-+#define RG_USB20_FORCE_TAP_OFST (12)
-+#define RG_USB20_TAPSEL_OFST (0)
-+
-+//U3D_U2PHYDTM0
-+#define RG_UART_MODE_OFST (30)
-+#define FORCE_UART_I_OFST (29)
-+#define FORCE_UART_BIAS_EN_OFST (28)
-+#define FORCE_UART_TX_OE_OFST (27)
-+#define FORCE_UART_EN_OFST (26)
-+#define FORCE_USB_CLKEN_OFST (25)
-+#define FORCE_DRVVBUS_OFST (24)
-+#define FORCE_DATAIN_OFST (23)
-+#define FORCE_TXVALID_OFST (22)
-+#define FORCE_DM_PULLDOWN_OFST (21)
-+#define FORCE_DP_PULLDOWN_OFST (20)
-+#define FORCE_XCVRSEL_OFST (19)
-+#define FORCE_SUSPENDM_OFST (18)
-+#define FORCE_TERMSEL_OFST (17)
-+#define FORCE_OPMODE_OFST (16)
-+#define UTMI_MUXSEL_OFST (15)
-+#define RG_RESET_OFST (14)
-+#define RG_DATAIN_OFST (10)
-+#define RG_TXVALIDH_OFST (9)
-+#define RG_TXVALID_OFST (8)
-+#define RG_DMPULLDOWN_OFST (7)
-+#define RG_DPPULLDOWN_OFST (6)
-+#define RG_XCVRSEL_OFST (4)
-+#define RG_SUSPENDM_OFST (3)
-+#define RG_TERMSEL_OFST (2)
-+#define RG_OPMODE_OFST (0)
-+
-+//U3D_U2PHYDTM1
-+#define RG_USB20_PRBS7_EN_OFST (31)
-+#define RG_USB20_PRBS7_BITCNT_OFST (24)
-+#define RG_USB20_CLK48M_EN_OFST (23)
-+#define RG_USB20_CLK60M_EN_OFST (22)
-+#define RG_UART_I_OFST (19)
-+#define RG_UART_BIAS_EN_OFST (18)
-+#define RG_UART_TX_OE_OFST (17)
-+#define RG_UART_EN_OFST (16)
-+#define FORCE_VBUSVALID_OFST (13)
-+#define FORCE_SESSEND_OFST (12)
-+#define FORCE_BVALID_OFST (11)
-+#define FORCE_AVALID_OFST (10)
-+#define FORCE_IDDIG_OFST (9)
-+#define FORCE_IDPULLUP_OFST (8)
-+#define RG_VBUSVALID_OFST (5)
-+#define RG_SESSEND_OFST (4)
-+#define RG_BVALID_OFST (3)
-+#define RG_AVALID_OFST (2)
-+#define RG_IDDIG_OFST (1)
-+#define RG_IDPULLUP_OFST (0)
-+
-+//U3D_U2PHYDMON0
-+#define RG_USB20_PRBS7_BERTH_OFST (0)
-+
-+//U3D_U2PHYDMON1
-+#define USB20_UART_O_OFST (31)
-+#define RGO_USB20_LB_PASS_OFST (30)
-+#define RGO_USB20_LB_DONE_OFST (29)
-+#define AD_USB20_BVALID_OFST (28)
-+#define USB20_IDDIG_OFST (27)
-+#define AD_USB20_VBUSVALID_OFST (26)
-+#define AD_USB20_SESSEND_OFST (25)
-+#define AD_USB20_AVALID_OFST (24)
-+#define USB20_LINE_STATE_OFST (22)
-+#define USB20_HST_DISCON_OFST (21)
-+#define USB20_TX_READY_OFST (20)
-+#define USB20_RX_ERROR_OFST (19)
-+#define USB20_RX_ACTIVE_OFST (18)
-+#define USB20_RX_VALIDH_OFST (17)
-+#define USB20_RX_VALID_OFST (16)
-+#define USB20_DATA_OUT_OFST (0)
-+
-+//U3D_U2PHYDMON2
-+#define RGO_TXVALID_CNT_OFST (24)
-+#define RGO_RXACTIVE_CNT_OFST (16)
-+#define RGO_USB20_LB_BERCNT_OFST (8)
-+#define USB20_PROBE_OUT_OFST (0)
-+
-+//U3D_U2PHYDMON3
-+#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
-+#define RGO_USB20_PRBS7_DONE_OFST (3)
-+#define RGO_USB20_PRBS7_LOCK_OFST (2)
-+#define RGO_USB20_PRBS7_PASS_OFST (1)
-+#define RGO_USB20_PRBS7_PASSTH_OFST (0)
-+
-+//U3D_U2PHYBC12C
-+#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
-+#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
-+#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
-+#define RG_CHGDT_ISRC_LEV_OFST (14)
-+#define RG_CHGDT_VDATSRC_OFST (13)
-+#define RG_CHGDT_BGVREF_SEL_OFST (10)
-+#define RG_CHGDT_RDVREF_SEL_OFST (8)
-+#define RG_CHGDT_ISRC_DP_OFST (7)
-+#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
-+#define RG_CHGDT_VDAT_DM_OFST (5)
-+#define RG_CHGDT_OPOUT_DP_OFST (4)
-+#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
-+#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
-+#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
-+#define RG_CHGDT_EN_OFST (0)
-+
-+//U3D_U2PHYBC12C1
-+#define RG_CHGDT_REV_OFST (0)
-+
-+//U3D_REGFCOM
-+#define RG_PAGE_OFST (24)
-+#define I2C_MODE_OFST (16)
-+
-+
-+///////////////////////////////////////////////////////////////////////////////
-+
-+struct u3phya_reg {
-+ //0x0
-+ PHY_LE32 reg0;
-+ PHY_LE32 reg1;
-+ PHY_LE32 reg2;
-+ PHY_LE32 reg3;
-+ //0x10
-+ PHY_LE32 reg4;
-+ PHY_LE32 reg5;
-+ PHY_LE32 reg6;
-+ PHY_LE32 reg7;
-+ //0x20
-+ PHY_LE32 reg8;
-+ PHY_LE32 reg9;
-+ PHY_LE32 rega;
-+ PHY_LE32 regb;
-+ //0x30
-+ PHY_LE32 regc;
-+ PHY_LE32 regd;
-+ PHY_LE32 rege;
-+};
-+
-+//U3D_reg0
-+#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
-+#define RG_SSUSB_CHPEN (0x1<<30) //30:30
-+#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
-+#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
-+#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
-+#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
-+#define RG_SSUSB_REF_EN (0x1<<15) //15:15
-+#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
-+#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
-+#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
-+#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
-+#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
-+
-+//U3D_reg1
-+#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
-+#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
-+#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
-+#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
-+#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
-+#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
-+#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
-+#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
-+#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
-+
-+//U3D_reg2
-+#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
-+#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
-+#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
-+#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
-+#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
-+#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
-+#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
-+#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
-+#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
-+#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
-+#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
-+#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
-+#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
-+#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
-+#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
-+
-+//U3D_reg3
-+#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
-+
-+//U3D_reg4
-+#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
-+
-+//U3D_reg5
-+#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
-+#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
-+#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
-+#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
-+#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
-+#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
-+#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
-+#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
-+#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
-+#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
-+#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
-+
-+//U3D_reg6
-+#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
-+#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
-+#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
-+#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
-+#define RG_SSUSB_TX_SR (0x7<<20) //22:20
-+#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
-+#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
-+#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
-+#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
-+#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
-+#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
-+#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
-+#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
-+#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
-+
-+//U3D_reg7
-+#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
-+#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
-+#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
-+#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
-+#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
-+#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
-+#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
-+#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
-+#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
-+#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
-+#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
-+
-+//U3D_reg8
-+#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
-+
-+//U3D_reg9
-+#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
-+#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
-+
-+//U3D_regA
-+#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
-+#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
-+#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
-+#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
-+#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
-+#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
-+#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
-+#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
-+#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
-+#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
-+#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
-+#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
-+#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
-+#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
-+#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
-+#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
-+#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
-+#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
-+#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
-+#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
-+#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
-+
-+//U3D_regB
-+#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
-+#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
-+#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
-+#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
-+#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
-+#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
-+#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
-+#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
-+#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
-+#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
-+#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
-+#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
-+#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
-+#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
-+
-+//U3D_regC
-+#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
-+#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
-+#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
-+#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
-+
-+//U3D_redD
-+#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
-+#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
-+
-+//U3D_regE
-+#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
-+#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
-+#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
-+#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
-+#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
-+
-+
-+/* OFFSET */
-+
-+//U3D_reg0
-+#define RG_SSUSB_BGR_EN_OFST (31)
-+#define RG_SSUSB_CHPEN_OFST (30)
-+#define RG_SSUSB_BG_DIV_OFST (28)
-+#define RG_SSUSB_INTR_EN_OFST (26)
-+#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
-+#define RG_SSUSB_MPX_SEL_OFST (16)
-+#define RG_SSUSB_REF_EN_OFST (15)
-+#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
-+#define RG_SSUSB_BG_RASEL_OFST (9)
-+#define RG_SSUSB_BG_RBSEL_OFST (7)
-+#define RG_SSUSB_BG_MONEN_OFST (6)
-+#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
-+
-+//U3D_reg1
-+#define RG_PCIE_CLKDRV_SLEW_OFST (30)
-+#define RG_PCIE_CLKDRV_AMP_OFST (27)
-+#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
-+#define RG_SSUSB_XTAL_MON_EN_OFST (25)
-+#define RG_SSUSB_XTAL_HYS_OFST (24)
-+#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
-+#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
-+#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
-+#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
-+
-+//U3D_reg2
-+#define RG_SSUSB_SYSPLL_LF_OFST (31)
-+#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
-+#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
-+#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
-+#define RG_SSUSB_SYSPLL_BLP_OFST (20)
-+#define RG_SSUSB_SYSPLL_BP_OFST (19)
-+#define RG_SSUSB_SYSPLL_BR_OFST (18)
-+#define RG_SSUSB_SYSPLL_BC_OFST (17)
-+#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
-+#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
-+#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
-+#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
-+#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
-+#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
-+#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
-+
-+//U3D_reg3
-+#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
-+
-+//U3D_reg4
-+#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
-+
-+//U3D_reg5
-+#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
-+#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
-+#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
-+#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
-+#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
-+#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
-+#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
-+#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
-+#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
-+#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
-+#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
-+
-+//U3D_reg6
-+#define RG_SSUSB_TX250MCK_INVB_OFST (31)
-+#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
-+#define RG_SSUSB_IDRV_CALIB_OFST (24)
-+#define RG_SSUSB_TX_R50_FON_OFST (23)
-+#define RG_SSUSB_TX_SR_OFST (20)
-+#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
-+#define RG_SSUSB_RXDET_RSEL_OFST (14)
-+#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
-+#define RG_SSUSB_CKMON_EN_OFST (11)
-+#define RG_SSUSB_CKMON_SEL_OFST (8)
-+#define RG_SSUSB_TX_VLMON_EN_OFST (7)
-+#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
-+#define RG_SSUSB_RXLBTX_EN_OFST (5)
-+#define RG_SSUSB_TXLBRX_EN_OFST (4)
-+
-+//U3D_reg7
-+#define RG_SSUSB_RESERVE_OFST (12)
-+#define RG_SSUSB_PLL_CKCTRL_OFST (10)
-+#define RG_SSUSB_PLL_POSDIV_OFST (8)
-+#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
-+#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
-+#define RG_SSUSB_PLL_EP_EN_OFST (5)
-+#define RG_SSUSB_PLL_VOD_EN_OFST (4)
-+#define RG_SSUSB_PLL_V11_EN_OFST (3)
-+#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
-+#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
-+#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
-+
-+//U3D_reg8
-+#define RG_SSUSB_PLL_RESERVE_OFST (0)
-+
-+//U3D_reg9
-+#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
-+#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
-+
-+//U3D_regA
-+#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
-+#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
-+#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
-+#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
-+#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
-+#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
-+#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
-+#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
-+#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
-+#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
-+#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
-+#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
-+#define RG_SSUSB_CDR_MONMUX_OFST (11)
-+#define RG_SSUSB_CDR_CKCTRL_OFST (9)
-+#define RG_SSUSB_CDR_ACCEN_OFST (8)
-+#define RG_SSUSB_CDR_BYPASS_OFST (6)
-+#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
-+#define RG_SSUSB_CDR_EPEN_OFST (3)
-+#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
-+#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
-+#define RG_SSUSB_CDR_MONEN_OFST (0)
-+
-+//U3D_regB
-+#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
-+#define RG_SSUSB_CDR_REGOD_OFST (29)
-+#define RG_SSUSB_RX_DAC_EN_OFST (26)
-+#define RG_SSUSB_RX_DAC_PWD_OFST (25)
-+#define RG_SSUSB_EQ_CURSEL_OFST (24)
-+#define RG_SSUSB_RX_DAC_MUX_OFST (19)
-+#define RG_SSUSB_RX_R2T_EN_OFST (18)
-+#define RG_SSUSB_RX_T2R_EN_OFST (17)
-+#define RG_SSUSB_RX_50_LOWER_OFST (14)
-+#define RG_SSUSB_RX_50_TAR_OFST (12)
-+#define RG_SSUSB_RX_SW_CTRL_OFST (7)
-+#define RG_PCIE_SIGDET_VTH_OFST (5)
-+#define RG_PCIE_SIGDET_LPF_OFST (3)
-+#define RG_SSUSB_LFPS_MON_EN_OFST (2)
-+
-+//U3D_regC
-+#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
-+#define RG_SSUSB_CDR_RESERVE_OFST (16)
-+#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
-+#define RG_PCIE_RX_RESERVE_OFST (0)
-+
-+//U3D_redD
-+#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
-+#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
-+
-+//U3D_regE
-+#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
-+#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
-+#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
-+#define RG_SSUSB_RX_PD_RST_OFST (1)
-+#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
-+
-+///////////////////////////////////////////////////////////////////////////////
-+
-+struct u3phya_da_reg {
-+ //0x0
-+ PHY_LE32 reg0;
-+ PHY_LE32 reg1;
-+ PHY_LE32 reg4;
-+ PHY_LE32 reg5;
-+ //0x10
-+ PHY_LE32 reg6;
-+ PHY_LE32 reg7;
-+ PHY_LE32 reg8;
-+ PHY_LE32 reg9;
-+ //0x20
-+ PHY_LE32 reg10;
-+ PHY_LE32 reg12;
-+ PHY_LE32 reg13;
-+ PHY_LE32 reg14;
-+ //0x30
-+ PHY_LE32 reg15;
-+ PHY_LE32 reg16;
-+ PHY_LE32 reg19;
-+ PHY_LE32 reg20;
-+ //0x40
-+ PHY_LE32 reg21;
-+ PHY_LE32 reg23;
-+ PHY_LE32 reg25;
-+ PHY_LE32 reg26;
-+ //0x50
-+ PHY_LE32 reg28;
-+ PHY_LE32 reg29;
-+ PHY_LE32 reg30;
-+ PHY_LE32 reg31;
-+ //0x60
-+ PHY_LE32 reg32;
-+ PHY_LE32 reg33;
-+};
-+
-+//U3D_reg0
-+#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
-+#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
-+#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
-+#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
-+#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
-+#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
-+#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
-+#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
-+#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
-+#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
-+#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
-+#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
-+#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
-+#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
-+#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
-+
-+//U3D_reg1
-+#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
-+#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
-+#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
-+#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
-+#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
-+#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
-+#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
-+#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
-+#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
-+#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
-+#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
-+#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
-+#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
-+#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
-+#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
-+
-+//U3D_reg4
-+#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
-+#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
-+#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
-+#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
-+#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
-+#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
-+#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
-+#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
-+#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
-+#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
-+
-+//U3D_reg5
-+#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
-+#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
-+#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
-+#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
-+#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
-+#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
-+#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
-+#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
-+#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
-+#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
-+
-+//U3D_reg6
-+#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
-+#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
-+#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
-+#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
-+#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
-+
-+//U3D_reg7
-+#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
-+#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
-+#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
-+#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
-+#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
-+
-+//U3D_reg8
-+#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
-+#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
-+#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
-+#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
-+#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
-+
-+//U3D_reg9
-+#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
-+#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
-+#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
-+#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
-+
-+//U3D_reg10
-+#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
-+#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
-+#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
-+#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
-+#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
-+#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
-+
-+//U3D_reg12
-+#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
-+
-+//U3D_reg13
-+#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
-+
-+//U3D_reg14
-+#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
-+
-+//U3D_reg15
-+#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
-+
-+//U3D_reg16
-+#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
-+
-+//U3D_reg19
-+#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
-+#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
-+
-+//U3D_reg20
-+#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
-+#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
-+
-+//U3D_reg21
-+#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
-+#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
-+
-+//U3D_reg23
-+#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
-+#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
-+
-+//U3D_reg25
-+#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
-+#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
-+
-+//U3D_reg26
-+#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
-+#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
-+#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
-+#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
-+#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
-+
-+//U3D_reg28
-+#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
-+#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
-+#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
-+#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
-+#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
-+
-+//U3D_reg29
-+#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
-+#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
-+#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
-+#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
-+#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
-+
-+//U3D_reg30
-+#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
-+#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
-+#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
-+#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
-+#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
-+
-+//U3D_reg31
-+#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
-+#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
-+#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
-+#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
-+
-+//U3D_reg32
-+#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
-+#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
-+#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
-+#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
-+#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
-+#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
-+#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
-+#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
-+#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
-+#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
-+#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
-+#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
-+#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
-+#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
-+#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
-+#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
-+
-+//U3D_reg33
-+#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
-+#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
-+#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
-+#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
-+#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
-+#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
-+#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
-+#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
-+#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
-+#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
-+
-+
-+/* OFFSET */
-+
-+//U3D_reg0
-+#define RG_PCIE_SPEED_PE2D_OFST (24)
-+#define RG_PCIE_SPEED_PE2H_OFST (23)
-+#define RG_PCIE_SPEED_PE1D_OFST (22)
-+#define RG_PCIE_SPEED_PE1H_OFST (21)
-+#define RG_PCIE_SPEED_U3_OFST (20)
-+#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
-+#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
-+#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
-+#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
-+#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
-+#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
-+#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
-+#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
-+#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
-+#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
-+
-+//U3D_reg1
-+#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
-+#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
-+#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
-+#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
-+#define RG_USB20_REFCK_SEL_U3_OFST (26)
-+#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
-+#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
-+#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
-+#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
-+#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
-+#define RG_PCIE_MODE_PE2D_OFST (8)
-+#define RG_PCIE_MODE_PE2H_OFST (3)
-+#define RG_PCIE_MODE_PE1D_OFST (2)
-+#define RG_PCIE_MODE_PE1H_OFST (1)
-+#define RG_PCIE_MODE_U3_OFST (0)
-+
-+//U3D_reg4
-+#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
-+#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
-+#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
-+#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
-+#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
-+#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
-+#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
-+#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
-+#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
-+#define RG_SSUSB_PLL_BC_U3_OFST (0)
-+
-+//U3D_reg5
-+#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
-+#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
-+#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
-+#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
-+#define RG_SSUSB_PLL_BR_U3_OFST (15)
-+#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
-+#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
-+#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
-+#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
-+#define RG_SSUSB_PLL_IC_U3_OFST (0)
-+
-+//U3D_reg6
-+#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
-+#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
-+#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
-+#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
-+#define RG_SSUSB_PLL_IR_U3_OFST (0)
-+
-+//U3D_reg7
-+#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
-+#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
-+#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
-+#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
-+#define RG_SSUSB_PLL_BP_U3_OFST (0)
-+
-+//U3D_reg8
-+#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
-+#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
-+#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
-+#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
-+#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
-+
-+//U3D_reg9
-+#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
-+#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
-+#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
-+#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
-+
-+//U3D_reg10
-+#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
-+#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
-+#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
-+#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
-+#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
-+#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
-+
-+//U3D_reg12
-+#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
-+
-+//U3D_reg13
-+#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
-+
-+//U3D_reg14
-+#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
-+
-+//U3D_reg15
-+#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
-+
-+//U3D_reg16
-+#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
-+
-+//U3D_reg19
-+#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
-+#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
-+
-+//U3D_reg20
-+#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
-+#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
-+
-+//U3D_reg21
-+#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
-+#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
-+
-+//U3D_reg23
-+#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
-+#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
-+
-+//U3D_reg25
-+#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
-+#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
-+
-+//U3D_reg26
-+#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
-+#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
-+#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
-+#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
-+#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
-+
-+//U3D_reg28
-+#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
-+#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
-+#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
-+#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
-+#define RG_SSUSB_CDR_BPA_U3_OFST (0)
-+
-+//U3D_reg29
-+#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
-+#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
-+#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
-+#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
-+#define RG_SSUSB_CDR_BPB_U3_OFST (0)
-+
-+//U3D_reg30
-+#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
-+#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
-+#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
-+#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
-+#define RG_SSUSB_CDR_BR_U3_OFST (0)
-+
-+//U3D_reg31
-+#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
-+#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
-+#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
-+#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
-+
-+//U3D_reg32
-+#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
-+#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
-+#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
-+#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
-+#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
-+#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
-+#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
-+#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
-+#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
-+#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
-+#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
-+#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
-+#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
-+#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
-+#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
-+#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
-+
-+//U3D_reg33
-+#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
-+#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
-+#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
-+#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
-+#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
-+#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
-+#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
-+#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
-+#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
-+#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
-+
-+
-+///////////////////////////////////////////////////////////////////////////////
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