ar71xx: fix NAND controller base for QCA955x SoCs
authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Tue, 1 Jan 2013 13:10:26 +0000 (13:10 +0000)
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Tue, 1 Jan 2013 13:10:26 +0000 (13:10 +0000)
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34942 3c298f89-4303-0410-b956-a3cf2f4a3e73

target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch

index 407de36..26c87c8 100644 (file)
@@ -50,7 +50,7 @@
  #define QCA955X_EHCI_SIZE     0x200
 +#define QCA955X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
 +#define QCA955X_GMAC_SIZE     0x40
-+#define QCA955X_NFC_BASE      0x1b000200
++#define QCA955X_NFC_BASE      0x1b800200
 +#define QCA955X_NFC_SIZE      0xb8
  
  #define AR9300_OTP_BASE               0x14000
index 38290e8..aa96205 100644 (file)
@@ -48,7 +48,7 @@
  #define QCA955X_EHCI_SIZE     0x200
 +#define QCA955X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
 +#define QCA955X_GMAC_SIZE     0x40
-+#define QCA955X_NFC_BASE      0x1b000200
++#define QCA955X_NFC_BASE      0x1b800200
 +#define QCA955X_NFC_SIZE      0xb8
  
  #define AR9300_OTP_BASE               0x14000