X-Git-Url: https://git.archive.openwrt.org/?p=openwrt.git;a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Farch%2Fmips%2Fath79%2Fdev-eth.c;h=2f2825f94507f450834355517ffdacf26e7e0f3b;hp=d2d0ee87f07a45c29b54aa26c240d9c90bc08760;hb=876efdff0a3eae9deb6679383036e3a135e494e5;hpb=527f8049cd8db420e785450dda1eeaad2020ca5d diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index d2d0ee87f0..2f2825f945 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -39,7 +40,7 @@ static struct resource ath79_mdio0_resources[] = { } }; -static struct ag71xx_mdio_platform_data ath79_mdio0_data; +struct ag71xx_mdio_platform_data ath79_mdio0_data; struct platform_device ath79_mdio0_device = { .name = "ag71xx-mdio", @@ -60,7 +61,7 @@ static struct resource ath79_mdio1_resources[] = { } }; -static struct ag71xx_mdio_platform_data ath79_mdio1_data; +struct ag71xx_mdio_platform_data ath79_mdio1_data; struct platform_device ath79_mdio1_device = { .name = "ag71xx-mdio", @@ -181,7 +182,9 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) if (ath79_soc == ATH79_SOC_AR9341 || ath79_soc == ATH79_SOC_AR9342 || ath79_soc == ATH79_SOC_AR9344 || - ath79_soc == ATH79_SOC_QCA9558) + ath79_soc == ATH79_SOC_QCA9556 || + ath79_soc == ATH79_SOC_QCA9558 || + ath79_soc == ATH79_SOC_QCA956X) max_id = 1; else max_id = 0; @@ -195,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_TP9343: mdio_dev = &ath79_mdio1_device; mdio_data = &ath79_mdio1_data; break; @@ -202,7 +207,9 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA956X: if (id == 0) { mdio_dev = &ath79_mdio0_device; mdio_data = &ath79_mdio0_data; @@ -250,7 +257,18 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) } mdio_data->is_ar934x = 1; break; + + case ATH79_SOC_QCA9533: + case ATH79_SOC_TP9343: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: + mdio_data->is_ar934x = 1; + break; + + case ATH79_SOC_QCA956X: if (id == 1) mdio_data->builtin_switch = 1; mdio_data->is_ar934x = 1; @@ -355,6 +373,36 @@ static void ar934x_set_speed_ge0(int speed) iounmap(base); } +static void qca955x_set_speed_xmii(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(0, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG); + iounmap(base); +} + +static void qca955x_set_speed_sgmii(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(1, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG); + iounmap(base); +} + +static void qca956x_set_speed_sgmii(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(0, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG); + iounmap(base); +} + static void ath79_set_speed_dummy(int speed) { } @@ -412,8 +460,8 @@ static struct resource ath79_eth0_resources[] = { }, { .name = "mac_irq", .flags = IORESOURCE_IRQ, - .start = ATH79_CPU_IRQ_GE0, - .end = ATH79_CPU_IRQ_GE0, + .start = ATH79_CPU_IRQ(4), + .end = ATH79_CPU_IRQ(4), }, }; @@ -440,8 +488,8 @@ static struct resource ath79_eth1_resources[] = { }, { .name = "mac_irq", .flags = IORESOURCE_IRQ, - .start = ATH79_CPU_IRQ_GE1, - .end = ATH79_CPU_IRQ_GE1, + .start = ATH79_CPU_IRQ(5), + .end = ATH79_CPU_IRQ(5), }, }; @@ -485,6 +533,10 @@ struct ag71xx_switch_platform_data ath79_switch_data; #define AR934X_PLL_VAL_100 0x00000101 #define AR934X_PLL_VAL_10 0x00001616 +#define QCA956X_PLL_VAL_1000 0x03000000 +#define QCA956X_PLL_VAL_100 0x00000101 +#define QCA956X_PLL_VAL_10 0x00001919 + static void __init ath79_init_eth_pll_data(unsigned int id) { struct ath79_eth_pll_data *pll_data; @@ -540,12 +592,21 @@ static void __init ath79_init_eth_pll_data(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: + case ATH79_SOC_TP9343: pll_10 = AR934X_PLL_VAL_10; pll_100 = AR934X_PLL_VAL_100; pll_1000 = AR934X_PLL_VAL_1000; break; + case ATH79_SOC_QCA956X: + pll_10 = QCA956X_PLL_VAL_10; + pll_100 = QCA956X_PLL_VAL_100; + pll_1000 = QCA956X_PLL_VAL_1000; + break; + default: BUG(); } @@ -596,6 +657,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_TP9343: pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; break; @@ -605,7 +668,6 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: - case ATH79_SOC_QCA9558: switch (pdata->phy_if_mode) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -617,6 +679,19 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, } break; + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA956X: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: + break; + default: + return -EINVAL; + } + break; + default: BUG(); } @@ -645,6 +720,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA956X: + case ATH79_SOC_TP9343: pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; break; @@ -654,7 +731,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: - case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9533: switch (pdata->phy_if_mode) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -664,6 +741,18 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, } break; + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: + break; + default: + return -EINVAL; + } + break; + default: BUG(); } @@ -691,6 +780,84 @@ void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio) iounmap(base); } +void __init ath79_setup_ar934x_eth_cfg(u32 mask) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_MII_GMAC0 | + AR934X_ETH_CFG_GMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + t |= mask; + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + /* flush write */ + __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, + unsigned int rxdv) +{ + void __iomem *base; + u32 t; + + rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK; + rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT | + AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT); + + t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT | + rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT); + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + /* flush write */ + __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +void __init ath79_setup_qca955x_eth_cfg(u32 mask) +{ + void __iomem *base; + u32 t, m; + + m = QCA955X_ETH_CFG_RGMII_EN | + QCA955X_ETH_CFG_MII_GE0 | + QCA955X_ETH_CFG_GMII_GE0 | + QCA955X_ETH_CFG_MII_GE0_MASTER | + QCA955X_ETH_CFG_MII_GE0_SLAVE | + QCA955X_ETH_CFG_GE0_ERR_EN | + QCA955X_ETH_CFG_GE0_SGMII | + QCA955X_ETH_CFG_RMII_GE0 | + QCA955X_ETH_CFG_MII_CNTL_SPEED | + QCA955X_ETH_CFG_RMII_GE0_MASTER; + + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); + + t &= ~m; + t |= mask; + + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + static int ath79_eth_instance __initdata; void __init ath79_register_eth(unsigned int id) { @@ -712,6 +879,9 @@ void __init ath79_register_eth(unsigned int id) pdata = pdev->dev.platform_data; + pdata->max_frame_len = 1540; + pdata->desc_pktlen_mask = 0xfff; + err = ath79_setup_phy_if_mode(id, pdata); if (err) { printk(KERN_ERR @@ -841,13 +1011,13 @@ void __init ath79_register_eth(unsigned int id) pdata->set_speed = ath79_set_speed_dummy; pdata->speed = SPEED_1000; + pdata->has_gbit = 1; pdata->duplex = DUPLEX_FULL; pdata->switch_data = &ath79_switch_data; ath79_switch_data.phy_poll_mask |= BIT(4); } - pdata->has_gbit = 1; pdata->is_ar724x = 1; if (!pdata->fifo_cfg1) @@ -861,7 +1031,7 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: - case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9533: if (id == 0) { pdata->reset_bit = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO; @@ -882,6 +1052,113 @@ void __init ath79_register_eth(unsigned int id) pdata->has_gbit = 1; pdata->is_ar724x = 1; + pdata->max_frame_len = SZ_16K - 1; + pdata->desc_pktlen_mask = SZ_16K - 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_TP9343: + if (id == 0) { + pdata->reset_bit = AR933X_RESET_GE0_MAC | + AR933X_RESET_GE0_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + if (!pdata->phy_mask) + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit = AR933X_RESET_GE1_MAC | + AR933X_RESET_GE1_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + if (id == 0) { + pdata->reset_bit = QCA955X_RESET_GE0_MAC | + QCA955X_RESET_GE0_MDIO; + pdata->set_speed = qca955x_set_speed_xmii; + } else { + pdata->reset_bit = QCA955X_RESET_GE1_MAC | + QCA955X_RESET_GE1_MDIO; + pdata->set_speed = qca955x_set_speed_sgmii; + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + /* + * Limit the maximum frame length to 4095 bytes. + * Although the documentation says that the hardware + * limit is 16383 bytes but that does not work in + * practice. It seems that the hardware only updates + * the lowest 12 bits of the packet length field + * in the RX descriptor. + */ + pdata->max_frame_len = SZ_4K - 1; + pdata->desc_pktlen_mask = SZ_16K - 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_QCA956X: + if (id == 0) { + pdata->reset_bit = QCA955X_RESET_GE0_MAC | + QCA955X_RESET_GE0_MDIO; + + if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII) + pdata->set_speed = qca956x_set_speed_sgmii; + else + pdata->set_speed = ath79_set_speed_ge0; + } else { + pdata->reset_bit = QCA955X_RESET_GE1_MAC | + QCA955X_RESET_GE1_MDIO; + + pdata->set_speed = ath79_set_speed_dummy; + + pdata->switch_data = &ath79_switch_data; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + + /* reset the built-in switch */ + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH); + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + if (!pdata->fifo_cfg1) pdata->fifo_cfg1 = 0x0010ffff; if (!pdata->fifo_cfg2) @@ -897,6 +1174,7 @@ void __init ath79_register_eth(unsigned int id) switch (pdata->phy_if_mode) { case PHY_INTERFACE_MODE_GMII: case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: if (!pdata->has_gbit) { printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", id); @@ -919,7 +1197,6 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: - case ATH79_SOC_QCA9558: if (id == 0) pdata->mii_bus_dev = &ath79_mdio0_device.dev; else @@ -929,9 +1206,21 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_TP9343: pdata->mii_bus_dev = &ath79_mdio1_device.dev; break; + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + /* don't assign any MDIO device by default */ + break; + + case ATH79_SOC_QCA956X: + if (pdata->phy_if_mode != PHY_INTERFACE_MODE_SGMII) + pdata->mii_bus_dev = &ath79_mdio1_device.dev; + break; + default: pdata->mii_bus_dev = &ath79_mdio0_device.dev; break; @@ -940,10 +1229,10 @@ void __init ath79_register_eth(unsigned int id) /* Reset the device */ ath79_device_reset_set(pdata->reset_bit); - mdelay(100); + msleep(100); ath79_device_reset_clear(pdata->reset_bit); - mdelay(100); + msleep(100); platform_device_register(pdev); ath79_eth_instance++; @@ -954,35 +1243,42 @@ void __init ath79_set_mac_base(unsigned char *mac) memcpy(ath79_mac_base, mac, ETH_ALEN); } -void __init ath79_parse_mac_addr(char *mac_str) +void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac) { - u8 tmp[ETH_ALEN]; int t; t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", - &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); if (t != ETH_ALEN) t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", - &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); - if (t == ETH_ALEN) - ath79_set_mac_base(tmp); - else - printk(KERN_DEBUG "ar71xx: failed to parse mac address " - "\"%s\"\n", mac_str); + if (t != ETH_ALEN || !is_valid_ether_addr(mac)) { + memset(mac, 0, ETH_ALEN); + printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n", + mac_str); + } +} + +static void __init ath79_set_mac_base_ascii(char *str) +{ + u8 mac[ETH_ALEN]; + + ath79_parse_ascii_mac(str, mac); + ath79_set_mac_base(mac); } static int __init ath79_ethaddr_setup(char *str) { - ath79_parse_mac_addr(str); + ath79_set_mac_base_ascii(str); return 1; } __setup("ethaddr=", ath79_ethaddr_setup); static int __init ath79_kmac_setup(char *str) { - ath79_parse_mac_addr(str); + ath79_set_mac_base_ascii(str); return 1; } __setup("kmac=", ath79_kmac_setup); @@ -992,7 +1288,10 @@ void __init ath79_init_mac(unsigned char *dst, const unsigned char *src, { int t; - if (!is_valid_ether_addr(src)) { + if (!dst) + return; + + if (!src || !is_valid_ether_addr(src)) { memset(dst, '\0', ETH_ALEN); return; } @@ -1012,7 +1311,10 @@ void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src) { int i; - if (!is_valid_ether_addr(src)) { + if (!dst) + return; + + if (!src || !is_valid_ether_addr(src)) { memset(dst, '\0', ETH_ALEN); return; }