X-Git-Url: https://git.archive.openwrt.org/?p=openwrt.git;a=blobdiff_plain;f=package%2Fkernel%2Fmac80211%2Fpatches%2F300-pending_work.patch;h=f70ac791046867f1524b6b4de0e869fee9b837bd;hp=4532a03d570888ee912cd071bac793dc7d05cb3e;hb=0f6201a699bc024bf4593a19ca5a2b05b2c78d7e;hpb=aa9c777a930d139484e38588baa52c6737f6b9e3 diff --git a/package/kernel/mac80211/patches/300-pending_work.patch b/package/kernel/mac80211/patches/300-pending_work.patch index 4532a03d57..f70ac79104 100644 --- a/package/kernel/mac80211/patches/300-pending_work.patch +++ b/package/kernel/mac80211/patches/300-pending_work.patch @@ -67,7 +67,15 @@ obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c -@@ -26,6 +26,7 @@ +@@ -17,6 +17,7 @@ + #include "hw.h" + #include "ar9003_mac.h" + #include "ar9003_2p2_initvals.h" ++#include "ar9003_buffalo_initvals.h" + #include "ar9485_initvals.h" + #include "ar9340_initvals.h" + #include "ar9330_1p1_initvals.h" +@@ -26,6 +27,7 @@ #include "ar9462_2p0_initvals.h" #include "ar9462_2p1_initvals.h" #include "ar9565_1p0_initvals.h" @@ -75,7 +83,20 @@ /* General hardware code for the AR9003 hadware family */ -@@ -187,17 +188,17 @@ static void ar9003_hw_init_mode_regs(str +@@ -148,7 +150,11 @@ static void ar9003_hw_init_mode_regs(str + ar9340Modes_high_ob_db_tx_gain_table_1p0); + + INIT_INI_ARRAY(&ah->iniModesFastClock, +- ar9340Modes_fast_clock_1p0); ++ ar9340Modes_fast_clock_1p0); ++ INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ++ ar9340_1p0_baseband_core_txfir_coeff_japan_2484); ++ INIT_INI_ARRAY(&ah->ini_dfs, ++ ar9340_1p0_baseband_postamble_dfs_channel); + + if (!ah->is_clk_25mhz) + INIT_INI_ARRAY(&ah->iniAdditional, +@@ -187,17 +193,17 @@ static void ar9003_hw_init_mode_regs(str INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ar9485_1_1_baseband_core_txfir_coeff_japan_2484); @@ -104,7 +125,7 @@ } else if (AR_SREV_9462_21(ah)) { INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p1_mac_core); -@@ -223,6 +224,10 @@ static void ar9003_hw_init_mode_regs(str +@@ -223,6 +229,10 @@ static void ar9003_hw_init_mode_regs(str ar9462_2p1_modes_fast_clock); INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ar9462_2p1_baseband_core_txfir_coeff_japan_2484); @@ -115,7 +136,7 @@ } else if (AR_SREV_9462_20(ah)) { INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core); -@@ -247,18 +252,18 @@ static void ar9003_hw_init_mode_regs(str +@@ -247,18 +257,18 @@ static void ar9003_hw_init_mode_regs(str ar9462_2p0_soc_postamble); INIT_INI_ARRAY(&ah->iniModesRxGain, @@ -138,10 +159,16 @@ INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ar9462_2p0_baseband_core_txfir_coeff_japan_2484); -@@ -331,6 +336,41 @@ static void ar9003_hw_init_mode_regs(str +@@ -330,7 +340,46 @@ static void ar9003_hw_init_mode_regs(str + ar9580_1p0_low_ob_db_tx_gain_table); INIT_INI_ARRAY(&ah->iniModesFastClock, - ar9580_1p0_modes_fast_clock); +- ar9580_1p0_modes_fast_clock); ++ ar9580_1p0_modes_fast_clock); ++ INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ++ ar9580_1p0_baseband_core_txfir_coeff_japan_2484); ++ INIT_INI_ARRAY(&ah->ini_dfs, ++ ar9580_1p0_baseband_postamble_dfs_channel); + } else if (AR_SREV_9565_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], + ar9565_1p1_mac_core); @@ -180,7 +207,20 @@ } else if (AR_SREV_9565(ah)) { INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9565_1p0_mac_core); -@@ -440,7 +480,10 @@ static void ar9003_tx_gain_table_mode0(s +@@ -411,7 +460,11 @@ static void ar9003_hw_init_mode_regs(str + + /* Fast clock modal settings */ + INIT_INI_ARRAY(&ah->iniModesFastClock, +- ar9300Modes_fast_clock_2p2); ++ ar9300Modes_fast_clock_2p2); ++ INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ++ ar9300_2p2_baseband_core_txfir_coeff_japan_2484); ++ INIT_INI_ARRAY(&ah->ini_dfs, ++ ar9300_2p2_baseband_postamble_dfs_channel); + } + } + +@@ -440,7 +493,10 @@ static void ar9003_tx_gain_table_mode0(s ar9462_2p1_modes_low_ob_db_tx_gain); else if (AR_SREV_9462_20(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, @@ -192,7 +232,7 @@ else if (AR_SREV_9565(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9565_1p0_modes_low_ob_db_tx_gain_table); -@@ -474,7 +517,10 @@ static void ar9003_tx_gain_table_mode1(s +@@ -474,7 +530,10 @@ static void ar9003_tx_gain_table_mode1(s ar9462_2p1_modes_high_ob_db_tx_gain); else if (AR_SREV_9462_20(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, @@ -204,7 +244,7 @@ else if (AR_SREV_9565(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9565_1p0_modes_high_ob_db_tx_gain_table); -@@ -500,6 +546,9 @@ static void ar9003_tx_gain_table_mode2(s +@@ -500,6 +559,9 @@ static void ar9003_tx_gain_table_mode2(s else if (AR_SREV_9580(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9580_1p0_low_ob_db_tx_gain_table); @@ -214,7 +254,7 @@ else if (AR_SREV_9565(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9565_1p0_modes_low_ob_db_tx_gain_table); -@@ -525,6 +574,9 @@ static void ar9003_tx_gain_table_mode3(s +@@ -525,12 +587,20 @@ static void ar9003_tx_gain_table_mode3(s else if (AR_SREV_9580(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9580_1p0_high_power_tx_gain_table); @@ -224,7 +264,21 @@ else if (AR_SREV_9565(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9565_1p0_modes_high_power_tx_gain_table); -@@ -546,7 +598,7 @@ static void ar9003_tx_gain_table_mode4(s +- else +- INIT_INI_ARRAY(&ah->iniModesTxGain, +- ar9300Modes_high_power_tx_gain_table_2p2); ++ else { ++ if (ah->config.tx_gain_buffalo) ++ INIT_INI_ARRAY(&ah->iniModesTxGain, ++ ar9300Modes_high_power_tx_gain_table_buffalo); ++ else ++ INIT_INI_ARRAY(&ah->iniModesTxGain, ++ ar9300Modes_high_power_tx_gain_table_2p2); ++ } + } + + static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) +@@ -546,7 +616,7 @@ static void ar9003_tx_gain_table_mode4(s ar9462_2p1_modes_mix_ob_db_tx_gain); else if (AR_SREV_9462_20(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, @@ -233,7 +287,7 @@ else INIT_INI_ARRAY(&ah->iniModesTxGain, ar9300Modes_mixed_ob_db_tx_gain_table_2p2); -@@ -581,6 +633,13 @@ static void ar9003_tx_gain_table_mode6(s +@@ -581,6 +651,13 @@ static void ar9003_tx_gain_table_mode6(s ar9580_1p0_type6_tx_gain_table); } @@ -247,7 +301,7 @@ typedef void (*ath_txgain_tab)(struct ath_hw *ah); static void ar9003_tx_gain_table_apply(struct ath_hw *ah) -@@ -593,6 +652,7 @@ static void ar9003_tx_gain_table_apply(s +@@ -593,6 +670,7 @@ static void ar9003_tx_gain_table_apply(s ar9003_tx_gain_table_mode4, ar9003_tx_gain_table_mode5, ar9003_tx_gain_table_mode6, @@ -255,7 +309,7 @@ }; int idx = ar9003_hw_get_tx_gain_idx(ah); -@@ -629,7 +689,10 @@ static void ar9003_rx_gain_table_mode0(s +@@ -629,7 +707,10 @@ static void ar9003_rx_gain_table_mode0(s ar9462_2p1_common_rx_gain); else if (AR_SREV_9462_20(ah)) INIT_INI_ARRAY(&ah->iniModesRxGain, @@ -267,7 +321,7 @@ else if (AR_SREV_9565(ah)) INIT_INI_ARRAY(&ah->iniModesRxGain, ar9565_1p0_Common_rx_gain_table); -@@ -657,7 +720,7 @@ static void ar9003_rx_gain_table_mode1(s +@@ -657,7 +738,7 @@ static void ar9003_rx_gain_table_mode1(s ar9462_2p1_common_wo_xlna_rx_gain); else if (AR_SREV_9462_20(ah)) INIT_INI_ARRAY(&ah->iniModesRxGain, @@ -276,7 +330,7 @@ else if (AR_SREV_9550(ah)) { INIT_INI_ARRAY(&ah->iniModesRxGain, ar955x_1p0_common_wo_xlna_rx_gain_table); -@@ -666,6 +729,9 @@ static void ar9003_rx_gain_table_mode1(s +@@ -666,6 +747,9 @@ static void ar9003_rx_gain_table_mode1(s } else if (AR_SREV_9580(ah)) INIT_INI_ARRAY(&ah->iniModesRxGain, ar9580_1p0_wo_xlna_rx_gain_table); @@ -286,7 +340,7 @@ else if (AR_SREV_9565(ah)) INIT_INI_ARRAY(&ah->iniModesRxGain, ar9565_1p0_common_wo_xlna_rx_gain_table); -@@ -687,7 +753,7 @@ static void ar9003_rx_gain_table_mode2(s +@@ -687,7 +771,7 @@ static void ar9003_rx_gain_table_mode2(s ar9462_2p1_baseband_postamble_5g_xlna); } else if (AR_SREV_9462_20(ah)) { INIT_INI_ARRAY(&ah->iniModesRxGain, @@ -295,7 +349,7 @@ INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, ar9462_2p0_baseband_core_mix_rxgain); INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, -@@ -701,12 +767,12 @@ static void ar9003_rx_gain_table_mode3(s +@@ -701,12 +785,12 @@ static void ar9003_rx_gain_table_mode3(s { if (AR_SREV_9462_21(ah)) { INIT_INI_ARRAY(&ah->iniModesRxGain, @@ -310,7 +364,7 @@ INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, ar9462_2p0_baseband_postamble_5g_xlna); } -@@ -750,6 +816,9 @@ static void ar9003_hw_init_mode_gain_reg +@@ -750,6 +834,9 @@ static void ar9003_hw_init_mode_gain_reg static void ar9003_hw_configpcipowersave(struct ath_hw *ah, bool power_off) { @@ -320,7 +374,7 @@ /* * Increase L1 Entry Latency. Some WB222 boards don't have * this change in eeprom/OTP. -@@ -775,18 +844,13 @@ static void ar9003_hw_configpcipowersave +@@ -775,18 +862,13 @@ static void ar9003_hw_configpcipowersave * Configire PCIE after Ini init. SERDES values now come from ini file * This enables PCIe low power mode. */ @@ -348,523 +402,1282 @@ --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h -@@ -1447,4 +1447,106 @@ static const u32 ar9340_1p0_soc_preamble - {0x00007038, 0x000004c2}, - }; +@@ -18,6 +18,20 @@ + #ifndef INITVALS_9340_H + #define INITVALS_9340_H -+static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = { -+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ -+ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, -+ {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, -+ {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, -+ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, -+ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, -+ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -+ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, -+ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, -+ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, -+ {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, -+ {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400}, -+ {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402}, -+ {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404}, -+ {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603}, -+ {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02}, -+ {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04}, -+ {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20}, -+ {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20}, -+ {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22}, -+ {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24}, -+ {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640}, -+ {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660}, -+ {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861}, -+ {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81}, -+ {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83}, -+ {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84}, -+ {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3}, -+ {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5}, -+ {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9}, -+ {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb}, -+ {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, -+ {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, -+ {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, -+ {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, -+ {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, -+ {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, -+ {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, -+ {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, -+ {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, -+ {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, -+ {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200}, -+ {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202}, -+ {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400}, -+ {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402}, -+ {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404}, -+ {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603}, -+ {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02}, -+ {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04}, -+ {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20}, -+ {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20}, -+ {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22}, -+ {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24}, -+ {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640}, -+ {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660}, -+ {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861}, -+ {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81}, -+ {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83}, -+ {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84}, -+ {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3}, -+ {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5}, -+ {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9}, -+ {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb}, -+ {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, -+ {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, -+ {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, -+ {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, -+ {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, -+ {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, -+ {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, -+ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -+ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -+ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -+ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -+ {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -+ {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, -+ {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, -+ {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501}, -+ {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03}, -+ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, -+ {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04}, -+ {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005}, -+ {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, -+ {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, -+ {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, -+ {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, -+ {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, -+ {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, -+ {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, -+ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, -+ {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4}, -+ {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266}, -+ {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015}, -+ {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000}, -+ {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4}, -+ {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266}, -+ {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011}, -+ {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c}, -+ {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030}, -+}; ++#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble + - #endif /* INITVALS_9340_H */ ---- a/drivers/net/wireless/ath/ath9k/ath9k.h -+++ b/drivers/net/wireless/ath/ath9k/ath9k.h -@@ -459,6 +459,7 @@ void ath_check_ani(struct ath_softc *sc) - int ath_update_survey_stats(struct ath_softc *sc); - void ath_update_survey_nf(struct ath_softc *sc, int channel); - void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); -+void ath_ps_full_sleep(unsigned long data); - - /**********/ - /* BTCOEX */ -@@ -570,6 +571,34 @@ static inline void ath_fill_led_pin(stru - } - #endif - -+/************************/ -+/* Wake on Wireless LAN */ -+/************************/ ++#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble + -+#ifdef CONFIG_ATH9K_WOW -+void ath9k_init_wow(struct ieee80211_hw *hw); -+int ath9k_suspend(struct ieee80211_hw *hw, -+ struct cfg80211_wowlan *wowlan); -+int ath9k_resume(struct ieee80211_hw *hw); -+void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled); -+#else -+static inline void ath9k_init_wow(struct ieee80211_hw *hw) -+{ -+} -+static inline int ath9k_suspend(struct ieee80211_hw *hw, -+ struct cfg80211_wowlan *wowlan) -+{ -+ return 0; -+} -+static inline int ath9k_resume(struct ieee80211_hw *hw) -+{ -+ return 0; -+} -+static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) -+{ -+} -+#endif /* CONFIG_ATH9K_WOW */ ++#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2 + - /*******************************/ - /* Antenna diversity/combining */ - /*******************************/ -@@ -632,15 +661,16 @@ void ath_ant_comb_scan(struct ath_softc - /* Main driver core */ - /********************/ - --#define ATH9K_PCI_CUS198 0x0001 --#define ATH9K_PCI_CUS230 0x0002 --#define ATH9K_PCI_CUS217 0x0004 --#define ATH9K_PCI_CUS252 0x0008 --#define ATH9K_PCI_WOW 0x0010 --#define ATH9K_PCI_BT_ANT_DIV 0x0020 --#define ATH9K_PCI_D3_L1_WAR 0x0040 --#define ATH9K_PCI_AR9565_1ANT 0x0080 --#define ATH9K_PCI_AR9565_2ANT 0x0100 -+#define ATH9K_PCI_CUS198 0x0001 -+#define ATH9K_PCI_CUS230 0x0002 -+#define ATH9K_PCI_CUS217 0x0004 -+#define ATH9K_PCI_CUS252 0x0008 -+#define ATH9K_PCI_WOW 0x0010 -+#define ATH9K_PCI_BT_ANT_DIV 0x0020 -+#define ATH9K_PCI_D3_L1_WAR 0x0040 -+#define ATH9K_PCI_AR9565_1ANT 0x0080 -+#define ATH9K_PCI_AR9565_2ANT 0x0100 -+#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200 - - /* - * Default cache line size, in bytes. -@@ -723,6 +753,7 @@ struct ath_softc { - struct work_struct hw_check_work; - struct work_struct hw_reset_work; - struct completion paprd_complete; -+ wait_queue_head_t tx_wait; - - unsigned int hw_busy_count; - unsigned long sc_flags; -@@ -759,6 +790,7 @@ struct ath_softc { - struct delayed_work tx_complete_work; - struct delayed_work hw_pll_work; - struct timer_list rx_poll_timer; -+ struct timer_list sleep_timer; - - #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT - struct ath_btcoex btcoex; -@@ -783,7 +815,7 @@ struct ath_softc { - bool tx99_state; - s16 tx99_power; - --#ifdef CONFIG_PM_SLEEP -+#ifdef CONFIG_ATH9K_WOW - atomic_t wow_got_bmiss_intr; - atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ - u32 wow_intr_before_sleep; -@@ -946,10 +978,25 @@ struct fft_sample_ht20_40 { - u8 data[SPECTRAL_HT20_40_NUM_BINS]; - } __packed; - --int ath9k_tx99_init(struct ath_softc *sc); --void ath9k_tx99_deinit(struct ath_softc *sc); -+/********/ -+/* TX99 */ -+/********/ ++#define ar9340Common_rx_gain_table_1p0 ar9300Common_rx_gain_table_2p2 + -+#ifdef CONFIG_ATH9K_TX99 -+void ath9k_tx99_init_debug(struct ath_softc *sc); - int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, - struct ath_tx_control *txctl); -+#else -+static inline void ath9k_tx99_init_debug(struct ath_softc *sc) -+{ -+} -+static inline int ath9k_tx99_send(struct ath_softc *sc, -+ struct sk_buff *skb, -+ struct ath_tx_control *txctl) -+{ -+ return 0; -+} -+#endif /* CONFIG_ATH9K_TX99 */ ++#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2 ++ ++#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484 ++ ++#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel ++ + static const u32 ar9340_1p0_radio_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800}, +@@ -100,8 +114,6 @@ static const u32 ar9340Modes_lowest_ob_d + {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, + }; - void ath9k_tasklet(unsigned long data); - int ath_cabq_update(struct ath_softc *); -@@ -966,6 +1013,9 @@ extern bool is_ath9k_unloaded; +-#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2 +- + static const u32 ar9340_1p0_radio_core[][2] = { + /* Addr allmodes */ + {0x00016000, 0x36db6db6}, +@@ -215,16 +227,12 @@ static const u32 ar9340_1p0_radio_core_4 + {0x0000824c, 0x0001e800}, + }; - u8 ath9k_parse_mpdudensity(u8 mpdudensity); - irqreturn_t ath_isr(int irq, void *dev); -+int ath_reset(struct ath_softc *sc); -+void ath_cancel_work(struct ath_softc *sc); -+void ath_restart_work(struct ath_softc *sc); - int ath9k_init_device(u16 devid, struct ath_softc *sc, - const struct ath_bus_ops *bus_ops); - void ath9k_deinit_device(struct ath_softc *sc); ---- a/drivers/net/wireless/ath/ath9k/debug.c -+++ b/drivers/net/wireless/ath/ath9k/debug.c -@@ -1782,111 +1782,6 @@ void ath9k_deinit_debug(struct ath_softc - } - } - --static ssize_t read_file_tx99(struct file *file, char __user *user_buf, -- size_t count, loff_t *ppos) --{ -- struct ath_softc *sc = file->private_data; -- char buf[3]; -- unsigned int len; -- -- len = sprintf(buf, "%d\n", sc->tx99_state); -- return simple_read_from_buffer(user_buf, count, ppos, buf, len); --} -- --static ssize_t write_file_tx99(struct file *file, const char __user *user_buf, -- size_t count, loff_t *ppos) --{ -- struct ath_softc *sc = file->private_data; -- struct ath_common *common = ath9k_hw_common(sc->sc_ah); -- char buf[32]; -- bool start; -- ssize_t len; -- int r; -- -- if (sc->nvifs > 1) -- return -EOPNOTSUPP; -- -- len = min(count, sizeof(buf) - 1); -- if (copy_from_user(buf, user_buf, len)) -- return -EFAULT; -- -- if (strtobool(buf, &start)) -- return -EINVAL; -- -- if (start == sc->tx99_state) { -- if (!start) -- return count; -- ath_dbg(common, XMIT, "Resetting TX99\n"); -- ath9k_tx99_deinit(sc); -- } -- -- if (!start) { -- ath9k_tx99_deinit(sc); -- return count; -- } -- -- r = ath9k_tx99_init(sc); -- if (r) -- return r; -- -- return count; --} -- --static const struct file_operations fops_tx99 = { -- .read = read_file_tx99, -- .write = write_file_tx99, -- .open = simple_open, -- .owner = THIS_MODULE, -- .llseek = default_llseek, --}; -- --static ssize_t read_file_tx99_power(struct file *file, -- char __user *user_buf, -- size_t count, loff_t *ppos) --{ -- struct ath_softc *sc = file->private_data; -- char buf[32]; -- unsigned int len; -- -- len = sprintf(buf, "%d (%d dBm)\n", -- sc->tx99_power, -- sc->tx99_power / 2); -- -- return simple_read_from_buffer(user_buf, count, ppos, buf, len); --} -- --static ssize_t write_file_tx99_power(struct file *file, -- const char __user *user_buf, -- size_t count, loff_t *ppos) --{ -- struct ath_softc *sc = file->private_data; -- int r; -- u8 tx_power; -- -- r = kstrtou8_from_user(user_buf, count, 0, &tx_power); -- if (r) -- return r; -- -- if (tx_power > MAX_RATE_POWER) -- return -EINVAL; -- -- sc->tx99_power = tx_power; -- -- ath9k_ps_wakeup(sc); -- ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power); -- ath9k_ps_restore(sc); +-#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble - -- return count; --} -- --static const struct file_operations fops_tx99_power = { -- .read = read_file_tx99_power, -- .write = write_file_tx99_power, -- .open = simple_open, -- .owner = THIS_MODULE, -- .llseek = default_llseek, --}; +-#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble - - int ath9k_init_debug(struct ath_hw *ah) - { - struct ath_common *common = ath9k_hw_common(ah); -@@ -1903,6 +1798,7 @@ int ath9k_init_debug(struct ath_hw *ah) - #endif - - ath9k_dfs_init_debug(sc); -+ ath9k_tx99_init_debug(sc); - - debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc, - &fops_dma); -@@ -1978,15 +1874,6 @@ int ath9k_init_debug(struct ath_hw *ah) - debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc, - &fops_btcoex); - #endif -- if (config_enabled(CPTCFG_ATH9K_TX99) && -- AR_SREV_9300_20_OR_LATER(ah)) { -- debugfs_create_file("tx99", S_IRUSR | S_IWUSR, -- sc->debug.debugfs_phy, sc, -- &fops_tx99); -- debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR, -- sc->debug.debugfs_phy, sc, -- &fops_tx99_power); -- } - - return 0; - } ---- a/drivers/net/wireless/ath/ath9k/hw.c -+++ b/drivers/net/wireless/ath/ath9k/hw.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - - #include "hw.h" -@@ -454,7 +455,6 @@ static void ath9k_hw_init_config(struct - } - - ah->config.rx_intr_mitigation = true; -- ah->config.pcieSerDesWrite = true; - - /* - * We need this for PCI devices only (Cardbus, PCI, miniPCI) -@@ -1502,8 +1502,9 @@ static bool ath9k_hw_channel_change(stru - int r; - - if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { -- band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan); -- mode_diff = (chan->channelFlags != ah->curchan->channelFlags); -+ u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; -+ band_switch = !!(flags_diff & CHANNEL_5GHZ); -+ mode_diff = !!(flags_diff & ~CHANNEL_HT); - } - - for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { -@@ -1815,7 +1816,7 @@ static int ath9k_hw_do_fastcc(struct ath - * If cross-band fcc is not supoprted, bail out if channelFlags differ. - */ - if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && -- chan->channelFlags != ah->curchan->channelFlags) -+ ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) - goto fail; - - if (!ath9k_hw_check_alive(ah)) -@@ -1856,10 +1857,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st - struct ath9k_hw_cal_data *caldata, bool fastcc) - { - struct ath_common *common = ath9k_hw_common(ah); -+ struct timespec ts; - u32 saveLedState; - u32 saveDefAntenna; - u32 macStaId1; - u64 tsf = 0; -+ s64 usec = 0; - int r; - bool start_mci_reset = false; - bool save_fullsleep = ah->chip_fullsleep; -@@ -1902,10 +1905,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st - - macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; - -- /* For chips on which RTC reset is done, save TSF before it gets cleared */ -- if (AR_SREV_9100(ah) || -- (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) -- tsf = ath9k_hw_gettsf64(ah); -+ /* Save TSF before chip reset, a cold reset clears it */ -+ tsf = ath9k_hw_gettsf64(ah); -+ getrawmonotonic(&ts); -+ usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000; - - saveLedState = REG_READ(ah, AR_CFG_LED) & - (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | -@@ -1938,8 +1941,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st - } - - /* Restore TSF */ -- if (tsf) -- ath9k_hw_settsf64(ah, tsf); -+ getrawmonotonic(&ts); -+ usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec; -+ ath9k_hw_settsf64(ah, tsf + usec); - - if (AR_SREV_9280_20_OR_LATER(ah)) - REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); ---- a/drivers/net/wireless/ath/ath9k/hw.h -+++ b/drivers/net/wireless/ath/ath9k/hw.h -@@ -283,7 +283,6 @@ struct ath9k_ops_config { - int additional_swba_backoff; - int ack_6mb; - u32 cwm_ignore_extcca; -- bool pcieSerDesWrite; - u8 pcie_clock_req; - u32 pcie_waen; - u8 analog_shiftreg; -@@ -316,6 +315,7 @@ struct ath9k_ops_config { - u32 ant_ctrl_comm2g_switch_enable; - bool xatten_margin_cfg; - bool alt_mingainidx; -+ bool no_pll_pwrsave; + static const u32 ar9340_1p0_baseband_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, + {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e}, + {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, +- {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, ++ {0x00009828, 0x06903081, 0x06903081, 0x09103881, 0x09103881}, + {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, + {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c}, + {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4}, +@@ -340,9 +348,9 @@ static const u32 ar9340_1p0_baseband_cor + {0x0000a370, 0x00000000}, + {0x0000a390, 0x00000001}, + {0x0000a394, 0x00000444}, +- {0x0000a398, 0x001f0e0f}, +- {0x0000a39c, 0x0075393f}, +- {0x0000a3a0, 0xb79f6427}, ++ {0x0000a398, 0x00000000}, ++ {0x0000a39c, 0x210d0401}, ++ {0x0000a3a0, 0xab9a7144}, + {0x0000a3a4, 0x00000000}, + {0x0000a3a8, 0xaaaaaaaa}, + {0x0000a3ac, 0x3c466478}, +@@ -714,266 +722,6 @@ static const u32 ar9340Modes_ub124_tx_ga + {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000}, }; - enum ath9k_int { -@@ -920,7 +920,7 @@ struct ath_hw { - /* Enterprise mode cap */ - u32 ent_mode; - --#ifdef CONFIG_PM_SLEEP -+#ifdef CONFIG_ATH9K_WOW - u32 wow_event_mask; - #endif - bool is_clk_25mhz; -@@ -1126,7 +1126,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw - #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */ - - --#ifdef CONFIG_PM_SLEEP -+#ifdef CONFIG_ATH9K_WOW - const char *ath9k_hw_wow_event_to_string(u32 wow_event); - void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, - u8 *user_mask, int pattern_count, ---- a/drivers/net/wireless/ath/ath9k/init.c -+++ b/drivers/net/wireless/ath/ath9k/init.c -@@ -609,6 +609,11 @@ static void ath9k_init_platform(struct a - ah->config.pcie_waen = 0x0040473b; - ath_info(common, "Enable WAR for ASPM D3/L1\n"); - } -+ -+ if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { -+ ah->config.no_pll_pwrsave = true; -+ ath_info(common, "Disable PLL PowerSave\n"); -+ } - } - - static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, -@@ -683,6 +688,7 @@ static int ath9k_init_softc(u16 devid, s - common = ath9k_hw_common(ah); - sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); - sc->tx99_power = MAX_RATE_POWER + 1; -+ init_waitqueue_head(&sc->tx_wait); +-static const u32 ar9340Common_rx_gain_table_1p0[][2] = { +- /* Addr allmodes */ +- {0x0000a000, 0x00010000}, +- {0x0000a004, 0x00030002}, +- {0x0000a008, 0x00050004}, +- {0x0000a00c, 0x00810080}, +- {0x0000a010, 0x00830082}, +- {0x0000a014, 0x01810180}, +- {0x0000a018, 0x01830182}, +- {0x0000a01c, 0x01850184}, +- {0x0000a020, 0x01890188}, +- {0x0000a024, 0x018b018a}, +- {0x0000a028, 0x018d018c}, +- {0x0000a02c, 0x01910190}, +- {0x0000a030, 0x01930192}, +- {0x0000a034, 0x01950194}, +- {0x0000a038, 0x038a0196}, +- {0x0000a03c, 0x038c038b}, +- {0x0000a040, 0x0390038d}, +- {0x0000a044, 0x03920391}, +- {0x0000a048, 0x03940393}, +- {0x0000a04c, 0x03960395}, +- {0x0000a050, 0x00000000}, +- {0x0000a054, 0x00000000}, +- {0x0000a058, 0x00000000}, +- {0x0000a05c, 0x00000000}, +- {0x0000a060, 0x00000000}, +- {0x0000a064, 0x00000000}, +- {0x0000a068, 0x00000000}, +- {0x0000a06c, 0x00000000}, +- {0x0000a070, 0x00000000}, +- {0x0000a074, 0x00000000}, +- {0x0000a078, 0x00000000}, +- {0x0000a07c, 0x00000000}, +- {0x0000a080, 0x22222229}, +- {0x0000a084, 0x1d1d1d1d}, +- {0x0000a088, 0x1d1d1d1d}, +- {0x0000a08c, 0x1d1d1d1d}, +- {0x0000a090, 0x171d1d1d}, +- {0x0000a094, 0x11111717}, +- {0x0000a098, 0x00030311}, +- {0x0000a09c, 0x00000000}, +- {0x0000a0a0, 0x00000000}, +- {0x0000a0a4, 0x00000000}, +- {0x0000a0a8, 0x00000000}, +- {0x0000a0ac, 0x00000000}, +- {0x0000a0b0, 0x00000000}, +- {0x0000a0b4, 0x00000000}, +- {0x0000a0b8, 0x00000000}, +- {0x0000a0bc, 0x00000000}, +- {0x0000a0c0, 0x001f0000}, +- {0x0000a0c4, 0x01000101}, +- {0x0000a0c8, 0x011e011f}, +- {0x0000a0cc, 0x011c011d}, +- {0x0000a0d0, 0x02030204}, +- {0x0000a0d4, 0x02010202}, +- {0x0000a0d8, 0x021f0200}, +- {0x0000a0dc, 0x0302021e}, +- {0x0000a0e0, 0x03000301}, +- {0x0000a0e4, 0x031e031f}, +- {0x0000a0e8, 0x0402031d}, +- {0x0000a0ec, 0x04000401}, +- {0x0000a0f0, 0x041e041f}, +- {0x0000a0f4, 0x0502041d}, +- {0x0000a0f8, 0x05000501}, +- {0x0000a0fc, 0x051e051f}, +- {0x0000a100, 0x06010602}, +- {0x0000a104, 0x061f0600}, +- {0x0000a108, 0x061d061e}, +- {0x0000a10c, 0x07020703}, +- {0x0000a110, 0x07000701}, +- {0x0000a114, 0x00000000}, +- {0x0000a118, 0x00000000}, +- {0x0000a11c, 0x00000000}, +- {0x0000a120, 0x00000000}, +- {0x0000a124, 0x00000000}, +- {0x0000a128, 0x00000000}, +- {0x0000a12c, 0x00000000}, +- {0x0000a130, 0x00000000}, +- {0x0000a134, 0x00000000}, +- {0x0000a138, 0x00000000}, +- {0x0000a13c, 0x00000000}, +- {0x0000a140, 0x001f0000}, +- {0x0000a144, 0x01000101}, +- {0x0000a148, 0x011e011f}, +- {0x0000a14c, 0x011c011d}, +- {0x0000a150, 0x02030204}, +- {0x0000a154, 0x02010202}, +- {0x0000a158, 0x021f0200}, +- {0x0000a15c, 0x0302021e}, +- {0x0000a160, 0x03000301}, +- {0x0000a164, 0x031e031f}, +- {0x0000a168, 0x0402031d}, +- {0x0000a16c, 0x04000401}, +- {0x0000a170, 0x041e041f}, +- {0x0000a174, 0x0502041d}, +- {0x0000a178, 0x05000501}, +- {0x0000a17c, 0x051e051f}, +- {0x0000a180, 0x06010602}, +- {0x0000a184, 0x061f0600}, +- {0x0000a188, 0x061d061e}, +- {0x0000a18c, 0x07020703}, +- {0x0000a190, 0x07000701}, +- {0x0000a194, 0x00000000}, +- {0x0000a198, 0x00000000}, +- {0x0000a19c, 0x00000000}, +- {0x0000a1a0, 0x00000000}, +- {0x0000a1a4, 0x00000000}, +- {0x0000a1a8, 0x00000000}, +- {0x0000a1ac, 0x00000000}, +- {0x0000a1b0, 0x00000000}, +- {0x0000a1b4, 0x00000000}, +- {0x0000a1b8, 0x00000000}, +- {0x0000a1bc, 0x00000000}, +- {0x0000a1c0, 0x00000000}, +- {0x0000a1c4, 0x00000000}, +- {0x0000a1c8, 0x00000000}, +- {0x0000a1cc, 0x00000000}, +- {0x0000a1d0, 0x00000000}, +- {0x0000a1d4, 0x00000000}, +- {0x0000a1d8, 0x00000000}, +- {0x0000a1dc, 0x00000000}, +- {0x0000a1e0, 0x00000000}, +- {0x0000a1e4, 0x00000000}, +- {0x0000a1e8, 0x00000000}, +- {0x0000a1ec, 0x00000000}, +- {0x0000a1f0, 0x00000396}, +- {0x0000a1f4, 0x00000396}, +- {0x0000a1f8, 0x00000396}, +- {0x0000a1fc, 0x00000196}, +- {0x0000b000, 0x00010000}, +- {0x0000b004, 0x00030002}, +- {0x0000b008, 0x00050004}, +- {0x0000b00c, 0x00810080}, +- {0x0000b010, 0x00830082}, +- {0x0000b014, 0x01810180}, +- {0x0000b018, 0x01830182}, +- {0x0000b01c, 0x01850184}, +- {0x0000b020, 0x02810280}, +- {0x0000b024, 0x02830282}, +- {0x0000b028, 0x02850284}, +- {0x0000b02c, 0x02890288}, +- {0x0000b030, 0x028b028a}, +- {0x0000b034, 0x0388028c}, +- {0x0000b038, 0x038a0389}, +- {0x0000b03c, 0x038c038b}, +- {0x0000b040, 0x0390038d}, +- {0x0000b044, 0x03920391}, +- {0x0000b048, 0x03940393}, +- {0x0000b04c, 0x03960395}, +- {0x0000b050, 0x00000000}, +- {0x0000b054, 0x00000000}, +- {0x0000b058, 0x00000000}, +- {0x0000b05c, 0x00000000}, +- {0x0000b060, 0x00000000}, +- {0x0000b064, 0x00000000}, +- {0x0000b068, 0x00000000}, +- {0x0000b06c, 0x00000000}, +- {0x0000b070, 0x00000000}, +- {0x0000b074, 0x00000000}, +- {0x0000b078, 0x00000000}, +- {0x0000b07c, 0x00000000}, +- {0x0000b080, 0x23232323}, +- {0x0000b084, 0x21232323}, +- {0x0000b088, 0x19191c1e}, +- {0x0000b08c, 0x12141417}, +- {0x0000b090, 0x07070e0e}, +- {0x0000b094, 0x03030305}, +- {0x0000b098, 0x00000003}, +- {0x0000b09c, 0x00000000}, +- {0x0000b0a0, 0x00000000}, +- {0x0000b0a4, 0x00000000}, +- {0x0000b0a8, 0x00000000}, +- {0x0000b0ac, 0x00000000}, +- {0x0000b0b0, 0x00000000}, +- {0x0000b0b4, 0x00000000}, +- {0x0000b0b8, 0x00000000}, +- {0x0000b0bc, 0x00000000}, +- {0x0000b0c0, 0x003f0020}, +- {0x0000b0c4, 0x00400041}, +- {0x0000b0c8, 0x0140005f}, +- {0x0000b0cc, 0x0160015f}, +- {0x0000b0d0, 0x017e017f}, +- {0x0000b0d4, 0x02410242}, +- {0x0000b0d8, 0x025f0240}, +- {0x0000b0dc, 0x027f0260}, +- {0x0000b0e0, 0x0341027e}, +- {0x0000b0e4, 0x035f0340}, +- {0x0000b0e8, 0x037f0360}, +- {0x0000b0ec, 0x04400441}, +- {0x0000b0f0, 0x0460045f}, +- {0x0000b0f4, 0x0541047f}, +- {0x0000b0f8, 0x055f0540}, +- {0x0000b0fc, 0x057f0560}, +- {0x0000b100, 0x06400641}, +- {0x0000b104, 0x0660065f}, +- {0x0000b108, 0x067e067f}, +- {0x0000b10c, 0x07410742}, +- {0x0000b110, 0x075f0740}, +- {0x0000b114, 0x077f0760}, +- {0x0000b118, 0x07800781}, +- {0x0000b11c, 0x07a0079f}, +- {0x0000b120, 0x07c107bf}, +- {0x0000b124, 0x000007c0}, +- {0x0000b128, 0x00000000}, +- {0x0000b12c, 0x00000000}, +- {0x0000b130, 0x00000000}, +- {0x0000b134, 0x00000000}, +- {0x0000b138, 0x00000000}, +- {0x0000b13c, 0x00000000}, +- {0x0000b140, 0x003f0020}, +- {0x0000b144, 0x00400041}, +- {0x0000b148, 0x0140005f}, +- {0x0000b14c, 0x0160015f}, +- {0x0000b150, 0x017e017f}, +- {0x0000b154, 0x02410242}, +- {0x0000b158, 0x025f0240}, +- {0x0000b15c, 0x027f0260}, +- {0x0000b160, 0x0341027e}, +- {0x0000b164, 0x035f0340}, +- {0x0000b168, 0x037f0360}, +- {0x0000b16c, 0x04400441}, +- {0x0000b170, 0x0460045f}, +- {0x0000b174, 0x0541047f}, +- {0x0000b178, 0x055f0540}, +- {0x0000b17c, 0x057f0560}, +- {0x0000b180, 0x06400641}, +- {0x0000b184, 0x0660065f}, +- {0x0000b188, 0x067e067f}, +- {0x0000b18c, 0x07410742}, +- {0x0000b190, 0x075f0740}, +- {0x0000b194, 0x077f0760}, +- {0x0000b198, 0x07800781}, +- {0x0000b19c, 0x07a0079f}, +- {0x0000b1a0, 0x07c107bf}, +- {0x0000b1a4, 0x000007c0}, +- {0x0000b1a8, 0x00000000}, +- {0x0000b1ac, 0x00000000}, +- {0x0000b1b0, 0x00000000}, +- {0x0000b1b4, 0x00000000}, +- {0x0000b1b8, 0x00000000}, +- {0x0000b1bc, 0x00000000}, +- {0x0000b1c0, 0x00000000}, +- {0x0000b1c4, 0x00000000}, +- {0x0000b1c8, 0x00000000}, +- {0x0000b1cc, 0x00000000}, +- {0x0000b1d0, 0x00000000}, +- {0x0000b1d4, 0x00000000}, +- {0x0000b1d8, 0x00000000}, +- {0x0000b1dc, 0x00000000}, +- {0x0000b1e0, 0x00000000}, +- {0x0000b1e4, 0x00000000}, +- {0x0000b1e8, 0x00000000}, +- {0x0000b1ec, 0x00000000}, +- {0x0000b1f0, 0x00000396}, +- {0x0000b1f4, 0x00000396}, +- {0x0000b1f8, 0x00000396}, +- {0x0000b1fc, 0x00000196}, +-}; +- + static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, +@@ -1437,8 +1185,6 @@ static const u32 ar9340_1p0_mac_core[][2 + {0x000083d0, 0x000101ff}, + }; + +-#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2 +- + static const u32 ar9340_1p0_soc_preamble[][2] = { + /* Addr allmodes */ + {0x00007008, 0x00000000}, +@@ -1447,4 +1193,106 @@ static const u32 ar9340_1p0_soc_preamble + {0x00007038, 0x000004c2}, + }; + ++static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = { ++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ ++ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, ++ {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, ++ {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, ++ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, ++ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, ++ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, ++ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, ++ {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, ++ {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400}, ++ {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402}, ++ {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404}, ++ {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603}, ++ {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02}, ++ {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04}, ++ {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20}, ++ {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20}, ++ {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22}, ++ {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24}, ++ {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640}, ++ {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660}, ++ {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861}, ++ {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81}, ++ {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83}, ++ {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84}, ++ {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3}, ++ {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5}, ++ {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9}, ++ {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb}, ++ {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, ++ {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, ++ {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, ++ {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, ++ {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, ++ {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, ++ {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec}, ++ {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, ++ {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, ++ {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, ++ {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200}, ++ {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202}, ++ {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400}, ++ {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402}, ++ {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404}, ++ {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603}, ++ {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02}, ++ {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04}, ++ {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20}, ++ {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20}, ++ {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22}, ++ {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24}, ++ {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640}, ++ {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660}, ++ {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861}, ++ {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81}, ++ {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83}, ++ {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84}, ++ {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3}, ++ {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5}, ++ {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9}, ++ {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb}, ++ {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, ++ {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, ++ {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, ++ {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, ++ {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, ++ {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, ++ {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, ++ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, ++ {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, ++ {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501}, ++ {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03}, ++ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, ++ {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04}, ++ {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005}, ++ {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, ++ {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, ++ {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, ++ {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, ++ {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, ++ {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, ++ {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, ++ {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4}, ++ {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266}, ++ {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015}, ++ {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000}, ++ {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4}, ++ {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266}, ++ {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011}, ++ {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c}, ++ {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030}, ++}; ++ + #endif /* INITVALS_9340_H */ +--- a/drivers/net/wireless/ath/ath9k/ath9k.h ++++ b/drivers/net/wireless/ath/ath9k/ath9k.h +@@ -459,6 +459,7 @@ void ath_check_ani(struct ath_softc *sc) + int ath_update_survey_stats(struct ath_softc *sc); + void ath_update_survey_nf(struct ath_softc *sc, int channel); + void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); ++void ath_ps_full_sleep(unsigned long data); + + /**********/ + /* BTCOEX */ +@@ -476,20 +477,19 @@ enum bt_op_flags { + }; + + struct ath_btcoex { +- bool hw_timer_enabled; + spinlock_t btcoex_lock; + struct timer_list period_timer; /* Timer for BT period */ ++ struct timer_list no_stomp_timer; + u32 bt_priority_cnt; + unsigned long bt_priority_time; + unsigned long op_flags; + int bt_stomp_type; /* Types of BT stomping */ +- u32 btcoex_no_stomp; /* in usec */ ++ u32 btcoex_no_stomp; /* in msec */ + u32 btcoex_period; /* in msec */ +- u32 btscan_no_stomp; /* in usec */ ++ u32 btscan_no_stomp; /* in msec */ + u32 duty_cycle; + u32 bt_wait_time; + int rssi_count; +- struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ + struct ath_mci_profile mci; + u8 stomp_audio; + }; +@@ -570,6 +570,34 @@ static inline void ath_fill_led_pin(stru + } + #endif + ++/************************/ ++/* Wake on Wireless LAN */ ++/************************/ ++ ++#ifdef CONFIG_ATH9K_WOW ++void ath9k_init_wow(struct ieee80211_hw *hw); ++int ath9k_suspend(struct ieee80211_hw *hw, ++ struct cfg80211_wowlan *wowlan); ++int ath9k_resume(struct ieee80211_hw *hw); ++void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled); ++#else ++static inline void ath9k_init_wow(struct ieee80211_hw *hw) ++{ ++} ++static inline int ath9k_suspend(struct ieee80211_hw *hw, ++ struct cfg80211_wowlan *wowlan) ++{ ++ return 0; ++} ++static inline int ath9k_resume(struct ieee80211_hw *hw) ++{ ++ return 0; ++} ++static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) ++{ ++} ++#endif /* CONFIG_ATH9K_WOW */ ++ + /*******************************/ + /* Antenna diversity/combining */ + /*******************************/ +@@ -632,15 +660,16 @@ void ath_ant_comb_scan(struct ath_softc + /* Main driver core */ + /********************/ + +-#define ATH9K_PCI_CUS198 0x0001 +-#define ATH9K_PCI_CUS230 0x0002 +-#define ATH9K_PCI_CUS217 0x0004 +-#define ATH9K_PCI_CUS252 0x0008 +-#define ATH9K_PCI_WOW 0x0010 +-#define ATH9K_PCI_BT_ANT_DIV 0x0020 +-#define ATH9K_PCI_D3_L1_WAR 0x0040 +-#define ATH9K_PCI_AR9565_1ANT 0x0080 +-#define ATH9K_PCI_AR9565_2ANT 0x0100 ++#define ATH9K_PCI_CUS198 0x0001 ++#define ATH9K_PCI_CUS230 0x0002 ++#define ATH9K_PCI_CUS217 0x0004 ++#define ATH9K_PCI_CUS252 0x0008 ++#define ATH9K_PCI_WOW 0x0010 ++#define ATH9K_PCI_BT_ANT_DIV 0x0020 ++#define ATH9K_PCI_D3_L1_WAR 0x0040 ++#define ATH9K_PCI_AR9565_1ANT 0x0080 ++#define ATH9K_PCI_AR9565_2ANT 0x0100 ++#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200 + + /* + * Default cache line size, in bytes. +@@ -723,6 +752,7 @@ struct ath_softc { + struct work_struct hw_check_work; + struct work_struct hw_reset_work; + struct completion paprd_complete; ++ wait_queue_head_t tx_wait; + + unsigned int hw_busy_count; + unsigned long sc_flags; +@@ -759,6 +789,7 @@ struct ath_softc { + struct delayed_work tx_complete_work; + struct delayed_work hw_pll_work; + struct timer_list rx_poll_timer; ++ struct timer_list sleep_timer; + + #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT + struct ath_btcoex btcoex; +@@ -783,7 +814,7 @@ struct ath_softc { + bool tx99_state; + s16 tx99_power; + +-#ifdef CONFIG_PM_SLEEP ++#ifdef CONFIG_ATH9K_WOW + atomic_t wow_got_bmiss_intr; + atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ + u32 wow_intr_before_sleep; +@@ -946,10 +977,25 @@ struct fft_sample_ht20_40 { + u8 data[SPECTRAL_HT20_40_NUM_BINS]; + } __packed; + +-int ath9k_tx99_init(struct ath_softc *sc); +-void ath9k_tx99_deinit(struct ath_softc *sc); ++/********/ ++/* TX99 */ ++/********/ ++ ++#ifdef CONFIG_ATH9K_TX99 ++void ath9k_tx99_init_debug(struct ath_softc *sc); + int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, + struct ath_tx_control *txctl); ++#else ++static inline void ath9k_tx99_init_debug(struct ath_softc *sc) ++{ ++} ++static inline int ath9k_tx99_send(struct ath_softc *sc, ++ struct sk_buff *skb, ++ struct ath_tx_control *txctl) ++{ ++ return 0; ++} ++#endif /* CONFIG_ATH9K_TX99 */ + + void ath9k_tasklet(unsigned long data); + int ath_cabq_update(struct ath_softc *); +@@ -966,6 +1012,9 @@ extern bool is_ath9k_unloaded; + + u8 ath9k_parse_mpdudensity(u8 mpdudensity); + irqreturn_t ath_isr(int irq, void *dev); ++int ath_reset(struct ath_softc *sc); ++void ath_cancel_work(struct ath_softc *sc); ++void ath_restart_work(struct ath_softc *sc); + int ath9k_init_device(u16 devid, struct ath_softc *sc, + const struct ath_bus_ops *bus_ops); + void ath9k_deinit_device(struct ath_softc *sc); +--- a/drivers/net/wireless/ath/ath9k/debug.c ++++ b/drivers/net/wireless/ath/ath9k/debug.c +@@ -1782,111 +1782,6 @@ void ath9k_deinit_debug(struct ath_softc + } + } + +-static ssize_t read_file_tx99(struct file *file, char __user *user_buf, +- size_t count, loff_t *ppos) +-{ +- struct ath_softc *sc = file->private_data; +- char buf[3]; +- unsigned int len; +- +- len = sprintf(buf, "%d\n", sc->tx99_state); +- return simple_read_from_buffer(user_buf, count, ppos, buf, len); +-} +- +-static ssize_t write_file_tx99(struct file *file, const char __user *user_buf, +- size_t count, loff_t *ppos) +-{ +- struct ath_softc *sc = file->private_data; +- struct ath_common *common = ath9k_hw_common(sc->sc_ah); +- char buf[32]; +- bool start; +- ssize_t len; +- int r; +- +- if (sc->nvifs > 1) +- return -EOPNOTSUPP; +- +- len = min(count, sizeof(buf) - 1); +- if (copy_from_user(buf, user_buf, len)) +- return -EFAULT; +- +- if (strtobool(buf, &start)) +- return -EINVAL; +- +- if (start == sc->tx99_state) { +- if (!start) +- return count; +- ath_dbg(common, XMIT, "Resetting TX99\n"); +- ath9k_tx99_deinit(sc); +- } +- +- if (!start) { +- ath9k_tx99_deinit(sc); +- return count; +- } +- +- r = ath9k_tx99_init(sc); +- if (r) +- return r; +- +- return count; +-} +- +-static const struct file_operations fops_tx99 = { +- .read = read_file_tx99, +- .write = write_file_tx99, +- .open = simple_open, +- .owner = THIS_MODULE, +- .llseek = default_llseek, +-}; +- +-static ssize_t read_file_tx99_power(struct file *file, +- char __user *user_buf, +- size_t count, loff_t *ppos) +-{ +- struct ath_softc *sc = file->private_data; +- char buf[32]; +- unsigned int len; +- +- len = sprintf(buf, "%d (%d dBm)\n", +- sc->tx99_power, +- sc->tx99_power / 2); +- +- return simple_read_from_buffer(user_buf, count, ppos, buf, len); +-} +- +-static ssize_t write_file_tx99_power(struct file *file, +- const char __user *user_buf, +- size_t count, loff_t *ppos) +-{ +- struct ath_softc *sc = file->private_data; +- int r; +- u8 tx_power; +- +- r = kstrtou8_from_user(user_buf, count, 0, &tx_power); +- if (r) +- return r; +- +- if (tx_power > MAX_RATE_POWER) +- return -EINVAL; +- +- sc->tx99_power = tx_power; +- +- ath9k_ps_wakeup(sc); +- ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power); +- ath9k_ps_restore(sc); +- +- return count; +-} +- +-static const struct file_operations fops_tx99_power = { +- .read = read_file_tx99_power, +- .write = write_file_tx99_power, +- .open = simple_open, +- .owner = THIS_MODULE, +- .llseek = default_llseek, +-}; +- + int ath9k_init_debug(struct ath_hw *ah) + { + struct ath_common *common = ath9k_hw_common(ah); +@@ -1903,6 +1798,7 @@ int ath9k_init_debug(struct ath_hw *ah) + #endif + + ath9k_dfs_init_debug(sc); ++ ath9k_tx99_init_debug(sc); + + debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc, + &fops_dma); +@@ -1978,15 +1874,6 @@ int ath9k_init_debug(struct ath_hw *ah) + debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc, + &fops_btcoex); + #endif +- if (config_enabled(CPTCFG_ATH9K_TX99) && +- AR_SREV_9300_20_OR_LATER(ah)) { +- debugfs_create_file("tx99", S_IRUSR | S_IWUSR, +- sc->debug.debugfs_phy, sc, +- &fops_tx99); +- debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR, +- sc->debug.debugfs_phy, sc, +- &fops_tx99_power); +- } + + return 0; + } +--- a/drivers/net/wireless/ath/ath9k/hw.c ++++ b/drivers/net/wireless/ath/ath9k/hw.c +@@ -17,6 +17,8 @@ + #include + #include + #include ++#include ++#include + #include + + #include "hw.h" +@@ -438,23 +440,13 @@ static bool ath9k_hw_chip_test(struct at + + static void ath9k_hw_init_config(struct ath_hw *ah) + { +- int i; +- + ah->config.dma_beacon_response_time = 1; + ah->config.sw_beacon_response_time = 6; +- ah->config.additional_swba_backoff = 0; + ah->config.ack_6mb = 0x0; + ah->config.cwm_ignore_extcca = 0; +- ah->config.pcie_clock_req = 0; + ah->config.analog_shiftreg = 1; + +- for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { +- ah->config.spurchans[i][0] = AR_NO_SPUR; +- ah->config.spurchans[i][1] = AR_NO_SPUR; +- } +- + ah->config.rx_intr_mitigation = true; +- ah->config.pcieSerDesWrite = true; + + /* + * We need this for PCI devices only (Cardbus, PCI, miniPCI) +@@ -486,7 +478,6 @@ static void ath9k_hw_init_defaults(struc + ah->hw_version.magic = AR5416_MAGIC; + ah->hw_version.subvendorid = 0; + +- ah->atim_window = 0; + ah->sta_id1_defaults = + AR_STA_ID1_CRPT_MIC_ENABLE | + AR_STA_ID1_MCAST_KSRCH; +@@ -549,11 +540,11 @@ static int ath9k_hw_post_init(struct ath + * EEPROM needs to be initialized before we do this. + * This is required for regulatory compliance. + */ +- if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { ++ if (AR_SREV_9300_20_OR_LATER(ah)) { + u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); + if ((regdmn & 0xF0) == CTL_FCC) { +- ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ; +- ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ; ++ ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; ++ ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; + } + } + +@@ -1502,8 +1493,9 @@ static bool ath9k_hw_channel_change(stru + int r; + + if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { +- band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan); +- mode_diff = (chan->channelFlags != ah->curchan->channelFlags); ++ u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; ++ band_switch = !!(flags_diff & CHANNEL_5GHZ); ++ mode_diff = !!(flags_diff & ~CHANNEL_HT); + } + + for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { +@@ -1815,7 +1807,7 @@ static int ath9k_hw_do_fastcc(struct ath + * If cross-band fcc is not supoprted, bail out if channelFlags differ. + */ + if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && +- chan->channelFlags != ah->curchan->channelFlags) ++ ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) + goto fail; + + if (!ath9k_hw_check_alive(ah)) +@@ -1856,10 +1848,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st + struct ath9k_hw_cal_data *caldata, bool fastcc) + { + struct ath_common *common = ath9k_hw_common(ah); ++ struct timespec ts; + u32 saveLedState; + u32 saveDefAntenna; + u32 macStaId1; + u64 tsf = 0; ++ s64 usec = 0; + int r; + bool start_mci_reset = false; + bool save_fullsleep = ah->chip_fullsleep; +@@ -1902,10 +1896,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st + + macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; + +- /* For chips on which RTC reset is done, save TSF before it gets cleared */ +- if (AR_SREV_9100(ah) || +- (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) +- tsf = ath9k_hw_gettsf64(ah); ++ /* Save TSF before chip reset, a cold reset clears it */ ++ tsf = ath9k_hw_gettsf64(ah); ++ getrawmonotonic(&ts); ++ usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000; + + saveLedState = REG_READ(ah, AR_CFG_LED) & + (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | +@@ -1938,8 +1932,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st + } + + /* Restore TSF */ +- if (tsf) +- ath9k_hw_settsf64(ah, tsf); ++ getrawmonotonic(&ts); ++ usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec; ++ ath9k_hw_settsf64(ah, tsf + usec); + + if (AR_SREV_9280_20_OR_LATER(ah)) + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); +@@ -2261,9 +2256,6 @@ void ath9k_hw_beaconinit(struct ath_hw * + case NL80211_IFTYPE_ADHOC: + REG_SET_BIT(ah, AR_TXCFG, + AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); +- REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + +- TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); +- flags |= AR_NDP_TIMER_EN; + case NL80211_IFTYPE_MESH_POINT: + case NL80211_IFTYPE_AP: + REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); +@@ -2284,7 +2276,6 @@ void ath9k_hw_beaconinit(struct ath_hw * + REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); + REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); + REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); +- REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); + + REGWRITE_BUFFER_FLUSH(ah); + +@@ -2301,12 +2292,9 @@ void ath9k_hw_set_sta_beacon_timers(stru + + ENABLE_REGWRITE_BUFFER(ah); + +- REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); +- +- REG_WRITE(ah, AR_BEACON_PERIOD, +- TU_TO_USEC(bs->bs_intval)); +- REG_WRITE(ah, AR_DMA_BEACON_PERIOD, +- TU_TO_USEC(bs->bs_intval)); ++ REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); ++ REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); ++ REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); + + REGWRITE_BUFFER_FLUSH(ah); + +@@ -2334,9 +2322,8 @@ void ath9k_hw_set_sta_beacon_timers(stru + + ENABLE_REGWRITE_BUFFER(ah); + +- REG_WRITE(ah, AR_NEXT_DTIM, +- TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); +- REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); ++ REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); ++ REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); + + REG_WRITE(ah, AR_SLEEP1, + SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) +@@ -2350,8 +2337,8 @@ void ath9k_hw_set_sta_beacon_timers(stru + REG_WRITE(ah, AR_SLEEP2, + SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); + +- REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); +- REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); ++ REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); ++ REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); + + REGWRITE_BUFFER_FLUSH(ah); + +@@ -2987,20 +2974,6 @@ static const struct ath_gen_timer_config + + /* HW generic timer primitives */ + +-/* compute and clear index of rightmost 1 */ +-static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) +-{ +- u32 b; +- +- b = *mask; +- b &= (0-b); +- *mask &= ~b; +- b *= debruijn32; +- b >>= 27; +- +- return timer_table->gen_timer_index[b]; +-} +- + u32 ath9k_hw_gettsf32(struct ath_hw *ah) + { + return REG_READ(ah, AR_TSF_L32); +@@ -3016,6 +2989,10 @@ struct ath_gen_timer *ath_gen_timer_allo + struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; + struct ath_gen_timer *timer; + ++ if ((timer_index < AR_FIRST_NDP_TIMER) || ++ (timer_index >= ATH_MAX_GEN_TIMER)) ++ return NULL; ++ + timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); + if (timer == NULL) + return NULL; +@@ -3033,23 +3010,13 @@ EXPORT_SYMBOL(ath_gen_timer_alloc); + + void ath9k_hw_gen_timer_start(struct ath_hw *ah, + struct ath_gen_timer *timer, +- u32 trig_timeout, ++ u32 timer_next, + u32 timer_period) + { + struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; +- u32 tsf, timer_next; +- +- BUG_ON(!timer_period); +- +- set_bit(timer->index, &timer_table->timer_mask.timer_bits); +- +- tsf = ath9k_hw_gettsf32(ah); ++ u32 mask = 0; + +- timer_next = tsf + trig_timeout; +- +- ath_dbg(ath9k_hw_common(ah), BTCOEX, +- "current tsf %x period %x timer_next %x\n", +- tsf, timer_period, timer_next); ++ timer_table->timer_mask |= BIT(timer->index); + + /* + * Program generic timer registers +@@ -3075,10 +3042,19 @@ void ath9k_hw_gen_timer_start(struct ath + (1 << timer->index)); + } + +- /* Enable both trigger and thresh interrupt masks */ +- REG_SET_BIT(ah, AR_IMR_S5, +- (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | +- SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); ++ if (timer->trigger) ++ mask |= SM(AR_GENTMR_BIT(timer->index), ++ AR_IMR_S5_GENTIMER_TRIG); ++ if (timer->overflow) ++ mask |= SM(AR_GENTMR_BIT(timer->index), ++ AR_IMR_S5_GENTIMER_THRESH); ++ ++ REG_SET_BIT(ah, AR_IMR_S5, mask); ++ ++ if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { ++ ah->imask |= ATH9K_INT_GENTIMER; ++ ath9k_hw_set_interrupts(ah); ++ } + } + EXPORT_SYMBOL(ath9k_hw_gen_timer_start); + +@@ -3086,11 +3062,6 @@ void ath9k_hw_gen_timer_stop(struct ath_ + { + struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; + +- if ((timer->index < AR_FIRST_NDP_TIMER) || +- (timer->index >= ATH_MAX_GEN_TIMER)) { +- return; +- } +- + /* Clear generic timer enable bits. */ + REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, + gen_tmr_configuration[timer->index].mode_mask); +@@ -3110,7 +3081,12 @@ void ath9k_hw_gen_timer_stop(struct ath_ + (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | + SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); + +- clear_bit(timer->index, &timer_table->timer_mask.timer_bits); ++ timer_table->timer_mask &= ~BIT(timer->index); ++ ++ if (timer_table->timer_mask == 0) { ++ ah->imask &= ~ATH9K_INT_GENTIMER; ++ ath9k_hw_set_interrupts(ah); ++ } + } + EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); + +@@ -3131,32 +3107,32 @@ void ath_gen_timer_isr(struct ath_hw *ah + { + struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; + struct ath_gen_timer *timer; +- struct ath_common *common = ath9k_hw_common(ah); +- u32 trigger_mask, thresh_mask, index; ++ unsigned long trigger_mask, thresh_mask; ++ unsigned int index; + + /* get hardware generic timer interrupt status */ + trigger_mask = ah->intr_gen_timer_trigger; + thresh_mask = ah->intr_gen_timer_thresh; +- trigger_mask &= timer_table->timer_mask.val; +- thresh_mask &= timer_table->timer_mask.val; ++ trigger_mask &= timer_table->timer_mask; ++ thresh_mask &= timer_table->timer_mask; + + trigger_mask &= ~thresh_mask; + +- while (thresh_mask) { +- index = rightmost_index(timer_table, &thresh_mask); ++ for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { + timer = timer_table->timers[index]; +- BUG_ON(!timer); +- ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n", +- index); ++ if (!timer) ++ continue; ++ if (!timer->overflow) ++ continue; + timer->overflow(timer->arg); + } + +- while (trigger_mask) { +- index = rightmost_index(timer_table, &trigger_mask); ++ for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { + timer = timer_table->timers[index]; +- BUG_ON(!timer); +- ath_dbg(common, BTCOEX, +- "Gen timer[%d] trigger\n", index); ++ if (!timer) ++ continue; ++ if (!timer->trigger) ++ continue; + timer->trigger(timer->arg); + } + } +--- a/drivers/net/wireless/ath/ath9k/hw.h ++++ b/drivers/net/wireless/ath/ath9k/hw.h +@@ -168,7 +168,7 @@ + #define CAB_TIMEOUT_VAL 10 + #define BEACON_TIMEOUT_VAL 10 + #define MIN_BEACON_TIMEOUT_VAL 1 +-#define SLEEP_SLOP 3 ++#define SLEEP_SLOP TU_TO_USEC(3) + + #define INIT_CONFIG_STATUS 0x00000000 + #define INIT_RSSI_THR 0x00000700 +@@ -280,11 +280,8 @@ struct ath9k_hw_capabilities { + struct ath9k_ops_config { + int dma_beacon_response_time; + int sw_beacon_response_time; +- int additional_swba_backoff; + int ack_6mb; + u32 cwm_ignore_extcca; +- bool pcieSerDesWrite; +- u8 pcie_clock_req; + u32 pcie_waen; + u8 analog_shiftreg; + u32 ofdm_trig_low; +@@ -295,18 +292,11 @@ struct ath9k_ops_config { + int serialize_regmode; + bool rx_intr_mitigation; + bool tx_intr_mitigation; +-#define SPUR_DISABLE 0 +-#define SPUR_ENABLE_IOCTL 1 +-#define SPUR_ENABLE_EEPROM 2 +-#define AR_SPUR_5413_1 1640 +-#define AR_SPUR_5413_2 1200 + #define AR_NO_SPUR 0x8000 + #define AR_BASE_FREQ_2GHZ 2300 + #define AR_BASE_FREQ_5GHZ 4900 + #define AR_SPUR_FEEQ_BOUND_HT40 19 + #define AR_SPUR_FEEQ_BOUND_HT20 10 +- int spurmode; +- u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; + u8 max_txtrig_level; + u16 ani_poll_interval; /* ANI poll interval in ms */ + +@@ -316,6 +306,8 @@ struct ath9k_ops_config { + u32 ant_ctrl_comm2g_switch_enable; + bool xatten_margin_cfg; + bool alt_mingainidx; ++ bool no_pll_pwrsave; ++ bool tx_gain_buffalo; + }; + + enum ath9k_int { +@@ -459,10 +451,6 @@ struct ath9k_beacon_state { + u32 bs_intval; + #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ + u32 bs_dtimperiod; +- u16 bs_cfpperiod; +- u16 bs_cfpmaxduration; +- u32 bs_cfpnext; +- u16 bs_timoffset; + u16 bs_bmissthreshold; + u32 bs_sleepduration; + u32 bs_tsfoor_threshold; +@@ -498,12 +486,6 @@ struct ath9k_hw_version { + + #define AR_GENTMR_BIT(_index) (1 << (_index)) + +-/* +- * Using de Bruijin sequence to look up 1's index in a 32 bit number +- * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 +- */ +-#define debruijn32 0x077CB531U +- + struct ath_gen_timer_configuration { + u32 next_addr; + u32 period_addr; +@@ -519,12 +501,8 @@ struct ath_gen_timer { + }; + + struct ath_gen_timer_table { +- u32 gen_timer_index[32]; + struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; +- union { +- unsigned long timer_bits; +- u16 val; +- } timer_mask; ++ u16 timer_mask; + }; + + struct ath_hw_antcomb_conf { +@@ -785,7 +763,6 @@ struct ath_hw { + u32 txurn_interrupt_mask; + atomic_t intr_ref_cnt; + bool chip_fullsleep; +- u32 atim_window; + u32 modes_index; + + /* Calibration */ +@@ -864,6 +841,7 @@ struct ath_hw { + u32 gpio_mask; + u32 gpio_val; + ++ struct ar5416IniArray ini_dfs; + struct ar5416IniArray iniModes; + struct ar5416IniArray iniCommon; + struct ar5416IniArray iniBB_RfGain; +@@ -920,7 +898,7 @@ struct ath_hw { + /* Enterprise mode cap */ + u32 ent_mode; + +-#ifdef CONFIG_PM_SLEEP ++#ifdef CONFIG_ATH9K_WOW + u32 wow_event_mask; + #endif + bool is_clk_25mhz; +@@ -1126,7 +1104,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw + #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */ + + +-#ifdef CONFIG_PM_SLEEP ++#ifdef CONFIG_ATH9K_WOW + const char *ath9k_hw_wow_event_to_string(u32 wow_event); + void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, + u8 *user_mask, int pattern_count, +--- a/drivers/net/wireless/ath/ath9k/init.c ++++ b/drivers/net/wireless/ath/ath9k/init.c +@@ -554,7 +554,7 @@ static void ath9k_init_misc(struct ath_s + sc->spec_config.fft_period = 0xF; + } + +-static void ath9k_init_platform(struct ath_softc *sc) ++static void ath9k_init_pcoem_platform(struct ath_softc *sc) + { + struct ath_hw *ah = sc->sc_ah; + struct ath9k_hw_capabilities *pCap = &ah->caps; +@@ -609,6 +609,11 @@ static void ath9k_init_platform(struct a + ah->config.pcie_waen = 0x0040473b; + ath_info(common, "Enable WAR for ASPM D3/L1\n"); + } ++ ++ if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { ++ ah->config.no_pll_pwrsave = true; ++ ath_info(common, "Disable PLL PowerSave\n"); ++ } + } + + static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, +@@ -656,6 +661,27 @@ static void ath9k_eeprom_release(struct + release_firmware(sc->sc_ah->eeprom_blob); + } + ++static int ath9k_init_soc_platform(struct ath_softc *sc) ++{ ++ struct ath9k_platform_data *pdata = sc->dev->platform_data; ++ struct ath_hw *ah = sc->sc_ah; ++ int ret = 0; ++ ++ if (!pdata) ++ return 0; ++ ++ if (pdata->eeprom_name) { ++ ret = ath9k_eeprom_request(sc, pdata->eeprom_name); ++ if (ret) ++ return ret; ++ } ++ ++ if (pdata->tx_gain_buffalo) ++ ah->config.tx_gain_buffalo = true; ++ ++ return ret; ++} ++ + static int ath9k_init_softc(u16 devid, struct ath_softc *sc, + const struct ath_bus_ops *bus_ops) + { +@@ -683,6 +709,7 @@ static int ath9k_init_softc(u16 devid, s + common = ath9k_hw_common(ah); + sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); + sc->tx99_power = MAX_RATE_POWER + 1; ++ init_waitqueue_head(&sc->tx_wait); if (!pdata) { ah->ah_flags |= AH_USE_EEPROM; -@@ -730,6 +736,7 @@ static int ath9k_init_softc(u16 devid, s +@@ -708,7 +735,11 @@ static int ath9k_init_softc(u16 devid, s + /* + * Platform quirks. + */ +- ath9k_init_platform(sc); ++ ath9k_init_pcoem_platform(sc); ++ ++ ret = ath9k_init_soc_platform(sc); ++ if (ret) ++ return ret; + + /* + * Enable WLAN/BT RX Antenna diversity only when: +@@ -722,7 +753,6 @@ static int ath9k_init_softc(u16 devid, s + common->bt_ant_diversity = 1; + + spin_lock_init(&common->cc_lock); +- + spin_lock_init(&sc->sc_serial_rw); + spin_lock_init(&sc->sc_pm_lock); + mutex_init(&sc->mutex); +@@ -730,6 +760,7 @@ static int ath9k_init_softc(u16 devid, s tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, (unsigned long)sc); @@ -872,7 +1685,20 @@ INIT_WORK(&sc->hw_reset_work, ath_reset_work); INIT_WORK(&sc->hw_check_work, ath_hw_check); INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); -@@ -845,7 +852,8 @@ static const struct ieee80211_iface_limi +@@ -743,12 +774,6 @@ static int ath9k_init_softc(u16 devid, s + ath_read_cachesize(common, &csz); + common->cachelsz = csz << 2; /* convert to bytes */ + +- if (pdata && pdata->eeprom_name) { +- ret = ath9k_eeprom_request(sc, pdata->eeprom_name); +- if (ret) +- return ret; +- } +- + /* Initializes the hardware for all supported chipsets */ + ret = ath9k_hw_init(ah); + if (ret) +@@ -845,7 +870,8 @@ static const struct ieee80211_iface_limi }; static const struct ieee80211_iface_limit if_dfs_limits[] = { @@ -882,7 +1708,7 @@ }; static const struct ieee80211_iface_combination if_comb[] = { -@@ -862,20 +870,11 @@ static const struct ieee80211_iface_comb +@@ -862,20 +888,11 @@ static const struct ieee80211_iface_comb .max_interfaces = 1, .num_different_channels = 1, .beacon_int_infra_match = true, @@ -905,7 +1731,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) { struct ath_hw *ah = sc->sc_ah; -@@ -925,16 +924,6 @@ void ath9k_set_hw_capab(struct ath_softc +@@ -925,16 +942,6 @@ void ath9k_set_hw_capab(struct ath_softc hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; @@ -922,7 +1748,7 @@ hw->queues = 4; hw->max_rates = 4; hw->channel_change_time = 5000; -@@ -960,6 +949,7 @@ void ath9k_set_hw_capab(struct ath_softc +@@ -960,6 +967,7 @@ void ath9k_set_hw_capab(struct ath_softc hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &sc->sbands[IEEE80211_BAND_5GHZ]; @@ -930,7 +1756,7 @@ ath9k_reload_chainmask_settings(sc); SET_IEEE80211_PERM_ADDR(hw, common->macaddr); -@@ -1058,6 +1048,7 @@ static void ath9k_deinit_softc(struct at +@@ -1058,6 +1066,7 @@ static void ath9k_deinit_softc(struct at if (ATH_TXQ_SETUP(sc, i)) ath_tx_cleanupq(sc, &sc->tx.txq[i]); @@ -1010,7 +1836,7 @@ { ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); -@@ -487,6 +504,8 @@ void ath9k_tasklet(unsigned long data) +@@ -487,8 +504,13 @@ void ath9k_tasklet(unsigned long data) ath_tx_edma_tasklet(sc); else ath_tx_tasklet(sc); @@ -1018,8 +1844,13 @@ + wake_up(&sc->tx_wait); } ++ if (status & ATH9K_INT_GENTIMER) ++ ath_gen_timer_isr(sc->sc_ah); ++ ath9k_btcoex_handle_interrupt(sc, status); -@@ -579,7 +598,8 @@ irqreturn_t ath_isr(int irq, void *dev) + + /* re-enable hardware interrupt */ +@@ -579,7 +601,8 @@ irqreturn_t ath_isr(int irq, void *dev) goto chip_reset; } @@ -1029,7 +1860,7 @@ if (status & ATH9K_INT_BMISS) { if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { ath_dbg(common, ANY, "during WoW we got a BMISS\n"); -@@ -588,6 +608,8 @@ irqreturn_t ath_isr(int irq, void *dev) +@@ -588,6 +611,8 @@ irqreturn_t ath_isr(int irq, void *dev) } } #endif @@ -1038,7 +1869,7 @@ if (status & ATH9K_INT_SWBA) tasklet_schedule(&sc->bcon_tasklet); -@@ -627,7 +649,7 @@ chip_reset: +@@ -627,7 +652,7 @@ chip_reset: #undef SCHED_INTR } @@ -1047,7 +1878,16 @@ { int r; -@@ -1817,13 +1839,31 @@ static void ath9k_set_coverage_class(str +@@ -735,6 +760,8 @@ static int ath9k_start(struct ieee80211_ + */ + ath9k_cmn_init_crypto(sc->sc_ah); + ++ ath9k_hw_reset_tsf(ah); ++ + spin_unlock_bh(&sc->sc_pcu_lock); + + mutex_unlock(&sc->mutex); +@@ -1817,13 +1844,31 @@ static void ath9k_set_coverage_class(str mutex_unlock(&sc->mutex); } @@ -1081,7 +1921,7 @@ bool drain_txq; mutex_lock(&sc->mutex); -@@ -1841,25 +1881,9 @@ static void ath9k_flush(struct ieee80211 +@@ -1841,25 +1886,9 @@ static void ath9k_flush(struct ieee80211 return; } @@ -1110,7 +1950,7 @@ if (drop) { ath9k_ps_wakeup(sc); -@@ -2021,333 +2045,6 @@ static int ath9k_get_antenna(struct ieee +@@ -2021,333 +2050,6 @@ static int ath9k_get_antenna(struct ieee return 0; } @@ -1444,7 +2284,7 @@ static void ath9k_sw_scan_start(struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; -@@ -2373,134 +2070,6 @@ static void ath9k_channel_switch_beacon( +@@ -2373,134 +2075,6 @@ static void ath9k_channel_switch_beacon( sc->csa_vif = vif; } @@ -1579,7 +2419,7 @@ struct ieee80211_ops ath9k_ops = { .tx = ath9k_tx, .start = ath9k_start, -@@ -2531,7 +2100,7 @@ struct ieee80211_ops ath9k_ops = { +@@ -2531,7 +2105,7 @@ struct ieee80211_ops ath9k_ops = { .set_antenna = ath9k_set_antenna, .get_antenna = ath9k_get_antenna, @@ -2272,7 +3112,18 @@ -EXPORT_SYMBOL(ath9k_hw_wow_enable); --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c -@@ -1786,6 +1786,9 @@ bool ath_drain_all_txq(struct ath_softc +@@ -1276,6 +1276,10 @@ static void ath_tx_fill_desc(struct ath_ + if (!rts_thresh || (len > rts_thresh)) + rts = true; + } ++ ++ if (!aggr) ++ len = fi->framelen; ++ + ath_buf_set_rate(sc, bf, &info, len, rts); + } + +@@ -1786,6 +1790,9 @@ bool ath_drain_all_txq(struct ath_softc if (!ATH_TXQ_SETUP(sc, i)) continue; @@ -2282,7 +3133,7 @@ if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) npend |= BIT(i); } -@@ -2749,6 +2752,8 @@ void ath_tx_node_cleanup(struct ath_soft +@@ -2749,6 +2756,8 @@ void ath_tx_node_cleanup(struct ath_soft } } @@ -2291,7 +3142,7 @@ int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, struct ath_tx_control *txctl) { -@@ -2791,3 +2796,5 @@ int ath9k_tx99_send(struct ath_softc *sc +@@ -2791,3 +2800,5 @@ int ath9k_tx99_send(struct ath_softc *sc return 0; } @@ -5184,9 +6035,47 @@ /* * RXGAIN initvals. */ +@@ -1281,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs + static void ar9003_hw_set_radar_params(struct ath_hw *ah, + struct ath_hw_radar_conf *conf) + { ++ unsigned int regWrites = 0; + u32 radar_0 = 0, radar_1 = 0; + + if (!conf) { +@@ -1307,6 +1359,11 @@ static void ar9003_hw_set_radar_params(s + REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); + else + REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); ++ ++ if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { ++ REG_WRITE_ARRAY(&ah->ini_dfs, ++ IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); ++ } + } + + static void ar9003_hw_set_radar_conf(struct ath_hw *ah) --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h -@@ -656,13 +656,24 @@ +@@ -341,14 +341,15 @@ + #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 + #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 + ++#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95 ++#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100 ++ + #define AR_PHY_CCA_NOM_VAL_9462_2GHZ -127 + #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ -127 + #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ -60 +-#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95 + #define AR_PHY_CCA_NOM_VAL_9462_5GHZ -127 + #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ -127 + #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ -60 +-#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100 + + #define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118 + +@@ -656,13 +657,24 @@ #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002) #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1) #define AR_PHY_65NM_CH0_SYNTH7 0x16098 @@ -5232,7 +6121,53 @@ } --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c -@@ -1040,14 +1040,14 @@ static void ar9003_hw_cl_cal_post_proc(s +@@ -898,7 +898,7 @@ static void ar9003_hw_tx_iq_cal_reload(s + + static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g) + { +- int offset[8], total = 0, test; ++ int offset[8] = {0}, total = 0, test; + int agc_out, i; + + REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain), +@@ -923,12 +923,18 @@ static void ar9003_hw_manual_peak_cal(st + AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1); + REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), + AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1); +- if (is_2g) +- REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), +- AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0); +- else ++ ++ if (AR_SREV_9330_11(ah)) { + REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), +- AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0); ++ AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0); ++ } else { ++ if (is_2g) ++ REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), ++ AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0); ++ else ++ REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), ++ AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0); ++ } + + for (i = 6; i > 0; i--) { + offset[i] = BIT(i - 1); +@@ -964,9 +970,9 @@ static void ar9003_hw_manual_peak_cal(st + AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0); + } + +-static void ar9003_hw_do_manual_peak_cal(struct ath_hw *ah, +- struct ath9k_channel *chan, +- bool run_rtt_cal) ++static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah, ++ struct ath9k_channel *chan, ++ bool run_rtt_cal) + { + struct ath9k_hw_cal_data *caldata = ah->caldata; + int i; +@@ -1040,14 +1046,14 @@ static void ar9003_hw_cl_cal_post_proc(s } } @@ -5250,7 +6185,7 @@ bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT); u32 rx_delay = 0; u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL | -@@ -1119,22 +1119,12 @@ static bool ar9003_hw_init_cal(struct at +@@ -1119,22 +1125,12 @@ static bool ar9003_hw_init_cal(struct at REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL); txiqcal_done = run_agc_cal = true; @@ -5273,7 +6208,16 @@ if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { rx_delay = REG_READ(ah, AR_PHY_RX_DELAY); /* Disable BB_active */ -@@ -1228,13 +1218,109 @@ skip_tx_iqcal: +@@ -1155,7 +1151,7 @@ skip_tx_iqcal: + AR_PHY_AGC_CONTROL_CAL, + 0, AH_WAIT_TIMEOUT); + +- ar9003_hw_do_manual_peak_cal(ah, chan, run_rtt_cal); ++ ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal); + } + + if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { +@@ -1228,13 +1224,112 @@ skip_tx_iqcal: return true; } @@ -5326,6 +6270,9 @@ + +skip_tx_iqcal: + if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) { ++ if (AR_SREV_9330_11(ah)) ++ ar9003_hw_manual_peak_cal(ah, 0, IS_CHAN_2GHZ(chan)); ++ + /* Calibrate the AGC */ + REG_WRITE(ah, AR_PHY_AGC_CONTROL, + REG_READ(ah, AR_PHY_AGC_CONTROL) | @@ -5411,6 +6358,15 @@ } --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +@@ -3965,7 +3965,7 @@ static void ar9003_hw_apply_tuning_caps( + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; + +- if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ if (AR_SREV_9340(ah)) + return; + + if (eep->baseEepHeader.featureEnable & 0x40) { @@ -3984,18 +3984,20 @@ static void ar9003_hw_quick_drop_apply(s int quick_drop; s32 t[3], f[3] = {5180, 5500, 5785}; @@ -5450,6 +6406,15 @@ return; if (!AR_SREV_9300(ah)) +@@ -4120,7 +4122,7 @@ static void ath9k_hw_ar9300_set_board_va + ar9003_hw_xlna_bias_strength_apply(ah, is2ghz); + ar9003_hw_atten_apply(ah, chan); + ar9003_hw_quick_drop_apply(ah, chan->channel); +- if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah)) ++ if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah)) + ar9003_hw_internal_regulator_apply(ah); + ar9003_hw_apply_tuning_caps(ah); + ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz); --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h @@ -735,6 +735,7 @@ struct ieee80211_sub_if_data { @@ -5512,7 +6477,16 @@ --- a/net/mac80211/ibss.c +++ b/net/mac80211/ibss.c -@@ -550,12 +550,12 @@ int ieee80211_ibss_finish_csa(struct iee +@@ -534,7 +534,7 @@ int ieee80211_ibss_finish_csa(struct iee + int err; + u16 capability; + +- sdata_lock(sdata); ++ sdata_assert_lock(sdata); + /* update cfg80211 bss information with the new channel */ + if (!is_zero_ether_addr(ifibss->bssid)) { + capability = WLAN_CAPABILITY_IBSS; +@@ -550,16 +550,15 @@ int ieee80211_ibss_finish_csa(struct iee capability); /* XXX: should not really modify cfg80211 data */ if (cbss) { @@ -5527,7 +6501,11 @@ /* generate the beacon */ err = ieee80211_ibss_csa_beacon(sdata, NULL); -@@ -922,7 +922,7 @@ ieee80211_ibss_process_chanswitch(struct +- sdata_unlock(sdata); + if (err < 0) + return err; + +@@ -922,7 +921,7 @@ ieee80211_ibss_process_chanswitch(struct IEEE80211_MAX_QUEUE_MAP, IEEE80211_QUEUE_STOP_REASON_CSA); @@ -5943,7 +6921,267 @@ - {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, -}; - --static const u32 ar9462_2p1_common_rx_gain[][2] = { +-static const u32 ar9462_2p1_common_rx_gain[][2] = { +- /* Addr allmodes */ +- {0x0000a000, 0x00010000}, +- {0x0000a004, 0x00030002}, +- {0x0000a008, 0x00050004}, +- {0x0000a00c, 0x00810080}, +- {0x0000a010, 0x00830082}, +- {0x0000a014, 0x01810180}, +- {0x0000a018, 0x01830182}, +- {0x0000a01c, 0x01850184}, +- {0x0000a020, 0x01890188}, +- {0x0000a024, 0x018b018a}, +- {0x0000a028, 0x018d018c}, +- {0x0000a02c, 0x01910190}, +- {0x0000a030, 0x01930192}, +- {0x0000a034, 0x01950194}, +- {0x0000a038, 0x038a0196}, +- {0x0000a03c, 0x038c038b}, +- {0x0000a040, 0x0390038d}, +- {0x0000a044, 0x03920391}, +- {0x0000a048, 0x03940393}, +- {0x0000a04c, 0x03960395}, +- {0x0000a050, 0x00000000}, +- {0x0000a054, 0x00000000}, +- {0x0000a058, 0x00000000}, +- {0x0000a05c, 0x00000000}, +- {0x0000a060, 0x00000000}, +- {0x0000a064, 0x00000000}, +- {0x0000a068, 0x00000000}, +- {0x0000a06c, 0x00000000}, +- {0x0000a070, 0x00000000}, +- {0x0000a074, 0x00000000}, +- {0x0000a078, 0x00000000}, +- {0x0000a07c, 0x00000000}, +- {0x0000a080, 0x22222229}, +- {0x0000a084, 0x1d1d1d1d}, +- {0x0000a088, 0x1d1d1d1d}, +- {0x0000a08c, 0x1d1d1d1d}, +- {0x0000a090, 0x171d1d1d}, +- {0x0000a094, 0x11111717}, +- {0x0000a098, 0x00030311}, +- {0x0000a09c, 0x00000000}, +- {0x0000a0a0, 0x00000000}, +- {0x0000a0a4, 0x00000000}, +- {0x0000a0a8, 0x00000000}, +- {0x0000a0ac, 0x00000000}, +- {0x0000a0b0, 0x00000000}, +- {0x0000a0b4, 0x00000000}, +- {0x0000a0b8, 0x00000000}, +- {0x0000a0bc, 0x00000000}, +- {0x0000a0c0, 0x001f0000}, +- {0x0000a0c4, 0x01000101}, +- {0x0000a0c8, 0x011e011f}, +- {0x0000a0cc, 0x011c011d}, +- {0x0000a0d0, 0x02030204}, +- {0x0000a0d4, 0x02010202}, +- {0x0000a0d8, 0x021f0200}, +- {0x0000a0dc, 0x0302021e}, +- {0x0000a0e0, 0x03000301}, +- {0x0000a0e4, 0x031e031f}, +- {0x0000a0e8, 0x0402031d}, +- {0x0000a0ec, 0x04000401}, +- {0x0000a0f0, 0x041e041f}, +- {0x0000a0f4, 0x0502041d}, +- {0x0000a0f8, 0x05000501}, +- {0x0000a0fc, 0x051e051f}, +- {0x0000a100, 0x06010602}, +- {0x0000a104, 0x061f0600}, +- {0x0000a108, 0x061d061e}, +- {0x0000a10c, 0x07020703}, +- {0x0000a110, 0x07000701}, +- {0x0000a114, 0x00000000}, +- {0x0000a118, 0x00000000}, +- {0x0000a11c, 0x00000000}, +- {0x0000a120, 0x00000000}, +- {0x0000a124, 0x00000000}, +- {0x0000a128, 0x00000000}, +- {0x0000a12c, 0x00000000}, +- {0x0000a130, 0x00000000}, +- {0x0000a134, 0x00000000}, +- {0x0000a138, 0x00000000}, +- {0x0000a13c, 0x00000000}, +- {0x0000a140, 0x001f0000}, +- {0x0000a144, 0x01000101}, +- {0x0000a148, 0x011e011f}, +- {0x0000a14c, 0x011c011d}, +- {0x0000a150, 0x02030204}, +- {0x0000a154, 0x02010202}, +- {0x0000a158, 0x021f0200}, +- {0x0000a15c, 0x0302021e}, +- {0x0000a160, 0x03000301}, +- {0x0000a164, 0x031e031f}, +- {0x0000a168, 0x0402031d}, +- {0x0000a16c, 0x04000401}, +- {0x0000a170, 0x041e041f}, +- {0x0000a174, 0x0502041d}, +- {0x0000a178, 0x05000501}, +- {0x0000a17c, 0x051e051f}, +- {0x0000a180, 0x06010602}, +- {0x0000a184, 0x061f0600}, +- {0x0000a188, 0x061d061e}, +- {0x0000a18c, 0x07020703}, +- {0x0000a190, 0x07000701}, +- {0x0000a194, 0x00000000}, +- {0x0000a198, 0x00000000}, +- {0x0000a19c, 0x00000000}, +- {0x0000a1a0, 0x00000000}, +- {0x0000a1a4, 0x00000000}, +- {0x0000a1a8, 0x00000000}, +- {0x0000a1ac, 0x00000000}, +- {0x0000a1b0, 0x00000000}, +- {0x0000a1b4, 0x00000000}, +- {0x0000a1b8, 0x00000000}, +- {0x0000a1bc, 0x00000000}, +- {0x0000a1c0, 0x00000000}, +- {0x0000a1c4, 0x00000000}, +- {0x0000a1c8, 0x00000000}, +- {0x0000a1cc, 0x00000000}, +- {0x0000a1d0, 0x00000000}, +- {0x0000a1d4, 0x00000000}, +- {0x0000a1d8, 0x00000000}, +- {0x0000a1dc, 0x00000000}, +- {0x0000a1e0, 0x00000000}, +- {0x0000a1e4, 0x00000000}, +- {0x0000a1e8, 0x00000000}, +- {0x0000a1ec, 0x00000000}, +- {0x0000a1f0, 0x00000396}, +- {0x0000a1f4, 0x00000396}, +- {0x0000a1f8, 0x00000396}, +- {0x0000a1fc, 0x00000196}, +- {0x0000b000, 0x00010000}, +- {0x0000b004, 0x00030002}, +- {0x0000b008, 0x00050004}, +- {0x0000b00c, 0x00810080}, +- {0x0000b010, 0x00830082}, +- {0x0000b014, 0x01810180}, +- {0x0000b018, 0x01830182}, +- {0x0000b01c, 0x01850184}, +- {0x0000b020, 0x02810280}, +- {0x0000b024, 0x02830282}, +- {0x0000b028, 0x02850284}, +- {0x0000b02c, 0x02890288}, +- {0x0000b030, 0x028b028a}, +- {0x0000b034, 0x0388028c}, +- {0x0000b038, 0x038a0389}, +- {0x0000b03c, 0x038c038b}, +- {0x0000b040, 0x0390038d}, +- {0x0000b044, 0x03920391}, +- {0x0000b048, 0x03940393}, +- {0x0000b04c, 0x03960395}, +- {0x0000b050, 0x00000000}, +- {0x0000b054, 0x00000000}, +- {0x0000b058, 0x00000000}, +- {0x0000b05c, 0x00000000}, +- {0x0000b060, 0x00000000}, +- {0x0000b064, 0x00000000}, +- {0x0000b068, 0x00000000}, +- {0x0000b06c, 0x00000000}, +- {0x0000b070, 0x00000000}, +- {0x0000b074, 0x00000000}, +- {0x0000b078, 0x00000000}, +- {0x0000b07c, 0x00000000}, +- {0x0000b080, 0x2a2d2f32}, +- {0x0000b084, 0x21232328}, +- {0x0000b088, 0x19191c1e}, +- {0x0000b08c, 0x12141417}, +- {0x0000b090, 0x07070e0e}, +- {0x0000b094, 0x03030305}, +- {0x0000b098, 0x00000003}, +- {0x0000b09c, 0x00000000}, +- {0x0000b0a0, 0x00000000}, +- {0x0000b0a4, 0x00000000}, +- {0x0000b0a8, 0x00000000}, +- {0x0000b0ac, 0x00000000}, +- {0x0000b0b0, 0x00000000}, +- {0x0000b0b4, 0x00000000}, +- {0x0000b0b8, 0x00000000}, +- {0x0000b0bc, 0x00000000}, +- {0x0000b0c0, 0x003f0020}, +- {0x0000b0c4, 0x00400041}, +- {0x0000b0c8, 0x0140005f}, +- {0x0000b0cc, 0x0160015f}, +- {0x0000b0d0, 0x017e017f}, +- {0x0000b0d4, 0x02410242}, +- {0x0000b0d8, 0x025f0240}, +- {0x0000b0dc, 0x027f0260}, +- {0x0000b0e0, 0x0341027e}, +- {0x0000b0e4, 0x035f0340}, +- {0x0000b0e8, 0x037f0360}, +- {0x0000b0ec, 0x04400441}, +- {0x0000b0f0, 0x0460045f}, +- {0x0000b0f4, 0x0541047f}, +- {0x0000b0f8, 0x055f0540}, +- {0x0000b0fc, 0x057f0560}, +- {0x0000b100, 0x06400641}, +- {0x0000b104, 0x0660065f}, +- {0x0000b108, 0x067e067f}, +- {0x0000b10c, 0x07410742}, +- {0x0000b110, 0x075f0740}, +- {0x0000b114, 0x077f0760}, +- {0x0000b118, 0x07800781}, +- {0x0000b11c, 0x07a0079f}, +- {0x0000b120, 0x07c107bf}, +- {0x0000b124, 0x000007c0}, +- {0x0000b128, 0x00000000}, +- {0x0000b12c, 0x00000000}, +- {0x0000b130, 0x00000000}, +- {0x0000b134, 0x00000000}, +- {0x0000b138, 0x00000000}, +- {0x0000b13c, 0x00000000}, +- {0x0000b140, 0x003f0020}, +- {0x0000b144, 0x00400041}, +- {0x0000b148, 0x0140005f}, +- {0x0000b14c, 0x0160015f}, +- {0x0000b150, 0x017e017f}, +- {0x0000b154, 0x02410242}, +- {0x0000b158, 0x025f0240}, +- {0x0000b15c, 0x027f0260}, +- {0x0000b160, 0x0341027e}, +- {0x0000b164, 0x035f0340}, +- {0x0000b168, 0x037f0360}, +- {0x0000b16c, 0x04400441}, +- {0x0000b170, 0x0460045f}, +- {0x0000b174, 0x0541047f}, +- {0x0000b178, 0x055f0540}, +- {0x0000b17c, 0x057f0560}, +- {0x0000b180, 0x06400641}, +- {0x0000b184, 0x0660065f}, +- {0x0000b188, 0x067e067f}, +- {0x0000b18c, 0x07410742}, +- {0x0000b190, 0x075f0740}, +- {0x0000b194, 0x077f0760}, +- {0x0000b198, 0x07800781}, +- {0x0000b19c, 0x07a0079f}, +- {0x0000b1a0, 0x07c107bf}, +- {0x0000b1a4, 0x000007c0}, +- {0x0000b1a8, 0x00000000}, +- {0x0000b1ac, 0x00000000}, +- {0x0000b1b0, 0x00000000}, +- {0x0000b1b4, 0x00000000}, +- {0x0000b1b8, 0x00000000}, +- {0x0000b1bc, 0x00000000}, +- {0x0000b1c0, 0x00000000}, +- {0x0000b1c4, 0x00000000}, +- {0x0000b1c8, 0x00000000}, +- {0x0000b1cc, 0x00000000}, +- {0x0000b1d0, 0x00000000}, +- {0x0000b1d4, 0x00000000}, +- {0x0000b1d8, 0x00000000}, +- {0x0000b1dc, 0x00000000}, +- {0x0000b1e0, 0x00000000}, +- {0x0000b1e4, 0x00000000}, +- {0x0000b1e8, 0x00000000}, +- {0x0000b1ec, 0x00000000}, +- {0x0000b1f0, 0x00000396}, +- {0x0000b1f4, 0x00000396}, +- {0x0000b1f8, 0x00000396}, +- {0x0000b1fc, 0x00000196}, +-}; +- +-static const u32 ar9462_2p1_common_mixed_rx_gain[][2] = { - /* Addr allmodes */ - {0x0000a000, 0x00010000}, - {0x0000a004, 0x00030002}, @@ -5956,10 +7194,10 @@ - {0x0000a020, 0x01890188}, - {0x0000a024, 0x018b018a}, - {0x0000a028, 0x018d018c}, -- {0x0000a02c, 0x01910190}, -- {0x0000a030, 0x01930192}, -- {0x0000a034, 0x01950194}, -- {0x0000a038, 0x038a0196}, +- {0x0000a02c, 0x03820190}, +- {0x0000a030, 0x03840383}, +- {0x0000a034, 0x03880385}, +- {0x0000a038, 0x038a0389}, - {0x0000a03c, 0x038c038b}, - {0x0000a040, 0x0390038d}, - {0x0000a044, 0x03920391}, @@ -5977,14 +7215,14 @@ - {0x0000a074, 0x00000000}, - {0x0000a078, 0x00000000}, - {0x0000a07c, 0x00000000}, -- {0x0000a080, 0x22222229}, -- {0x0000a084, 0x1d1d1d1d}, -- {0x0000a088, 0x1d1d1d1d}, -- {0x0000a08c, 0x1d1d1d1d}, -- {0x0000a090, 0x171d1d1d}, -- {0x0000a094, 0x11111717}, -- {0x0000a098, 0x00030311}, -- {0x0000a09c, 0x00000000}, +- {0x0000a080, 0x29292929}, +- {0x0000a084, 0x29292929}, +- {0x0000a088, 0x29292929}, +- {0x0000a08c, 0x29292929}, +- {0x0000a090, 0x22292929}, +- {0x0000a094, 0x1d1d2222}, +- {0x0000a098, 0x0c111117}, +- {0x0000a09c, 0x00030303}, - {0x0000a0a0, 0x00000000}, - {0x0000a0a4, 0x00000000}, - {0x0000a0a8, 0x00000000}, @@ -6203,7 +7441,27 @@ - {0x0000b1fc, 0x00000196}, -}; - --static const u32 ar9462_2p1_common_mixed_rx_gain[][2] = { +-static const u32 ar9462_2p1_baseband_core_mix_rxgain[][2] = { +- /* Addr allmodes */ +- {0x00009fd0, 0x0a2d6b93}, +-}; +- +-static const u32 ar9462_2p1_baseband_postamble_mix_rxgain[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae}, +- {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da}, +- {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81}, +- {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8}, +- {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e}, +- {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e}, +-}; +- +-static const u32 ar9462_2p1_baseband_postamble_5g_xlna[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, +-}; +- +-static const u32 ar9462_2p1_common_wo_xlna_rx_gain[][2] = { - /* Addr allmodes */ - {0x0000a000, 0x00010000}, - {0x0000a004, 0x00030002}, @@ -6365,14 +7623,14 @@ - {0x0000b074, 0x00000000}, - {0x0000b078, 0x00000000}, - {0x0000b07c, 0x00000000}, -- {0x0000b080, 0x2a2d2f32}, -- {0x0000b084, 0x21232328}, -- {0x0000b088, 0x19191c1e}, -- {0x0000b08c, 0x12141417}, -- {0x0000b090, 0x07070e0e}, -- {0x0000b094, 0x03030305}, -- {0x0000b098, 0x00000003}, -- {0x0000b09c, 0x00000000}, +- {0x0000b080, 0x32323232}, +- {0x0000b084, 0x2f2f3232}, +- {0x0000b088, 0x23282a2d}, +- {0x0000b08c, 0x1c1e2123}, +- {0x0000b090, 0x14171919}, +- {0x0000b094, 0x0e0e1214}, +- {0x0000b098, 0x03050707}, +- {0x0000b09c, 0x00030303}, - {0x0000b0a0, 0x00000000}, - {0x0000b0a4, 0x00000000}, - {0x0000b0a8, 0x00000000}, @@ -6463,27 +7721,7 @@ - {0x0000b1fc, 0x00000196}, -}; - --static const u32 ar9462_2p1_baseband_core_mix_rxgain[][2] = { -- /* Addr allmodes */ -- {0x00009fd0, 0x0a2d6b93}, --}; -- --static const u32 ar9462_2p1_baseband_postamble_mix_rxgain[][5] = { -- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ -- {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae}, -- {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da}, -- {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81}, -- {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8}, -- {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e}, -- {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e}, --}; -- --static const u32 ar9462_2p1_baseband_postamble_5g_xlna[][5] = { -- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ -- {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, --}; -- --static const u32 ar9462_2p1_common_wo_xlna_rx_gain[][2] = { +-static const u32 ar9462_2p1_common_5g_xlna_only_rx_gain[][2] = { - /* Addr allmodes */ - {0x0000a000, 0x00010000}, - {0x0000a004, 0x00030002}, @@ -6645,14 +7883,14 @@ - {0x0000b074, 0x00000000}, - {0x0000b078, 0x00000000}, - {0x0000b07c, 0x00000000}, -- {0x0000b080, 0x32323232}, -- {0x0000b084, 0x2f2f3232}, -- {0x0000b088, 0x23282a2d}, -- {0x0000b08c, 0x1c1e2123}, -- {0x0000b090, 0x14171919}, -- {0x0000b094, 0x0e0e1214}, -- {0x0000b098, 0x03050707}, -- {0x0000b09c, 0x00030303}, +- {0x0000b080, 0x2a2d2f32}, +- {0x0000b084, 0x21232328}, +- {0x0000b088, 0x19191c1e}, +- {0x0000b08c, 0x12141417}, +- {0x0000b090, 0x07070e0e}, +- {0x0000b094, 0x03030305}, +- {0x0000b098, 0x00000003}, +- {0x0000b09c, 0x00000000}, - {0x0000b0a0, 0x00000000}, - {0x0000b0a4, 0x00000000}, - {0x0000b0a8, 0x00000000}, @@ -6743,7 +7981,583 @@ - {0x0000b1fc, 0x00000196}, -}; - --static const u32 ar9462_2p1_common_5g_xlna_only_rx_gain[][2] = { +-static const u32 ar9462_2p1_modes_low_ob_db_tx_gain[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, +- {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, +- {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, +- {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, +- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, +- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, +- {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, +- {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, +- {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, +- {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, +- {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402}, +- {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, +- {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, +- {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, +- {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, +- {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20}, +- {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20}, +- {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22}, +- {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24}, +- {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640}, +- {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, +- {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, +- {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, +- {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83}, +- {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84}, +- {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3}, +- {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5}, +- {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9}, +- {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb}, +- {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, +- {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, +- {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501}, +- {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03}, +- {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, +- {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04}, +- {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005}, +- {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, +- {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, +- {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, +- {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, +- {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, +- {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, +- {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, +- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +- {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, +- {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060}, +- {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, +- {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, +- {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, +- {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, +-}; +- +-static const u32 ar9462_2p1_modes_high_ob_db_tx_gain[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, +- {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, +- {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, +- {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, +- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +- {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de}, +- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, +- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, +- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, +- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, +- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, +- {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400}, +- {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402}, +- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, +- {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603}, +- {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02}, +- {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04}, +- {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20}, +- {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20}, +- {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22}, +- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24}, +- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640}, +- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660}, +- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861}, +- {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81}, +- {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83}, +- {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84}, +- {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3}, +- {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5}, +- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9}, +- {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb}, +- {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec}, +- {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0}, +- {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4}, +- {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, +- {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, +- {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, +- {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, +- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, +- {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, +- {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, +- {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, +- {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, +- {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, +- {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, +- {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, +- {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, +- {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, +- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +- {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, +- {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060}, +- {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, +- {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, +- {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, +- {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, +-}; +- +-static const u32 ar9462_2p1_modes_mix_ob_db_tx_gain[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, +- {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, +- {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, +- {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, +- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +- {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de}, +- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, +- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, +- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, +- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, +- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, +- {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400}, +- {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402}, +- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, +- {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603}, +- {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02}, +- {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04}, +- {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20}, +- {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20}, +- {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22}, +- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24}, +- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640}, +- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660}, +- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861}, +- {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81}, +- {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83}, +- {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84}, +- {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3}, +- {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5}, +- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9}, +- {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb}, +- {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec}, +- {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0}, +- {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4}, +- {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, +- {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, +- {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, +- {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, +- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, +- {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, +- {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, +- {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, +- {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, +- {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, +- {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, +- {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, +- {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, +- {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, +- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +-}; +- +-static const u32 ar9462_2p1_modes_fast_clock[][3] = { +- /* Addr 5G_HT20 5G_HT40 */ +- {0x00001030, 0x00000268, 0x000004d0}, +- {0x00001070, 0x0000018c, 0x00000318}, +- {0x000010b0, 0x00000fd0, 0x00001fa0}, +- {0x00008014, 0x044c044c, 0x08980898}, +- {0x0000801c, 0x148ec02b, 0x148ec057}, +- {0x00008318, 0x000044c0, 0x00008980}, +- {0x00009e00, 0x0372131c, 0x0372131c}, +- {0x0000a230, 0x0000400b, 0x00004016}, +- {0x0000a254, 0x00000898, 0x00001130}, +-}; +- +-static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = { +- /* Addr allmodes */ +- {0x0000a398, 0x00000000}, +- {0x0000a39c, 0x6f7f0301}, +- {0x0000a3a0, 0xca9228ee}, +-}; +- + #endif /* INITVALS_9462_2P1_H */ +--- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h ++++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h +@@ -20,24 +20,11 @@ + + /* AR9485 1.1 */ + +-static const u32 ar9485_1_1_mac_postamble[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, +- {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, +- {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, +- {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, +- {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, +- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, +- {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, +- {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, +-}; ++#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1 + +-static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = { +- /* Addr allmodes */ +- {0x00018c00, 0x18012e5e}, +- {0x00018c04, 0x000801d8}, +- {0x00018c08, 0x0000080c}, +-}; ++#define ar9485_1_1_mac_postamble ar9331_1p1_mac_postamble ++ ++#define ar9485_1_1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484 + + static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = { + /* Addr allmodes */ +@@ -553,100 +540,6 @@ static const u32 ar9485Modes_low_ob_db_t + {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260}, + }; + +-static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, +- {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0x7999a83a, 0x7999a83a}, +- {0x0000a2dc, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552}, +- {0x0000a2e0, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552}, +- {0x0000a2e4, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552}, +- {0x0000a2e8, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552}, +- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8}, +- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000}, +- {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002}, +- {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004}, +- {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200}, +- {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202}, +- {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400}, +- {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402}, +- {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404}, +- {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603}, +- {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605}, +- {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03}, +- {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04}, +- {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20}, +- {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21}, +- {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62}, +- {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63}, +- {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65}, +- {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66}, +- {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645}, +- {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865}, +- {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86}, +- {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9}, +- {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb}, +- {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, +- {0x0000a580, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a584, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a588, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a58c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a590, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a594, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a598, 0x00000000, 0x00000000, 0x01404501, 0x01404501}, +- {0x0000a59c, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02}, +- {0x0000a5a0, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02}, +- {0x0000a5a4, 0x00000000, 0x00000000, 0x02808803, 0x02808803}, +- {0x0000a5a8, 0x00000000, 0x00000000, 0x04c14b04, 0x04c14b04}, +- {0x0000a5ac, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305}, +- {0x0000a5b0, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305}, +- {0x0000a5b4, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305}, +- {0x0000a5b8, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305}, +- {0x0000a5bc, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305}, +- {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db}, +- {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260}, +-}; +- + static const u32 ar9485Modes_green_spur_ob_db_tx_gain_1_1[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003}, +@@ -1101,20 +994,6 @@ static const u32 ar9485_common_rx_gain_1 + {0x0000a1fc, 0x00000296}, + }; + +-static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { +- /* Addr allmodes */ +- {0x00018c00, 0x18052e5e}, +- {0x00018c04, 0x000801d8}, +- {0x00018c08, 0x0000080c}, +-}; +- +-static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = { +- /* Addr allmodes */ +- {0x00018c00, 0x18053e5e}, +- {0x00018c04, 0x000801d8}, +- {0x00018c08, 0x0000080c}, +-}; +- + static const u32 ar9485_1_1_soc_preamble[][2] = { + /* Addr allmodes */ + {0x00004014, 0xba280400}, +@@ -1173,13 +1052,6 @@ static const u32 ar9485_1_1_baseband_pos + {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + }; + +-static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = { +- /* Addr allmodes */ +- {0x00018c00, 0x18013e5e}, +- {0x00018c04, 0x000801d8}, +- {0x00018c08, 0x0000080c}, +-}; +- + static const u32 ar9485_1_1_radio_postamble[][2] = { + /* Addr allmodes */ + {0x0001609c, 0x0b283f31}, +@@ -1351,11 +1223,18 @@ static const u32 ar9485_1_1_mac_core[][2 + {0x000083d0, 0x000301ff}, + }; + +-static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = { ++static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = { + /* Addr allmodes */ +- {0x0000a398, 0x00000000}, +- {0x0000a39c, 0x6f7f0301}, +- {0x0000a3a0, 0xca9228ee}, ++ {0x00018c00, 0x18013e5e}, ++ {0x00018c04, 0x000801d8}, ++ {0x00018c08, 0x0000080c}, ++}; ++ ++static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = { ++ /* Addr allmodes */ ++ {0x00018c00, 0x1801265e}, ++ {0x00018c04, 0x000801d8}, ++ {0x00018c08, 0x0000080c}, + }; + + #endif /* INITVALS_9485_H */ +--- a/drivers/net/wireless/ath/ath9k/pci.c ++++ b/drivers/net/wireless/ath/ath9k/pci.c +@@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i + 0x3219), + .driver_data = ATH9K_PCI_BT_ANT_DIV }, + ++ /* AR9485 cards with PLL power-save disabled by default. */ ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_AZWAVE, ++ 0x2C97), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_AZWAVE, ++ 0x2100), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ 0x1C56, /* ASKEY */ ++ 0x4001), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ 0x11AD, /* LITEON */ ++ 0x6627), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ 0x11AD, /* LITEON */ ++ 0x6628), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_FOXCONN, ++ 0xE04E), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_FOXCONN, ++ 0xE04F), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ 0x144F, /* ASKEY */ ++ 0x7197), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ 0x1B9A, /* XAVI */ ++ 0x2000), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ 0x1B9A, /* XAVI */ ++ 0x2001), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_AZWAVE, ++ 0x1186), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_AZWAVE, ++ 0x1F86), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_AZWAVE, ++ 0x1195), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_AZWAVE, ++ 0x1F95), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ 0x1B9A, /* XAVI */ ++ 0x1C00), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ 0x1B9A, /* XAVI */ ++ 0x1C01), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, ++ 0x0032, ++ PCI_VENDOR_ID_ASUSTEK, ++ 0x850D), ++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, ++ + { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ + { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ + +--- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h ++++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h +@@ -20,7 +20,15 @@ + + /* AR9462 2.0 */ + +-static const u32 ar9462_modes_fast_clock_2p0[][3] = { ++#define ar9462_2p0_mac_postamble ar9331_1p1_mac_postamble ++ ++#define ar9462_2p0_common_wo_xlna_rx_gain ar9300Common_wo_xlna_rx_gain_table_2p2 ++ ++#define ar9462_2p0_common_5g_xlna_only_rxgain ar9462_2p0_common_mixed_rx_gain ++ ++#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484 ++ ++static const u32 ar9462_2p0_modes_fast_clock[][3] = { + /* Addr 5G_HT20 5G_HT40 */ + {0x00001030, 0x00000268, 0x000004d0}, + {0x00001070, 0x0000018c, 0x00000318}, +@@ -33,13 +41,6 @@ static const u32 ar9462_modes_fast_clock + {0x0000a254, 0x00000898, 0x00001130}, + }; + +-static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = { +- /* Addr allmodes */ +- {0x00018c00, 0x18253ede}, +- {0x00018c04, 0x000801d8}, +- {0x00018c08, 0x0003780c}, +-}; +- + static const u32 ar9462_2p0_baseband_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d}, +@@ -99,7 +100,7 @@ static const u32 ar9462_2p0_baseband_pos + {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, + }; + +-static const u32 ar9462_common_rx_gain_table_2p0[][2] = { ++static const u32 ar9462_2p0_common_rx_gain[][2] = { + /* Addr allmodes */ + {0x0000a000, 0x00010000}, + {0x0000a004, 0x00030002}, +@@ -359,20 +360,13 @@ static const u32 ar9462_common_rx_gain_t + {0x0000b1fc, 0x00000196}, + }; + +-static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = { ++static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = { + /* Addr allmodes */ + {0x00018c00, 0x18213ede}, + {0x00018c04, 0x000801d8}, + {0x00018c08, 0x0003780c}, + }; + +-static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = { +- /* Addr allmodes */ +- {0x00018c00, 0x18212ede}, +- {0x00018c04, 0x000801d8}, +- {0x00018c08, 0x0003780c}, +-}; +- + static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, +@@ -380,348 +374,81 @@ static const u32 ar9462_2p0_radio_postam + {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, + }; + +-static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = { - /* Addr allmodes */ - {0x0000a000, 0x00010000}, - {0x0000a004, 0x00030002}, @@ -6905,14 +8719,14 @@ - {0x0000b074, 0x00000000}, - {0x0000b078, 0x00000000}, - {0x0000b07c, 0x00000000}, -- {0x0000b080, 0x2a2d2f32}, -- {0x0000b084, 0x21232328}, -- {0x0000b088, 0x19191c1e}, -- {0x0000b08c, 0x12141417}, -- {0x0000b090, 0x07070e0e}, -- {0x0000b094, 0x03030305}, -- {0x0000b098, 0x00000003}, -- {0x0000b09c, 0x00000000}, +- {0x0000b080, 0x32323232}, +- {0x0000b084, 0x2f2f3232}, +- {0x0000b088, 0x23282a2d}, +- {0x0000b08c, 0x1c1e2123}, +- {0x0000b090, 0x14171919}, +- {0x0000b094, 0x0e0e1214}, +- {0x0000b098, 0x03050707}, +- {0x0000b09c, 0x00030303}, - {0x0000b0a0, 0x00000000}, - {0x0000b0a4, 0x00000000}, - {0x0000b0a8, 0x00000000}, @@ -7003,7 +8817,14 @@ - {0x0000b1fc, 0x00000196}, -}; - --static const u32 ar9462_2p1_modes_low_ob_db_tx_gain[][5] = { +-static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = { +- /* Addr allmodes */ +- {0x0000a398, 0x00000000}, +- {0x0000a39c, 0x6f7f0301}, +- {0x0000a3a0, 0xca9228ee}, +-}; +- +-static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = { - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, - {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, @@ -7059,450 +8880,420 @@ - {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, - {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, - {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, -- {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, -- {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, -- {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, -- {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, -- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, -- {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, -- {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060}, -- {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, -- {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, -- {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, -- {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, --}; -- --static const u32 ar9462_2p1_modes_high_ob_db_tx_gain[][5] = { -- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ -- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, -- {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, -- {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, -- {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, -- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, -- {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de}, -- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, -- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, -- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, -- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, -- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, -- {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400}, -- {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402}, -- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, -- {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603}, -- {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02}, -- {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04}, -- {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20}, -- {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20}, -- {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22}, -- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24}, -- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640}, -- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660}, -- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861}, -- {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81}, -- {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83}, -- {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84}, -- {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3}, -- {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5}, -- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9}, -- {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb}, -- {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec}, -- {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0}, -- {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4}, -- {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, -- {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, -- {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, -- {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6}, -- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, -- {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, -- {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, -- {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, -- {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, -- {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, -- {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, -- {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, -- {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, -- {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, -- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, -- {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, -- {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060}, -- {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, -- {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4}, -- {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, -- {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, --}; -- --static const u32 ar9462_2p1_modes_mix_ob_db_tx_gain[][5] = { -- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ -- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, -- {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, -- {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, -- {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, -- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, -- {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de}, -- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, -- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002}, -- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004}, -- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200}, -- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202}, -- {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400}, -- {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402}, -- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404}, -- {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603}, -- {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02}, -- {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04}, -- {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20}, -- {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20}, -- {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22}, -- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24}, -- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640}, -- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660}, -- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861}, -- {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81}, -- {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83}, -- {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84}, -- {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3}, -- {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5}, -- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9}, -- {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb}, -- {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec}, -- {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0}, -- {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4}, -- {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, -- {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, -- {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, -- {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6}, -- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, -- {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, -- {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, -- {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, -- {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, -- {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, -- {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, -- {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, -- {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, -- {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, -- {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, -- {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, +- {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, +- {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, +- {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, +- {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, - {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +- {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, +- {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060}, +- {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, +- {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, +- {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, +- {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, -}; - --static const u32 ar9462_2p1_modes_fast_clock[][3] = { -- /* Addr 5G_HT20 5G_HT40 */ -- {0x00001030, 0x00000268, 0x000004d0}, -- {0x00001070, 0x0000018c, 0x00000318}, -- {0x000010b0, 0x00000fd0, 0x00001fa0}, -- {0x00008014, 0x044c044c, 0x08980898}, -- {0x0000801c, 0x148ec02b, 0x148ec057}, -- {0x00008318, 0x000044c0, 0x00008980}, -- {0x00009e00, 0x0372131c, 0x0372131c}, -- {0x0000a230, 0x0000400b, 0x00004016}, -- {0x0000a254, 0x00000898, 0x00001130}, --}; -- --static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = { -- /* Addr allmodes */ -- {0x0000a398, 0x00000000}, -- {0x0000a39c, 0x6f7f0301}, -- {0x0000a3a0, 0xca9228ee}, --}; -- - #endif /* INITVALS_9462_2P1_H */ ---- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h -+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h -@@ -32,13 +32,6 @@ static const u32 ar9485_1_1_mac_postambl - {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, - }; - --static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = { -- /* Addr allmodes */ -- {0x00018c00, 0x18012e5e}, -- {0x00018c04, 0x000801d8}, -- {0x00018c08, 0x0000080c}, --}; -- - static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = { - /* Addr allmodes */ - {0x00009e00, 0x037216a0}, -@@ -1101,20 +1094,6 @@ static const u32 ar9485_common_rx_gain_1 - {0x0000a1fc, 0x00000296}, - }; - --static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { -- /* Addr allmodes */ -- {0x00018c00, 0x18052e5e}, -- {0x00018c04, 0x000801d8}, -- {0x00018c08, 0x0000080c}, --}; -- --static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = { -- /* Addr allmodes */ -- {0x00018c00, 0x18053e5e}, -- {0x00018c04, 0x000801d8}, -- {0x00018c08, 0x0000080c}, --}; -- - static const u32 ar9485_1_1_soc_preamble[][2] = { - /* Addr allmodes */ - {0x00004014, 0xba280400}, -@@ -1173,13 +1152,6 @@ static const u32 ar9485_1_1_baseband_pos - {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, - }; - --static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = { -- /* Addr allmodes */ -- {0x00018c00, 0x18013e5e}, -- {0x00018c04, 0x000801d8}, -- {0x00018c08, 0x0000080c}, +-static const u32 ar9462_2p0_soc_postamble[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033}, -}; - - static const u32 ar9485_1_1_radio_postamble[][2] = { - /* Addr allmodes */ - {0x0001609c, 0x0b283f31}, -@@ -1358,4 +1330,18 @@ static const u32 ar9485_1_1_baseband_cor - {0x0000a3a0, 0xca9228ee}, - }; - -+static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = { -+ /* Addr allmodes */ -+ {0x00018c00, 0x18013e5e}, -+ {0x00018c04, 0x000801d8}, -+ {0x00018c08, 0x0000080c}, +-static const u32 ar9462_2p0_baseband_core[][2] = { ++static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = { ++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ ++ {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, ++ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, ++ {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, ++ {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, ++ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, ++ {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, ++ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, ++ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, ++ {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, ++ {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, ++ {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402}, ++ {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, ++ {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, ++ {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, ++ {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, ++ {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20}, ++ {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20}, ++ {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22}, ++ {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24}, ++ {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640}, ++ {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, ++ {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, ++ {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, ++ {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83}, ++ {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84}, ++ {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3}, ++ {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5}, ++ {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9}, ++ {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb}, ++ {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, ++ {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, ++ {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, ++ {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, ++ {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, ++ {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, ++ {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, ++ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, ++ {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, ++ {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501}, ++ {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03}, ++ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, ++ {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04}, ++ {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005}, ++ {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, ++ {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, ++ {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, ++ {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, ++ {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, ++ {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, ++ {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, ++ {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, ++ {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060}, ++ {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, ++ {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, ++ {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, ++ {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, +}; + -+static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = { -+ /* Addr allmodes */ -+ {0x00018c00, 0x1801265e}, -+ {0x00018c04, 0x000801d8}, -+ {0x00018c08, 0x0000080c}, ++static const u32 ar9462_2p0_soc_postamble[][5] = { ++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ ++ {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033}, +}; + - #endif /* INITVALS_9485_H */ ---- a/drivers/net/wireless/ath/ath9k/pci.c -+++ b/drivers/net/wireless/ath/ath9k/pci.c -@@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i - 0x3219), - .driver_data = ATH9K_PCI_BT_ANT_DIV }, - -+ /* AR9485 cards with PLL power-save disabled by default. */ -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_AZWAVE, -+ 0x2C97), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_AZWAVE, -+ 0x2100), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ 0x1C56, /* ASKEY */ -+ 0x4001), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ 0x11AD, /* LITEON */ -+ 0x6627), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ 0x11AD, /* LITEON */ -+ 0x6628), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_FOXCONN, -+ 0xE04E), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_FOXCONN, -+ 0xE04F), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ 0x144F, /* ASKEY */ -+ 0x7197), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ 0x1B9A, /* XAVI */ -+ 0x2000), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ 0x1B9A, /* XAVI */ -+ 0x2001), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_AZWAVE, -+ 0x1186), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_AZWAVE, -+ 0x1F86), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_AZWAVE, -+ 0x1195), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_AZWAVE, -+ 0x1F95), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ 0x1B9A, /* XAVI */ -+ 0x1C00), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ 0x1B9A, /* XAVI */ -+ 0x1C01), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, -+ 0x0032, -+ PCI_VENDOR_ID_ASUSTEK, -+ 0x850D), -+ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE }, -+ - { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ - { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ - ---- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h -+++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h -@@ -20,7 +20,7 @@ ++static const u32 ar9462_2p0_baseband_core[][2] = { + /* Addr allmodes */ + {0x00009800, 0xafe68e30}, + {0x00009804, 0xfd14e000}, +@@ -879,7 +606,7 @@ static const u32 ar9462_2p0_radio_postam + {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, + }; - /* AR9462 2.0 */ +-static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = { ++static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, + {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, +@@ -942,7 +669,7 @@ static const u32 ar9462_modes_mix_ob_db_ + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, + }; --static const u32 ar9462_modes_fast_clock_2p0[][3] = { -+static const u32 ar9462_2p0_modes_fast_clock[][3] = { - /* Addr 5G_HT20 5G_HT40 */ - {0x00001030, 0x00000268, 0x000004d0}, - {0x00001070, 0x0000018c, 0x00000318}, -@@ -33,13 +33,6 @@ static const u32 ar9462_modes_fast_clock - {0x0000a254, 0x00000898, 0x00001130}, +-static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = { ++static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, + {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, +@@ -1240,19 +967,7 @@ static const u32 ar9462_2p0_mac_core[][2 + {0x000083d0, 0x000301ff}, }; --static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = { -- /* Addr allmodes */ -- {0x00018c00, 0x18253ede}, -- {0x00018c04, 0x000801d8}, -- {0x00018c08, 0x0003780c}, +-static const u32 ar9462_2p0_mac_postamble[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, +- {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, +- {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, +- {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, +- {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, +- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, +- {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, +- {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, -}; - - static const u32 ar9462_2p0_baseband_postamble[][5] = { - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ - {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d}, -@@ -99,7 +92,7 @@ static const u32 ar9462_2p0_baseband_pos - {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, - }; - --static const u32 ar9462_common_rx_gain_table_2p0[][2] = { -+static const u32 ar9462_2p0_common_rx_gain[][2] = { +-static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = { ++static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = { /* Addr allmodes */ {0x0000a000, 0x00010000}, {0x0000a004, 0x00030002}, -@@ -359,20 +352,13 @@ static const u32 ar9462_common_rx_gain_t - {0x0000b1fc, 0x00000196}, - }; - --static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = { -+static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = { - /* Addr allmodes */ - {0x00018c00, 0x18213ede}, - {0x00018c04, 0x000801d8}, - {0x00018c08, 0x0003780c}, +@@ -1517,266 +1232,6 @@ static const u32 ar9462_2p0_baseband_pos + {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, }; --static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = { +-static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = { - /* Addr allmodes */ -- {0x00018c00, 0x18212ede}, -- {0x00018c04, 0x000801d8}, -- {0x00018c08, 0x0003780c}, +- {0x0000a000, 0x00010000}, +- {0x0000a004, 0x00030002}, +- {0x0000a008, 0x00050004}, +- {0x0000a00c, 0x00810080}, +- {0x0000a010, 0x00830082}, +- {0x0000a014, 0x01810180}, +- {0x0000a018, 0x01830182}, +- {0x0000a01c, 0x01850184}, +- {0x0000a020, 0x01890188}, +- {0x0000a024, 0x018b018a}, +- {0x0000a028, 0x018d018c}, +- {0x0000a02c, 0x03820190}, +- {0x0000a030, 0x03840383}, +- {0x0000a034, 0x03880385}, +- {0x0000a038, 0x038a0389}, +- {0x0000a03c, 0x038c038b}, +- {0x0000a040, 0x0390038d}, +- {0x0000a044, 0x03920391}, +- {0x0000a048, 0x03940393}, +- {0x0000a04c, 0x03960395}, +- {0x0000a050, 0x00000000}, +- {0x0000a054, 0x00000000}, +- {0x0000a058, 0x00000000}, +- {0x0000a05c, 0x00000000}, +- {0x0000a060, 0x00000000}, +- {0x0000a064, 0x00000000}, +- {0x0000a068, 0x00000000}, +- {0x0000a06c, 0x00000000}, +- {0x0000a070, 0x00000000}, +- {0x0000a074, 0x00000000}, +- {0x0000a078, 0x00000000}, +- {0x0000a07c, 0x00000000}, +- {0x0000a080, 0x29292929}, +- {0x0000a084, 0x29292929}, +- {0x0000a088, 0x29292929}, +- {0x0000a08c, 0x29292929}, +- {0x0000a090, 0x22292929}, +- {0x0000a094, 0x1d1d2222}, +- {0x0000a098, 0x0c111117}, +- {0x0000a09c, 0x00030303}, +- {0x0000a0a0, 0x00000000}, +- {0x0000a0a4, 0x00000000}, +- {0x0000a0a8, 0x00000000}, +- {0x0000a0ac, 0x00000000}, +- {0x0000a0b0, 0x00000000}, +- {0x0000a0b4, 0x00000000}, +- {0x0000a0b8, 0x00000000}, +- {0x0000a0bc, 0x00000000}, +- {0x0000a0c0, 0x001f0000}, +- {0x0000a0c4, 0x01000101}, +- {0x0000a0c8, 0x011e011f}, +- {0x0000a0cc, 0x011c011d}, +- {0x0000a0d0, 0x02030204}, +- {0x0000a0d4, 0x02010202}, +- {0x0000a0d8, 0x021f0200}, +- {0x0000a0dc, 0x0302021e}, +- {0x0000a0e0, 0x03000301}, +- {0x0000a0e4, 0x031e031f}, +- {0x0000a0e8, 0x0402031d}, +- {0x0000a0ec, 0x04000401}, +- {0x0000a0f0, 0x041e041f}, +- {0x0000a0f4, 0x0502041d}, +- {0x0000a0f8, 0x05000501}, +- {0x0000a0fc, 0x051e051f}, +- {0x0000a100, 0x06010602}, +- {0x0000a104, 0x061f0600}, +- {0x0000a108, 0x061d061e}, +- {0x0000a10c, 0x07020703}, +- {0x0000a110, 0x07000701}, +- {0x0000a114, 0x00000000}, +- {0x0000a118, 0x00000000}, +- {0x0000a11c, 0x00000000}, +- {0x0000a120, 0x00000000}, +- {0x0000a124, 0x00000000}, +- {0x0000a128, 0x00000000}, +- {0x0000a12c, 0x00000000}, +- {0x0000a130, 0x00000000}, +- {0x0000a134, 0x00000000}, +- {0x0000a138, 0x00000000}, +- {0x0000a13c, 0x00000000}, +- {0x0000a140, 0x001f0000}, +- {0x0000a144, 0x01000101}, +- {0x0000a148, 0x011e011f}, +- {0x0000a14c, 0x011c011d}, +- {0x0000a150, 0x02030204}, +- {0x0000a154, 0x02010202}, +- {0x0000a158, 0x021f0200}, +- {0x0000a15c, 0x0302021e}, +- {0x0000a160, 0x03000301}, +- {0x0000a164, 0x031e031f}, +- {0x0000a168, 0x0402031d}, +- {0x0000a16c, 0x04000401}, +- {0x0000a170, 0x041e041f}, +- {0x0000a174, 0x0502041d}, +- {0x0000a178, 0x05000501}, +- {0x0000a17c, 0x051e051f}, +- {0x0000a180, 0x06010602}, +- {0x0000a184, 0x061f0600}, +- {0x0000a188, 0x061d061e}, +- {0x0000a18c, 0x07020703}, +- {0x0000a190, 0x07000701}, +- {0x0000a194, 0x00000000}, +- {0x0000a198, 0x00000000}, +- {0x0000a19c, 0x00000000}, +- {0x0000a1a0, 0x00000000}, +- {0x0000a1a4, 0x00000000}, +- {0x0000a1a8, 0x00000000}, +- {0x0000a1ac, 0x00000000}, +- {0x0000a1b0, 0x00000000}, +- {0x0000a1b4, 0x00000000}, +- {0x0000a1b8, 0x00000000}, +- {0x0000a1bc, 0x00000000}, +- {0x0000a1c0, 0x00000000}, +- {0x0000a1c4, 0x00000000}, +- {0x0000a1c8, 0x00000000}, +- {0x0000a1cc, 0x00000000}, +- {0x0000a1d0, 0x00000000}, +- {0x0000a1d4, 0x00000000}, +- {0x0000a1d8, 0x00000000}, +- {0x0000a1dc, 0x00000000}, +- {0x0000a1e0, 0x00000000}, +- {0x0000a1e4, 0x00000000}, +- {0x0000a1e8, 0x00000000}, +- {0x0000a1ec, 0x00000000}, +- {0x0000a1f0, 0x00000396}, +- {0x0000a1f4, 0x00000396}, +- {0x0000a1f8, 0x00000396}, +- {0x0000a1fc, 0x00000196}, +- {0x0000b000, 0x00010000}, +- {0x0000b004, 0x00030002}, +- {0x0000b008, 0x00050004}, +- {0x0000b00c, 0x00810080}, +- {0x0000b010, 0x00830082}, +- {0x0000b014, 0x01810180}, +- {0x0000b018, 0x01830182}, +- {0x0000b01c, 0x01850184}, +- {0x0000b020, 0x02810280}, +- {0x0000b024, 0x02830282}, +- {0x0000b028, 0x02850284}, +- {0x0000b02c, 0x02890288}, +- {0x0000b030, 0x028b028a}, +- {0x0000b034, 0x0388028c}, +- {0x0000b038, 0x038a0389}, +- {0x0000b03c, 0x038c038b}, +- {0x0000b040, 0x0390038d}, +- {0x0000b044, 0x03920391}, +- {0x0000b048, 0x03940393}, +- {0x0000b04c, 0x03960395}, +- {0x0000b050, 0x00000000}, +- {0x0000b054, 0x00000000}, +- {0x0000b058, 0x00000000}, +- {0x0000b05c, 0x00000000}, +- {0x0000b060, 0x00000000}, +- {0x0000b064, 0x00000000}, +- {0x0000b068, 0x00000000}, +- {0x0000b06c, 0x00000000}, +- {0x0000b070, 0x00000000}, +- {0x0000b074, 0x00000000}, +- {0x0000b078, 0x00000000}, +- {0x0000b07c, 0x00000000}, +- {0x0000b080, 0x2a2d2f32}, +- {0x0000b084, 0x21232328}, +- {0x0000b088, 0x19191c1e}, +- {0x0000b08c, 0x12141417}, +- {0x0000b090, 0x07070e0e}, +- {0x0000b094, 0x03030305}, +- {0x0000b098, 0x00000003}, +- {0x0000b09c, 0x00000000}, +- {0x0000b0a0, 0x00000000}, +- {0x0000b0a4, 0x00000000}, +- {0x0000b0a8, 0x00000000}, +- {0x0000b0ac, 0x00000000}, +- {0x0000b0b0, 0x00000000}, +- {0x0000b0b4, 0x00000000}, +- {0x0000b0b8, 0x00000000}, +- {0x0000b0bc, 0x00000000}, +- {0x0000b0c0, 0x003f0020}, +- {0x0000b0c4, 0x00400041}, +- {0x0000b0c8, 0x0140005f}, +- {0x0000b0cc, 0x0160015f}, +- {0x0000b0d0, 0x017e017f}, +- {0x0000b0d4, 0x02410242}, +- {0x0000b0d8, 0x025f0240}, +- {0x0000b0dc, 0x027f0260}, +- {0x0000b0e0, 0x0341027e}, +- {0x0000b0e4, 0x035f0340}, +- {0x0000b0e8, 0x037f0360}, +- {0x0000b0ec, 0x04400441}, +- {0x0000b0f0, 0x0460045f}, +- {0x0000b0f4, 0x0541047f}, +- {0x0000b0f8, 0x055f0540}, +- {0x0000b0fc, 0x057f0560}, +- {0x0000b100, 0x06400641}, +- {0x0000b104, 0x0660065f}, +- {0x0000b108, 0x067e067f}, +- {0x0000b10c, 0x07410742}, +- {0x0000b110, 0x075f0740}, +- {0x0000b114, 0x077f0760}, +- {0x0000b118, 0x07800781}, +- {0x0000b11c, 0x07a0079f}, +- {0x0000b120, 0x07c107bf}, +- {0x0000b124, 0x000007c0}, +- {0x0000b128, 0x00000000}, +- {0x0000b12c, 0x00000000}, +- {0x0000b130, 0x00000000}, +- {0x0000b134, 0x00000000}, +- {0x0000b138, 0x00000000}, +- {0x0000b13c, 0x00000000}, +- {0x0000b140, 0x003f0020}, +- {0x0000b144, 0x00400041}, +- {0x0000b148, 0x0140005f}, +- {0x0000b14c, 0x0160015f}, +- {0x0000b150, 0x017e017f}, +- {0x0000b154, 0x02410242}, +- {0x0000b158, 0x025f0240}, +- {0x0000b15c, 0x027f0260}, +- {0x0000b160, 0x0341027e}, +- {0x0000b164, 0x035f0340}, +- {0x0000b168, 0x037f0360}, +- {0x0000b16c, 0x04400441}, +- {0x0000b170, 0x0460045f}, +- {0x0000b174, 0x0541047f}, +- {0x0000b178, 0x055f0540}, +- {0x0000b17c, 0x057f0560}, +- {0x0000b180, 0x06400641}, +- {0x0000b184, 0x0660065f}, +- {0x0000b188, 0x067e067f}, +- {0x0000b18c, 0x07410742}, +- {0x0000b190, 0x075f0740}, +- {0x0000b194, 0x077f0760}, +- {0x0000b198, 0x07800781}, +- {0x0000b19c, 0x07a0079f}, +- {0x0000b1a0, 0x07c107bf}, +- {0x0000b1a4, 0x000007c0}, +- {0x0000b1a8, 0x00000000}, +- {0x0000b1ac, 0x00000000}, +- {0x0000b1b0, 0x00000000}, +- {0x0000b1b4, 0x00000000}, +- {0x0000b1b8, 0x00000000}, +- {0x0000b1bc, 0x00000000}, +- {0x0000b1c0, 0x00000000}, +- {0x0000b1c4, 0x00000000}, +- {0x0000b1c8, 0x00000000}, +- {0x0000b1cc, 0x00000000}, +- {0x0000b1d0, 0x00000000}, +- {0x0000b1d4, 0x00000000}, +- {0x0000b1d8, 0x00000000}, +- {0x0000b1dc, 0x00000000}, +- {0x0000b1e0, 0x00000000}, +- {0x0000b1e4, 0x00000000}, +- {0x0000b1e8, 0x00000000}, +- {0x0000b1ec, 0x00000000}, +- {0x0000b1f0, 0x00000396}, +- {0x0000b1f4, 0x00000396}, +- {0x0000b1f8, 0x00000396}, +- {0x0000b1fc, 0x00000196}, -}; - - static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = { - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ - {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, -@@ -380,7 +366,7 @@ static const u32 ar9462_2p0_radio_postam - {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, - }; - --static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = { -+static const u32 ar9462_2p0_common_wo_xlna_rx_gain[][2] = { - /* Addr allmodes */ - {0x0000a000, 0x00010000}, - {0x0000a004, 0x00030002}, -@@ -647,7 +633,7 @@ static const u32 ar9462_2p0_baseband_cor - {0x0000a3a0, 0xca9228ee}, - }; - --static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = { -+static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = { - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, - {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, -@@ -879,7 +865,7 @@ static const u32 ar9462_2p0_radio_postam - {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, - }; - --static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = { -+static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = { - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, - {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, -@@ -942,7 +928,7 @@ static const u32 ar9462_modes_mix_ob_db_ - {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, - }; - --static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = { -+static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = { - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, - {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, -@@ -1252,7 +1238,7 @@ static const u32 ar9462_2p0_mac_postambl - {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, - }; - --static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = { -+static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = { - /* Addr allmodes */ - {0x0000a000, 0x00010000}, - {0x0000a004, 0x00030002}, -@@ -1517,7 +1503,7 @@ static const u32 ar9462_2p0_baseband_pos - {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282}, - }; - --static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = { -+static const u32 ar9462_2p0_common_5g_xlna_only_rxgain[][2] = { + static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] = { /* Addr allmodes */ - {0x0000a000, 0x00010000}, - {0x0000a004, 0x00030002}, + {0x00009fd0, 0x0a2d6b93}, --- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h +@@ -303,7 +303,7 @@ static const u32 ar9300_2p2_mac_postambl + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, +- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, ++ {0x00008120, 0x18f04800, 0x18f04800, 0x18f04810, 0x18f04810}, + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, + }; @@ -352,7 +352,7 @@ static const u32 ar9300_2p2_baseband_pos {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110}, {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, @@ -7542,6 +9333,205 @@ {0x0000a3f8, 0x0c9bd380}, {0x0000a3fc, 0x000f0f01}, {0x0000a400, 0x8fa91f01}, +@@ -534,107 +534,107 @@ static const u32 ar9300_2p2_baseband_cor + + static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, +- {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, +- {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352}, ++ {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584}, ++ {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800}, + {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +- {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9}, +- {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, +- {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002}, +- {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004}, +- {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200}, +- {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202}, +- {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400}, +- {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402}, +- {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404}, +- {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603}, +- {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02}, +- {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04}, +- {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20}, +- {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20}, +- {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22}, +- {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24}, +- {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640}, +- {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660}, +- {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861}, +- {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81}, +- {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83}, +- {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84}, +- {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3}, +- {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5}, +- {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9}, +- {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb}, +- {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, +- {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, +- {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, +- {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, +- {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, +- {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, +- {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, +- {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000}, +- {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002}, +- {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004}, +- {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200}, +- {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202}, +- {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400}, +- {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402}, +- {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404}, +- {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603}, +- {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02}, +- {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04}, +- {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20}, +- {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20}, +- {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22}, +- {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24}, +- {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640}, +- {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660}, +- {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861}, +- {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81}, +- {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83}, +- {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84}, +- {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3}, +- {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5}, +- {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9}, +- {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb}, +- {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, +- {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, +- {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, +- {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, +- {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, +- {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, +- {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, ++ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, ++ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, ++ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, ++ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, ++ {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202}, ++ {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400}, ++ {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402}, ++ {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404}, ++ {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603}, ++ {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02}, ++ {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04}, ++ {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20}, ++ {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20}, ++ {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22}, ++ {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24}, ++ {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640}, ++ {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660}, ++ {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861}, ++ {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81}, ++ {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83}, ++ {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84}, ++ {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3}, ++ {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5}, ++ {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9}, ++ {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb}, ++ {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec}, ++ {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec}, ++ {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec}, ++ {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec}, ++ {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec}, ++ {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec}, ++ {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec}, ++ {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, ++ {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, ++ {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, ++ {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200}, ++ {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202}, ++ {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400}, ++ {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402}, ++ {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404}, ++ {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603}, ++ {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02}, ++ {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04}, ++ {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20}, ++ {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20}, ++ {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22}, ++ {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24}, ++ {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640}, ++ {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660}, ++ {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861}, ++ {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81}, ++ {0x0000a5cc, 0x5e88442e, 0x5e88442e, 0x47801a83, 0x47801a83}, ++ {0x0000a5d0, 0x628a4431, 0x628a4431, 0x4a801c84, 0x4a801c84}, ++ {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3}, ++ {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5}, ++ {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9}, ++ {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb}, ++ {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec}, ++ {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec}, ++ {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec}, ++ {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec}, ++ {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec}, ++ {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec}, ++ {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec}, + {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, +- {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, +- {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, +- {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, +- {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, +- {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, +- {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, +- {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, +- {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, +- {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, +- {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000}, ++ {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000}, ++ {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000}, ++ {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000}, ++ {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501}, ++ {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501}, ++ {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03}, ++ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, ++ {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04}, ++ {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005}, ++ {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005}, ++ {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005}, ++ {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005}, ++ {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005}, ++ {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352}, ++ {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584}, ++ {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800}, + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, +- {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, +- {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, +- {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352}, ++ {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584}, ++ {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800}, + {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, +- {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, ++ {0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001}, + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, +- {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, ++ {0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001}, + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, +- {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, ++ {0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001}, + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, + }; + @@ -644,7 +644,7 @@ static const u32 ar9300Modes_high_ob_db_ {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800}, @@ -7574,7 +9564,7 @@ {0x00008250, 0x00000000}, {0x00008254, 0x00000000}, {0x00008258, 0x00000000}, -@@ -1726,14 +1726,14 @@ static const u32 ar9300PciePhy_pll_on_cl +@@ -1726,16 +1726,30 @@ static const u32 ar9300PciePhy_pll_on_cl static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = { /* Addr allmodes */ @@ -7591,6 +9581,22 @@ {0x00004040, 0x0008003b}, {0x00004044, 0x00000000}, }; + ++static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = { ++ /* Addr allmodes */ ++ {0x0000a398, 0x00000000}, ++ {0x0000a39c, 0x6f7f0301}, ++ {0x0000a3a0, 0xca9228ee}, ++}; ++ ++static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = { ++ /* Addr 5G 2G */ ++ {0x00009824, 0x5ac668d0, 0x5ac668d0}, ++ {0x00009e0c, 0x6d4000e2, 0x6d4000e2}, ++ {0x00009e14, 0x37b9625e, 0x37b9625e}, ++}; ++ + #endif /* INITVALS_9003_2P2_H */ --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p1_initvals.h @@ -0,0 +1,64 @@ @@ -7680,7 +9686,7 @@ + #define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2 -+#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484 ++#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484 + static const u32 ar9580_1p0_radio_postamble[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ @@ -7698,9 +9704,12 @@ {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, }; -@@ -44,9 +60,9 @@ static const u32 ar9580_1p0_baseband_cor - {0x00009814, 0x3280c00a}, - {0x00009818, 0x00000000}, +@@ -41,12 +57,10 @@ static const u32 ar9580_1p0_baseband_cor + {0x00009804, 0xfd14e000}, + {0x00009808, 0x9c0a9f6b}, + {0x0000980c, 0x04900000}, +- {0x00009814, 0x3280c00a}, +- {0x00009818, 0x00000000}, {0x0000981c, 0x00020028}, - {0x00009834, 0x6400a290}, + {0x00009834, 0x6400a190}, @@ -7710,7 +9719,7 @@ {0x00009880, 0x201fff00}, {0x00009884, 0x00001042}, {0x000098a4, 0x00200400}, -@@ -67,7 +83,7 @@ static const u32 ar9580_1p0_baseband_cor +@@ -67,7 +81,7 @@ static const u32 ar9580_1p0_baseband_cor {0x00009d04, 0x40206c10}, {0x00009d08, 0x009c4060}, {0x00009d0c, 0x9883800a}, @@ -7719,7 +9728,7 @@ {0x00009d14, 0x00c0040b}, {0x00009d18, 0x00000000}, {0x00009e08, 0x0038230c}, -@@ -198,8 +214,6 @@ static const u32 ar9580_1p0_baseband_cor +@@ -198,8 +212,6 @@ static const u32 ar9580_1p0_baseband_cor {0x0000c420, 0x00000000}, }; @@ -7728,7 +9737,7 @@ static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, -@@ -306,7 +320,112 @@ static const u32 ar9580_1p0_low_ob_db_tx +@@ -306,7 +318,112 @@ static const u32 ar9580_1p0_low_ob_db_tx {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, }; @@ -7842,7 +9851,7 @@ static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ -@@ -414,8 +533,6 @@ static const u32 ar9580_1p0_lowest_ob_db +@@ -414,8 +531,6 @@ static const u32 ar9580_1p0_lowest_ob_db {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, }; @@ -7851,7 +9860,7 @@ static const u32 ar9580_1p0_mac_core[][2] = { /* Addr allmodes */ {0x00000008, 0x00000000}, -@@ -679,14 +796,6 @@ static const u32 ar9580_1p0_mixed_ob_db_ +@@ -679,14 +794,6 @@ static const u32 ar9580_1p0_mixed_ob_db_ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, }; @@ -7866,12 +9875,13 @@ static const u32 ar9580_1p0_type6_tx_gain_table[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352}, -@@ -761,160 +870,264 @@ static const u32 ar9580_1p0_type6_tx_gai +@@ -761,165 +868,271 @@ static const u32 ar9580_1p0_type6_tx_gai {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, }; -static const u32 ar9580_1p0_soc_preamble[][2] = { -- /* Addr allmodes */ ++static const u32 ar9580_1p0_rx_gain_table[][2] = { + /* Addr allmodes */ - {0x000040a4, 0x00a0c1c9}, - {0x00007008, 0x00000000}, - {0x00007020, 0x00000000}, @@ -7883,8 +9893,7 @@ -#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0 - -static const u32 ar9580_1p0_radio_core[][2] = { -+static const u32 ar9580_1p0_rx_gain_table[][2] = { - /* Addr allmodes */ +- /* Addr allmodes */ - {0x00016000, 0x36db6db6}, - {0x00016004, 0x6db6db40}, - {0x00016008, 0x73f00000}, @@ -8283,44 +10292,2389 @@ + {0x0000b1fc, 0x00000196}, }; - static const u32 ar9580_1p0_baseband_postamble[][5] = { -@@ -956,7 +1169,7 @@ static const u32 ar9580_1p0_baseband_pos - {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110}, - {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, - {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, -- {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982}, -+ {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982}, - {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b}, - {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, - {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, ---- a/drivers/net/wireless/ath/ath9k/reg.h -+++ b/drivers/net/wireless/ath/ath9k/reg.h -@@ -809,6 +809,8 @@ - #define AR_SREV_REVISION_9462_21 3 - #define AR_SREV_VERSION_9565 0x2C0 - #define AR_SREV_REVISION_9565_10 0 -+#define AR_SREV_REVISION_9565_101 1 -+#define AR_SREV_REVISION_9565_11 2 - #define AR_SREV_VERSION_9550 0x400 + static const u32 ar9580_1p0_baseband_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, ++ {0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a}, ++ {0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, + {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, + {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, +@@ -956,7 +1169,7 @@ static const u32 ar9580_1p0_baseband_pos + {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110}, + {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, + {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, +- {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982}, ++ {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982}, + {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b}, + {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, +@@ -994,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll + {0x00004044, 0x00000000}, + }; + ++static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = { ++ /* Addr 5G 2G */ ++ {0x00009814, 0x3400c00f, 0x3400c00f}, ++ {0x00009824, 0x5ac668d0, 0x5ac668d0}, ++ {0x00009828, 0x06903080, 0x06903080}, ++ {0x00009e0c, 0x6d4000e2, 0x6d4000e2}, ++ {0x00009e14, 0x37b9625e, 0x37b9625e}, ++}; ++ + #endif /* INITVALS_9580_1P0_H */ +--- a/drivers/net/wireless/ath/ath9k/reg.h ++++ b/drivers/net/wireless/ath/ath9k/reg.h +@@ -809,6 +809,8 @@ + #define AR_SREV_REVISION_9462_21 3 + #define AR_SREV_VERSION_9565 0x2C0 + #define AR_SREV_REVISION_9565_10 0 ++#define AR_SREV_REVISION_9565_101 1 ++#define AR_SREV_REVISION_9565_11 2 + #define AR_SREV_VERSION_9550 0x400 + + #define AR_SREV_5416(_ah) \ +@@ -881,9 +883,6 @@ + + #define AR_SREV_9330(_ah) \ + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330)) +-#define AR_SREV_9330_10(_ah) \ +- (AR_SREV_9330((_ah)) && \ +- ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_10)) + #define AR_SREV_9330_11(_ah) \ + (AR_SREV_9330((_ah)) && \ + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11)) +@@ -927,10 +926,18 @@ + + #define AR_SREV_9565(_ah) \ + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565)) +- + #define AR_SREV_9565_10(_ah) \ + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10)) ++#define AR_SREV_9565_101(_ah) \ ++ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ ++ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101)) ++#define AR_SREV_9565_11(_ah) \ ++ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ ++ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11)) ++#define AR_SREV_9565_11_OR_LATER(_ah) \ ++ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ ++ ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11)) + + #define AR_SREV_9550(_ah) \ + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550)) +--- a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h ++++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h +@@ -18,6 +18,10 @@ + #ifndef INITVALS_9330_1P1_H + #define INITVALS_9330_1P1_H + ++#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484 ++ ++#define ar9331_modes_high_power_tx_gain_1p1 ar9331_modes_lowest_ob_db_tx_gain_1p1 ++ + static const u32 ar9331_1p1_baseband_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005}, +@@ -55,7 +59,7 @@ static const u32 ar9331_1p1_baseband_pos + {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, ++ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18}, + {0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982}, + {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a}, + {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +@@ -252,7 +256,7 @@ static const u32 ar9331_modes_low_ob_db_ + {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84}, + {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000}, + {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000}, +- {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0}, ++ {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d4, 0x000050d4}, + {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000}, + {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002}, + {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004}, +@@ -337,8 +341,6 @@ static const u32 ar9331_modes_low_ob_db_ + {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000}, + }; + +-#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484 +- + static const u32 ar9331_1p1_xtal_25M[][2] = { + /* Addr allmodes */ + {0x00007038, 0x000002f8}, +@@ -373,17 +375,17 @@ static const u32 ar9331_1p1_radio_core[] + {0x000160b4, 0x92480040}, + {0x000160c0, 0x006db6db}, + {0x000160c4, 0x0186db60}, +- {0x000160c8, 0x6db4db6c}, ++ {0x000160c8, 0x6db6db6c}, + {0x000160cc, 0x6de6c300}, + {0x000160d0, 0x14500820}, + {0x00016100, 0x04cb0001}, + {0x00016104, 0xfff80015}, + {0x00016108, 0x00080010}, + {0x0001610c, 0x00170000}, +- {0x00016140, 0x10800000}, ++ {0x00016140, 0x50804000}, + {0x00016144, 0x01884080}, + {0x00016148, 0x000080c0}, +- {0x00016280, 0x01000015}, ++ {0x00016280, 0x01001015}, + {0x00016284, 0x14d20000}, + {0x00016288, 0x00318000}, + {0x0001628c, 0x50000000}, +@@ -622,12 +624,12 @@ static const u32 ar9331_1p1_baseband_cor + {0x0000a370, 0x00000000}, + {0x0000a390, 0x00000001}, + {0x0000a394, 0x00000444}, +- {0x0000a398, 0x001f0e0f}, +- {0x0000a39c, 0x0075393f}, +- {0x0000a3a0, 0xb79f6427}, +- {0x0000a3a4, 0x00000000}, +- {0x0000a3a8, 0xaaaaaaaa}, +- {0x0000a3ac, 0x3c466478}, ++ {0x0000a398, 0x00000000}, ++ {0x0000a39c, 0x210d0401}, ++ {0x0000a3a0, 0xab9a7144}, ++ {0x0000a3a4, 0x00000011}, ++ {0x0000a3a8, 0x3c3c003d}, ++ {0x0000a3ac, 0x30310030}, + {0x0000a3c0, 0x20202020}, + {0x0000a3c4, 0x22222220}, + {0x0000a3c8, 0x20200020}, +@@ -686,100 +688,18 @@ static const u32 ar9331_1p1_baseband_cor + {0x0000a7dc, 0x00000001}, + }; + +-static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = { ++static const u32 ar9331_1p1_mac_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a}, +- {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52}, +- {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84}, +- {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000}, +- {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000}, +- {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0}, +- {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000}, +- {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002}, +- {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004}, +- {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200}, +- {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202}, +- {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400}, +- {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402}, +- {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404}, +- {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00}, +- {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02}, +- {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04}, +- {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20}, +- {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22}, +- {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24}, +- {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43}, +- {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42}, +- {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44}, +- {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64}, +- {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66}, +- {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6}, +- {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000}, +- {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002}, +- {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004}, +- {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200}, +- {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202}, +- {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400}, +- {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402}, +- {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404}, +- {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603}, +- {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02}, +- {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04}, +- {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20}, +- {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20}, +- {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22}, +- {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24}, +- {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640}, +- {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660}, +- {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861}, +- {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81}, +- {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83}, +- {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84}, +- {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3}, +- {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5}, +- {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9}, +- {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb}, +- {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec}, +- {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec}, +- {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec}, +- {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec}, +- {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec}, +- {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec}, +- {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec}, +- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, +- {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, +- {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802}, +- {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802}, +- {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03}, +- {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04}, +- {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04}, +- {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04}, +- {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04}, +- {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04}, +- {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04}, +- {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db}, +- {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000}, ++ {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, ++ {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, ++ {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, ++ {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, ++ {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, ++ {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, ++ {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, ++ {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, + }; + +-#define ar9331_1p1_mac_postamble ar9300_2p2_mac_postamble +- + static const u32 ar9331_1p1_soc_preamble[][2] = { + /* Addr allmodes */ + {0x00007020, 0x00000000}, +--- a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h ++++ b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h +@@ -18,6 +18,28 @@ + #ifndef INITVALS_9330_1P2_H + #define INITVALS_9330_1P2_H + ++#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2 ++ ++#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2 ++ ++#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2 ++ ++#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ++ ++#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M ++ ++#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M ++ ++#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble ++ ++#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble ++ ++#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble ++ ++#define ar9331_1p2_mac_core ar9331_1p1_mac_core ++ ++#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1 ++ + static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7}, +@@ -103,57 +125,6 @@ static const u32 ar9331_modes_high_ob_db + {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004}, + }; + +-#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2 +- +-#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_power_tx_gain_1p2 +- +-#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_low_ob_db_tx_gain_1p2 +- +-static const u32 ar9331_1p2_baseband_postamble[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005}, +- {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e}, +- {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, +- {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, +- {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, +- {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c}, +- {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044}, +- {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4}, +- {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020}, +- {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, +- {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e}, +- {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, +- {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, +- {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, +- {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221}, +- {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222}, +- {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324}, +- {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010}, +- {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, +- {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0}, +- {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, +- {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, +- {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff}, +- {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, +- {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, +- {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, +- {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, +- {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, +- {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501}, +- {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, +- {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, +- {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, +- {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981}, +- {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a}, +- {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020}, +- {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +-}; +- + static const u32 ar9331_1p2_radio_core[][2] = { + /* Addr allmodes */ + {0x00016000, 0x36db6db6}, +@@ -219,24 +190,318 @@ static const u32 ar9331_1p2_radio_core[] + {0x000163d4, 0x00000000}, + }; + +-#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484 +- +-#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M +- +-#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M +- +-#define ar9331_1p2_baseband_core ar9331_1p1_baseband_core +- +-#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble +- +-#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble +- +-#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble +- +-#define ar9331_1p2_mac_core ar9331_1p1_mac_core ++static const u32 ar9331_1p2_baseband_core[][2] = { ++ /* Addr allmodes */ ++ {0x00009800, 0xafe68e30}, ++ {0x00009804, 0xfd14e000}, ++ {0x00009808, 0x9c0a8f6b}, ++ {0x0000980c, 0x04800000}, ++ {0x00009814, 0x9280c00a}, ++ {0x00009818, 0x00000000}, ++ {0x0000981c, 0x00020028}, ++ {0x00009834, 0x5f3ca3de}, ++ {0x00009838, 0x0108ecff}, ++ {0x0000983c, 0x14750600}, ++ {0x00009880, 0x201fff00}, ++ {0x00009884, 0x00001042}, ++ {0x000098a4, 0x00200400}, ++ {0x000098b0, 0x32840bbe}, ++ {0x000098d0, 0x004b6a8e}, ++ {0x000098d4, 0x00000820}, ++ {0x000098dc, 0x00000000}, ++ {0x000098f0, 0x00000000}, ++ {0x000098f4, 0x00000000}, ++ {0x00009c04, 0x00000000}, ++ {0x00009c08, 0x03200000}, ++ {0x00009c0c, 0x00000000}, ++ {0x00009c10, 0x00000000}, ++ {0x00009c14, 0x00046384}, ++ {0x00009c18, 0x05b6b440}, ++ {0x00009c1c, 0x00b6b440}, ++ {0x00009d00, 0xc080a333}, ++ {0x00009d04, 0x40206c10}, ++ {0x00009d08, 0x009c4060}, ++ {0x00009d0c, 0x1883800a}, ++ {0x00009d10, 0x01834061}, ++ {0x00009d14, 0x00c00400}, ++ {0x00009d18, 0x00000000}, ++ {0x00009e08, 0x0038233c}, ++ {0x00009e24, 0x9927b515}, ++ {0x00009e28, 0x12ef0200}, ++ {0x00009e30, 0x06336f77}, ++ {0x00009e34, 0x6af6532f}, ++ {0x00009e38, 0x0cc80c00}, ++ {0x00009e40, 0x0d261820}, ++ {0x00009e4c, 0x00001004}, ++ {0x00009e50, 0x00ff03f1}, ++ {0x00009fc0, 0x803e4788}, ++ {0x00009fc4, 0x0001efb5}, ++ {0x00009fcc, 0x40000014}, ++ {0x0000a20c, 0x00000000}, ++ {0x0000a220, 0x00000000}, ++ {0x0000a224, 0x00000000}, ++ {0x0000a228, 0x10002310}, ++ {0x0000a23c, 0x00000000}, ++ {0x0000a244, 0x0c000000}, ++ {0x0000a2a0, 0x00000001}, ++ {0x0000a2c0, 0x00000001}, ++ {0x0000a2c8, 0x00000000}, ++ {0x0000a2cc, 0x18c43433}, ++ {0x0000a2d4, 0x00000000}, ++ {0x0000a2dc, 0x00000000}, ++ {0x0000a2e0, 0x00000000}, ++ {0x0000a2e4, 0x00000000}, ++ {0x0000a2e8, 0x00000000}, ++ {0x0000a2ec, 0x00000000}, ++ {0x0000a2f0, 0x00000000}, ++ {0x0000a2f4, 0x00000000}, ++ {0x0000a2f8, 0x00000000}, ++ {0x0000a344, 0x00000000}, ++ {0x0000a34c, 0x00000000}, ++ {0x0000a350, 0x0000a000}, ++ {0x0000a364, 0x00000000}, ++ {0x0000a370, 0x00000000}, ++ {0x0000a390, 0x00000001}, ++ {0x0000a394, 0x00000444}, ++ {0x0000a398, 0x001f0e0f}, ++ {0x0000a39c, 0x0075393f}, ++ {0x0000a3a0, 0xb79f6427}, ++ {0x0000a3a4, 0x00000000}, ++ {0x0000a3a8, 0xaaaaaaaa}, ++ {0x0000a3ac, 0x3c466478}, ++ {0x0000a3c0, 0x20202020}, ++ {0x0000a3c4, 0x22222220}, ++ {0x0000a3c8, 0x20200020}, ++ {0x0000a3cc, 0x20202020}, ++ {0x0000a3d0, 0x20202020}, ++ {0x0000a3d4, 0x20202020}, ++ {0x0000a3d8, 0x20202020}, ++ {0x0000a3dc, 0x20202020}, ++ {0x0000a3e0, 0x20202020}, ++ {0x0000a3e4, 0x20202020}, ++ {0x0000a3e8, 0x20202020}, ++ {0x0000a3ec, 0x20202020}, ++ {0x0000a3f0, 0x00000000}, ++ {0x0000a3f4, 0x00000006}, ++ {0x0000a3f8, 0x0cdbd380}, ++ {0x0000a3fc, 0x000f0f01}, ++ {0x0000a400, 0x8fa91f01}, ++ {0x0000a404, 0x00000000}, ++ {0x0000a408, 0x0e79e5c6}, ++ {0x0000a40c, 0x00820820}, ++ {0x0000a414, 0x1ce739ce}, ++ {0x0000a418, 0x2d001dce}, ++ {0x0000a41c, 0x1ce739ce}, ++ {0x0000a420, 0x000001ce}, ++ {0x0000a424, 0x1ce739ce}, ++ {0x0000a428, 0x000001ce}, ++ {0x0000a42c, 0x1ce739ce}, ++ {0x0000a430, 0x1ce739ce}, ++ {0x0000a434, 0x00000000}, ++ {0x0000a438, 0x00001801}, ++ {0x0000a43c, 0x00000000}, ++ {0x0000a440, 0x00000000}, ++ {0x0000a444, 0x00000000}, ++ {0x0000a448, 0x04000000}, ++ {0x0000a44c, 0x00000001}, ++ {0x0000a450, 0x00010000}, ++ {0x0000a458, 0x00000000}, ++ {0x0000a640, 0x00000000}, ++ {0x0000a644, 0x3fad9d74}, ++ {0x0000a648, 0x0048060a}, ++ {0x0000a64c, 0x00003c37}, ++ {0x0000a670, 0x03020100}, ++ {0x0000a674, 0x09080504}, ++ {0x0000a678, 0x0d0c0b0a}, ++ {0x0000a67c, 0x13121110}, ++ {0x0000a680, 0x31301514}, ++ {0x0000a684, 0x35343332}, ++ {0x0000a688, 0x00000036}, ++ {0x0000a690, 0x00000838}, ++ {0x0000a7c0, 0x00000000}, ++ {0x0000a7c4, 0xfffffffc}, ++ {0x0000a7c8, 0x00000000}, ++ {0x0000a7cc, 0x00000000}, ++ {0x0000a7d0, 0x00000000}, ++ {0x0000a7d4, 0x00000004}, ++ {0x0000a7dc, 0x00000001}, ++}; + +-#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1 ++static const u32 ar9331_1p2_baseband_postamble[][5] = { ++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ ++ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005}, ++ {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e}, ++ {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, ++ {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, ++ {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, ++ {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c}, ++ {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044}, ++ {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4}, ++ {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020}, ++ {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, ++ {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e}, ++ {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, ++ {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, ++ {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, ++ {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221}, ++ {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222}, ++ {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324}, ++ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010}, ++ {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, ++ {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0}, ++ {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, ++ {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, ++ {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff}, ++ {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, ++ {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, ++ {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, ++ {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, ++ {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, ++ {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501}, ++ {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, ++ {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, ++ {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, ++ {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981}, ++ {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a}, ++ {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020}, ++ {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++}; + +-#define ar9331_common_rx_gain_1p2 ar9485_common_rx_gain_1_1 ++static const u32 ar9331_common_rx_gain_1p2[][2] = { ++ /* Addr allmodes */ ++ {0x0000a000, 0x00010000}, ++ {0x0000a004, 0x00030002}, ++ {0x0000a008, 0x00050004}, ++ {0x0000a00c, 0x00810080}, ++ {0x0000a010, 0x01800082}, ++ {0x0000a014, 0x01820181}, ++ {0x0000a018, 0x01840183}, ++ {0x0000a01c, 0x01880185}, ++ {0x0000a020, 0x018a0189}, ++ {0x0000a024, 0x02850284}, ++ {0x0000a028, 0x02890288}, ++ {0x0000a02c, 0x03850384}, ++ {0x0000a030, 0x03890388}, ++ {0x0000a034, 0x038b038a}, ++ {0x0000a038, 0x038d038c}, ++ {0x0000a03c, 0x03910390}, ++ {0x0000a040, 0x03930392}, ++ {0x0000a044, 0x03950394}, ++ {0x0000a048, 0x00000396}, ++ {0x0000a04c, 0x00000000}, ++ {0x0000a050, 0x00000000}, ++ {0x0000a054, 0x00000000}, ++ {0x0000a058, 0x00000000}, ++ {0x0000a05c, 0x00000000}, ++ {0x0000a060, 0x00000000}, ++ {0x0000a064, 0x00000000}, ++ {0x0000a068, 0x00000000}, ++ {0x0000a06c, 0x00000000}, ++ {0x0000a070, 0x00000000}, ++ {0x0000a074, 0x00000000}, ++ {0x0000a078, 0x00000000}, ++ {0x0000a07c, 0x00000000}, ++ {0x0000a080, 0x28282828}, ++ {0x0000a084, 0x28282828}, ++ {0x0000a088, 0x28282828}, ++ {0x0000a08c, 0x28282828}, ++ {0x0000a090, 0x28282828}, ++ {0x0000a094, 0x21212128}, ++ {0x0000a098, 0x171c1c1c}, ++ {0x0000a09c, 0x02020212}, ++ {0x0000a0a0, 0x00000202}, ++ {0x0000a0a4, 0x00000000}, ++ {0x0000a0a8, 0x00000000}, ++ {0x0000a0ac, 0x00000000}, ++ {0x0000a0b0, 0x00000000}, ++ {0x0000a0b4, 0x00000000}, ++ {0x0000a0b8, 0x00000000}, ++ {0x0000a0bc, 0x00000000}, ++ {0x0000a0c0, 0x001f0000}, ++ {0x0000a0c4, 0x111f1100}, ++ {0x0000a0c8, 0x111d111e}, ++ {0x0000a0cc, 0x111b111c}, ++ {0x0000a0d0, 0x22032204}, ++ {0x0000a0d4, 0x22012202}, ++ {0x0000a0d8, 0x221f2200}, ++ {0x0000a0dc, 0x221d221e}, ++ {0x0000a0e0, 0x33013302}, ++ {0x0000a0e4, 0x331f3300}, ++ {0x0000a0e8, 0x4402331e}, ++ {0x0000a0ec, 0x44004401}, ++ {0x0000a0f0, 0x441e441f}, ++ {0x0000a0f4, 0x55015502}, ++ {0x0000a0f8, 0x551f5500}, ++ {0x0000a0fc, 0x6602551e}, ++ {0x0000a100, 0x66006601}, ++ {0x0000a104, 0x661e661f}, ++ {0x0000a108, 0x7703661d}, ++ {0x0000a10c, 0x77017702}, ++ {0x0000a110, 0x00007700}, ++ {0x0000a114, 0x00000000}, ++ {0x0000a118, 0x00000000}, ++ {0x0000a11c, 0x00000000}, ++ {0x0000a120, 0x00000000}, ++ {0x0000a124, 0x00000000}, ++ {0x0000a128, 0x00000000}, ++ {0x0000a12c, 0x00000000}, ++ {0x0000a130, 0x00000000}, ++ {0x0000a134, 0x00000000}, ++ {0x0000a138, 0x00000000}, ++ {0x0000a13c, 0x00000000}, ++ {0x0000a140, 0x001f0000}, ++ {0x0000a144, 0x111f1100}, ++ {0x0000a148, 0x111d111e}, ++ {0x0000a14c, 0x111b111c}, ++ {0x0000a150, 0x22032204}, ++ {0x0000a154, 0x22012202}, ++ {0x0000a158, 0x221f2200}, ++ {0x0000a15c, 0x221d221e}, ++ {0x0000a160, 0x33013302}, ++ {0x0000a164, 0x331f3300}, ++ {0x0000a168, 0x4402331e}, ++ {0x0000a16c, 0x44004401}, ++ {0x0000a170, 0x441e441f}, ++ {0x0000a174, 0x55015502}, ++ {0x0000a178, 0x551f5500}, ++ {0x0000a17c, 0x6602551e}, ++ {0x0000a180, 0x66006601}, ++ {0x0000a184, 0x661e661f}, ++ {0x0000a188, 0x7703661d}, ++ {0x0000a18c, 0x77017702}, ++ {0x0000a190, 0x00007700}, ++ {0x0000a194, 0x00000000}, ++ {0x0000a198, 0x00000000}, ++ {0x0000a19c, 0x00000000}, ++ {0x0000a1a0, 0x00000000}, ++ {0x0000a1a4, 0x00000000}, ++ {0x0000a1a8, 0x00000000}, ++ {0x0000a1ac, 0x00000000}, ++ {0x0000a1b0, 0x00000000}, ++ {0x0000a1b4, 0x00000000}, ++ {0x0000a1b8, 0x00000000}, ++ {0x0000a1bc, 0x00000000}, ++ {0x0000a1c0, 0x00000000}, ++ {0x0000a1c4, 0x00000000}, ++ {0x0000a1c8, 0x00000000}, ++ {0x0000a1cc, 0x00000000}, ++ {0x0000a1d0, 0x00000000}, ++ {0x0000a1d4, 0x00000000}, ++ {0x0000a1d8, 0x00000000}, ++ {0x0000a1dc, 0x00000000}, ++ {0x0000a1e0, 0x00000000}, ++ {0x0000a1e4, 0x00000000}, ++ {0x0000a1e8, 0x00000000}, ++ {0x0000a1ec, 0x00000000}, ++ {0x0000a1f0, 0x00000396}, ++ {0x0000a1f4, 0x00000396}, ++ {0x0000a1f8, 0x00000396}, ++ {0x0000a1fc, 0x00000296}, ++}; + + #endif /* INITVALS_9330_1P2_H */ +--- a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h ++++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h +@@ -20,6 +20,14 @@ + + /* AR955X 1.0 */ + ++#define ar955x_1p0_soc_postamble ar9300_2p2_soc_postamble ++ ++#define ar955x_1p0_common_rx_gain_table ar9300Common_rx_gain_table_2p2 ++ ++#define ar955x_1p0_common_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2 ++ ++#define ar955x_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484 ++ + static const u32 ar955x_1p0_radio_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330}, +@@ -37,13 +45,6 @@ static const u32 ar955x_1p0_radio_postam + {0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008}, + }; + +-static const u32 ar955x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { +- /* Addr allmodes */ +- {0x0000a398, 0x00000000}, +- {0x0000a39c, 0x6f7f0301}, +- {0x0000a3a0, 0xca9228ee}, +-}; +- + static const u32 ar955x_1p0_baseband_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, +@@ -473,266 +474,6 @@ static const u32 ar955x_1p0_mac_core[][2 + {0x000083d0, 0x8c7901ff}, + }; + +-static const u32 ar955x_1p0_common_rx_gain_table[][2] = { +- /* Addr allmodes */ +- {0x0000a000, 0x00010000}, +- {0x0000a004, 0x00030002}, +- {0x0000a008, 0x00050004}, +- {0x0000a00c, 0x00810080}, +- {0x0000a010, 0x00830082}, +- {0x0000a014, 0x01810180}, +- {0x0000a018, 0x01830182}, +- {0x0000a01c, 0x01850184}, +- {0x0000a020, 0x01890188}, +- {0x0000a024, 0x018b018a}, +- {0x0000a028, 0x018d018c}, +- {0x0000a02c, 0x01910190}, +- {0x0000a030, 0x01930192}, +- {0x0000a034, 0x01950194}, +- {0x0000a038, 0x038a0196}, +- {0x0000a03c, 0x038c038b}, +- {0x0000a040, 0x0390038d}, +- {0x0000a044, 0x03920391}, +- {0x0000a048, 0x03940393}, +- {0x0000a04c, 0x03960395}, +- {0x0000a050, 0x00000000}, +- {0x0000a054, 0x00000000}, +- {0x0000a058, 0x00000000}, +- {0x0000a05c, 0x00000000}, +- {0x0000a060, 0x00000000}, +- {0x0000a064, 0x00000000}, +- {0x0000a068, 0x00000000}, +- {0x0000a06c, 0x00000000}, +- {0x0000a070, 0x00000000}, +- {0x0000a074, 0x00000000}, +- {0x0000a078, 0x00000000}, +- {0x0000a07c, 0x00000000}, +- {0x0000a080, 0x22222229}, +- {0x0000a084, 0x1d1d1d1d}, +- {0x0000a088, 0x1d1d1d1d}, +- {0x0000a08c, 0x1d1d1d1d}, +- {0x0000a090, 0x171d1d1d}, +- {0x0000a094, 0x11111717}, +- {0x0000a098, 0x00030311}, +- {0x0000a09c, 0x00000000}, +- {0x0000a0a0, 0x00000000}, +- {0x0000a0a4, 0x00000000}, +- {0x0000a0a8, 0x00000000}, +- {0x0000a0ac, 0x00000000}, +- {0x0000a0b0, 0x00000000}, +- {0x0000a0b4, 0x00000000}, +- {0x0000a0b8, 0x00000000}, +- {0x0000a0bc, 0x00000000}, +- {0x0000a0c0, 0x001f0000}, +- {0x0000a0c4, 0x01000101}, +- {0x0000a0c8, 0x011e011f}, +- {0x0000a0cc, 0x011c011d}, +- {0x0000a0d0, 0x02030204}, +- {0x0000a0d4, 0x02010202}, +- {0x0000a0d8, 0x021f0200}, +- {0x0000a0dc, 0x0302021e}, +- {0x0000a0e0, 0x03000301}, +- {0x0000a0e4, 0x031e031f}, +- {0x0000a0e8, 0x0402031d}, +- {0x0000a0ec, 0x04000401}, +- {0x0000a0f0, 0x041e041f}, +- {0x0000a0f4, 0x0502041d}, +- {0x0000a0f8, 0x05000501}, +- {0x0000a0fc, 0x051e051f}, +- {0x0000a100, 0x06010602}, +- {0x0000a104, 0x061f0600}, +- {0x0000a108, 0x061d061e}, +- {0x0000a10c, 0x07020703}, +- {0x0000a110, 0x07000701}, +- {0x0000a114, 0x00000000}, +- {0x0000a118, 0x00000000}, +- {0x0000a11c, 0x00000000}, +- {0x0000a120, 0x00000000}, +- {0x0000a124, 0x00000000}, +- {0x0000a128, 0x00000000}, +- {0x0000a12c, 0x00000000}, +- {0x0000a130, 0x00000000}, +- {0x0000a134, 0x00000000}, +- {0x0000a138, 0x00000000}, +- {0x0000a13c, 0x00000000}, +- {0x0000a140, 0x001f0000}, +- {0x0000a144, 0x01000101}, +- {0x0000a148, 0x011e011f}, +- {0x0000a14c, 0x011c011d}, +- {0x0000a150, 0x02030204}, +- {0x0000a154, 0x02010202}, +- {0x0000a158, 0x021f0200}, +- {0x0000a15c, 0x0302021e}, +- {0x0000a160, 0x03000301}, +- {0x0000a164, 0x031e031f}, +- {0x0000a168, 0x0402031d}, +- {0x0000a16c, 0x04000401}, +- {0x0000a170, 0x041e041f}, +- {0x0000a174, 0x0502041d}, +- {0x0000a178, 0x05000501}, +- {0x0000a17c, 0x051e051f}, +- {0x0000a180, 0x06010602}, +- {0x0000a184, 0x061f0600}, +- {0x0000a188, 0x061d061e}, +- {0x0000a18c, 0x07020703}, +- {0x0000a190, 0x07000701}, +- {0x0000a194, 0x00000000}, +- {0x0000a198, 0x00000000}, +- {0x0000a19c, 0x00000000}, +- {0x0000a1a0, 0x00000000}, +- {0x0000a1a4, 0x00000000}, +- {0x0000a1a8, 0x00000000}, +- {0x0000a1ac, 0x00000000}, +- {0x0000a1b0, 0x00000000}, +- {0x0000a1b4, 0x00000000}, +- {0x0000a1b8, 0x00000000}, +- {0x0000a1bc, 0x00000000}, +- {0x0000a1c0, 0x00000000}, +- {0x0000a1c4, 0x00000000}, +- {0x0000a1c8, 0x00000000}, +- {0x0000a1cc, 0x00000000}, +- {0x0000a1d0, 0x00000000}, +- {0x0000a1d4, 0x00000000}, +- {0x0000a1d8, 0x00000000}, +- {0x0000a1dc, 0x00000000}, +- {0x0000a1e0, 0x00000000}, +- {0x0000a1e4, 0x00000000}, +- {0x0000a1e8, 0x00000000}, +- {0x0000a1ec, 0x00000000}, +- {0x0000a1f0, 0x00000396}, +- {0x0000a1f4, 0x00000396}, +- {0x0000a1f8, 0x00000396}, +- {0x0000a1fc, 0x00000196}, +- {0x0000b000, 0x00010000}, +- {0x0000b004, 0x00030002}, +- {0x0000b008, 0x00050004}, +- {0x0000b00c, 0x00810080}, +- {0x0000b010, 0x00830082}, +- {0x0000b014, 0x01810180}, +- {0x0000b018, 0x01830182}, +- {0x0000b01c, 0x01850184}, +- {0x0000b020, 0x02810280}, +- {0x0000b024, 0x02830282}, +- {0x0000b028, 0x02850284}, +- {0x0000b02c, 0x02890288}, +- {0x0000b030, 0x028b028a}, +- {0x0000b034, 0x0388028c}, +- {0x0000b038, 0x038a0389}, +- {0x0000b03c, 0x038c038b}, +- {0x0000b040, 0x0390038d}, +- {0x0000b044, 0x03920391}, +- {0x0000b048, 0x03940393}, +- {0x0000b04c, 0x03960395}, +- {0x0000b050, 0x00000000}, +- {0x0000b054, 0x00000000}, +- {0x0000b058, 0x00000000}, +- {0x0000b05c, 0x00000000}, +- {0x0000b060, 0x00000000}, +- {0x0000b064, 0x00000000}, +- {0x0000b068, 0x00000000}, +- {0x0000b06c, 0x00000000}, +- {0x0000b070, 0x00000000}, +- {0x0000b074, 0x00000000}, +- {0x0000b078, 0x00000000}, +- {0x0000b07c, 0x00000000}, +- {0x0000b080, 0x23232323}, +- {0x0000b084, 0x21232323}, +- {0x0000b088, 0x19191c1e}, +- {0x0000b08c, 0x12141417}, +- {0x0000b090, 0x07070e0e}, +- {0x0000b094, 0x03030305}, +- {0x0000b098, 0x00000003}, +- {0x0000b09c, 0x00000000}, +- {0x0000b0a0, 0x00000000}, +- {0x0000b0a4, 0x00000000}, +- {0x0000b0a8, 0x00000000}, +- {0x0000b0ac, 0x00000000}, +- {0x0000b0b0, 0x00000000}, +- {0x0000b0b4, 0x00000000}, +- {0x0000b0b8, 0x00000000}, +- {0x0000b0bc, 0x00000000}, +- {0x0000b0c0, 0x003f0020}, +- {0x0000b0c4, 0x00400041}, +- {0x0000b0c8, 0x0140005f}, +- {0x0000b0cc, 0x0160015f}, +- {0x0000b0d0, 0x017e017f}, +- {0x0000b0d4, 0x02410242}, +- {0x0000b0d8, 0x025f0240}, +- {0x0000b0dc, 0x027f0260}, +- {0x0000b0e0, 0x0341027e}, +- {0x0000b0e4, 0x035f0340}, +- {0x0000b0e8, 0x037f0360}, +- {0x0000b0ec, 0x04400441}, +- {0x0000b0f0, 0x0460045f}, +- {0x0000b0f4, 0x0541047f}, +- {0x0000b0f8, 0x055f0540}, +- {0x0000b0fc, 0x057f0560}, +- {0x0000b100, 0x06400641}, +- {0x0000b104, 0x0660065f}, +- {0x0000b108, 0x067e067f}, +- {0x0000b10c, 0x07410742}, +- {0x0000b110, 0x075f0740}, +- {0x0000b114, 0x077f0760}, +- {0x0000b118, 0x07800781}, +- {0x0000b11c, 0x07a0079f}, +- {0x0000b120, 0x07c107bf}, +- {0x0000b124, 0x000007c0}, +- {0x0000b128, 0x00000000}, +- {0x0000b12c, 0x00000000}, +- {0x0000b130, 0x00000000}, +- {0x0000b134, 0x00000000}, +- {0x0000b138, 0x00000000}, +- {0x0000b13c, 0x00000000}, +- {0x0000b140, 0x003f0020}, +- {0x0000b144, 0x00400041}, +- {0x0000b148, 0x0140005f}, +- {0x0000b14c, 0x0160015f}, +- {0x0000b150, 0x017e017f}, +- {0x0000b154, 0x02410242}, +- {0x0000b158, 0x025f0240}, +- {0x0000b15c, 0x027f0260}, +- {0x0000b160, 0x0341027e}, +- {0x0000b164, 0x035f0340}, +- {0x0000b168, 0x037f0360}, +- {0x0000b16c, 0x04400441}, +- {0x0000b170, 0x0460045f}, +- {0x0000b174, 0x0541047f}, +- {0x0000b178, 0x055f0540}, +- {0x0000b17c, 0x057f0560}, +- {0x0000b180, 0x06400641}, +- {0x0000b184, 0x0660065f}, +- {0x0000b188, 0x067e067f}, +- {0x0000b18c, 0x07410742}, +- {0x0000b190, 0x075f0740}, +- {0x0000b194, 0x077f0760}, +- {0x0000b198, 0x07800781}, +- {0x0000b19c, 0x07a0079f}, +- {0x0000b1a0, 0x07c107bf}, +- {0x0000b1a4, 0x000007c0}, +- {0x0000b1a8, 0x00000000}, +- {0x0000b1ac, 0x00000000}, +- {0x0000b1b0, 0x00000000}, +- {0x0000b1b4, 0x00000000}, +- {0x0000b1b8, 0x00000000}, +- {0x0000b1bc, 0x00000000}, +- {0x0000b1c0, 0x00000000}, +- {0x0000b1c4, 0x00000000}, +- {0x0000b1c8, 0x00000000}, +- {0x0000b1cc, 0x00000000}, +- {0x0000b1d0, 0x00000000}, +- {0x0000b1d4, 0x00000000}, +- {0x0000b1d8, 0x00000000}, +- {0x0000b1dc, 0x00000000}, +- {0x0000b1e0, 0x00000000}, +- {0x0000b1e4, 0x00000000}, +- {0x0000b1e8, 0x00000000}, +- {0x0000b1ec, 0x00000000}, +- {0x0000b1f0, 0x00000396}, +- {0x0000b1f4, 0x00000396}, +- {0x0000b1f8, 0x00000396}, +- {0x0000b1fc, 0x00000196}, +-}; +- + static const u32 ar955x_1p0_baseband_core[][2] = { + /* Addr allmodes */ + {0x00009800, 0xafe68e30}, +@@ -891,266 +632,6 @@ static const u32 ar955x_1p0_baseband_cor + {0x0000c420, 0x00000000}, + }; + +-static const u32 ar955x_1p0_common_wo_xlna_rx_gain_table[][2] = { +- /* Addr allmodes */ +- {0x0000a000, 0x00010000}, +- {0x0000a004, 0x00030002}, +- {0x0000a008, 0x00050004}, +- {0x0000a00c, 0x00810080}, +- {0x0000a010, 0x00830082}, +- {0x0000a014, 0x01810180}, +- {0x0000a018, 0x01830182}, +- {0x0000a01c, 0x01850184}, +- {0x0000a020, 0x01890188}, +- {0x0000a024, 0x018b018a}, +- {0x0000a028, 0x018d018c}, +- {0x0000a02c, 0x03820190}, +- {0x0000a030, 0x03840383}, +- {0x0000a034, 0x03880385}, +- {0x0000a038, 0x038a0389}, +- {0x0000a03c, 0x038c038b}, +- {0x0000a040, 0x0390038d}, +- {0x0000a044, 0x03920391}, +- {0x0000a048, 0x03940393}, +- {0x0000a04c, 0x03960395}, +- {0x0000a050, 0x00000000}, +- {0x0000a054, 0x00000000}, +- {0x0000a058, 0x00000000}, +- {0x0000a05c, 0x00000000}, +- {0x0000a060, 0x00000000}, +- {0x0000a064, 0x00000000}, +- {0x0000a068, 0x00000000}, +- {0x0000a06c, 0x00000000}, +- {0x0000a070, 0x00000000}, +- {0x0000a074, 0x00000000}, +- {0x0000a078, 0x00000000}, +- {0x0000a07c, 0x00000000}, +- {0x0000a080, 0x29292929}, +- {0x0000a084, 0x29292929}, +- {0x0000a088, 0x29292929}, +- {0x0000a08c, 0x29292929}, +- {0x0000a090, 0x22292929}, +- {0x0000a094, 0x1d1d2222}, +- {0x0000a098, 0x0c111117}, +- {0x0000a09c, 0x00030303}, +- {0x0000a0a0, 0x00000000}, +- {0x0000a0a4, 0x00000000}, +- {0x0000a0a8, 0x00000000}, +- {0x0000a0ac, 0x00000000}, +- {0x0000a0b0, 0x00000000}, +- {0x0000a0b4, 0x00000000}, +- {0x0000a0b8, 0x00000000}, +- {0x0000a0bc, 0x00000000}, +- {0x0000a0c0, 0x001f0000}, +- {0x0000a0c4, 0x01000101}, +- {0x0000a0c8, 0x011e011f}, +- {0x0000a0cc, 0x011c011d}, +- {0x0000a0d0, 0x02030204}, +- {0x0000a0d4, 0x02010202}, +- {0x0000a0d8, 0x021f0200}, +- {0x0000a0dc, 0x0302021e}, +- {0x0000a0e0, 0x03000301}, +- {0x0000a0e4, 0x031e031f}, +- {0x0000a0e8, 0x0402031d}, +- {0x0000a0ec, 0x04000401}, +- {0x0000a0f0, 0x041e041f}, +- {0x0000a0f4, 0x0502041d}, +- {0x0000a0f8, 0x05000501}, +- {0x0000a0fc, 0x051e051f}, +- {0x0000a100, 0x06010602}, +- {0x0000a104, 0x061f0600}, +- {0x0000a108, 0x061d061e}, +- {0x0000a10c, 0x07020703}, +- {0x0000a110, 0x07000701}, +- {0x0000a114, 0x00000000}, +- {0x0000a118, 0x00000000}, +- {0x0000a11c, 0x00000000}, +- {0x0000a120, 0x00000000}, +- {0x0000a124, 0x00000000}, +- {0x0000a128, 0x00000000}, +- {0x0000a12c, 0x00000000}, +- {0x0000a130, 0x00000000}, +- {0x0000a134, 0x00000000}, +- {0x0000a138, 0x00000000}, +- {0x0000a13c, 0x00000000}, +- {0x0000a140, 0x001f0000}, +- {0x0000a144, 0x01000101}, +- {0x0000a148, 0x011e011f}, +- {0x0000a14c, 0x011c011d}, +- {0x0000a150, 0x02030204}, +- {0x0000a154, 0x02010202}, +- {0x0000a158, 0x021f0200}, +- {0x0000a15c, 0x0302021e}, +- {0x0000a160, 0x03000301}, +- {0x0000a164, 0x031e031f}, +- {0x0000a168, 0x0402031d}, +- {0x0000a16c, 0x04000401}, +- {0x0000a170, 0x041e041f}, +- {0x0000a174, 0x0502041d}, +- {0x0000a178, 0x05000501}, +- {0x0000a17c, 0x051e051f}, +- {0x0000a180, 0x06010602}, +- {0x0000a184, 0x061f0600}, +- {0x0000a188, 0x061d061e}, +- {0x0000a18c, 0x07020703}, +- {0x0000a190, 0x07000701}, +- {0x0000a194, 0x00000000}, +- {0x0000a198, 0x00000000}, +- {0x0000a19c, 0x00000000}, +- {0x0000a1a0, 0x00000000}, +- {0x0000a1a4, 0x00000000}, +- {0x0000a1a8, 0x00000000}, +- {0x0000a1ac, 0x00000000}, +- {0x0000a1b0, 0x00000000}, +- {0x0000a1b4, 0x00000000}, +- {0x0000a1b8, 0x00000000}, +- {0x0000a1bc, 0x00000000}, +- {0x0000a1c0, 0x00000000}, +- {0x0000a1c4, 0x00000000}, +- {0x0000a1c8, 0x00000000}, +- {0x0000a1cc, 0x00000000}, +- {0x0000a1d0, 0x00000000}, +- {0x0000a1d4, 0x00000000}, +- {0x0000a1d8, 0x00000000}, +- {0x0000a1dc, 0x00000000}, +- {0x0000a1e0, 0x00000000}, +- {0x0000a1e4, 0x00000000}, +- {0x0000a1e8, 0x00000000}, +- {0x0000a1ec, 0x00000000}, +- {0x0000a1f0, 0x00000396}, +- {0x0000a1f4, 0x00000396}, +- {0x0000a1f8, 0x00000396}, +- {0x0000a1fc, 0x00000196}, +- {0x0000b000, 0x00010000}, +- {0x0000b004, 0x00030002}, +- {0x0000b008, 0x00050004}, +- {0x0000b00c, 0x00810080}, +- {0x0000b010, 0x00830082}, +- {0x0000b014, 0x01810180}, +- {0x0000b018, 0x01830182}, +- {0x0000b01c, 0x01850184}, +- {0x0000b020, 0x02810280}, +- {0x0000b024, 0x02830282}, +- {0x0000b028, 0x02850284}, +- {0x0000b02c, 0x02890288}, +- {0x0000b030, 0x028b028a}, +- {0x0000b034, 0x0388028c}, +- {0x0000b038, 0x038a0389}, +- {0x0000b03c, 0x038c038b}, +- {0x0000b040, 0x0390038d}, +- {0x0000b044, 0x03920391}, +- {0x0000b048, 0x03940393}, +- {0x0000b04c, 0x03960395}, +- {0x0000b050, 0x00000000}, +- {0x0000b054, 0x00000000}, +- {0x0000b058, 0x00000000}, +- {0x0000b05c, 0x00000000}, +- {0x0000b060, 0x00000000}, +- {0x0000b064, 0x00000000}, +- {0x0000b068, 0x00000000}, +- {0x0000b06c, 0x00000000}, +- {0x0000b070, 0x00000000}, +- {0x0000b074, 0x00000000}, +- {0x0000b078, 0x00000000}, +- {0x0000b07c, 0x00000000}, +- {0x0000b080, 0x32323232}, +- {0x0000b084, 0x2f2f3232}, +- {0x0000b088, 0x23282a2d}, +- {0x0000b08c, 0x1c1e2123}, +- {0x0000b090, 0x14171919}, +- {0x0000b094, 0x0e0e1214}, +- {0x0000b098, 0x03050707}, +- {0x0000b09c, 0x00030303}, +- {0x0000b0a0, 0x00000000}, +- {0x0000b0a4, 0x00000000}, +- {0x0000b0a8, 0x00000000}, +- {0x0000b0ac, 0x00000000}, +- {0x0000b0b0, 0x00000000}, +- {0x0000b0b4, 0x00000000}, +- {0x0000b0b8, 0x00000000}, +- {0x0000b0bc, 0x00000000}, +- {0x0000b0c0, 0x003f0020}, +- {0x0000b0c4, 0x00400041}, +- {0x0000b0c8, 0x0140005f}, +- {0x0000b0cc, 0x0160015f}, +- {0x0000b0d0, 0x017e017f}, +- {0x0000b0d4, 0x02410242}, +- {0x0000b0d8, 0x025f0240}, +- {0x0000b0dc, 0x027f0260}, +- {0x0000b0e0, 0x0341027e}, +- {0x0000b0e4, 0x035f0340}, +- {0x0000b0e8, 0x037f0360}, +- {0x0000b0ec, 0x04400441}, +- {0x0000b0f0, 0x0460045f}, +- {0x0000b0f4, 0x0541047f}, +- {0x0000b0f8, 0x055f0540}, +- {0x0000b0fc, 0x057f0560}, +- {0x0000b100, 0x06400641}, +- {0x0000b104, 0x0660065f}, +- {0x0000b108, 0x067e067f}, +- {0x0000b10c, 0x07410742}, +- {0x0000b110, 0x075f0740}, +- {0x0000b114, 0x077f0760}, +- {0x0000b118, 0x07800781}, +- {0x0000b11c, 0x07a0079f}, +- {0x0000b120, 0x07c107bf}, +- {0x0000b124, 0x000007c0}, +- {0x0000b128, 0x00000000}, +- {0x0000b12c, 0x00000000}, +- {0x0000b130, 0x00000000}, +- {0x0000b134, 0x00000000}, +- {0x0000b138, 0x00000000}, +- {0x0000b13c, 0x00000000}, +- {0x0000b140, 0x003f0020}, +- {0x0000b144, 0x00400041}, +- {0x0000b148, 0x0140005f}, +- {0x0000b14c, 0x0160015f}, +- {0x0000b150, 0x017e017f}, +- {0x0000b154, 0x02410242}, +- {0x0000b158, 0x025f0240}, +- {0x0000b15c, 0x027f0260}, +- {0x0000b160, 0x0341027e}, +- {0x0000b164, 0x035f0340}, +- {0x0000b168, 0x037f0360}, +- {0x0000b16c, 0x04400441}, +- {0x0000b170, 0x0460045f}, +- {0x0000b174, 0x0541047f}, +- {0x0000b178, 0x055f0540}, +- {0x0000b17c, 0x057f0560}, +- {0x0000b180, 0x06400641}, +- {0x0000b184, 0x0660065f}, +- {0x0000b188, 0x067e067f}, +- {0x0000b18c, 0x07410742}, +- {0x0000b190, 0x075f0740}, +- {0x0000b194, 0x077f0760}, +- {0x0000b198, 0x07800781}, +- {0x0000b19c, 0x07a0079f}, +- {0x0000b1a0, 0x07c107bf}, +- {0x0000b1a4, 0x000007c0}, +- {0x0000b1a8, 0x00000000}, +- {0x0000b1ac, 0x00000000}, +- {0x0000b1b0, 0x00000000}, +- {0x0000b1b4, 0x00000000}, +- {0x0000b1b8, 0x00000000}, +- {0x0000b1bc, 0x00000000}, +- {0x0000b1c0, 0x00000000}, +- {0x0000b1c4, 0x00000000}, +- {0x0000b1c8, 0x00000000}, +- {0x0000b1cc, 0x00000000}, +- {0x0000b1d0, 0x00000000}, +- {0x0000b1d4, 0x00000000}, +- {0x0000b1d8, 0x00000000}, +- {0x0000b1dc, 0x00000000}, +- {0x0000b1e0, 0x00000000}, +- {0x0000b1e4, 0x00000000}, +- {0x0000b1e8, 0x00000000}, +- {0x0000b1ec, 0x00000000}, +- {0x0000b1f0, 0x00000396}, +- {0x0000b1f4, 0x00000396}, +- {0x0000b1f8, 0x00000396}, +- {0x0000b1fc, 0x00000196}, +-}; +- + static const u32 ar955x_1p0_soc_preamble[][2] = { + /* Addr allmodes */ + {0x00007000, 0x00000000}, +@@ -1263,11 +744,6 @@ static const u32 ar955x_1p0_modes_no_xpa + {0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401}, + }; + +-static const u32 ar955x_1p0_soc_postamble[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023}, +-}; +- + static const u32 ar955x_1p0_modes_fast_clock[][3] = { + /* Addr 5G_HT20 5G_HT40 */ + {0x00001030, 0x00000268, 0x000004d0}, +--- a/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h ++++ b/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h +@@ -20,6 +20,12 @@ + + /* AR9565 1.0 */ + ++#define ar9565_1p0_mac_postamble ar9331_1p1_mac_postamble ++ ++#define ar9565_1p0_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table ++ ++#define ar9565_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484 ++ + static const u32 ar9565_1p0_mac_core[][2] = { + /* Addr allmodes */ + {0x00000008, 0x00000000}, +@@ -182,18 +188,6 @@ static const u32 ar9565_1p0_mac_core[][2 + {0x000083d0, 0x800301ff}, + }; + +-static const u32 ar9565_1p0_mac_postamble[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, +- {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, +- {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, +- {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, +- {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, +- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, +- {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, +- {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, +-}; +- + static const u32 ar9565_1p0_baseband_core[][2] = { + /* Addr allmodes */ + {0x00009800, 0xafe68e30}, +@@ -711,66 +705,6 @@ static const u32 ar9565_1p0_Common_rx_ga + {0x0000b1fc, 0x00000196}, + }; + +-static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = { +- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +- {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52}, +- {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84}, +- {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000}, +- {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000}, +- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, +- {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, +- {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004}, +- {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, +- {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, +- {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, +- {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402}, +- {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, +- {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, +- {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, +- {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, +- {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20}, +- {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20}, +- {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22}, +- {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24}, +- {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640}, +- {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, +- {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, +- {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, +- {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83}, +- {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84}, +- {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3}, +- {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5}, +- {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9}, +- {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb}, +- {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, +- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4}, +- {0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +- {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, +-}; +- + static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = { + /* Addr allmodes */ + {0x00018c00, 0x18212ede}, +@@ -1231,11 +1165,4 @@ static const u32 ar9565_1p0_modes_high_p + {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + }; + +-static const u32 ar9565_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { +- /* Addr allmodes */ +- {0x0000a398, 0x00000000}, +- {0x0000a39c, 0x6f7f0301}, +- {0x0000a3a0, 0xca9228ee}, +-}; +- + #endif /* INITVALS_9565_1P0_H */ +--- a/include/linux/ath9k_platform.h ++++ b/include/linux/ath9k_platform.h +@@ -32,6 +32,8 @@ struct ath9k_platform_data { + u32 gpio_val; + + bool is_clk_25mhz; ++ bool tx_gain_buffalo; ++ + int (*get_mac_revision)(void); + int (*external_reset)(void); + }; +--- /dev/null ++++ b/drivers/net/wireless/ath/ath9k/ar9003_buffalo_initvals.h +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (c) 2013 Qualcomm Atheros Inc. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#ifndef INITVALS_9003_BUFFALO_H ++#define INITVALS_9003_BUFFALO_H ++ ++static const u32 ar9300Modes_high_power_tx_gain_table_buffalo[][5] = { ++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ ++ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, ++ {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, ++ {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, ++ {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9}, ++ {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, ++ {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002}, ++ {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004}, ++ {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200}, ++ {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202}, ++ {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400}, ++ {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402}, ++ {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404}, ++ {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603}, ++ {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02}, ++ {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04}, ++ {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20}, ++ {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20}, ++ {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22}, ++ {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24}, ++ {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640}, ++ {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660}, ++ {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861}, ++ {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81}, ++ {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83}, ++ {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84}, ++ {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3}, ++ {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5}, ++ {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9}, ++ {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb}, ++ {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, ++ {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, ++ {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, ++ {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, ++ {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, ++ {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, ++ {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, ++ {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000}, ++ {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002}, ++ {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004}, ++ {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200}, ++ {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202}, ++ {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400}, ++ {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402}, ++ {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404}, ++ {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603}, ++ {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02}, ++ {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04}, ++ {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20}, ++ {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20}, ++ {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22}, ++ {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24}, ++ {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640}, ++ {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660}, ++ {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861}, ++ {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81}, ++ {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83}, ++ {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84}, ++ {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3}, ++ {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5}, ++ {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9}, ++ {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb}, ++ {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, ++ {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, ++ {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, ++ {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, ++ {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, ++ {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, ++ {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, ++ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, ++ {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000}, ++ {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000}, ++ {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501}, ++ {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501}, ++ {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03}, ++ {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04}, ++ {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04}, ++ {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, ++ {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, ++ {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, ++ {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, ++ {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005}, ++ {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, ++ {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, ++ {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, ++ {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, ++ {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, ++ {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800}, ++ {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000}, ++ {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, ++ {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, ++ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, ++ {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, ++ {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, ++ {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, ++ {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, ++ {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001}, ++ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, ++}; ++ ++#endif /* INITVALS_9003_BUFFALO_H */ +--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c ++++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c +@@ -76,9 +76,16 @@ static bool ar9002_hw_get_isr(struct ath + mask2 |= ATH9K_INT_CST; + if (isr2 & AR_ISR_S2_TSFOOR) + mask2 |= ATH9K_INT_TSFOOR; ++ ++ if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { ++ REG_WRITE(ah, AR_ISR_S2, isr2); ++ isr &= ~AR_ISR_BCNMISC; ++ } + } + +- isr = REG_READ(ah, AR_ISR_RAC); ++ if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) ++ isr = REG_READ(ah, AR_ISR_RAC); ++ + if (isr == 0xffffffff) { + *masked = 0; + return false; +@@ -97,11 +104,23 @@ static bool ar9002_hw_get_isr(struct ath + + *masked |= ATH9K_INT_TX; + +- s0_s = REG_READ(ah, AR_ISR_S0_S); ++ if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) { ++ s0_s = REG_READ(ah, AR_ISR_S0_S); ++ s1_s = REG_READ(ah, AR_ISR_S1_S); ++ } else { ++ s0_s = REG_READ(ah, AR_ISR_S0); ++ REG_WRITE(ah, AR_ISR_S0, s0_s); ++ s1_s = REG_READ(ah, AR_ISR_S1); ++ REG_WRITE(ah, AR_ISR_S1, s1_s); ++ ++ isr &= ~(AR_ISR_TXOK | ++ AR_ISR_TXDESC | ++ AR_ISR_TXERR | ++ AR_ISR_TXEOL); ++ } ++ + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); +- +- s1_s = REG_READ(ah, AR_ISR_S1_S); + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); + } +@@ -120,7 +139,12 @@ static bool ar9002_hw_get_isr(struct ath + if (isr & AR_ISR_GENTMR) { + u32 s5_s; - #define AR_SREV_5416(_ah) \ -@@ -927,10 +929,18 @@ +- s5_s = REG_READ(ah, AR_ISR_S5_S); ++ if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) { ++ s5_s = REG_READ(ah, AR_ISR_S5_S); ++ } else { ++ s5_s = REG_READ(ah, AR_ISR_S5); ++ } ++ + ah->intr_gen_timer_trigger = + MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); - #define AR_SREV_9565(_ah) \ - (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565)) +@@ -133,6 +157,16 @@ static bool ar9002_hw_get_isr(struct ath + if ((s5_s & AR_ISR_S5_TIM_TIMER) && + !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) + *masked |= ATH9K_INT_TIM_TIMER; ++ ++ if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { ++ REG_WRITE(ah, AR_ISR_S5, s5_s); ++ isr &= ~AR_ISR_GENTMR; ++ } ++ } ++ ++ if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { ++ REG_WRITE(ah, AR_ISR, isr); ++ REG_READ(ah, AR_ISR); + } + + if (sync_cause) { +--- a/drivers/net/wireless/ath/ath9k/antenna.c ++++ b/drivers/net/wireless/ath/ath9k/antenna.c +@@ -724,14 +724,14 @@ void ath_ant_comb_scan(struct ath_softc + struct ath_ant_comb *antcomb = &sc->ant_comb; + int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set; + int curr_main_set; +- int main_rssi = rs->rs_rssi_ctl0; +- int alt_rssi = rs->rs_rssi_ctl1; ++ int main_rssi = rs->rs_rssi_ctl[0]; ++ int alt_rssi = rs->rs_rssi_ctl[1]; + int rx_ant_conf, main_ant_conf; + bool short_scan = false, ret; + +- rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) & ++ rx_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_CURRENT_SHIFT) & + ATH_ANT_RX_MASK; +- main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) & ++ main_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_MAIN_SHIFT) & + ATH_ANT_RX_MASK; + + if (alt_rssi >= antcomb->low_rssi_thresh) { +--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c ++++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c +@@ -32,12 +32,8 @@ static int ar9002_hw_init_mode_regs(stru + return 0; + } + +- if (ah->config.pcie_clock_req) +- INIT_INI_ARRAY(&ah->iniPcieSerdes, +- ar9280PciePhy_clkreq_off_L1_9280); +- else +- INIT_INI_ARRAY(&ah->iniPcieSerdes, +- ar9280PciePhy_clkreq_always_on_L1_9280); ++ INIT_INI_ARRAY(&ah->iniPcieSerdes, ++ ar9280PciePhy_clkreq_always_on_L1_9280); + + if (AR_SREV_9287_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); +--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c ++++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c +@@ -201,7 +201,6 @@ static void ar9002_hw_spur_mitigate(stru + ath9k_hw_get_channel_centers(ah, chan, ¢ers); + freq = centers.synth_center; + +- ah->config.spurmode = SPUR_ENABLE_EEPROM; + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); + +--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c ++++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c +@@ -476,12 +476,12 @@ int ath9k_hw_process_rxdesc_edma(struct + + /* XXX: Keycache */ + rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined); +- rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00); +- rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01); +- rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02); +- rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10); +- rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11); +- rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12); ++ rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_RxRSSIAnt00); ++ rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_RxRSSIAnt01); ++ rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_RxRSSIAnt02); ++ rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_RxRSSIAnt10); ++ rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_RxRSSIAnt11); ++ rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_RxRSSIAnt12); + + if (rxsp->status11 & AR_RxKeyIdxValid) + rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); +--- a/drivers/net/wireless/ath/ath9k/beacon.c ++++ b/drivers/net/wireless/ath/ath9k/beacon.c +@@ -431,6 +431,33 @@ static void ath9k_beacon_init(struct ath + ath9k_hw_enable_interrupts(ah); + } + ++/* Calculate the modulo of a 64 bit TSF snapshot with a TU divisor */ ++static u32 ath9k_mod_tsf64_tu(u64 tsf, u32 div_tu) ++{ ++ u32 tsf_mod, tsf_hi, tsf_lo, mod_hi, mod_lo; ++ ++ tsf_mod = tsf & (BIT(10) - 1); ++ tsf_hi = tsf >> 32; ++ tsf_lo = ((u32) tsf) >> 10; ++ ++ mod_hi = tsf_hi % div_tu; ++ mod_lo = ((mod_hi << 22) + tsf_lo) % div_tu; ++ ++ return (mod_lo << 10) | tsf_mod; ++} ++ ++static u32 ath9k_get_next_tbtt(struct ath_softc *sc, u64 tsf, ++ unsigned int interval) ++{ ++ struct ath_hw *ah = sc->sc_ah; ++ unsigned int offset; ++ ++ tsf += TU_TO_USEC(FUDGE + ah->config.sw_beacon_response_time); ++ offset = ath9k_mod_tsf64_tu(tsf, interval); ++ ++ return (u32) tsf + TU_TO_USEC(interval) - offset; ++} ++ + /* + * For multi-bss ap support beacons are either staggered evenly over N slots or + * burst together. For the former arrange for the SWBA to be delivered for each +@@ -446,7 +473,8 @@ static void ath9k_beacon_config_ap(struc + /* NB: the beacon interval is kept internally in TU's */ + intval = TU_TO_USEC(conf->beacon_interval); + intval /= ATH_BCBUF; +- nexttbtt = intval; ++ nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah), ++ conf->beacon_interval); + + if (conf->enable_beacon) + ah->imask |= ATH9K_INT_SWBA; +@@ -458,7 +486,7 @@ static void ath9k_beacon_config_ap(struc + (conf->enable_beacon) ? "Enable" : "Disable", + nexttbtt, intval, conf->beacon_interval); + +- ath9k_beacon_init(sc, nexttbtt, intval, true); ++ ath9k_beacon_init(sc, nexttbtt, intval, false); + } + + /* +@@ -475,11 +503,9 @@ static void ath9k_beacon_config_sta(stru + struct ath_hw *ah = sc->sc_ah; + struct ath_common *common = ath9k_hw_common(ah); + struct ath9k_beacon_state bs; +- int dtimperiod, dtimcount, sleepduration; +- int cfpperiod, cfpcount; +- u32 nexttbtt = 0, intval, tsftu; ++ int dtim_intval, sleepduration; ++ u32 nexttbtt = 0, intval; + u64 tsf; +- int num_beacons, offset, dtim_dec_count, cfp_dec_count; + + /* No need to configure beacon if we are not associated */ + if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { +@@ -492,53 +518,25 @@ static void ath9k_beacon_config_sta(stru + intval = conf->beacon_interval; + + /* +- * Setup dtim and cfp parameters according to ++ * Setup dtim parameters according to + * last beacon we received (which may be none). + */ +- dtimperiod = conf->dtim_period; +- dtimcount = conf->dtim_count; +- if (dtimcount >= dtimperiod) /* NB: sanity check */ +- dtimcount = 0; +- cfpperiod = 1; /* NB: no PCF support yet */ +- cfpcount = 0; - - #define AR_SREV_9565_10(_ah) \ - (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ - ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10)) -+#define AR_SREV_9565_101(_ah) \ -+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ -+ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101)) -+#define AR_SREV_9565_11(_ah) \ -+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ -+ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11)) -+#define AR_SREV_9565_11_OR_LATER(_ah) \ -+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ -+ ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11)) ++ dtim_intval = intval * conf->dtim_period; + sleepduration = conf->listen_interval * intval; - #define AR_SREV_9550(_ah) \ - (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550)) + /* + * Pull nexttbtt forward to reflect the current +- * TSF and calculate dtim+cfp state for the result. ++ * TSF and calculate dtim state for the result. + */ + tsf = ath9k_hw_gettsf64(ah); +- tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; +- +- num_beacons = tsftu / intval + 1; +- offset = tsftu % intval; +- nexttbtt = tsftu - offset; +- if (offset) +- nexttbtt += intval; +- +- /* DTIM Beacon every dtimperiod Beacon */ +- dtim_dec_count = num_beacons % dtimperiod; +- /* CFP every cfpperiod DTIM Beacon */ +- cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod; +- if (dtim_dec_count) +- cfp_dec_count++; +- +- dtimcount -= dtim_dec_count; +- if (dtimcount < 0) +- dtimcount += dtimperiod; +- +- cfpcount -= cfp_dec_count; +- if (cfpcount < 0) +- cfpcount += cfpperiod; ++ nexttbtt = ath9k_get_next_tbtt(sc, tsf, intval); + +- bs.bs_intval = intval; ++ bs.bs_intval = TU_TO_USEC(intval); ++ bs.bs_dtimperiod = conf->dtim_period * bs.bs_intval; + bs.bs_nexttbtt = nexttbtt; +- bs.bs_dtimperiod = dtimperiod*intval; +- bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; +- bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; +- bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; +- bs.bs_cfpmaxduration = 0; ++ bs.bs_nextdtim = nexttbtt; ++ if (conf->dtim_period > 1) ++ bs.bs_nextdtim = ath9k_get_next_tbtt(sc, tsf, dtim_intval); + + /* + * Calculate the number of consecutive beacons to miss* before taking +@@ -566,18 +564,16 @@ static void ath9k_beacon_config_sta(stru + * XXX fixed at 100ms + */ + +- bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration); ++ bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100), ++ sleepduration)); + if (bs.bs_sleepduration > bs.bs_dtimperiod) + bs.bs_sleepduration = bs.bs_dtimperiod; + + /* TSF out of range threshold fixed at 1 second */ + bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; + +- ath_dbg(common, BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); +- ath_dbg(common, BEACON, +- "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", +- bs.bs_bmissthreshold, bs.bs_sleepduration, +- bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); ++ ath_dbg(common, BEACON, "bmiss: %u sleep: %u\n", ++ bs.bs_bmissthreshold, bs.bs_sleepduration); + + /* Set the computed STA beacon timers */ + +@@ -600,25 +596,11 @@ static void ath9k_beacon_config_adhoc(st + + intval = TU_TO_USEC(conf->beacon_interval); + +- if (conf->ibss_creator) { ++ if (conf->ibss_creator) + nexttbtt = intval; +- } else { +- u32 tbtt, offset, tsftu; +- u64 tsf; +- +- /* +- * Pull nexttbtt forward to reflect the current +- * sync'd TSF. +- */ +- tsf = ath9k_hw_gettsf64(ah); +- tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE; +- offset = tsftu % conf->beacon_interval; +- tbtt = tsftu - offset; +- if (offset) +- tbtt += conf->beacon_interval; +- +- nexttbtt = TU_TO_USEC(tbtt); +- } ++ else ++ nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah), ++ conf->beacon_interval); + + if (conf->enable_beacon) + ah->imask |= ATH9K_INT_SWBA; +--- a/drivers/net/wireless/ath/ath9k/btcoex.c ++++ b/drivers/net/wireless/ath/ath9k/btcoex.c +@@ -66,7 +66,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_ + .bt_first_slot_time = 5, + .bt_hold_rx_clear = true, + }; +- u32 i, idx; + bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity; + + if (AR_SREV_9300_20_OR_LATER(ah)) +@@ -88,11 +87,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_ + SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) | + SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) | + AR_BT_DISABLE_BT_ANT; +- +- for (i = 0; i < 32; i++) { +- idx = (debruijn32 << i) >> 27; +- ah->hw_gen_timers.gen_timer_index[idx] = i; +- } + } + EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw); + +--- a/drivers/net/wireless/ath/ath9k/dfs.c ++++ b/drivers/net/wireless/ath/ath9k/dfs.c +@@ -158,8 +158,8 @@ void ath9k_dfs_process_phyerr(struct ath + return; + } + +- ard.rssi = rs->rs_rssi_ctl0; +- ard.ext_rssi = rs->rs_rssi_ext0; ++ ard.rssi = rs->rs_rssi_ctl[0]; ++ ard.ext_rssi = rs->rs_rssi_ext[0]; + + /* + * hardware stores this as 8 bit signed value. +--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c ++++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c +@@ -1085,31 +1085,7 @@ static void ath9k_hw_4k_set_board_values + + static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) + { +-#define EEP_MAP4K_SPURCHAN \ +- (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) +- struct ath_common *common = ath9k_hw_common(ah); +- +- u16 spur_val = AR_NO_SPUR; +- +- ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n", +- i, is2GHz, ah->config.spurchans[i][is2GHz]); +- +- switch (ah->config.spurmode) { +- case SPUR_DISABLE: +- break; +- case SPUR_ENABLE_IOCTL: +- spur_val = ah->config.spurchans[i][is2GHz]; +- ath_dbg(common, ANI, "Getting spur val from new loc. %d\n", +- spur_val); +- break; +- case SPUR_ENABLE_EEPROM: +- spur_val = EEP_MAP4K_SPURCHAN; +- break; +- } +- +- return spur_val; +- +-#undef EEP_MAP4K_SPURCHAN ++ return ah->eeprom.map4k.modalHeader.spurChans[i].spurChan; + } + + const struct eeprom_ops eep_4k_ops = { +--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c ++++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c +@@ -1004,31 +1004,7 @@ static void ath9k_hw_ar9287_set_board_va + static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, + u16 i, bool is2GHz) + { +-#define EEP_MAP9287_SPURCHAN \ +- (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) +- +- struct ath_common *common = ath9k_hw_common(ah); +- u16 spur_val = AR_NO_SPUR; +- +- ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n", +- i, is2GHz, ah->config.spurchans[i][is2GHz]); +- +- switch (ah->config.spurmode) { +- case SPUR_DISABLE: +- break; +- case SPUR_ENABLE_IOCTL: +- spur_val = ah->config.spurchans[i][is2GHz]; +- ath_dbg(common, ANI, "Getting spur val from new loc. %d\n", +- spur_val); +- break; +- case SPUR_ENABLE_EEPROM: +- spur_val = EEP_MAP9287_SPURCHAN; +- break; +- } +- +- return spur_val; +- +-#undef EEP_MAP9287_SPURCHAN ++ return ah->eeprom.map9287.modalHeader.spurChans[i].spurChan; + } + + const struct eeprom_ops eep_ar9287_ops = { +--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c ++++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c +@@ -1348,31 +1348,7 @@ static void ath9k_hw_def_set_txpower(str + + static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) + { +-#define EEP_DEF_SPURCHAN \ +- (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) +- struct ath_common *common = ath9k_hw_common(ah); +- +- u16 spur_val = AR_NO_SPUR; +- +- ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n", +- i, is2GHz, ah->config.spurchans[i][is2GHz]); +- +- switch (ah->config.spurmode) { +- case SPUR_DISABLE: +- break; +- case SPUR_ENABLE_IOCTL: +- spur_val = ah->config.spurchans[i][is2GHz]; +- ath_dbg(common, ANI, "Getting spur val from new loc. %d\n", +- spur_val); +- break; +- case SPUR_ENABLE_EEPROM: +- spur_val = EEP_DEF_SPURCHAN; +- break; +- } +- +- return spur_val; +- +-#undef EEP_DEF_SPURCHAN ++ return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan; + } + + const struct eeprom_ops eep_def_ops = { +--- a/drivers/net/wireless/ath/ath9k/gpio.c ++++ b/drivers/net/wireless/ath/ath9k/gpio.c +@@ -157,36 +157,6 @@ static void ath_detect_bt_priority(struc + } + } + +-static void ath9k_gen_timer_start(struct ath_hw *ah, +- struct ath_gen_timer *timer, +- u32 trig_timeout, +- u32 timer_period) +-{ +- ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period); +- +- if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { +- ath9k_hw_disable_interrupts(ah); +- ah->imask |= ATH9K_INT_GENTIMER; +- ath9k_hw_set_interrupts(ah); +- ath9k_hw_enable_interrupts(ah); +- } +-} +- +-static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) +-{ +- struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; +- +- ath9k_hw_gen_timer_stop(ah, timer); +- +- /* if no timer is enabled, turn off interrupt mask */ +- if (timer_table->timer_mask.val == 0) { +- ath9k_hw_disable_interrupts(ah); +- ah->imask &= ~ATH9K_INT_GENTIMER; +- ath9k_hw_set_interrupts(ah); +- ath9k_hw_enable_interrupts(ah); +- } +-} +- + static void ath_mci_ftp_adjust(struct ath_softc *sc) + { + struct ath_btcoex *btcoex = &sc->btcoex; +@@ -257,19 +227,9 @@ static void ath_btcoex_period_timer(unsi + + spin_unlock_bh(&btcoex->btcoex_lock); + +- /* +- * btcoex_period is in msec while (btocex/btscan_)no_stomp are in usec, +- * ensure that we properly convert btcoex_period to usec +- * for any comparision with (btcoex/btscan_)no_stomp. +- */ +- if (btcoex->btcoex_period * 1000 != btcoex->btcoex_no_stomp) { +- if (btcoex->hw_timer_enabled) +- ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer); +- +- ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period, +- timer_period * 10); +- btcoex->hw_timer_enabled = true; +- } ++ if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) ++ mod_timer(&btcoex->no_stomp_timer, ++ jiffies + msecs_to_jiffies(timer_period)); + + ath9k_ps_restore(sc); + +@@ -282,7 +242,7 @@ skip_hw_wakeup: + * Generic tsf based hw timer which configures weight + * registers to time slice between wlan and bt traffic + */ +-static void ath_btcoex_no_stomp_timer(void *arg) ++static void ath_btcoex_no_stomp_timer(unsigned long arg) + { + struct ath_softc *sc = (struct ath_softc *)arg; + struct ath_hw *ah = sc->sc_ah; +@@ -311,24 +271,18 @@ static int ath_init_btcoex_timer(struct + struct ath_btcoex *btcoex = &sc->btcoex; + + btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD; +- btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 1000 * ++ btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * + btcoex->btcoex_period / 100; +- btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 1000 * ++ btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * + btcoex->btcoex_period / 100; + + setup_timer(&btcoex->period_timer, ath_btcoex_period_timer, + (unsigned long) sc); ++ setup_timer(&btcoex->no_stomp_timer, ath_btcoex_no_stomp_timer, ++ (unsigned long) sc); + + spin_lock_init(&btcoex->btcoex_lock); + +- btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah, +- ath_btcoex_no_stomp_timer, +- ath_btcoex_no_stomp_timer, +- (void *) sc, AR_FIRST_NDP_TIMER); +- +- if (!btcoex->no_stomp_timer) +- return -ENOMEM; +- + return 0; + } + +@@ -343,10 +297,7 @@ void ath9k_btcoex_timer_resume(struct at + ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n"); + + /* make sure duty cycle timer is also stopped when resuming */ +- if (btcoex->hw_timer_enabled) { +- ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer); +- btcoex->hw_timer_enabled = false; +- } ++ del_timer_sync(&btcoex->no_stomp_timer); + + btcoex->bt_priority_cnt = 0; + btcoex->bt_priority_time = jiffies; +@@ -363,24 +314,16 @@ void ath9k_btcoex_timer_resume(struct at + void ath9k_btcoex_timer_pause(struct ath_softc *sc) + { + struct ath_btcoex *btcoex = &sc->btcoex; +- struct ath_hw *ah = sc->sc_ah; + + del_timer_sync(&btcoex->period_timer); +- +- if (btcoex->hw_timer_enabled) { +- ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer); +- btcoex->hw_timer_enabled = false; +- } ++ del_timer_sync(&btcoex->no_stomp_timer); + } + + void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) + { + struct ath_btcoex *btcoex = &sc->btcoex; + +- if (btcoex->hw_timer_enabled) { +- ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer); +- btcoex->hw_timer_enabled = false; +- } ++ del_timer_sync(&btcoex->no_stomp_timer); + } + + u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen) +@@ -400,12 +343,6 @@ u16 ath9k_btcoex_aggr_limit(struct ath_s + + void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status) + { +- struct ath_hw *ah = sc->sc_ah; +- +- if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) +- if (status & ATH9K_INT_GENTIMER) +- ath_gen_timer_isr(sc->sc_ah); +- + if (status & ATH9K_INT_MCI) + ath_mci_intr(sc); + } +@@ -447,10 +384,6 @@ void ath9k_deinit_btcoex(struct ath_soft + { + struct ath_hw *ah = sc->sc_ah; + +- if ((sc->btcoex.no_stomp_timer) && +- ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE) +- ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); +- + if (ath9k_hw_mci_is_enabled(ah)) + ath_mci_cleanup(sc); + } +--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c ++++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c +@@ -70,11 +70,11 @@ static void ath9k_htc_beacon_config_sta( + struct ath9k_beacon_state bs; + enum ath9k_int imask = 0; + int dtimperiod, dtimcount, sleepduration; +- int cfpperiod, cfpcount, bmiss_timeout; ++ int bmiss_timeout; + u32 nexttbtt = 0, intval, tsftu; + __be32 htc_imask = 0; + u64 tsf; +- int num_beacons, offset, dtim_dec_count, cfp_dec_count; ++ int num_beacons, offset, dtim_dec_count; + int ret __attribute__ ((unused)); + u8 cmd_rsp; + +@@ -84,7 +84,7 @@ static void ath9k_htc_beacon_config_sta( + bmiss_timeout = (ATH_DEFAULT_BMISS_LIMIT * bss_conf->beacon_interval); + + /* +- * Setup dtim and cfp parameters according to ++ * Setup dtim parameters according to + * last beacon we received (which may be none). + */ + dtimperiod = bss_conf->dtim_period; +@@ -93,8 +93,6 @@ static void ath9k_htc_beacon_config_sta( + dtimcount = 1; + if (dtimcount >= dtimperiod) /* NB: sanity check */ + dtimcount = 0; +- cfpperiod = 1; /* NB: no PCF support yet */ +- cfpcount = 0; + + sleepduration = intval; + if (sleepduration <= 0) +@@ -102,7 +100,7 @@ static void ath9k_htc_beacon_config_sta( + + /* + * Pull nexttbtt forward to reflect the current +- * TSF and calculate dtim+cfp state for the result. ++ * TSF and calculate dtim state for the result. + */ + tsf = ath9k_hw_gettsf64(priv->ah); + tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; +@@ -115,26 +113,14 @@ static void ath9k_htc_beacon_config_sta( + + /* DTIM Beacon every dtimperiod Beacon */ + dtim_dec_count = num_beacons % dtimperiod; +- /* CFP every cfpperiod DTIM Beacon */ +- cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod; +- if (dtim_dec_count) +- cfp_dec_count++; +- + dtimcount -= dtim_dec_count; + if (dtimcount < 0) + dtimcount += dtimperiod; + +- cfpcount -= cfp_dec_count; +- if (cfpcount < 0) +- cfpcount += cfpperiod; +- +- bs.bs_intval = intval; +- bs.bs_nexttbtt = nexttbtt; +- bs.bs_dtimperiod = dtimperiod*intval; +- bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; +- bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; +- bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; +- bs.bs_cfpmaxduration = 0; ++ bs.bs_intval = TU_TO_USEC(intval); ++ bs.bs_nexttbtt = TU_TO_USEC(nexttbtt); ++ bs.bs_dtimperiod = dtimperiod * bs.bs_intval; ++ bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount * bs.bs_intval; + + /* + * Calculate the number of consecutive beacons to miss* before taking +@@ -161,7 +147,8 @@ static void ath9k_htc_beacon_config_sta( + * XXX fixed at 100ms + */ + +- bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration); ++ bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100), ++ sleepduration)); + if (bs.bs_sleepduration > bs.bs_dtimperiod) + bs.bs_sleepduration = bs.bs_dtimperiod; + +@@ -170,10 +157,8 @@ static void ath9k_htc_beacon_config_sta( + + ath_dbg(common, CONFIG, "intval: %u tsf: %llu tsftu: %u\n", + intval, tsf, tsftu); +- ath_dbg(common, CONFIG, +- "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", +- bs.bs_bmissthreshold, bs.bs_sleepduration, +- bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); ++ ath_dbg(common, CONFIG, "bmiss: %u sleep: %u\n", ++ bs.bs_bmissthreshold, bs.bs_sleepduration); + + /* Set the computed STA beacon timers */ + +--- a/drivers/net/wireless/ath/ath9k/mac.c ++++ b/drivers/net/wireless/ath/ath9k/mac.c +@@ -481,8 +481,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw + | AR_Q_MISC_CBR_INCR_DIS0); + value = (qi->tqi_readyTime - + (ah->config.sw_beacon_response_time - +- ah->config.dma_beacon_response_time) - +- ah->config.additional_swba_backoff) * 1024; ++ ah->config.dma_beacon_response_time)) * 1024; + REG_WRITE(ah, AR_QRDYTIMECFG(q), + value | AR_Q_RDYTIMECFG_EN); + REG_SET_BIT(ah, AR_DMISC(q), +@@ -550,25 +549,25 @@ int ath9k_hw_rxprocdesc(struct ath_hw *a + + if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) { + rs->rs_rssi = ATH9K_RSSI_BAD; +- rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD; +- rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD; +- rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD; +- rs->rs_rssi_ext0 = ATH9K_RSSI_BAD; +- rs->rs_rssi_ext1 = ATH9K_RSSI_BAD; +- rs->rs_rssi_ext2 = ATH9K_RSSI_BAD; ++ rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD; ++ rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD; ++ rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD; ++ rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD; ++ rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD; ++ rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD; + } else { + rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); +- rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, ++ rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0, + AR_RxRSSIAnt00); +- rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, ++ rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0, + AR_RxRSSIAnt01); +- rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, ++ rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0, + AR_RxRSSIAnt02); +- rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4, ++ rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4, + AR_RxRSSIAnt10); +- rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4, ++ rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4, + AR_RxRSSIAnt11); +- rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4, ++ rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4, + AR_RxRSSIAnt12); + } + if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) +--- a/drivers/net/wireless/ath/ath9k/mac.h ++++ b/drivers/net/wireless/ath/ath9k/mac.h +@@ -133,12 +133,8 @@ struct ath_rx_status { + u8 rs_rate; + u8 rs_antenna; + u8 rs_more; +- int8_t rs_rssi_ctl0; +- int8_t rs_rssi_ctl1; +- int8_t rs_rssi_ctl2; +- int8_t rs_rssi_ext0; +- int8_t rs_rssi_ext1; +- int8_t rs_rssi_ext2; ++ int8_t rs_rssi_ctl[3]; ++ int8_t rs_rssi_ext[3]; + u8 rs_isaggr; + u8 rs_firstaggr; + u8 rs_moreaggr; +--- a/drivers/net/wireless/ath/ath9k/mci.c ++++ b/drivers/net/wireless/ath/ath9k/mci.c +@@ -200,7 +200,7 @@ skip_tuning: + if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE) + btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE; + +- btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 * ++ btcoex->btcoex_no_stomp = btcoex->btcoex_period * + (100 - btcoex->duty_cycle) / 100; + + ath9k_hw_btcoex_enable(sc->sc_ah); +--- a/drivers/net/wireless/ath/ath9k/recv.c ++++ b/drivers/net/wireless/ath/ath9k/recv.c +@@ -906,6 +906,7 @@ static void ath9k_process_rssi(struct at + struct ath_hw *ah = common->ah; + int last_rssi; + int rssi = rx_stats->rs_rssi; ++ int i, j; + + /* + * RSSI is not available for subframes in an A-MPDU. +@@ -924,6 +925,20 @@ static void ath9k_process_rssi(struct at + return; + } + ++ for (i = 0, j = 0; i < ARRAY_SIZE(rx_stats->rs_rssi_ctl); i++) { ++ s8 rssi; ++ ++ if (!(ah->rxchainmask & BIT(i))) ++ continue; ++ ++ rssi = rx_stats->rs_rssi_ctl[i]; ++ if (rssi != ATH9K_RSSI_BAD) { ++ rxs->chains |= BIT(j); ++ rxs->chain_signal[j] = ah->noise + rssi; ++ } ++ j++; ++ } ++ + /* + * Update Beacon RSSI, this is used by ANI. + */ +@@ -1073,14 +1088,14 @@ static int ath_process_fft(struct ath_so + fft_sample_40.channel_type = chan_type; + + if (chan_type == NL80211_CHAN_HT40PLUS) { +- lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0); +- upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0); ++ lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]); ++ upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]); + + fft_sample_40.lower_noise = ah->noise; + fft_sample_40.upper_noise = ext_nf; + } else { +- lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0); +- upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0); ++ lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]); ++ upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]); + + fft_sample_40.lower_noise = ext_nf; + fft_sample_40.upper_noise = ah->noise; +@@ -1116,7 +1131,7 @@ static int ath_process_fft(struct ath_so + fft_sample_20.tlv.length = __cpu_to_be16(length); + fft_sample_20.freq = __cpu_to_be16(freq); + +- fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0); ++ fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]); + fft_sample_20.noise = ah->noise; + + mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;