* ar8216.c: AR8216 switch driver
*
* Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/lockdep.h>
+#include <linux/ar8216_platform.h>
+#include <linux/workqueue.h>
#include "ar8216.h"
/* size of the vlan table */
#define AR8X16_MAX_VLANS 128
#define AR8X16_PROBE_RETRIES 10
+#define AR8X16_MAX_PORTS 8
+
+#define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
struct ar8216_priv;
-#define AR8XXX_CAP_GIGE BIT(0)
+#define AR8XXX_CAP_GIGE BIT(0)
+#define AR8XXX_CAP_MIB_COUNTERS BIT(1)
+
+enum {
+ AR8XXX_VER_AR8216 = 0x01,
+ AR8XXX_VER_AR8236 = 0x03,
+ AR8XXX_VER_AR8316 = 0x10,
+ AR8XXX_VER_AR8327 = 0x12,
+};
+
+struct ar8xxx_mib_desc {
+ unsigned int size;
+ unsigned int offset;
+ const char *name;
+};
struct ar8xxx_chip {
unsigned long caps;
int (*atu_flush)(struct ar8216_priv *priv);
void (*vtu_flush)(struct ar8216_priv *priv);
void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
+
+ const struct ar8xxx_mib_desc *mib_decs;
+ unsigned num_mibs;
};
struct ar8216_priv {
struct switch_dev dev;
+ struct mii_bus *mii_bus;
struct phy_device *phy;
u32 (*read)(struct ar8216_priv *priv, int reg);
void (*write)(struct ar8216_priv *priv, int reg, u32 val);
const struct net_device_ops *ndo_old;
struct net_device_ops ndo;
struct mutex reg_mutex;
- int chip_type;
+ u8 chip_ver;
+ u8 chip_rev;
const struct ar8xxx_chip *chip;
bool initialized;
bool port4_phy;
- char buf[80];
+ char buf[2048];
bool init;
+ bool mii_lo_first;
+
+ struct mutex mib_lock;
+ struct delayed_work mib_work;
+ int mib_next_port;
+ u64 *mib_stats;
+
+ struct list_head list;
+ unsigned int use_count;
/* all fields below are cleared on reset */
bool vlan;
u16 vlan_id[AR8X16_MAX_VLANS];
u8 vlan_table[AR8X16_MAX_VLANS];
u8 vlan_tagged;
- u16 pvid[AR8216_NUM_PORTS];
+ u16 pvid[AR8X16_MAX_PORTS];
};
-#define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
+#define MIB_DESC(_s , _o, _n) \
+ { \
+ .size = (_s), \
+ .offset = (_o), \
+ .name = (_n), \
+ }
+
+static const struct ar8xxx_mib_desc ar8216_mibs[] = {
+ MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
+ MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
+ MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
+ MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
+ MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
+ MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
+ MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
+ MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
+ MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
+ MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
+ MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
+ MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
+ MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
+ MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
+ MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
+ MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
+ MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
+ MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
+ MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
+ MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
+ MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
+ MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
+ MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
+ MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
+ MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
+ MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
+ MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
+ MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
+ MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
+ MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
+ MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
+ MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
+ MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
+ MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
+ MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
+ MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
+ MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
+};
+
+static const struct ar8xxx_mib_desc ar8236_mibs[] = {
+ MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
+ MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
+ MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
+ MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
+ MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
+ MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
+ MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
+ MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
+ MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
+ MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
+ MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
+ MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
+ MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
+ MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
+ MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
+ MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
+ MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
+ MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
+ MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
+ MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
+ MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
+ MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
+ MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
+ MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
+ MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
+ MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
+ MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
+ MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
+ MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
+ MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
+ MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
+ MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
+ MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
+ MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
+ MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
+ MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
+ MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
+ MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
+ MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
+};
+
+static DEFINE_MUTEX(ar8xxx_dev_list_lock);
+static LIST_HEAD(ar8xxx_dev_list);
+
+static inline struct ar8216_priv *
+swdev_to_ar8216(struct switch_dev *swdev)
+{
+ return container_of(swdev, struct ar8216_priv, dev);
+}
static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
{
return priv->chip->caps & AR8XXX_CAP_GIGE;
}
+static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
+{
+ return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
+}
+
+static inline bool chip_is_ar8216(struct ar8216_priv *priv)
+{
+ return priv->chip_ver == AR8XXX_VER_AR8216;
+}
+
+static inline bool chip_is_ar8236(struct ar8216_priv *priv)
+{
+ return priv->chip_ver == AR8XXX_VER_AR8236;
+}
+
+static inline bool chip_is_ar8316(struct ar8216_priv *priv)
+{
+ return priv->chip_ver == AR8XXX_VER_AR8316;
+}
+
+static inline bool chip_is_ar8327(struct ar8216_priv *priv)
+{
+ return priv->chip_ver == AR8XXX_VER_AR8327;
+}
+
static inline void
split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
{
static u32
ar8216_mii_read(struct ar8216_priv *priv, int reg)
{
- struct phy_device *phy = priv->phy;
- struct mii_bus *bus = phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
u16 lo, hi;
static void
ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
{
- struct phy_device *phy = priv->phy;
- struct mii_bus *bus = phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, r3;
u16 lo, hi;
bus->write(bus, 0x18, 0, r3);
usleep_range(1000, 2000); /* wait for the page switch to propagate */
- bus->write(bus, 0x10 | r2, r1 + 1, hi);
- bus->write(bus, 0x10 | r2, r1, lo);
+ if (priv->mii_lo_first) {
+ bus->write(bus, 0x10 | r2, r1, lo);
+ bus->write(bus, 0x10 | r2, r1 + 1, hi);
+ } else {
+ bus->write(bus, 0x10 | r2, r1 + 1, hi);
+ bus->write(bus, 0x10 | r2, r1, lo);
+ }
mutex_unlock(&bus->mdio_lock);
}
ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
u16 dbg_addr, u16 dbg_data)
{
- struct mii_bus *bus = priv->phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
mutex_lock(&bus->mdio_lock);
bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
mutex_unlock(&bus->mdio_lock);
}
+static void
+ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
+{
+ struct mii_bus *bus = priv->mii_bus;
+
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
+ bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
+ mutex_unlock(&bus->mdio_lock);
+}
+
static u32
ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
{
return v;
}
+static inline void
+ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
+{
+ u32 v;
+
+ lockdep_assert_held(&priv->reg_mutex);
+
+ v = priv->read(priv, reg);
+ v |= val;
+ priv->write(priv, reg, v);
+}
+
+static int
+ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
+ unsigned timeout)
+{
+ int i;
+
+ for (i = 0; i < timeout; i++) {
+ u32 t;
+
+ t = priv->read(priv, reg);
+ if ((t & mask) == val)
+ return 0;
+
+ usleep_range(1000, 2000);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int
+ar8216_mib_op(struct ar8216_priv *priv, u32 op)
+{
+ unsigned mib_func;
+ int ret;
+
+ lockdep_assert_held(&priv->mib_lock);
+
+ if (chip_is_ar8327(priv))
+ mib_func = AR8327_REG_MIB_FUNC;
+ else
+ mib_func = AR8216_REG_MIB_FUNC;
+
+ mutex_lock(&priv->reg_mutex);
+ /* Capture the hardware statistics for all ports */
+ ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
+ mutex_unlock(&priv->reg_mutex);
+
+ /* Wait for the capturing to complete. */
+ ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
+ if (ret)
+ goto out;
+
+ ret = 0;
+
+out:
+ return ret;
+}
+
+static int
+ar8216_mib_capture(struct ar8216_priv *priv)
+{
+ return ar8216_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
+}
+
+static int
+ar8216_mib_flush(struct ar8216_priv *priv)
+{
+ return ar8216_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
+}
+
+static void
+ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
+{
+ unsigned int base;
+ u64 *mib_stats;
+ int i;
+
+ WARN_ON(port >= priv->dev.ports);
+
+ lockdep_assert_held(&priv->mib_lock);
+
+ if (chip_is_ar8327(priv))
+ base = AR8327_REG_PORT_STATS_BASE(port);
+ else if (chip_is_ar8236(priv) ||
+ chip_is_ar8316(priv))
+ base = AR8236_REG_PORT_STATS_BASE(port);
+ else
+ base = AR8216_REG_PORT_STATS_BASE(port);
+
+ mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
+ for (i = 0; i < priv->chip->num_mibs; i++) {
+ const struct ar8xxx_mib_desc *mib;
+ u64 t;
+
+ mib = &priv->chip->mib_decs[i];
+ t = priv->read(priv, base + mib->offset);
+ if (mib->size == 2) {
+ u64 hi;
+
+ hi = priv->read(priv, base + mib->offset + 4);
+ t |= hi << 32;
+ }
+
+ if (flush)
+ mib_stats[i] = 0;
+ else
+ mib_stats[i] += t;
+ }
+}
+
static void
ar8216_read_port_link(struct ar8216_priv *priv, int port,
struct switch_port_link *link)
}
}
-static int
-ar8216_mangle_tx(struct sk_buff *skb, struct net_device *dev)
+static struct sk_buff *
+ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
{
struct ar8216_priv *priv = dev->phy_ptr;
unsigned char *buf;
buf[1] = 0x80;
send:
- return priv->ndo_old->ndo_start_xmit(skb, dev);
+ return skb;
error:
dev_kfree_skb_any(skb);
- return 0;
+ return NULL;
}
-static int
-ar8216_mangle_rx(struct sk_buff *skb, int napi)
+static void
+ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
{
struct ar8216_priv *priv;
- struct net_device *dev;
unsigned char *buf;
int port, vlan;
- dev = skb->dev;
- if (!dev)
- goto error;
-
priv = dev->phy_ptr;
if (!priv)
- goto error;
+ return;
/* don't strip the header if vlan mode is disabled */
if (!priv->vlan)
- goto recv;
+ return;
/* strip header, get vlan id */
buf = skb->data;
/* check for vlan header presence */
if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
- goto recv;
+ return;
port = buf[0] & 0xf;
/* no need to fix up packets coming from a tagged source */
if (priv->vlan_tagged & (1 << port))
- goto recv;
+ return;
/* lookup port vid from local table, the switch passes an invalid vlan id */
vlan = priv->vlan_id[priv->pvid[port]];
buf[14 + 2] &= 0xf0;
buf[14 + 2] |= vlan >> 8;
buf[15 + 2] = vlan & 0xff;
-
-recv:
- skb->protocol = eth_type_trans(skb, skb->dev);
-
- if (napi)
- return netif_receive_skb(skb);
- else
- return netif_rx(skb);
-
-error:
- /* no vlan? eat the packet! */
- dev_kfree_skb_any(skb);
- return NET_RX_DROP;
-}
-
-static int
-ar8216_netif_rx(struct sk_buff *skb)
-{
- return ar8216_mangle_rx(skb, 0);
-}
-
-static int
-ar8216_netif_receive_skb(struct sk_buff *skb)
-{
- return ar8216_mangle_rx(skb, 1);
}
static int
{
u32 header;
- if (priv->vlan && port == AR8216_PORT_CPU && priv->chip_type == AR8216)
+ if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
header = AR8216_PORT_CTRL_HEADER;
else
header = 0;
(pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
}
+static int
+ar8216_hw_init(struct ar8216_priv *priv)
+{
+ return 0;
+}
+
+static void
+ar8216_init_globals(struct ar8216_priv *priv)
+{
+ /* standard atheros magic */
+ priv->write(priv, 0x38, 0xc000050e);
+
+ ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ AR8216_GCTRL_MTU, 1518 + 8 + 2);
+}
+
+static void
+ar8216_init_port(struct ar8216_priv *priv, int port)
+{
+ /* Enable port learning and tx */
+ priv->write(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_LEARN |
+ (4 << AR8216_PORT_CTRL_STATE_S));
+
+ priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
+
+ if (port == AR8216_PORT_CPU) {
+ priv->write(priv, AR8216_REG_PORT_STATUS(port),
+ AR8216_PORT_STATUS_LINK_UP |
+ (ar8xxx_has_gige(priv) ?
+ AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
+ AR8216_PORT_STATUS_TXMAC |
+ AR8216_PORT_STATUS_RXMAC |
+ (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
+ (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
+ AR8216_PORT_STATUS_DUPLEX);
+ } else {
+ priv->write(priv, AR8216_REG_PORT_STATUS(port),
+ AR8216_PORT_STATUS_LINK_AUTO);
+ }
+}
+
+static const struct ar8xxx_chip ar8216_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
+ .hw_init = ar8216_hw_init,
+ .init_globals = ar8216_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8216_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+
+ .num_mibs = ARRAY_SIZE(ar8216_mibs),
+ .mib_decs = ar8216_mibs,
+};
+
static void
ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
u32 members, u32 pvid)
}
static int
-ar8216_hw_init(struct ar8216_priv *priv)
-{
- return 0;
-}
-
-static int
ar8236_hw_init(struct ar8216_priv *priv)
{
int i;
return 0;
/* Initialize the PHYs */
- bus = priv->phy->bus;
+ bus = priv->mii_bus;
for (i = 0; i < 5; i++) {
mdiobus_write(bus, i, MII_ADVERTISE,
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
return 0;
}
+static void
+ar8236_init_globals(struct ar8216_priv *priv)
+{
+ /* enable jumbo frames */
+ ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ AR8316_GCTRL_MTU, 9018 + 8 + 2);
+
+ /* Enable MIB counters */
+ ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
+ (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
+ AR8236_MIB_EN);
+}
+
+static const struct ar8xxx_chip ar8236_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+ .hw_init = ar8236_hw_init,
+ .init_globals = ar8236_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8236_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+};
+
static int
ar8316_hw_init(struct ar8216_priv *priv)
{
u32 val, newval;
struct mii_bus *bus;
- val = priv->read(priv, 0x8);
+ val = priv->read(priv, AR8316_REG_POSTRIP);
if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
if (priv->port4_phy) {
/* value taken from Ubiquiti RouterStation Pro */
newval = 0x81461bea;
- printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
+ pr_info("ar8316: Using port 4 as PHY\n");
} else {
newval = 0x01261be2;
- printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
+ pr_info("ar8316: Using port 4 as switch port\n");
}
} else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
/* value taken from AVM Fritz!Box 7390 sources */
newval = 0x010e5b71;
} else {
/* no known value for phy interface */
- printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
- priv->phy->interface);
+ pr_err("ar8316: unsupported mii mode: %d.\n",
+ priv->phy->interface);
return -EINVAL;
}
if (val == newval)
goto out;
- priv->write(priv, 0x8, newval);
+ priv->write(priv, AR8316_REG_POSTRIP, newval);
/* Initialize the ports */
- bus = priv->phy->bus;
+ bus = priv->mii_bus;
for (i = 0; i < 5; i++) {
if ((i == 4) && priv->port4_phy &&
priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- msleep(1000);
}
+ msleep(1000);
+
out:
priv->initialized = true;
return 0;
}
static void
-ar8216_init_globals(struct ar8216_priv *priv)
-{
- /* standard atheros magic */
- priv->write(priv, 0x38, 0xc000050e);
-
- ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
- AR8216_GCTRL_MTU, 1518 + 8 + 2);
-}
-
-static void
-ar8236_init_globals(struct ar8216_priv *priv)
-{
- /* enable jumbo frames */
- ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
- AR8316_GCTRL_MTU, 9018 + 8 + 2);
-}
-
-static void
ar8316_init_globals(struct ar8216_priv *priv)
{
/* standard atheros magic */
/* enable jumbo frames */
ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8316_GCTRL_MTU, 9018 + 8 + 2);
+
+ /* Enable MIB counters */
+ ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
+ (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
+ AR8236_MIB_EN);
}
-static void
-ar8216_init_port(struct ar8216_priv *priv, int port)
+static const struct ar8xxx_chip ar8316_chip = {
+ .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
+ .hw_init = ar8316_hw_init,
+ .init_globals = ar8316_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8216_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+};
+
+static u32
+ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
{
- /* Enable port learning and tx */
- priv->write(priv, AR8216_REG_PORT_CTRL(port),
- AR8216_PORT_CTRL_LEARN |
- (4 << AR8216_PORT_CTRL_STATE_S));
+ u32 t;
- priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
+ if (!cfg)
+ return 0;
- if (port == AR8216_PORT_CPU) {
- priv->write(priv, AR8216_REG_PORT_STATUS(port),
- AR8216_PORT_STATUS_LINK_UP |
- ar8xxx_has_gige(priv) ? AR8216_PORT_SPEED_1000M :
- AR8216_PORT_SPEED_100M |
- AR8216_PORT_STATUS_TXMAC |
- AR8216_PORT_STATUS_RXMAC |
- ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
- ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
- AR8216_PORT_STATUS_DUPLEX);
- } else {
- priv->write(priv, AR8216_REG_PORT_STATUS(port),
- AR8216_PORT_STATUS_LINK_AUTO);
+ t = 0;
+ switch (cfg->mode) {
+ case AR8327_PAD_NC:
+ break;
+
+ case AR8327_PAD_MAC2MAC_MII:
+ t = AR8327_PAD_MAC_MII_EN;
+ if (cfg->rxclk_sel)
+ t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
+ if (cfg->txclk_sel)
+ t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
+ break;
+
+ case AR8327_PAD_MAC2MAC_GMII:
+ t = AR8327_PAD_MAC_GMII_EN;
+ if (cfg->rxclk_sel)
+ t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
+ if (cfg->txclk_sel)
+ t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
+ break;
+
+ case AR8327_PAD_MAC_SGMII:
+ t = AR8327_PAD_SGMII_EN;
+
+ /*
+ * WAR for the QUalcomm Atheros AP136 board.
+ * It seems that RGMII TX/RX delay settings needs to be
+ * applied for SGMII mode as well, The ethernet is not
+ * reliable without this.
+ */
+ t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
+ t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
+ if (cfg->rxclk_delay_en)
+ t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
+ if (cfg->txclk_delay_en)
+ t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
+
+ if (cfg->sgmii_delay_en)
+ t |= AR8327_PAD_SGMII_DELAY_EN;
+
+ break;
+
+ case AR8327_PAD_MAC2PHY_MII:
+ t = AR8327_PAD_PHY_MII_EN;
+ if (cfg->rxclk_sel)
+ t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
+ if (cfg->txclk_sel)
+ t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
+ break;
+
+ case AR8327_PAD_MAC2PHY_GMII:
+ t = AR8327_PAD_PHY_GMII_EN;
+ if (cfg->pipe_rxclk_sel)
+ t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
+ if (cfg->rxclk_sel)
+ t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
+ if (cfg->txclk_sel)
+ t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
+ break;
+
+ case AR8327_PAD_MAC_RGMII:
+ t = AR8327_PAD_RGMII_EN;
+ t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
+ t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
+ if (cfg->rxclk_delay_en)
+ t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
+ if (cfg->txclk_delay_en)
+ t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
+ break;
+
+ case AR8327_PAD_PHY_GMII:
+ t = AR8327_PAD_PHYX_GMII_EN;
+ break;
+
+ case AR8327_PAD_PHY_RGMII:
+ t = AR8327_PAD_PHYX_RGMII_EN;
+ break;
+
+ case AR8327_PAD_PHY_MII:
+ t = AR8327_PAD_PHYX_MII_EN;
+ break;
}
+
+ return t;
}
-static const struct ar8xxx_chip ar8216_chip = {
- .hw_init = ar8216_hw_init,
- .init_globals = ar8216_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8216_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
-};
+static void
+ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
+{
+ switch (priv->chip_rev) {
+ case 1:
+ /* For 100M waveform */
+ ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
+ /* Turn on Gigabit clock */
+ ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
+ break;
-static const struct ar8xxx_chip ar8236_chip = {
- .hw_init = ar8236_hw_init,
- .init_globals = ar8236_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8236_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
-};
+ case 2:
+ ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
+ ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
+ /* fallthrough */
+ case 4:
+ ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
+ ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
+
+ ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
+ ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
+ ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
+ break;
+ }
+}
-static const struct ar8xxx_chip ar8316_chip = {
- .caps = AR8XXX_CAP_GIGE,
- .hw_init = ar8316_hw_init,
- .init_globals = ar8316_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8216_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
+static int
+ar8327_hw_init(struct ar8216_priv *priv)
+{
+ struct ar8327_platform_data *pdata;
+ struct ar8327_led_cfg *led_cfg;
+ struct mii_bus *bus;
+ u32 pos, new_pos;
+ u32 t;
+ int i;
+
+ pdata = priv->phy->dev.platform_data;
+ if (!pdata)
+ return -EINVAL;
+
+ t = ar8327_get_pad_cfg(pdata->pad0_cfg);
+ priv->write(priv, AR8327_REG_PAD0_MODE, t);
+ t = ar8327_get_pad_cfg(pdata->pad5_cfg);
+ priv->write(priv, AR8327_REG_PAD5_MODE, t);
+ t = ar8327_get_pad_cfg(pdata->pad6_cfg);
+ priv->write(priv, AR8327_REG_PAD6_MODE, t);
+
+ pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
+ new_pos = pos;
+
+ led_cfg = pdata->led_cfg;
+ if (led_cfg) {
+ if (led_cfg->open_drain)
+ new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
+ else
+ new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
+
+ priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
+ priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
+ priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
+ priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
+ }
+
+ if (new_pos != pos) {
+ new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
+ priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
+ }
+
+ bus = priv->mii_bus;
+ for (i = 0; i < AR8327_NUM_PHYS; i++) {
+ ar8327_phy_fixup(priv, i);
+
+ /* start aneg on the PHY */
+ mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
+ ADVERTISE_PAUSE_CAP |
+ ADVERTISE_PAUSE_ASYM);
+ mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ }
+
+ msleep(1000);
+
+ return 0;
+}
+
+static void
+ar8327_init_globals(struct ar8216_priv *priv)
+{
+ u32 t;
+
+ /* enable CPU port and disable mirror port */
+ t = AR8327_FWD_CTRL0_CPU_PORT_EN |
+ AR8327_FWD_CTRL0_MIRROR_PORT;
+ priv->write(priv, AR8327_REG_FWD_CTRL0, t);
+
+ /* forward multicast and broadcast frames to CPU */
+ t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
+ (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
+ (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
+ priv->write(priv, AR8327_REG_FWD_CTRL1, t);
+
+ /* setup MTU */
+ ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
+ AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
+
+ /* Enable MIB counters */
+ ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
+ AR8327_MODULE_EN_MIB);
+}
+
+static void
+ar8327_config_port(struct ar8216_priv *priv, unsigned int port,
+ struct ar8327_port_cfg *cfg)
+{
+ u32 t;
+
+ if (!cfg || !cfg->force_link) {
+ priv->write(priv, AR8327_REG_PORT_STATUS(port),
+ AR8216_PORT_STATUS_LINK_AUTO);
+ return;
+ }
+
+ t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
+ t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
+ t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
+ t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
+
+ switch (cfg->speed) {
+ case AR8327_PORT_SPEED_10:
+ t |= AR8216_PORT_SPEED_10M;
+ break;
+ case AR8327_PORT_SPEED_100:
+ t |= AR8216_PORT_SPEED_100M;
+ break;
+ case AR8327_PORT_SPEED_1000:
+ t |= AR8216_PORT_SPEED_1000M;
+ break;
+ }
+
+ priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
+}
+
+static void
+ar8327_init_port(struct ar8216_priv *priv, int port)
+{
+ struct ar8327_platform_data *pdata;
+ struct ar8327_port_cfg *cfg;
+ u32 t;
+
+ pdata = priv->phy->dev.platform_data;
+
+ if (pdata && port == AR8216_PORT_CPU)
+ cfg = &pdata->port0_cfg;
+ else if (pdata && port == 6)
+ cfg = &pdata->port6_cfg;
+ else
+ cfg = NULL;
+
+ ar8327_config_port(priv, port, cfg);
+
+ priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
+
+ t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
+ t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
+ priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
+
+ t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
+ priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
+
+ t = AR8327_PORT_LOOKUP_LEARN;
+ t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
+ priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
+}
+
+static u32
+ar8327_read_port_status(struct ar8216_priv *priv, int port)
+{
+ return priv->read(priv, AR8327_REG_PORT_STATUS(port));
+}
+
+static int
+ar8327_atu_flush(struct ar8216_priv *priv)
+{
+ int ret;
+
+ ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
+ AR8327_ATU_FUNC_BUSY, 0);
+ if (!ret)
+ priv->write(priv, AR8327_REG_ATU_FUNC,
+ AR8327_ATU_FUNC_OP_FLUSH);
+
+ return ret;
+}
+
+static void
+ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
+{
+ if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
+ AR8327_VTU_FUNC1_BUSY, 0))
+ return;
+
+ if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
+ priv->write(priv, AR8327_REG_VTU_FUNC0, val);
+
+ op |= AR8327_VTU_FUNC1_BUSY;
+ priv->write(priv, AR8327_REG_VTU_FUNC1, op);
+}
+
+static void
+ar8327_vtu_flush(struct ar8216_priv *priv)
+{
+ ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
+}
+
+static void
+ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
+{
+ u32 op;
+ u32 val;
+ int i;
+
+ op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
+ val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
+ for (i = 0; i < AR8327_NUM_PORTS; i++) {
+ u32 mode;
+
+ if ((port_mask & BIT(i)) == 0)
+ mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
+ else if (priv->vlan == 0)
+ mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
+ else if (priv->vlan_tagged & BIT(i))
+ mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
+ else
+ mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
+
+ val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
+ }
+ ar8327_vtu_op(priv, op, val);
+}
+
+static void
+ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
+ u32 members, u32 pvid)
+{
+ u32 t;
+ u32 mode;
+
+ t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
+ t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
+ priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
+
+ mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
+ switch (egress) {
+ case AR8216_OUT_KEEP:
+ mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
+ break;
+ case AR8216_OUT_STRIP_VLAN:
+ mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
+ break;
+ case AR8216_OUT_ADD_VLAN:
+ mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
+ break;
+ }
+
+ t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
+ t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
+ priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
+
+ t = members;
+ t |= AR8327_PORT_LOOKUP_LEARN;
+ t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
+ t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
+ priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
+}
+
+static const struct ar8xxx_chip ar8327_chip = {
+ .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
+ .hw_init = ar8327_hw_init,
+ .init_globals = ar8327_init_globals,
+ .init_port = ar8327_init_port,
+ .setup_port = ar8327_setup_port,
+ .read_port_status = ar8327_read_port_status,
+ .atu_flush = ar8327_atu_flush,
+ .vtu_flush = ar8327_vtu_flush,
+ .vtu_load_vlan = ar8327_vtu_load_vlan,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
};
static int
ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
priv->vlan = !!val->value.i;
return 0;
}
ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
val->value.i = priv->vlan;
return 0;
}
static int
ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
/* make sure no invalid PVIDs get set */
static int
ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
*vlan = priv->pvid[port];
return 0;
}
ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
priv->vlan_id[val->port_vlan] = val->value.i;
return 0;
}
ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
val->value.i = priv->vlan_id[val->port_vlan];
return 0;
}
ar8216_sw_get_port_link(struct switch_dev *dev, int port,
struct switch_port_link *link)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
ar8216_read_port_link(priv, port, link);
return 0;
static int
ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
u8 ports = priv->vlan_table[val->port_vlan];
int i;
static int
ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
u8 *vt = &priv->vlan_table[val->port_vlan];
int i, j;
static int
ar8216_sw_hw_apply(struct switch_dev *dev)
{
- struct ar8216_priv *priv = to_ar8216(dev);
- u8 portmask[AR8216_NUM_PORTS];
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
+ u8 portmask[AR8X16_MAX_PORTS];
int i, j;
mutex_lock(&priv->reg_mutex);
static int
ar8216_sw_reset_switch(struct switch_dev *dev)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
int i;
mutex_lock(&priv->reg_mutex);
return ar8216_sw_hw_apply(dev);
}
+static int
+ar8216_sw_set_reset_mibs(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
+ unsigned int len;
+ int ret;
+
+ if (!ar8xxx_has_mib_counters(priv))
+ return -EOPNOTSUPP;
+
+ mutex_lock(&priv->mib_lock);
+
+ len = priv->dev.ports * priv->chip->num_mibs *
+ sizeof(*priv->mib_stats);
+ memset(priv->mib_stats, '\0', len);
+ ret = ar8216_mib_flush(priv);
+ if (ret)
+ goto unlock;
+
+ ret = 0;
+
+unlock:
+ mutex_unlock(&priv->mib_lock);
+ return ret;
+}
+
+static int
+ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
+ int port;
+ int ret;
+
+ if (!ar8xxx_has_mib_counters(priv))
+ return -EOPNOTSUPP;
+
+ port = val->port_vlan;
+ if (port >= dev->ports)
+ return -EINVAL;
+
+ mutex_lock(&priv->mib_lock);
+ ret = ar8216_mib_capture(priv);
+ if (ret)
+ goto unlock;
+
+ ar8216_mib_fetch_port_stat(priv, port, true);
+
+ ret = 0;
+
+unlock:
+ mutex_unlock(&priv->mib_lock);
+ return ret;
+}
+
+static int
+ar8216_sw_get_port_mib(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8216_priv *priv = swdev_to_ar8216(dev);
+ const struct ar8xxx_chip *chip = priv->chip;
+ u64 *mib_stats;
+ int port;
+ int ret;
+ char *buf = priv->buf;
+ int i, len = 0;
+
+ if (!ar8xxx_has_mib_counters(priv))
+ return -EOPNOTSUPP;
+
+ port = val->port_vlan;
+ if (port >= dev->ports)
+ return -EINVAL;
+
+ mutex_lock(&priv->mib_lock);
+ ret = ar8216_mib_capture(priv);
+ if (ret)
+ goto unlock;
+
+ ar8216_mib_fetch_port_stat(priv, port, false);
+
+ len += snprintf(buf + len, sizeof(priv->buf) - len,
+ "Port %d MIB counters\n",
+ port);
+
+ mib_stats = &priv->mib_stats[port * chip->num_mibs];
+ for (i = 0; i < chip->num_mibs; i++)
+ len += snprintf(buf + len, sizeof(priv->buf) - len,
+ "%-12s: %llu\n",
+ chip->mib_decs[i].name,
+ mib_stats[i]);
+
+ val->value.s = buf;
+ val->len = len;
+
+ ret = 0;
+
+unlock:
+ mutex_unlock(&priv->mib_lock);
+ return ret;
+}
+
static struct switch_attr ar8216_globals[] = {
{
.type = SWITCH_TYPE_INT,
.get = ar8216_sw_get_vlan,
.max = 1
},
+ {
+ .type = SWITCH_TYPE_NOVAL,
+ .name = "reset_mibs",
+ .description = "Reset all MIB counters",
+ .set = ar8216_sw_set_reset_mibs,
+ },
+
};
static struct switch_attr ar8216_port[] = {
+ {
+ .type = SWITCH_TYPE_NOVAL,
+ .name = "reset_mib",
+ .description = "Reset single port MIB counters",
+ .set = ar8216_sw_set_port_reset_mib,
+ },
+ {
+ .type = SWITCH_TYPE_STRING,
+ .name = "mib",
+ .description = "Get port's MIB counters",
+ .set = NULL,
+ .get = ar8216_sw_get_port_mib,
+ },
};
static struct switch_attr ar8216_vlan[] = {
u16 id;
int i;
- priv->chip_type = UNKNOWN;
-
- val = ar8216_mii_read(priv, AR8216_REG_CTRL);
+ val = priv->read(priv, AR8216_REG_CTRL);
if (val == ~0)
return -ENODEV;
for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
u16 t;
- val = ar8216_mii_read(priv, AR8216_REG_CTRL);
+ val = priv->read(priv, AR8216_REG_CTRL);
if (val == ~0)
return -ENODEV;
return -ENODEV;
}
- switch (id) {
- case 0x0101:
- priv->chip_type = AR8216;
+ priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
+ priv->chip_rev = (id & AR8216_CTRL_REVISION);
+
+ switch (priv->chip_ver) {
+ case AR8XXX_VER_AR8216:
priv->chip = &ar8216_chip;
break;
- case 0x0301:
- priv->chip_type = AR8236;
+ case AR8XXX_VER_AR8236:
priv->chip = &ar8236_chip;
break;
- case 0x1000:
- case 0x1001:
- priv->chip_type = AR8316;
+ case AR8XXX_VER_AR8316:
priv->chip = &ar8316_chip;
break;
+ case AR8XXX_VER_AR8327:
+ priv->mii_lo_first = true;
+ priv->chip = &ar8327_chip;
+ break;
default:
- printk(KERN_DEBUG
- "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
- (int)(id >> AR8216_CTRL_VERSION_S),
- (int)(id & AR8216_CTRL_REVISION),
- mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
- mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
+ pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
+ priv->chip_ver, priv->chip_rev);
return -ENODEV;
}
return 0;
}
+static void
+ar8xxx_mib_work_func(struct work_struct *work)
+{
+ struct ar8216_priv *priv;
+ int err;
+
+ priv = container_of(work, struct ar8216_priv, mib_work.work);
+
+ mutex_lock(&priv->mib_lock);
+
+ err = ar8216_mib_capture(priv);
+ if (err)
+ goto next_port;
+
+ ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
+
+next_port:
+ priv->mib_next_port++;
+ if (priv->mib_next_port >= priv->dev.ports)
+ priv->mib_next_port = 0;
+
+ mutex_unlock(&priv->mib_lock);
+ schedule_delayed_work(&priv->mib_work,
+ msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
+}
+
static int
-ar8216_config_init(struct phy_device *pdev)
+ar8xxx_mib_init(struct ar8216_priv *priv)
{
- struct ar8216_priv *priv = pdev->priv;
- struct net_device *dev = pdev->attached_dev;
- struct switch_dev *swdev;
- int ret;
+ unsigned int len;
- if (!priv) {
- priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
- if (priv == NULL)
- return -ENOMEM;
- }
+ if (!ar8xxx_has_mib_counters(priv))
+ return 0;
- priv->phy = pdev;
+ BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
- ret = ar8216_id_chip(priv);
- if (ret)
- goto err_free_priv;
+ len = priv->dev.ports * priv->chip->num_mibs *
+ sizeof(*priv->mib_stats);
+ priv->mib_stats = kzalloc(len, GFP_KERNEL);
- if (pdev->addr != 0) {
- if (ar8xxx_has_gige(priv)) {
- pdev->supported |= SUPPORTED_1000baseT_Full;
- pdev->advertising |= ADVERTISED_1000baseT_Full;
- }
+ if (!priv->mib_stats)
+ return -ENOMEM;
- if (priv->chip_type == AR8316) {
- /* check if we're attaching to the switch twice */
- pdev = pdev->bus->phy_map[0];
- if (!pdev) {
- kfree(priv);
- return 0;
- }
+ return 0;
+}
- /* switch device has not been initialized, reuse priv */
- if (!pdev->priv) {
- priv->port4_phy = true;
- pdev->priv = priv;
- return 0;
- }
+static void
+ar8xxx_mib_start(struct ar8216_priv *priv)
+{
+ if (!ar8xxx_has_mib_counters(priv))
+ return;
- kfree(priv);
+ schedule_delayed_work(&priv->mib_work,
+ msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
+}
- /* switch device has been initialized, reinit */
- priv = pdev->priv;
- priv->dev.ports = (AR8216_NUM_PORTS - 1);
- priv->initialized = false;
- priv->port4_phy = true;
- ar8316_hw_init(priv);
- return 0;
- }
+static void
+ar8xxx_mib_stop(struct ar8216_priv *priv)
+{
+ if (!ar8xxx_has_mib_counters(priv))
+ return;
- kfree(priv);
- return 0;
- }
+ cancel_delayed_work(&priv->mib_work);
+}
- printk(KERN_INFO "%s: AR%d switch driver attached.\n",
- pdev->attached_dev->name, priv->chip_type);
+static struct ar8216_priv *
+ar8xxx_create(void)
+{
+ struct ar8216_priv *priv;
- if (ar8xxx_has_gige(priv))
- pdev->supported = SUPPORTED_1000baseT_Full;
- else
- pdev->supported = SUPPORTED_100baseT_Full;
- pdev->advertising = pdev->supported;
+ priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
+ if (priv == NULL)
+ return NULL;
mutex_init(&priv->reg_mutex);
- priv->read = ar8216_mii_read;
- priv->write = ar8216_mii_write;
+ mutex_init(&priv->mib_lock);
+ INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
+
+ return priv;
+}
- pdev->priv = priv;
+static void
+ar8xxx_free(struct ar8216_priv *priv)
+{
+ kfree(priv->mib_stats);
+ kfree(priv);
+}
+
+static struct ar8216_priv *
+ar8xxx_create_mii(struct mii_bus *bus)
+{
+ struct ar8216_priv *priv;
+
+ priv = ar8xxx_create();
+ if (priv) {
+ priv->mii_bus = bus;
+ priv->read = ar8216_mii_read;
+ priv->write = ar8216_mii_write;
+ }
+
+ return priv;
+}
+
+static int
+ar8xxx_probe_switch(struct ar8216_priv *priv)
+{
+ struct switch_dev *swdev;
+ int ret;
+
+ ret = ar8216_id_chip(priv);
+ if (ret)
+ return ret;
swdev = &priv->dev;
swdev->cpu_port = AR8216_PORT_CPU;
swdev->ops = &ar8216_sw_ops;
- swdev->ports = AR8216_NUM_PORTS;
- if (priv->chip_type == AR8316) {
+ if (chip_is_ar8316(priv)) {
swdev->name = "Atheros AR8316";
swdev->vlans = AR8X16_MAX_VLANS;
-
- if (priv->port4_phy) {
- /* port 5 connected to the other mac, therefore unusable */
- swdev->ports = (AR8216_NUM_PORTS - 1);
- }
- } else if (priv->chip_type == AR8236) {
+ swdev->ports = AR8216_NUM_PORTS;
+ } else if (chip_is_ar8236(priv)) {
swdev->name = "Atheros AR8236";
swdev->vlans = AR8216_NUM_VLANS;
swdev->ports = AR8216_NUM_PORTS;
+ } else if (chip_is_ar8327(priv)) {
+ swdev->name = "Atheros AR8327";
+ swdev->vlans = AR8X16_MAX_VLANS;
+ swdev->ports = AR8327_NUM_PORTS;
} else {
swdev->name = "Atheros AR8216";
swdev->vlans = AR8216_NUM_VLANS;
+ swdev->ports = AR8216_NUM_PORTS;
}
- ret = register_switch(&priv->dev, pdev->attached_dev);
+ ret = ar8xxx_mib_init(priv);
if (ret)
- goto err_free_priv;
+ return ret;
+
+ return 0;
+}
+
+static int
+ar8216_config_init(struct phy_device *phydev)
+{
+ struct ar8216_priv *priv = phydev->priv;
+ struct net_device *dev = phydev->attached_dev;
+ struct switch_dev *swdev;
+ int ret;
+
+ if (WARN_ON(!priv))
+ return -ENODEV;
+
+ priv->phy = phydev;
+
+ if (phydev->addr != 0) {
+ if (chip_is_ar8316(priv)) {
+ /* switch device has been initialized, reinit */
+ priv->dev.ports = (AR8216_NUM_PORTS - 1);
+ priv->initialized = false;
+ priv->port4_phy = true;
+ ar8316_hw_init(priv);
+ return 0;
+ }
+
+ return 0;
+ }
+
+ swdev = &priv->dev;
+ swdev->alias = dev_name(&priv->mii_bus->dev);
+ ret = register_switch(swdev, NULL);
+ if (ret)
+ goto err;
+
+ pr_info("%s: %s switch registered on %s\n",
+ swdev->devname, swdev->name, dev_name(&priv->mii_bus->dev));
priv->init = true;
ret = priv->chip->hw_init(priv);
if (ret)
- goto err_free_priv;
+ goto err_unregister_switch;
ret = ar8216_sw_reset_switch(&priv->dev);
if (ret)
- goto err_free_priv;
-
- dev->phy_ptr = priv;
+ goto err_unregister_switch;
/* VID fixup only needed on ar8216 */
- if (pdev->addr == 0 && priv->chip_type == AR8216) {
- pdev->pkt_align = 2;
- pdev->netif_receive_skb = ar8216_netif_receive_skb;
- pdev->netif_rx = ar8216_netif_rx;
- priv->ndo_old = dev->netdev_ops;
- memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
- priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
- dev->netdev_ops = &priv->ndo;
+ if (chip_is_ar8216(priv)) {
+ dev->phy_ptr = priv;
+ dev->priv_flags |= IFF_NO_IP_ALIGN;
+ dev->eth_mangle_rx = ar8216_mangle_rx;
+ dev->eth_mangle_tx = ar8216_mangle_tx;
}
priv->init = false;
+ ar8xxx_mib_start(priv);
+
return 0;
-err_free_priv:
- kfree(priv);
+err_unregister_switch:
+ unregister_switch(&priv->dev);
+err:
return ret;
}
return genphy_config_aneg(phydev);
}
+static const u32 ar8xxx_phy_ids[] = {
+ 0x004dd033,
+ 0x004dd041,
+ 0x004dd042,
+};
+
+static bool
+ar8xxx_phy_match(u32 phy_id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
+ if (phy_id == ar8xxx_phy_ids[i])
+ return true;
+
+ return false;
+}
+
+static bool
+ar8xxx_is_possible(struct mii_bus *bus)
+{
+ unsigned i;
+
+ for (i = 0; i < 4; i++) {
+ u32 phy_id;
+
+ phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
+ phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
+ if (!ar8xxx_phy_match(phy_id)) {
+ pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
+ dev_name(&bus->dev), i, phy_id);
+ return false;
+ }
+ }
+
+ return true;
+}
+
static int
-ar8216_probe(struct phy_device *pdev)
+ar8216_probe(struct phy_device *phydev)
+{
+ struct ar8216_priv *priv;
+ int ret;
+
+ /* skip PHYs at unused adresses */
+ if (phydev->addr != 0 && phydev->addr != 4)
+ return -ENODEV;
+
+ if (!ar8xxx_is_possible(phydev->bus))
+ return -ENODEV;
+
+ mutex_lock(&ar8xxx_dev_list_lock);
+ list_for_each_entry(priv, &ar8xxx_dev_list, list)
+ if (priv->mii_bus == phydev->bus)
+ goto found;
+
+ priv = ar8xxx_create_mii(phydev->bus);
+ if (priv == NULL) {
+ ret = -ENOMEM;
+ goto unlock;
+ }
+
+ ret = ar8xxx_probe_switch(priv);
+ if (ret)
+ goto free_priv;
+
+found:
+ if (phydev->addr == 0) {
+ if (ar8xxx_has_gige(priv)) {
+ phydev->supported = SUPPORTED_1000baseT_Full;
+ phydev->advertising = ADVERTISED_1000baseT_Full;
+ } else {
+ phydev->supported = SUPPORTED_100baseT_Full;
+ phydev->advertising = ADVERTISED_100baseT_Full;
+ }
+ } else {
+ if (ar8xxx_has_gige(priv)) {
+ phydev->supported |= SUPPORTED_1000baseT_Full;
+ phydev->advertising |= ADVERTISED_1000baseT_Full;
+ }
+ }
+
+ phydev->priv = priv;
+ priv->use_count++;
+
+ list_add(&priv->list, &ar8xxx_dev_list);
+
+ mutex_unlock(&ar8xxx_dev_list_lock);
+
+ return 0;
+
+free_priv:
+ ar8xxx_free(priv);
+unlock:
+ mutex_unlock(&ar8xxx_dev_list_lock);
+ return ret;
+}
+
+static void
+ar8216_detach(struct phy_device *phydev)
{
- struct ar8216_priv priv;
+ struct net_device *dev = phydev->attached_dev;
+
+ if (!dev)
+ return;
- priv.phy = pdev;
- return ar8216_id_chip(&priv);
+ dev->phy_ptr = NULL;
+ dev->priv_flags &= ~IFF_NO_IP_ALIGN;
+ dev->eth_mangle_rx = NULL;
+ dev->eth_mangle_tx = NULL;
}
static void
-ar8216_remove(struct phy_device *pdev)
+ar8216_remove(struct phy_device *phydev)
{
- struct ar8216_priv *priv = pdev->priv;
- struct net_device *dev = pdev->attached_dev;
+ struct ar8216_priv *priv = phydev->priv;
- if (!priv)
+ if (WARN_ON(!priv))
return;
- if (priv->ndo_old && dev)
- dev->netdev_ops = priv->ndo_old;
- if (pdev->addr == 0)
- unregister_switch(&priv->dev);
- kfree(priv);
+ phydev->priv = NULL;
+ if (--priv->use_count > 0)
+ return;
+
+ mutex_lock(&ar8xxx_dev_list_lock);
+ list_del(&priv->list);
+ mutex_unlock(&ar8xxx_dev_list_lock);
+
+ unregister_switch(&priv->dev);
+ ar8xxx_mib_stop(priv);
+ ar8xxx_free(priv);
}
static struct phy_driver ar8216_driver = {
.features = PHY_BASIC_FEATURES,
.probe = ar8216_probe,
.remove = ar8216_remove,
+ .detach = ar8216_detach,
.config_init = &ar8216_config_init,
.config_aneg = &ar8216_config_aneg,
.read_status = &ar8216_read_status,
projects / openwrt.git / blobdiff