ar71xx: Add QCA955X GPIO mux and function definitions

[openwrt.git] / target / linux / ar71xx / patches-4.1 / 620-MIPS-ath79-add-support-for-QCA953x-SoC.patch

diff --git a/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 58ca1d5..b754589 100644 (file)
--- a/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -413,12 +413,13 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  
        id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
        major = id & REV_ID_MAJOR_MASK;
  
        id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
        major = id & REV_ID_MAJOR_MASK;

-@@ -152,6 +153,16 @@ static void __init ath79_detect_sys_type
+@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type

                rev = id & AR934X_REV_ID_REVISION_MASK;
                break;
  
 +      case REV_ID_MAJOR_QCA9533_V2:
 +              ver = 2;
                rev = id & AR934X_REV_ID_REVISION_MASK;
                break;
  
 +      case REV_ID_MAJOR_QCA9533_V2:
 +              ver = 2;

++              ath79_soc_rev = 2;

 +              /* drop through */
 +
 +      case REV_ID_MAJOR_QCA9533:
 +              /* drop through */
 +
 +      case REV_ID_MAJOR_QCA9533:


@@ -430,15 +431,23 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
        case REV_ID_MAJOR_QCA9556:
                ath79_soc = ATH79_SOC_QCA9556;
                chip = "9556";
        case REV_ID_MAJOR_QCA9556:
                ath79_soc = ATH79_SOC_QCA9556;
                chip = "9556";

-@@ -170,7 +181,7 @@ static void __init ath79_detect_sys_type
+@@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type
+               panic("ath79: unknown SoC, id:0x%08x", id);
+       }

  
  

-       ath79_soc_rev = rev;
+-      ath79_soc_rev = rev;
++      if (ver == 1)
++              ath79_soc_rev = rev;

  
 -      if (soc_is_qca955x())
  
 -      if (soc_is_qca955x())

+-              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
+-                      chip, rev);

 +      if (soc_is_qca953x() || soc_is_qca955x())
 +      if (soc_is_qca953x() || soc_is_qca955x())

-               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
-                       chip, rev);
++              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
++                      chip, ver, rev);

        else
        else

+               sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+       pr_info("SoC: %s\n", ath79_sys_type);

 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 @@ -105,6 +105,21 @@
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 @@ -105,6 +105,21 @@


@@ -617,7 +626,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*

-@@ -634,12 +747,32 @@
+@@ -634,6 +747,25 @@

  #define AR934X_GPIO_REG_OUT_FUNC5     0x40
  #define AR934X_GPIO_REG_FUNC          0x6c
  
  #define AR934X_GPIO_REG_OUT_FUNC5     0x40
  #define AR934X_GPIO_REG_FUNC          0x6c
  


@@ -640,9 +649,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5                45
 +
 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5                45
 +

- #define AR71XX_GPIO_COUNT             16
- #define AR7240_GPIO_COUNT             18
- #define AR7241_GPIO_COUNT             20
+ #define QCA955X_GPIO_REG_OUT_FUNC0    0x2c
+ #define QCA955X_GPIO_REG_OUT_FUNC1    0x30
+ #define QCA955X_GPIO_REG_OUT_FUNC2    0x34
+@@ -648,6 +780,7 @@

  #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23
  #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23


@@ -650,7 +660,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_GPIO_COUNT            24
  
  /*
  #define QCA955X_GPIO_COUNT            24
  
  /*

-@@ -663,6 +796,24 @@
+@@ -671,6 +804,24 @@

  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  


@@ -675,7 +685,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
  #define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
  #define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)
  #define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
  #define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
  #define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)

-@@ -804,6 +955,16 @@
+@@ -877,6 +1028,16 @@

  #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
  
  /*
  #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
  
  /*