ar71xx: refresh patches

[openwrt.git] / target / linux / ar71xx / patches-3.18 / 707-MIPS-ath79-add-support-for-QCA953x-SoC.patch

diff --git a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 11d91c2..09e9119 100644 (file)
--- a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -22,7 +22,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 
 --- a/arch/mips/ath79/Kconfig
 +++ b/arch/mips/ath79/Kconfig
-@@ -1158,6 +1158,10 @@ config SOC_AR934X
+@@ -1184,6 +1184,10 @@ config SOC_AR934X
        select PCI_AR724X if PCI
        def_bool n
  
@@ -33,7 +33,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  config SOC_QCA955X
        select HW_HAS_PCI
        select PCI_AR724X if PCI
-@@ -1200,7 +1204,7 @@ config ATH79_DEV_USB
+@@ -1226,7 +1230,7 @@ config ATH79_DEV_USB
        def_bool n
  
  config ATH79_DEV_WMAC
@@ -233,11 +233,12 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
        else
 --- a/arch/mips/ath79/early_printk.c
 +++ b/arch/mips/ath79/early_printk.c
-@@ -114,6 +114,7 @@ static void prom_putchar_init(void)
+@@ -114,6 +114,8 @@ static void prom_putchar_init(void)
        case REV_ID_MAJOR_AR9341:
        case REV_ID_MAJOR_AR9342:
        case REV_ID_MAJOR_AR9344:
 +      case REV_ID_MAJOR_QCA9533:
++      case REV_ID_MAJOR_QCA9533_V2:
        case REV_ID_MAJOR_QCA9556:
        case REV_ID_MAJOR_QCA9558:
                _prom_putchar = prom_putchar_ar71xx;
@@ -283,10 +284,22 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
                ath79_ip3_handler = ath79_default_ip3_handler;
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
-@@ -151,6 +151,12 @@ static void __init ath79_detect_sys_type
+@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
+       u32 major;
+       u32 minor;
+       u32 rev = 0;
++      u32 ver = 1;
+ 
+       id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
+       major = id & REV_ID_MAJOR_MASK;
+@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
                rev = id & AR934X_REV_ID_REVISION_MASK;
                break;
  
++      case REV_ID_MAJOR_QCA9533_V2:
++              ver = 2;
++              /* drop through */
++
 +      case REV_ID_MAJOR_QCA9533:
 +              ath79_soc = ATH79_SOC_QCA9533;
 +              chip = "9533";
@@ -296,15 +309,19 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
        case REV_ID_MAJOR_QCA9556:
                ath79_soc = ATH79_SOC_QCA9556;
                chip = "9556";
-@@ -169,7 +175,7 @@ static void __init ath79_detect_sys_type
+@@ -169,9 +180,9 @@ static void __init ath79_detect_sys_type
  
        ath79_soc_rev = rev;
  
 -      if (soc_is_qca955x())
+-              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
+-                      chip, rev);
 +      if (soc_is_qca953x() || soc_is_qca955x())
-               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
-                       chip, rev);
++              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
++                      chip, ver, rev);
        else
+               sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+       pr_info("SoC: %s\n", ath79_sys_type);
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 @@ -105,6 +105,9 @@
@@ -381,15 +398,16 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
  
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
-@@ -565,6 +611,7 @@
+@@ -565,6 +611,8 @@
  #define REV_ID_MAJOR_AR9341           0x0120
  #define REV_ID_MAJOR_AR9342           0x1120
  #define REV_ID_MAJOR_AR9344           0x2120
 +#define REV_ID_MAJOR_QCA9533          0x0140
++#define REV_ID_MAJOR_QCA9533_V2               0x0160
  #define REV_ID_MAJOR_QCA9556          0x0130
  #define REV_ID_MAJOR_QCA9558          0x1130
  
-@@ -587,6 +634,8 @@
+@@ -587,6 +635,8 @@
  
  #define AR934X_REV_ID_REVISION_MASK   0xf
  
@@ -398,7 +416,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*
-@@ -640,6 +689,7 @@
+@@ -640,6 +690,7 @@
  #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23