depends on ATH9K
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
-@@ -13,9 +13,9 @@ ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
+@@ -11,11 +11,13 @@ ath9k-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) +=
+ ath9k-$(CPTCFG_ATH9K_LEGACY_RATE_CONTROL) += rc.o
+ ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
ath9k-$(CPTCFG_ATH9K_AHB) += ahb.o
- ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
+-ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
ath9k-$(CPTCFG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
-ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += \
- dfs.o
+ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += dfs.o
+ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o
+ath9k-$(CPTCFG_ATH9K_WOW) += wow.o
++
++ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o \
++ spectral.o
obj-$(CPTCFG_ATH9K) += ath9k.o
-@@ -41,6 +41,8 @@ ath9k_hw-y:= \
+@@ -41,6 +43,8 @@ ath9k_hw-y:= \
ar9003_eeprom.o \
ar9003_paprd.o
obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
-@@ -581,6 +581,13 @@ static void ar9003_tx_gain_table_mode6(s
+@@ -17,6 +17,7 @@
+ #include "hw.h"
+ #include "ar9003_mac.h"
+ #include "ar9003_2p2_initvals.h"
++#include "ar9003_buffalo_initvals.h"
+ #include "ar9485_initvals.h"
+ #include "ar9340_initvals.h"
+ #include "ar9330_1p1_initvals.h"
+@@ -26,6 +27,7 @@
+ #include "ar9462_2p0_initvals.h"
+ #include "ar9462_2p1_initvals.h"
+ #include "ar9565_1p0_initvals.h"
++#include "ar9565_1p1_initvals.h"
+
+ /* General hardware code for the AR9003 hadware family */
+
+@@ -148,7 +150,11 @@ static void ar9003_hw_init_mode_regs(str
+ ar9340Modes_high_ob_db_tx_gain_table_1p0);
+
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9340Modes_fast_clock_1p0);
++ ar9340Modes_fast_clock_1p0);
++ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
++ ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
++ INIT_INI_ARRAY(&ah->ini_dfs,
++ ar9340_1p0_baseband_postamble_dfs_channel);
+
+ if (!ah->is_clk_25mhz)
+ INIT_INI_ARRAY(&ah->iniAdditional,
+@@ -187,17 +193,17 @@ static void ar9003_hw_init_mode_regs(str
+ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+ ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
+
+- /* Load PCIE SERDES settings from INI */
+-
+- /* Awake Setting */
+-
+- INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9485_1_1_pcie_phy_clkreq_disable_L1);
+-
+- /* Sleep Setting */
+-
+- INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- ar9485_1_1_pcie_phy_clkreq_disable_L1);
++ if (ah->config.no_pll_pwrsave) {
++ INIT_INI_ARRAY(&ah->iniPcieSerdes,
++ ar9485_1_1_pcie_phy_clkreq_disable_L1);
++ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
++ ar9485_1_1_pcie_phy_clkreq_disable_L1);
++ } else {
++ INIT_INI_ARRAY(&ah->iniPcieSerdes,
++ ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
++ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
++ ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
++ }
+ } else if (AR_SREV_9462_21(ah)) {
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+ ar9462_2p1_mac_core);
+@@ -223,6 +229,10 @@ static void ar9003_hw_init_mode_regs(str
+ ar9462_2p1_modes_fast_clock);
+ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+ ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
++ INIT_INI_ARRAY(&ah->iniPcieSerdes,
++ ar9462_2p1_pciephy_clkreq_disable_L1);
++ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
++ ar9462_2p1_pciephy_clkreq_disable_L1);
+ } else if (AR_SREV_9462_20(ah)) {
+
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
+@@ -247,18 +257,18 @@ static void ar9003_hw_init_mode_regs(str
+ ar9462_2p0_soc_postamble);
+
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_rx_gain_table_2p0);
++ ar9462_2p0_common_rx_gain);
+
+ /* Awake -> Sleep Setting */
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9462_pciephy_clkreq_disable_L1_2p0);
++ ar9462_2p0_pciephy_clkreq_disable_L1);
+ /* Sleep -> Awake Setting */
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- ar9462_pciephy_clkreq_disable_L1_2p0);
++ ar9462_2p0_pciephy_clkreq_disable_L1);
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9462_modes_fast_clock_2p0);
++ ar9462_2p0_modes_fast_clock);
+
+ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+ ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
+@@ -330,7 +340,46 @@ static void ar9003_hw_init_mode_regs(str
+ ar9580_1p0_low_ob_db_tx_gain_table);
+
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9580_1p0_modes_fast_clock);
++ ar9580_1p0_modes_fast_clock);
++ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
++ ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
++ INIT_INI_ARRAY(&ah->ini_dfs,
++ ar9580_1p0_baseband_postamble_dfs_channel);
++ } else if (AR_SREV_9565_11_OR_LATER(ah)) {
++ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
++ ar9565_1p1_mac_core);
++ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
++ ar9565_1p1_mac_postamble);
++
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
++ ar9565_1p1_baseband_core);
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
++ ar9565_1p1_baseband_postamble);
++
++ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
++ ar9565_1p1_radio_core);
++ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
++ ar9565_1p1_radio_postamble);
++
++ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
++ ar9565_1p1_soc_preamble);
++ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
++ ar9565_1p1_soc_postamble);
++
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
++ ar9565_1p1_Common_rx_gain_table);
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
++
++ INIT_INI_ARRAY(&ah->iniPcieSerdes,
++ ar9565_1p1_pciephy_clkreq_disable_L1);
++ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
++ ar9565_1p1_pciephy_clkreq_disable_L1);
++
++ INIT_INI_ARRAY(&ah->iniModesFastClock,
++ ar9565_1p1_modes_fast_clock);
++ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
++ ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
+ } else if (AR_SREV_9565(ah)) {
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+ ar9565_1p0_mac_core);
+@@ -411,7 +460,11 @@ static void ar9003_hw_init_mode_regs(str
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9300Modes_fast_clock_2p2);
++ ar9300Modes_fast_clock_2p2);
++ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
++ ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
++ INIT_INI_ARRAY(&ah->ini_dfs,
++ ar9300_2p2_baseband_postamble_dfs_channel);
+ }
+ }
+
+@@ -440,7 +493,10 @@ static void ar9003_tx_gain_table_mode0(s
+ ar9462_2p1_modes_low_ob_db_tx_gain);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9462_modes_low_ob_db_tx_gain_table_2p0);
++ ar9462_2p0_modes_low_ob_db_tx_gain);
++ else if (AR_SREV_9565_11(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9565_1p1_modes_low_ob_db_tx_gain_table);
+ else if (AR_SREV_9565(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9565_1p0_modes_low_ob_db_tx_gain_table);
+@@ -474,7 +530,10 @@ static void ar9003_tx_gain_table_mode1(s
+ ar9462_2p1_modes_high_ob_db_tx_gain);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9462_modes_high_ob_db_tx_gain_table_2p0);
++ ar9462_2p0_modes_high_ob_db_tx_gain);
++ else if (AR_SREV_9565_11(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9565_1p1_modes_high_ob_db_tx_gain_table);
+ else if (AR_SREV_9565(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9565_1p0_modes_high_ob_db_tx_gain_table);
+@@ -500,6 +559,9 @@ static void ar9003_tx_gain_table_mode2(s
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9580_1p0_low_ob_db_tx_gain_table);
++ else if (AR_SREV_9565_11(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9565_1p1_modes_low_ob_db_tx_gain_table);
+ else if (AR_SREV_9565(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9565_1p0_modes_low_ob_db_tx_gain_table);
+@@ -525,12 +587,20 @@ static void ar9003_tx_gain_table_mode3(s
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9580_1p0_high_power_tx_gain_table);
++ else if (AR_SREV_9565_11(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9565_1p1_modes_high_power_tx_gain_table);
+ else if (AR_SREV_9565(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9565_1p0_modes_high_power_tx_gain_table);
+- else
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_high_power_tx_gain_table_2p2);
++ else {
++ if (ah->config.tx_gain_buffalo)
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9300Modes_high_power_tx_gain_table_buffalo);
++ else
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9300Modes_high_power_tx_gain_table_2p2);
++ }
+ }
+
+ static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
+@@ -546,7 +616,7 @@ static void ar9003_tx_gain_table_mode4(s
+ ar9462_2p1_modes_mix_ob_db_tx_gain);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9462_modes_mix_ob_db_tx_gain_table_2p0);
++ ar9462_2p0_modes_mix_ob_db_tx_gain);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
+@@ -581,6 +651,13 @@ static void ar9003_tx_gain_table_mode6(s
ar9580_1p0_type6_tx_gain_table);
}
typedef void (*ath_txgain_tab)(struct ath_hw *ah);
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
-@@ -593,6 +600,7 @@ static void ar9003_tx_gain_table_apply(s
+@@ -593,6 +670,7 @@ static void ar9003_tx_gain_table_apply(s
ar9003_tx_gain_table_mode4,
ar9003_tx_gain_table_mode5,
ar9003_tx_gain_table_mode6,
};
int idx = ar9003_hw_get_tx_gain_idx(ah);
-@@ -750,6 +758,9 @@ static void ar9003_hw_init_mode_gain_reg
+@@ -629,7 +707,10 @@ static void ar9003_rx_gain_table_mode0(s
+ ar9462_2p1_common_rx_gain);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_rx_gain_table_2p0);
++ ar9462_2p0_common_rx_gain);
++ else if (AR_SREV_9565_11(ah))
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
++ ar9565_1p1_Common_rx_gain_table);
+ else if (AR_SREV_9565(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9565_1p0_Common_rx_gain_table);
+@@ -657,7 +738,7 @@ static void ar9003_rx_gain_table_mode1(s
+ ar9462_2p1_common_wo_xlna_rx_gain);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_wo_xlna_rx_gain_table_2p0);
++ ar9462_2p0_common_wo_xlna_rx_gain);
+ else if (AR_SREV_9550(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar955x_1p0_common_wo_xlna_rx_gain_table);
+@@ -666,6 +747,9 @@ static void ar9003_rx_gain_table_mode1(s
+ } else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9580_1p0_wo_xlna_rx_gain_table);
++ else if (AR_SREV_9565_11(ah))
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
++ ar9565_1p1_common_wo_xlna_rx_gain_table);
+ else if (AR_SREV_9565(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9565_1p0_common_wo_xlna_rx_gain_table);
+@@ -687,7 +771,7 @@ static void ar9003_rx_gain_table_mode2(s
+ ar9462_2p1_baseband_postamble_5g_xlna);
+ } else if (AR_SREV_9462_20(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_mixed_rx_gain_table_2p0);
++ ar9462_2p0_common_mixed_rx_gain);
+ INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
+ ar9462_2p0_baseband_core_mix_rxgain);
+ INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
+@@ -701,12 +785,12 @@ static void ar9003_rx_gain_table_mode3(s
+ {
+ if (AR_SREV_9462_21(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_2p1_common_5g_xlna_only_rx_gain);
++ ar9462_2p1_common_5g_xlna_only_rxgain);
+ INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
+ ar9462_2p1_baseband_postamble_5g_xlna);
+ } else if (AR_SREV_9462_20(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_2p0_5g_xlna_only_rxgain);
++ ar9462_2p0_common_5g_xlna_only_rxgain);
+ INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
+ ar9462_2p0_baseband_postamble_5g_xlna);
+ }
+@@ -750,6 +834,9 @@ static void ar9003_hw_init_mode_gain_reg
static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
bool power_off)
{
/*
* Increase L1 Entry Latency. Some WB222 boards don't have
* this change in eeprom/OTP.
-@@ -775,18 +786,13 @@ static void ar9003_hw_configpcipowersave
+@@ -775,18 +862,13 @@ static void ar9003_hw_configpcipowersave
* Configire PCIE after Ini init. SERDES values now come from ini file
* This enables PCIe low power mode.
*/
--- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
-@@ -1447,4 +1447,106 @@ static const u32 ar9340_1p0_soc_preamble
+@@ -18,6 +18,20 @@
+ #ifndef INITVALS_9340_H
+ #define INITVALS_9340_H
+
++#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
++
++#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
++
++#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
++
++#define ar9340Common_rx_gain_table_1p0 ar9300Common_rx_gain_table_2p2
++
++#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
++
++#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
++
++#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
++
+ static const u32 ar9340_1p0_radio_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
+@@ -100,8 +114,6 @@ static const u32 ar9340Modes_lowest_ob_d
+ {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
+ };
+
+-#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
+-
+ static const u32 ar9340_1p0_radio_core[][2] = {
+ /* Addr allmodes */
+ {0x00016000, 0x36db6db6},
+@@ -215,16 +227,12 @@ static const u32 ar9340_1p0_radio_core_4
+ {0x0000824c, 0x0001e800},
+ };
+
+-#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
+-
+-#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
+-
+ static const u32 ar9340_1p0_baseband_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
+ {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
+ {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+- {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
++ {0x00009828, 0x06903081, 0x06903081, 0x09103881, 0x09103881},
+ {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
+ {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
+ {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
+@@ -340,9 +348,9 @@ static const u32 ar9340_1p0_baseband_cor
+ {0x0000a370, 0x00000000},
+ {0x0000a390, 0x00000001},
+ {0x0000a394, 0x00000444},
+- {0x0000a398, 0x001f0e0f},
+- {0x0000a39c, 0x0075393f},
+- {0x0000a3a0, 0xb79f6427},
++ {0x0000a398, 0x00000000},
++ {0x0000a39c, 0x210d0401},
++ {0x0000a3a0, 0xab9a7144},
+ {0x0000a3a4, 0x00000000},
+ {0x0000a3a8, 0xaaaaaaaa},
+ {0x0000a3ac, 0x3c466478},
+@@ -714,266 +722,6 @@ static const u32 ar9340Modes_ub124_tx_ga
+ {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
+ };
+
+-static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x01910190},
+- {0x0000a030, 0x01930192},
+- {0x0000a034, 0x01950194},
+- {0x0000a038, 0x038a0196},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x22222229},
+- {0x0000a084, 0x1d1d1d1d},
+- {0x0000a088, 0x1d1d1d1d},
+- {0x0000a08c, 0x1d1d1d1d},
+- {0x0000a090, 0x171d1d1d},
+- {0x0000a094, 0x11111717},
+- {0x0000a098, 0x00030311},
+- {0x0000a09c, 0x00000000},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x23232323},
+- {0x0000b084, 0x21232323},
+- {0x0000b088, 0x19191c1e},
+- {0x0000b08c, 0x12141417},
+- {0x0000b090, 0x07070e0e},
+- {0x0000b094, 0x03030305},
+- {0x0000b098, 0x00000003},
+- {0x0000b09c, 0x00000000},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+ static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+@@ -1437,8 +1185,6 @@ static const u32 ar9340_1p0_mac_core[][2
+ {0x000083d0, 0x000101ff},
+ };
+
+-#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
+-
+ static const u32 ar9340_1p0_soc_preamble[][2] = {
+ /* Addr allmodes */
+ {0x00007008, 0x00000000},
+@@ -1447,4 +1193,106 @@ static const u32 ar9340_1p0_soc_preamble
{0x00007038, 0x000004c2},
};
#endif /* INITVALS_9340_H */
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
-@@ -459,6 +459,7 @@ void ath_check_ani(struct ath_softc *sc)
+@@ -27,40 +27,15 @@
+ #include "common.h"
+ #include "mci.h"
+ #include "dfs.h"
+-
+-/*
+- * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
+- * should rely on this file or its contents.
+- */
++#include "spectral.h"
+
+ struct ath_node;
++struct ath_rate_table;
+
+-/* Macro to expand scalars to 64-bit objects */
+-
+-#define ito64(x) (sizeof(x) == 1) ? \
+- (((unsigned long long int)(x)) & (0xff)) : \
+- (sizeof(x) == 2) ? \
+- (((unsigned long long int)(x)) & 0xffff) : \
+- ((sizeof(x) == 4) ? \
+- (((unsigned long long int)(x)) & 0xffffffff) : \
+- (unsigned long long int)(x))
+-
+-/* increment with wrap-around */
+-#define INCR(_l, _sz) do { \
+- (_l)++; \
+- (_l) &= ((_sz) - 1); \
+- } while (0)
+-
+-/* decrement with wrap-around */
+-#define DECR(_l, _sz) do { \
+- (_l)--; \
+- (_l) &= ((_sz) - 1); \
+- } while (0)
+-
+-#define TSF_TO_TU(_h,_l) \
+- ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
+-
+-#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
++extern struct ieee80211_ops ath9k_ops;
++extern int ath9k_modparam_nohwcrypt;
++extern int led_blink;
++extern bool is_ath9k_unloaded;
+
+ struct ath_config {
+ u16 txpowlimit;
+@@ -70,6 +45,17 @@ struct ath_config {
+ /* Descriptor Management */
+ /*************************/
+
++#define ATH_TXSTATUS_RING_SIZE 512
++
++/* Macro to expand scalars to 64-bit objects */
++#define ito64(x) (sizeof(x) == 1) ? \
++ (((unsigned long long int)(x)) & (0xff)) : \
++ (sizeof(x) == 2) ? \
++ (((unsigned long long int)(x)) & 0xffff) : \
++ ((sizeof(x) == 4) ? \
++ (((unsigned long long int)(x)) & 0xffffffff) : \
++ (unsigned long long int)(x))
++
+ #define ATH_TXBUF_RESET(_bf) do { \
+ (_bf)->bf_lastbf = NULL; \
+ (_bf)->bf_next = NULL; \
+@@ -77,23 +63,6 @@ struct ath_config {
+ sizeof(struct ath_buf_state)); \
+ } while (0)
+
+-/**
+- * enum buffer_type - Buffer type flags
+- *
+- * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
+- * @BUF_AGGR: Indicates whether the buffer can be aggregated
+- * (used in aggregation scheduling)
+- */
+-enum buffer_type {
+- BUF_AMPDU = BIT(0),
+- BUF_AGGR = BIT(1),
+-};
+-
+-#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
+-#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
+-
+-#define ATH_TXSTATUS_RING_SIZE 512
+-
+ #define DS2PHYS(_dd, _ds) \
+ ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
+ #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
+@@ -113,11 +82,20 @@ int ath_descdma_setup(struct ath_softc *
+ /* RX / TX */
+ /***********/
+
++#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
++
++/* increment with wrap-around */
++#define INCR(_l, _sz) do { \
++ (_l)++; \
++ (_l) &= ((_sz) - 1); \
++ } while (0)
++
+ #define ATH_RXBUF 512
+ #define ATH_TXBUF 512
+ #define ATH_TXBUF_RESERVE 5
+ #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
+ #define ATH_TXMAXTRY 13
++#define ATH_MAX_SW_RETRIES 30
+
+ #define TID_TO_WME_AC(_tid) \
+ ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
+@@ -133,6 +111,9 @@ int ath_descdma_setup(struct ath_softc *
+ #define ATH_AGGR_MIN_QDEPTH 2
+ /* minimum h/w qdepth for non-aggregated traffic */
+ #define ATH_NON_AGGR_MIN_QDEPTH 8
++#define ATH_TX_COMPLETE_POLL_INT 1000
++#define ATH_TXFIFO_DEPTH 8
++#define ATH_TX_ERROR 0x01
+
+ #define IEEE80211_SEQ_SEQ_SHIFT 4
+ #define IEEE80211_SEQ_MAX 4096
+@@ -167,9 +148,6 @@ int ath_descdma_setup(struct ath_softc *
+
+ #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
+
+-#define ATH_TX_COMPLETE_POLL_INT 1000
+-
+-#define ATH_TXFIFO_DEPTH 8
+ struct ath_txq {
+ int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
+ u32 axq_qnum; /* ath9k hardware queue number */
+@@ -214,6 +192,21 @@ struct ath_rxbuf {
+ dma_addr_t bf_buf_addr;
+ };
+
++/**
++ * enum buffer_type - Buffer type flags
++ *
++ * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
++ * @BUF_AGGR: Indicates whether the buffer can be aggregated
++ * (used in aggregation scheduling)
++ */
++enum buffer_type {
++ BUF_AMPDU = BIT(0),
++ BUF_AGGR = BIT(1),
++};
++
++#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
++#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
++
+ struct ath_buf_state {
+ u8 bf_type;
+ u8 bfs_paprd;
+@@ -278,7 +271,6 @@ struct ath_tx_control {
+ struct ieee80211_sta *sta;
+ };
+
+-#define ATH_TX_ERROR 0x01
+
+ /**
+ * @txq_map: Index is mac80211 queue number. This is
+@@ -372,6 +364,22 @@ struct ath_vif {
+ struct ath_buf *av_bcbuf;
+ };
+
++struct ath9k_vif_iter_data {
++ u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
++ u8 mask[ETH_ALEN]; /* bssid mask */
++ bool has_hw_macaddr;
++
++ int naps; /* number of AP vifs */
++ int nmeshes; /* number of mesh vifs */
++ int nstations; /* number of station vifs */
++ int nwds; /* number of WDS vifs */
++ int nadhocs; /* number of adhoc vifs */
++};
++
++void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
++ struct ieee80211_vif *vif,
++ struct ath9k_vif_iter_data *iter_data);
++
+ /*******************/
+ /* Beacon Handling */
+ /*******************/
+@@ -387,6 +395,9 @@ struct ath_vif {
+ #define ATH_DEFAULT_BMISS_LIMIT 10
+ #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
+
++#define TSF_TO_TU(_h,_l) \
++ ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
++
+ struct ath_beacon_config {
+ int beacon_interval;
+ u16 listen_interval;
+@@ -420,12 +431,10 @@ struct ath_beacon {
+ };
+
+ void ath9k_beacon_tasklet(unsigned long data);
+-bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
+ void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
+ u32 changed);
+ void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
+ void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
+-void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
+ void ath9k_set_beacon(struct ath_softc *sc);
+ bool ath9k_csa_is_finished(struct ath_softc *sc);
+
+@@ -440,10 +449,9 @@ bool ath9k_csa_is_finished(struct ath_so
+ #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
+ #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
+ #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
+-#define ATH_ANI_MAX_SKIP_COUNT 10
+-
+-#define ATH_PAPRD_TIMEOUT 100 /* msecs */
+-#define ATH_PLL_WORK_INTERVAL 100
++#define ATH_ANI_MAX_SKIP_COUNT 10
++#define ATH_PAPRD_TIMEOUT 100 /* msecs */
++#define ATH_PLL_WORK_INTERVAL 100
+
+ void ath_tx_complete_poll_work(struct work_struct *work);
+ void ath_reset_work(struct work_struct *work);
+@@ -459,6 +467,7 @@ void ath_check_ani(struct ath_softc *sc)
int ath_update_survey_stats(struct ath_softc *sc);
void ath_update_survey_nf(struct ath_softc *sc, int channel);
void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
/**********/
/* BTCOEX */
-@@ -570,6 +571,34 @@ static inline void ath_fill_led_pin(stru
+@@ -476,20 +485,19 @@ enum bt_op_flags {
+ };
+
+ struct ath_btcoex {
+- bool hw_timer_enabled;
+ spinlock_t btcoex_lock;
+ struct timer_list period_timer; /* Timer for BT period */
++ struct timer_list no_stomp_timer;
+ u32 bt_priority_cnt;
+ unsigned long bt_priority_time;
+ unsigned long op_flags;
+ int bt_stomp_type; /* Types of BT stomping */
+- u32 btcoex_no_stomp; /* in usec */
++ u32 btcoex_no_stomp; /* in msec */
+ u32 btcoex_period; /* in msec */
+- u32 btscan_no_stomp; /* in usec */
++ u32 btscan_no_stomp; /* in msec */
+ u32 duty_cycle;
+ u32 bt_wait_time;
+ int rssi_count;
+- struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
+ struct ath_mci_profile mci;
+ u8 stomp_audio;
+ };
+@@ -537,12 +545,6 @@ static inline int ath9k_dump_btcoex(stru
+ }
+ #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
+
+-struct ath9k_wow_pattern {
+- u8 pattern_bytes[MAX_PATTERN_SIZE];
+- u8 mask_bytes[MAX_PATTERN_SIZE];
+- u32 pattern_len;
+-};
+-
+ /********************/
+ /* LED Control */
+ /********************/
+@@ -570,6 +572,40 @@ static inline void ath_fill_led_pin(stru
}
#endif
+/* Wake on Wireless LAN */
+/************************/
+
-+#ifdef CONFIG_ATH9K_WOW
++struct ath9k_wow_pattern {
++ u8 pattern_bytes[MAX_PATTERN_SIZE];
++ u8 mask_bytes[MAX_PATTERN_SIZE];
++ u32 pattern_len;
++};
++
++#ifdef CPTCFG_ATH9K_WOW
+void ath9k_init_wow(struct ieee80211_hw *hw);
+int ath9k_suspend(struct ieee80211_hw *hw,
+ struct cfg80211_wowlan *wowlan);
/*******************************/
/* Antenna diversity/combining */
/*******************************/
-@@ -723,6 +752,7 @@ struct ath_softc {
+@@ -632,28 +668,24 @@ void ath_ant_comb_scan(struct ath_softc
+ /* Main driver core */
+ /********************/
+
+-#define ATH9K_PCI_CUS198 0x0001
+-#define ATH9K_PCI_CUS230 0x0002
+-#define ATH9K_PCI_CUS217 0x0004
+-#define ATH9K_PCI_CUS252 0x0008
+-#define ATH9K_PCI_WOW 0x0010
+-#define ATH9K_PCI_BT_ANT_DIV 0x0020
+-#define ATH9K_PCI_D3_L1_WAR 0x0040
+-#define ATH9K_PCI_AR9565_1ANT 0x0080
+-#define ATH9K_PCI_AR9565_2ANT 0x0100
++#define ATH9K_PCI_CUS198 0x0001
++#define ATH9K_PCI_CUS230 0x0002
++#define ATH9K_PCI_CUS217 0x0004
++#define ATH9K_PCI_CUS252 0x0008
++#define ATH9K_PCI_WOW 0x0010
++#define ATH9K_PCI_BT_ANT_DIV 0x0020
++#define ATH9K_PCI_D3_L1_WAR 0x0040
++#define ATH9K_PCI_AR9565_1ANT 0x0080
++#define ATH9K_PCI_AR9565_2ANT 0x0100
++#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
+
+ /*
+ * Default cache line size, in bytes.
+ * Used when PCI device not fully initialized by bootrom/BIOS
+ */
+ #define DEFAULT_CACHELINE 32
+-#define ATH_REGCLASSIDS_MAX 10
+ #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
+-#define ATH_MAX_SW_RETRIES 30
+-#define ATH_CHAN_MAX 255
+-
+ #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
+-#define ATH_RATE_DUMMY_MARKER 0
+
+ enum sc_op_flags {
+ SC_OP_INVALID,
+@@ -672,37 +704,6 @@ enum sc_op_flags {
+ #define PS_BEACON_SYNC BIT(4)
+ #define PS_WAIT_FOR_ANI BIT(5)
+
+-struct ath_rate_table;
+-
+-struct ath9k_vif_iter_data {
+- u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
+- u8 mask[ETH_ALEN]; /* bssid mask */
+- bool has_hw_macaddr;
+-
+- int naps; /* number of AP vifs */
+- int nmeshes; /* number of mesh vifs */
+- int nstations; /* number of station vifs */
+- int nwds; /* number of WDS vifs */
+- int nadhocs; /* number of adhoc vifs */
+-};
+-
+-/* enum spectral_mode:
+- *
+- * @SPECTRAL_DISABLED: spectral mode is disabled
+- * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
+- * something else.
+- * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
+- * is performed manually.
+- * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
+- * during a channel scan.
+- */
+-enum spectral_mode {
+- SPECTRAL_DISABLED = 0,
+- SPECTRAL_BACKGROUND,
+- SPECTRAL_MANUAL,
+- SPECTRAL_CHANSCAN,
+-};
+-
+ struct ath_softc {
+ struct ieee80211_hw *hw;
+ struct device *dev;
+@@ -723,6 +724,7 @@ struct ath_softc {
struct work_struct hw_check_work;
struct work_struct hw_reset_work;
struct completion paprd_complete;
unsigned int hw_busy_count;
unsigned long sc_flags;
-@@ -759,6 +789,7 @@ struct ath_softc {
+@@ -759,6 +761,7 @@ struct ath_softc {
struct delayed_work tx_complete_work;
struct delayed_work hw_pll_work;
struct timer_list rx_poll_timer;
#ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
struct ath_btcoex btcoex;
-@@ -783,7 +814,7 @@ struct ath_softc {
+@@ -783,199 +786,54 @@ struct ath_softc {
bool tx99_state;
s16 tx99_power;
atomic_t wow_got_bmiss_intr;
atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
u32 wow_intr_before_sleep;
-@@ -946,10 +977,25 @@ struct fft_sample_ht20_40 {
- u8 data[SPECTRAL_HT20_40_NUM_BINS];
- } __packed;
+ #endif
+ };
--int ath9k_tx99_init(struct ath_softc *sc);
--void ath9k_tx99_deinit(struct ath_softc *sc);
+-#define SPECTRAL_SCAN_BITMASK 0x10
+-/* Radar info packet format, used for DFS and spectral formats. */
+-struct ath_radar_info {
+- u8 pulse_length_pri;
+- u8 pulse_length_ext;
+- u8 pulse_bw_info;
+-} __packed;
+-
+-/* The HT20 spectral data has 4 bytes of additional information at it's end.
+- *
+- * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
+- * [7:0]: all bins max_magnitude[9:2]
+- * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
+- * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
+- */
+-struct ath_ht20_mag_info {
+- u8 all_bins[3];
+- u8 max_exp;
+-} __packed;
+-
+-#define SPECTRAL_HT20_NUM_BINS 56
+-
+-/* WARNING: don't actually use this struct! MAC may vary the amount of
+- * data by -1/+2. This struct is for reference only.
+- */
+-struct ath_ht20_fft_packet {
+- u8 data[SPECTRAL_HT20_NUM_BINS];
+- struct ath_ht20_mag_info mag_info;
+- struct ath_radar_info radar_info;
+-} __packed;
+-
+-#define SPECTRAL_HT20_TOTAL_DATA_LEN (sizeof(struct ath_ht20_fft_packet))
+-
+-/* Dynamic 20/40 mode:
+- *
+- * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
+- * [7:0]: lower bins max_magnitude[9:2]
+- * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
+- * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
+- * [7:0]: upper bins max_magnitude[9:2]
+- * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
+- * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
+- */
+-struct ath_ht20_40_mag_info {
+- u8 lower_bins[3];
+- u8 upper_bins[3];
+- u8 max_exp;
+-} __packed;
+-
+-#define SPECTRAL_HT20_40_NUM_BINS 128
+-
+-/* WARNING: don't actually use this struct! MAC may vary the amount of
+- * data. This struct is for reference only.
+- */
+-struct ath_ht20_40_fft_packet {
+- u8 data[SPECTRAL_HT20_40_NUM_BINS];
+- struct ath_ht20_40_mag_info mag_info;
+- struct ath_radar_info radar_info;
+-} __packed;
+-
+-
+-#define SPECTRAL_HT20_40_TOTAL_DATA_LEN (sizeof(struct ath_ht20_40_fft_packet))
+-
+-/* grabs the max magnitude from the all/upper/lower bins */
+-static inline u16 spectral_max_magnitude(u8 *bins)
+-{
+- return (bins[0] & 0xc0) >> 6 |
+- (bins[1] & 0xff) << 2 |
+- (bins[2] & 0x03) << 10;
+-}
+/********/
+/* TX99 */
+/********/
-+
+
+-/* return the max magnitude from the all/upper/lower bins */
+-static inline u8 spectral_max_index(u8 *bins)
+#ifdef CONFIG_ATH9K_TX99
+void ath9k_tx99_init_debug(struct ath_softc *sc);
- int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
- struct ath_tx_control *txctl);
++int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
++ struct ath_tx_control *txctl);
+#else
+static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
-+{
-+}
+ {
+- s8 m = (bins[2] & 0xfc) >> 2;
+-
+- /* TODO: this still doesn't always report the right values ... */
+- if (m > 32)
+- m |= 0xe0;
+- else
+- m &= ~0xe0;
+-
+- return m + 29;
+ }
+-
+-/* return the bitmap weight from the all/upper/lower bins */
+-static inline u8 spectral_bitmap_weight(u8 *bins)
+static inline int ath9k_tx99_send(struct ath_softc *sc,
+ struct sk_buff *skb,
+ struct ath_tx_control *txctl)
-+{
+ {
+- return bins[0] & 0x3f;
+ return 0;
-+}
+ }
+-
+-/* FFT sample format given to userspace via debugfs.
+- *
+- * Please keep the type/length at the front position and change
+- * other fields after adding another sample type
+- *
+- * TODO: this might need rework when switching to nl80211-based
+- * interface.
+- */
+-enum ath_fft_sample_type {
+- ATH_FFT_SAMPLE_HT20 = 1,
+- ATH_FFT_SAMPLE_HT20_40,
+-};
+-
+-struct fft_sample_tlv {
+- u8 type; /* see ath_fft_sample */
+- __be16 length;
+- /* type dependent data follows */
+-} __packed;
+-
+-struct fft_sample_ht20 {
+- struct fft_sample_tlv tlv;
+-
+- u8 max_exp;
+-
+- __be16 freq;
+- s8 rssi;
+- s8 noise;
+-
+- __be16 max_magnitude;
+- u8 max_index;
+- u8 bitmap_weight;
+-
+- __be64 tsf;
+-
+- u8 data[SPECTRAL_HT20_NUM_BINS];
+-} __packed;
+-
+-struct fft_sample_ht20_40 {
+- struct fft_sample_tlv tlv;
+-
+- u8 channel_type;
+- __be16 freq;
+-
+- s8 lower_rssi;
+- s8 upper_rssi;
+-
+- __be64 tsf;
+-
+- s8 lower_noise;
+- s8 upper_noise;
+-
+- __be16 lower_max_magnitude;
+- __be16 upper_max_magnitude;
+-
+- u8 lower_max_index;
+- u8 upper_max_index;
+-
+- u8 lower_bitmap_weight;
+- u8 upper_bitmap_weight;
+-
+- u8 max_exp;
+-
+- u8 data[SPECTRAL_HT20_40_NUM_BINS];
+-} __packed;
+-
+-int ath9k_tx99_init(struct ath_softc *sc);
+-void ath9k_tx99_deinit(struct ath_softc *sc);
+-int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
+- struct ath_tx_control *txctl);
+-
+-void ath9k_tasklet(unsigned long data);
+-int ath_cabq_update(struct ath_softc *);
+#endif /* CONFIG_ATH9K_TX99 */
- void ath9k_tasklet(unsigned long data);
- int ath_cabq_update(struct ath_softc *);
-@@ -966,6 +1012,9 @@ extern bool is_ath9k_unloaded;
+ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
+ {
+ common->bus_ops->read_cachesize(common, csz);
+ }
+-extern struct ieee80211_ops ath9k_ops;
+-extern int ath9k_modparam_nohwcrypt;
+-extern int led_blink;
+-extern bool is_ath9k_unloaded;
+-
++void ath9k_tasklet(unsigned long data);
++int ath_cabq_update(struct ath_softc *);
u8 ath9k_parse_mpdudensity(u8 mpdudensity);
irqreturn_t ath_isr(int irq, void *dev);
+int ath_reset(struct ath_softc *sc);
int ath9k_init_device(u16 devid, struct ath_softc *sc,
const struct ath_bus_ops *bus_ops);
void ath9k_deinit_device(struct ath_softc *sc);
+-void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
+ void ath9k_reload_chainmask_settings(struct ath_softc *sc);
+-
+-void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
+-int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
+- enum spectral_mode spectral_mode);
+-
++u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
++void ath_start_rfkill_poll(struct ath_softc *sc);
++void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
++void ath9k_ps_wakeup(struct ath_softc *sc);
++void ath9k_ps_restore(struct ath_softc *sc);
+
+ #ifdef CPTCFG_ATH9K_PCI
+ int ath_pci_init(void);
+@@ -993,15 +851,4 @@ static inline int ath_ahb_init(void) { r
+ static inline void ath_ahb_exit(void) {};
+ #endif
+
+-void ath9k_ps_wakeup(struct ath_softc *sc);
+-void ath9k_ps_restore(struct ath_softc *sc);
+-
+-u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
+-
+-void ath_start_rfkill_poll(struct ath_softc *sc);
+-extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
+-void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
+- struct ieee80211_vif *vif,
+- struct ath9k_vif_iter_data *iter_data);
+-
+ #endif /* ATH9K_H */
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
-@@ -1782,111 +1782,6 @@ void ath9k_deinit_debug(struct ath_softc
- }
- }
+@@ -17,7 +17,6 @@
+ #include <linux/slab.h>
+ #include <linux/vmalloc.h>
+ #include <linux/export.h>
+-#include <linux/relay.h>
+ #include <asm/unaligned.h>
--static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
-- size_t count, loff_t *ppos)
+ #include "ath9k.h"
+@@ -27,6 +26,47 @@
+ #define REG_READ_D(_ah, _reg) \
+ ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
+
++void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
++{
++ if (sync_cause)
++ sc->debug.stats.istats.sync_cause_all++;
++ if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
++ sc->debug.stats.istats.sync_rtc_irq++;
++ if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
++ sc->debug.stats.istats.sync_mac_irq++;
++ if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
++ sc->debug.stats.istats.eeprom_illegal_access++;
++ if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
++ sc->debug.stats.istats.apb_timeout++;
++ if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
++ sc->debug.stats.istats.pci_mode_conflict++;
++ if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
++ sc->debug.stats.istats.host1_fatal++;
++ if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
++ sc->debug.stats.istats.host1_perr++;
++ if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
++ sc->debug.stats.istats.trcv_fifo_perr++;
++ if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
++ sc->debug.stats.istats.radm_cpl_ep++;
++ if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
++ sc->debug.stats.istats.radm_cpl_dllp_abort++;
++ if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
++ sc->debug.stats.istats.radm_cpl_tlp_abort++;
++ if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
++ sc->debug.stats.istats.radm_cpl_ecrc_err++;
++ if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
++ sc->debug.stats.istats.radm_cpl_timeout++;
++ if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
++ sc->debug.stats.istats.local_timeout++;
++ if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
++ sc->debug.stats.istats.pm_access++;
++ if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
++ sc->debug.stats.istats.mac_awake++;
++ if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
++ sc->debug.stats.istats.mac_asleep++;
++ if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
++ sc->debug.stats.istats.mac_sleep_access++;
++}
+
+ static ssize_t ath9k_debugfs_read_buf(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+@@ -1016,297 +1056,6 @@ static const struct file_operations fops
+ .llseek = default_llseek,
+ };
+
+-static ssize_t read_file_spec_scan_ctl(struct file *file, char __user *user_buf,
+- size_t count, loff_t *ppos)
-{
- struct ath_softc *sc = file->private_data;
-- char buf[3];
+- char *mode = "";
- unsigned int len;
-
-- len = sprintf(buf, "%d\n", sc->tx99_state);
-- return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+- switch (sc->spectral_mode) {
+- case SPECTRAL_DISABLED:
+- mode = "disable";
+- break;
+- case SPECTRAL_BACKGROUND:
+- mode = "background";
+- break;
+- case SPECTRAL_CHANSCAN:
+- mode = "chanscan";
+- break;
+- case SPECTRAL_MANUAL:
+- mode = "manual";
+- break;
+- }
+- len = strlen(mode);
+- return simple_read_from_buffer(user_buf, count, ppos, mode, len);
-}
-
--static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
-- size_t count, loff_t *ppos)
+-static ssize_t write_file_spec_scan_ctl(struct file *file,
+- const char __user *user_buf,
+- size_t count, loff_t *ppos)
-{
- struct ath_softc *sc = file->private_data;
- struct ath_common *common = ath9k_hw_common(sc->sc_ah);
- char buf[32];
-- bool start;
- ssize_t len;
-- int r;
-
-- if (sc->nvifs > 1)
+- if (config_enabled(CPTCFG_ATH9K_TX99))
- return -EOPNOTSUPP;
-
- len = min(count, sizeof(buf) - 1);
- if (copy_from_user(buf, user_buf, len))
- return -EFAULT;
-
-- if (strtobool(buf, &start))
+- buf[len] = '\0';
+-
+- if (strncmp("trigger", buf, 7) == 0) {
+- ath9k_spectral_scan_trigger(sc->hw);
+- } else if (strncmp("background", buf, 9) == 0) {
+- ath9k_spectral_scan_config(sc->hw, SPECTRAL_BACKGROUND);
+- ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
+- } else if (strncmp("chanscan", buf, 8) == 0) {
+- ath9k_spectral_scan_config(sc->hw, SPECTRAL_CHANSCAN);
+- ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
+- } else if (strncmp("manual", buf, 6) == 0) {
+- ath9k_spectral_scan_config(sc->hw, SPECTRAL_MANUAL);
+- ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
+- } else if (strncmp("disable", buf, 7) == 0) {
+- ath9k_spectral_scan_config(sc->hw, SPECTRAL_DISABLED);
+- ath_dbg(common, CONFIG, "spectral scan: disabled\n");
+- } else {
- return -EINVAL;
--
-- if (start == sc->tx99_state) {
-- if (!start)
-- return count;
-- ath_dbg(common, XMIT, "Resetting TX99\n");
-- ath9k_tx99_deinit(sc);
- }
-
-- if (!start) {
-- ath9k_tx99_deinit(sc);
-- return count;
-- }
+- return count;
+-}
-
-- r = ath9k_tx99_init(sc);
-- if (r)
-- return r;
+-static const struct file_operations fops_spec_scan_ctl = {
+- .read = read_file_spec_scan_ctl,
+- .write = write_file_spec_scan_ctl,
+- .open = simple_open,
+- .owner = THIS_MODULE,
+- .llseek = default_llseek,
+-};
+-
+-static ssize_t read_file_spectral_short_repeat(struct file *file,
+- char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- char buf[32];
+- unsigned int len;
+-
+- len = sprintf(buf, "%d\n", sc->spec_config.short_repeat);
+- return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+-}
+-
+-static ssize_t write_file_spectral_short_repeat(struct file *file,
+- const char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- unsigned long val;
+- char buf[32];
+- ssize_t len;
+-
+- len = min(count, sizeof(buf) - 1);
+- if (copy_from_user(buf, user_buf, len))
+- return -EFAULT;
+-
+- buf[len] = '\0';
+- if (kstrtoul(buf, 0, &val))
+- return -EINVAL;
-
+- if (val < 0 || val > 1)
+- return -EINVAL;
+-
+- sc->spec_config.short_repeat = val;
- return count;
-}
-
--static const struct file_operations fops_tx99 = {
-- .read = read_file_tx99,
-- .write = write_file_tx99,
+-static const struct file_operations fops_spectral_short_repeat = {
+- .read = read_file_spectral_short_repeat,
+- .write = write_file_spectral_short_repeat,
- .open = simple_open,
- .owner = THIS_MODULE,
- .llseek = default_llseek,
-};
-
--static ssize_t read_file_tx99_power(struct file *file,
-- char __user *user_buf,
-- size_t count, loff_t *ppos)
+-static ssize_t read_file_spectral_count(struct file *file,
+- char __user *user_buf,
+- size_t count, loff_t *ppos)
-{
- struct ath_softc *sc = file->private_data;
- char buf[32];
- unsigned int len;
-
-- len = sprintf(buf, "%d (%d dBm)\n",
-- sc->tx99_power,
-- sc->tx99_power / 2);
--
+- len = sprintf(buf, "%d\n", sc->spec_config.count);
- return simple_read_from_buffer(user_buf, count, ppos, buf, len);
-}
-
--static ssize_t write_file_tx99_power(struct file *file,
-- const char __user *user_buf,
-- size_t count, loff_t *ppos)
+-static ssize_t write_file_spectral_count(struct file *file,
+- const char __user *user_buf,
+- size_t count, loff_t *ppos)
-{
- struct ath_softc *sc = file->private_data;
-- int r;
-- u8 tx_power;
+- unsigned long val;
+- char buf[32];
+- ssize_t len;
-
-- r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
-- if (r)
-- return r;
+- len = min(count, sizeof(buf) - 1);
+- if (copy_from_user(buf, user_buf, len))
+- return -EFAULT;
-
-- if (tx_power > MAX_RATE_POWER)
+- buf[len] = '\0';
+- if (kstrtoul(buf, 0, &val))
- return -EINVAL;
-
-- sc->tx99_power = tx_power;
--
-- ath9k_ps_wakeup(sc);
-- ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
-- ath9k_ps_restore(sc);
+- if (val < 0 || val > 255)
+- return -EINVAL;
-
+- sc->spec_config.count = val;
- return count;
-}
-
--static const struct file_operations fops_tx99_power = {
-- .read = read_file_tx99_power,
-- .write = write_file_tx99_power,
+-static const struct file_operations fops_spectral_count = {
+- .read = read_file_spectral_count,
+- .write = write_file_spectral_count,
- .open = simple_open,
- .owner = THIS_MODULE,
- .llseek = default_llseek,
-};
-
- int ath9k_init_debug(struct ath_hw *ah)
- {
- struct ath_common *common = ath9k_hw_common(ah);
-@@ -1903,6 +1798,7 @@ int ath9k_init_debug(struct ath_hw *ah)
- #endif
-
- ath9k_dfs_init_debug(sc);
-+ ath9k_tx99_init_debug(sc);
-
- debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
- &fops_dma);
-@@ -1978,15 +1874,6 @@ int ath9k_init_debug(struct ath_hw *ah)
- debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
- &fops_btcoex);
- #endif
-- if (config_enabled(CPTCFG_ATH9K_TX99) &&
-- AR_SREV_9300_20_OR_LATER(ah)) {
-- debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
-- sc->debug.debugfs_phy, sc,
-- &fops_tx99);
-- debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
-- sc->debug.debugfs_phy, sc,
-- &fops_tx99_power);
+-static ssize_t read_file_spectral_period(struct file *file,
+- char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- char buf[32];
+- unsigned int len;
+-
+- len = sprintf(buf, "%d\n", sc->spec_config.period);
+- return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+-}
+-
+-static ssize_t write_file_spectral_period(struct file *file,
+- const char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- unsigned long val;
+- char buf[32];
+- ssize_t len;
+-
+- len = min(count, sizeof(buf) - 1);
+- if (copy_from_user(buf, user_buf, len))
+- return -EFAULT;
+-
+- buf[len] = '\0';
+- if (kstrtoul(buf, 0, &val))
+- return -EINVAL;
+-
+- if (val < 0 || val > 255)
+- return -EINVAL;
+-
+- sc->spec_config.period = val;
+- return count;
+-}
+-
+-static const struct file_operations fops_spectral_period = {
+- .read = read_file_spectral_period,
+- .write = write_file_spectral_period,
+- .open = simple_open,
+- .owner = THIS_MODULE,
+- .llseek = default_llseek,
+-};
+-
+-static ssize_t read_file_spectral_fft_period(struct file *file,
+- char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- char buf[32];
+- unsigned int len;
+-
+- len = sprintf(buf, "%d\n", sc->spec_config.fft_period);
+- return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+-}
+-
+-static ssize_t write_file_spectral_fft_period(struct file *file,
+- const char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- unsigned long val;
+- char buf[32];
+- ssize_t len;
+-
+- len = min(count, sizeof(buf) - 1);
+- if (copy_from_user(buf, user_buf, len))
+- return -EFAULT;
+-
+- buf[len] = '\0';
+- if (kstrtoul(buf, 0, &val))
+- return -EINVAL;
+-
+- if (val < 0 || val > 15)
+- return -EINVAL;
+-
+- sc->spec_config.fft_period = val;
+- return count;
+-}
+-
+-static const struct file_operations fops_spectral_fft_period = {
+- .read = read_file_spectral_fft_period,
+- .write = write_file_spectral_fft_period,
+- .open = simple_open,
+- .owner = THIS_MODULE,
+- .llseek = default_llseek,
+-};
+-
+-static struct dentry *create_buf_file_handler(const char *filename,
+- struct dentry *parent,
+-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0))
+- umode_t mode,
+-#else
+- int mode,
+-#endif
+- struct rchan_buf *buf,
+- int *is_global)
+-{
+- struct dentry *buf_file;
+-
+- buf_file = debugfs_create_file(filename, mode, parent, buf,
+- &relay_file_operations);
+- *is_global = 1;
+- return buf_file;
+-}
+-
+-static int remove_buf_file_handler(struct dentry *dentry)
+-{
+- debugfs_remove(dentry);
+-
+- return 0;
+-}
+-
+-void ath_debug_send_fft_sample(struct ath_softc *sc,
+- struct fft_sample_tlv *fft_sample_tlv)
+-{
+- int length;
+- if (!sc->rfs_chan_spec_scan)
+- return;
+-
+- length = __be16_to_cpu(fft_sample_tlv->length) +
+- sizeof(*fft_sample_tlv);
+- relay_write(sc->rfs_chan_spec_scan, fft_sample_tlv, length);
+-}
+-
+-static struct rchan_callbacks rfs_spec_scan_cb = {
+- .create_buf_file = create_buf_file_handler,
+- .remove_buf_file = remove_buf_file_handler,
+-};
+-
+-
+ static ssize_t read_file_regidx(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+ {
+@@ -1776,117 +1525,9 @@ void ath9k_get_et_stats(struct ieee80211
+
+ void ath9k_deinit_debug(struct ath_softc *sc)
+ {
+- if (config_enabled(CPTCFG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) {
+- relay_close(sc->rfs_chan_spec_scan);
+- sc->rfs_chan_spec_scan = NULL;
+- }
++ ath9k_spectral_deinit_debug(sc);
+ }
+
+-static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- char buf[3];
+- unsigned int len;
+-
+- len = sprintf(buf, "%d\n", sc->tx99_state);
+- return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+-}
+-
+-static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+- char buf[32];
+- bool start;
+- ssize_t len;
+- int r;
+-
+- if (sc->nvifs > 1)
+- return -EOPNOTSUPP;
+-
+- len = min(count, sizeof(buf) - 1);
+- if (copy_from_user(buf, user_buf, len))
+- return -EFAULT;
+-
+- if (strtobool(buf, &start))
+- return -EINVAL;
+-
+- if (start == sc->tx99_state) {
+- if (!start)
+- return count;
+- ath_dbg(common, XMIT, "Resetting TX99\n");
+- ath9k_tx99_deinit(sc);
+- }
+-
+- if (!start) {
+- ath9k_tx99_deinit(sc);
+- return count;
+- }
+-
+- r = ath9k_tx99_init(sc);
+- if (r)
+- return r;
+-
+- return count;
+-}
+-
+-static const struct file_operations fops_tx99 = {
+- .read = read_file_tx99,
+- .write = write_file_tx99,
+- .open = simple_open,
+- .owner = THIS_MODULE,
+- .llseek = default_llseek,
+-};
+-
+-static ssize_t read_file_tx99_power(struct file *file,
+- char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- char buf[32];
+- unsigned int len;
+-
+- len = sprintf(buf, "%d (%d dBm)\n",
+- sc->tx99_power,
+- sc->tx99_power / 2);
+-
+- return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+-}
+-
+-static ssize_t write_file_tx99_power(struct file *file,
+- const char __user *user_buf,
+- size_t count, loff_t *ppos)
+-{
+- struct ath_softc *sc = file->private_data;
+- int r;
+- u8 tx_power;
+-
+- r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
+- if (r)
+- return r;
+-
+- if (tx_power > MAX_RATE_POWER)
+- return -EINVAL;
+-
+- sc->tx99_power = tx_power;
+-
+- ath9k_ps_wakeup(sc);
+- ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
+- ath9k_ps_restore(sc);
+-
+- return count;
+-}
+-
+-static const struct file_operations fops_tx99_power = {
+- .read = read_file_tx99_power,
+- .write = write_file_tx99_power,
+- .open = simple_open,
+- .owner = THIS_MODULE,
+- .llseek = default_llseek,
+-};
+-
+ int ath9k_init_debug(struct ath_hw *ah)
+ {
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -1903,6 +1544,8 @@ int ath9k_init_debug(struct ath_hw *ah)
+ #endif
+
+ ath9k_dfs_init_debug(sc);
++ ath9k_tx99_init_debug(sc);
++ ath9k_spectral_init_debug(sc);
+
+ debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
+ &fops_dma);
+@@ -1949,23 +1592,6 @@ int ath9k_init_debug(struct ath_hw *ah)
+ &fops_base_eeprom);
+ debugfs_create_file("modal_eeprom", S_IRUSR, sc->debug.debugfs_phy, sc,
+ &fops_modal_eeprom);
+- sc->rfs_chan_spec_scan = relay_open("spectral_scan",
+- sc->debug.debugfs_phy,
+- 1024, 256, &rfs_spec_scan_cb,
+- NULL);
+- debugfs_create_file("spectral_scan_ctl", S_IRUSR | S_IWUSR,
+- sc->debug.debugfs_phy, sc,
+- &fops_spec_scan_ctl);
+- debugfs_create_file("spectral_short_repeat", S_IRUSR | S_IWUSR,
+- sc->debug.debugfs_phy, sc,
+- &fops_spectral_short_repeat);
+- debugfs_create_file("spectral_count", S_IRUSR | S_IWUSR,
+- sc->debug.debugfs_phy, sc, &fops_spectral_count);
+- debugfs_create_file("spectral_period", S_IRUSR | S_IWUSR,
+- sc->debug.debugfs_phy, sc, &fops_spectral_period);
+- debugfs_create_file("spectral_fft_period", S_IRUSR | S_IWUSR,
+- sc->debug.debugfs_phy, sc,
+- &fops_spectral_fft_period);
+ debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
+ sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
+ debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
+@@ -1978,15 +1604,6 @@ int ath9k_init_debug(struct ath_hw *ah)
+ debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
+ &fops_btcoex);
+ #endif
+- if (config_enabled(CPTCFG_ATH9K_TX99) &&
+- AR_SREV_9300_20_OR_LATER(ah)) {
+- debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
+- sc->debug.debugfs_phy, sc,
+- &fops_tx99);
+- debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
+- sc->debug.debugfs_phy, sc,
+- &fops_tx99_power);
- }
return 0;
}
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -17,6 +17,7 @@
+@@ -17,6 +17,8 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/module.h>
+#include <linux/time.h>
++#include <linux/bitops.h>
#include <asm/unaligned.h>
#include "hw.h"
-@@ -454,7 +455,6 @@ static void ath9k_hw_init_config(struct
- }
+@@ -83,48 +85,6 @@ static void ath9k_hw_ani_cache_ini_regs(
+
+ #ifdef CPTCFG_ATH9K_DEBUGFS
+
+-void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
+-{
+- struct ath_softc *sc = common->priv;
+- if (sync_cause)
+- sc->debug.stats.istats.sync_cause_all++;
+- if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
+- sc->debug.stats.istats.sync_rtc_irq++;
+- if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
+- sc->debug.stats.istats.sync_mac_irq++;
+- if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
+- sc->debug.stats.istats.eeprom_illegal_access++;
+- if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
+- sc->debug.stats.istats.apb_timeout++;
+- if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
+- sc->debug.stats.istats.pci_mode_conflict++;
+- if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
+- sc->debug.stats.istats.host1_fatal++;
+- if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
+- sc->debug.stats.istats.host1_perr++;
+- if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
+- sc->debug.stats.istats.trcv_fifo_perr++;
+- if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
+- sc->debug.stats.istats.radm_cpl_ep++;
+- if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
+- sc->debug.stats.istats.radm_cpl_dllp_abort++;
+- if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
+- sc->debug.stats.istats.radm_cpl_tlp_abort++;
+- if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
+- sc->debug.stats.istats.radm_cpl_ecrc_err++;
+- if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
+- sc->debug.stats.istats.radm_cpl_timeout++;
+- if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
+- sc->debug.stats.istats.local_timeout++;
+- if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
+- sc->debug.stats.istats.pm_access++;
+- if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
+- sc->debug.stats.istats.mac_awake++;
+- if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
+- sc->debug.stats.istats.mac_asleep++;
+- if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
+- sc->debug.stats.istats.mac_sleep_access++;
+-}
+ #endif
+
+@@ -438,23 +398,13 @@ static bool ath9k_hw_chip_test(struct at
+
+ static void ath9k_hw_init_config(struct ath_hw *ah)
+ {
+- int i;
+-
+ ah->config.dma_beacon_response_time = 1;
+ ah->config.sw_beacon_response_time = 6;
+- ah->config.additional_swba_backoff = 0;
+ ah->config.ack_6mb = 0x0;
+ ah->config.cwm_ignore_extcca = 0;
+- ah->config.pcie_clock_req = 0;
+ ah->config.analog_shiftreg = 1;
+
+- for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+- ah->config.spurchans[i][0] = AR_NO_SPUR;
+- ah->config.spurchans[i][1] = AR_NO_SPUR;
+- }
+-
ah->config.rx_intr_mitigation = true;
- ah->config.pcieSerDesWrite = true;
/*
* We need this for PCI devices only (Cardbus, PCI, miniPCI)
-@@ -1502,8 +1502,9 @@ static bool ath9k_hw_channel_change(stru
- int r;
-
- if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
-- band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
-- mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
-+ u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
-+ band_switch = !!(flags_diff & CHANNEL_5GHZ);
-+ mode_diff = !!(flags_diff & ~CHANNEL_HT);
- }
-
- for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
-@@ -1815,7 +1816,7 @@ static int ath9k_hw_do_fastcc(struct ath
- * If cross-band fcc is not supoprted, bail out if channelFlags differ.
+@@ -486,7 +436,6 @@ static void ath9k_hw_init_defaults(struc
+ ah->hw_version.magic = AR5416_MAGIC;
+ ah->hw_version.subvendorid = 0;
+
+- ah->atim_window = 0;
+ ah->sta_id1_defaults =
+ AR_STA_ID1_CRPT_MIC_ENABLE |
+ AR_STA_ID1_MCAST_KSRCH;
+@@ -549,11 +498,11 @@ static int ath9k_hw_post_init(struct ath
+ * EEPROM needs to be initialized before we do this.
+ * This is required for regulatory compliance.
*/
- if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
-- chan->channelFlags != ah->curchan->channelFlags)
-+ ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
- goto fail;
-
- if (!ath9k_hw_check_alive(ah))
-@@ -1856,10 +1857,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
- struct ath9k_hw_cal_data *caldata, bool fastcc)
- {
- struct ath_common *common = ath9k_hw_common(ah);
-+ struct timespec ts;
- u32 saveLedState;
- u32 saveDefAntenna;
- u32 macStaId1;
- u64 tsf = 0;
-+ s64 usec = 0;
- int r;
- bool start_mci_reset = false;
- bool save_fullsleep = ah->chip_fullsleep;
-@@ -1902,10 +1905,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+- if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
++ if (AR_SREV_9300_20_OR_LATER(ah)) {
+ u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
+ if ((regdmn & 0xF0) == CTL_FCC) {
+- ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
+- ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
++ ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
++ ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
+ }
+ }
- macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
+@@ -1282,6 +1231,42 @@ void ath9k_hw_get_delta_slope_vals(struc
+ *coef_exponent = coef_exp - 16;
+ }
+
++/* AR9330 WAR:
++ * call external reset function to reset WMAC if:
++ * - doing a cold reset
++ * - we have pending frames in the TX queues.
++ */
++static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
++{
++ int i, npend = 0;
++
++ for (i = 0; i < AR_NUM_QCU; i++) {
++ npend = ath9k_hw_numtxpending(ah, i);
++ if (npend)
++ break;
++ }
++
++ if (ah->external_reset &&
++ (npend || type == ATH9K_RESET_COLD)) {
++ int reset_err = 0;
++
++ ath_dbg(ath9k_hw_common(ah), RESET,
++ "reset MAC via external reset\n");
++
++ reset_err = ah->external_reset();
++ if (reset_err) {
++ ath_err(ath9k_hw_common(ah),
++ "External reset failed, err=%d\n",
++ reset_err);
++ return false;
++ }
++
++ REG_WRITE(ah, AR_RTC_RESET, 1);
++ }
++
++ return true;
++}
++
+ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
+ {
+ u32 rst_flags;
+@@ -1332,38 +1317,8 @@ static bool ath9k_hw_set_reset(struct at
+ }
+
+ if (AR_SREV_9330(ah)) {
+- int npend = 0;
+- int i;
+-
+- /* AR9330 WAR:
+- * call external reset function to reset WMAC if:
+- * - doing a cold reset
+- * - we have pending frames in the TX queues
+- */
+-
+- for (i = 0; i < AR_NUM_QCU; i++) {
+- npend = ath9k_hw_numtxpending(ah, i);
+- if (npend)
+- break;
+- }
+-
+- if (ah->external_reset &&
+- (npend || type == ATH9K_RESET_COLD)) {
+- int reset_err = 0;
+-
+- ath_dbg(ath9k_hw_common(ah), RESET,
+- "reset MAC via external reset\n");
+-
+- reset_err = ah->external_reset();
+- if (reset_err) {
+- ath_err(ath9k_hw_common(ah),
+- "External reset failed, err=%d\n",
+- reset_err);
+- return false;
+- }
+-
+- REG_WRITE(ah, AR_RTC_RESET, 1);
+- }
++ if (!ath9k_hw_ar9330_reset_war(ah, type))
++ return false;
+ }
+
+ if (ath9k_hw_mci_is_enabled(ah))
+@@ -1373,7 +1328,12 @@ static bool ath9k_hw_set_reset(struct at
+
+ REGWRITE_BUFFER_FLUSH(ah);
+
+- udelay(50);
++ if (AR_SREV_9300_20_OR_LATER(ah))
++ udelay(50);
++ else if (AR_SREV_9100(ah))
++ udelay(10000);
++ else
++ udelay(100);
+
+ REG_WRITE(ah, AR_RTC_RC, 0);
+ if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
+@@ -1409,8 +1369,7 @@ static bool ath9k_hw_set_reset_power_on(
+
+ REGWRITE_BUFFER_FLUSH(ah);
+
+- if (!AR_SREV_9300_20_OR_LATER(ah))
+- udelay(2);
++ udelay(2);
+
+ if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
+ REG_WRITE(ah, AR_RC, 0);
+@@ -1502,8 +1461,9 @@ static bool ath9k_hw_channel_change(stru
+ int r;
+
+ if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
+- band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
+- mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
++ u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
++ band_switch = !!(flags_diff & CHANNEL_5GHZ);
++ mode_diff = !!(flags_diff & ~CHANNEL_HT);
+ }
+
+ for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
+@@ -1815,7 +1775,7 @@ static int ath9k_hw_do_fastcc(struct ath
+ * If cross-band fcc is not supoprted, bail out if channelFlags differ.
+ */
+ if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
+- chan->channelFlags != ah->curchan->channelFlags)
++ ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
+ goto fail;
+
+ if (!ath9k_hw_check_alive(ah))
+@@ -1856,10 +1816,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+ struct ath9k_hw_cal_data *caldata, bool fastcc)
+ {
+ struct ath_common *common = ath9k_hw_common(ah);
++ struct timespec ts;
+ u32 saveLedState;
+ u32 saveDefAntenna;
+ u32 macStaId1;
+ u64 tsf = 0;
++ s64 usec = 0;
+ int r;
+ bool start_mci_reset = false;
+ bool save_fullsleep = ah->chip_fullsleep;
+@@ -1902,10 +1864,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+
+ macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
- /* For chips on which RTC reset is done, save TSF before it gets cleared */
- if (AR_SREV_9100(ah) ||
+ /* Save TSF before chip reset, a cold reset clears it */
+ tsf = ath9k_hw_gettsf64(ah);
+ getrawmonotonic(&ts);
-+ usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
++ usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
saveLedState = REG_READ(ah, AR_CFG_LED) &
(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
-@@ -1938,8 +1941,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+@@ -1938,8 +1900,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
}
/* Restore TSF */
- if (tsf)
- ath9k_hw_settsf64(ah, tsf);
+ getrawmonotonic(&ts);
-+ usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
++ usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
+ ath9k_hw_settsf64(ah, tsf + usec);
if (AR_SREV_9280_20_OR_LATER(ah))
REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
+@@ -2261,9 +2224,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
+ case NL80211_IFTYPE_ADHOC:
+ REG_SET_BIT(ah, AR_TXCFG,
+ AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
+- REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
+- TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
+- flags |= AR_NDP_TIMER_EN;
+ case NL80211_IFTYPE_MESH_POINT:
+ case NL80211_IFTYPE_AP:
+ REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
+@@ -2284,7 +2244,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
+ REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
+ REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
+ REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
+- REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
+
+ REGWRITE_BUFFER_FLUSH(ah);
+
+@@ -2301,12 +2260,9 @@ void ath9k_hw_set_sta_beacon_timers(stru
+
+ ENABLE_REGWRITE_BUFFER(ah);
+
+- REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
+-
+- REG_WRITE(ah, AR_BEACON_PERIOD,
+- TU_TO_USEC(bs->bs_intval));
+- REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
+- TU_TO_USEC(bs->bs_intval));
++ REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
++ REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
++ REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
+
+ REGWRITE_BUFFER_FLUSH(ah);
+
+@@ -2334,9 +2290,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
+
+ ENABLE_REGWRITE_BUFFER(ah);
+
+- REG_WRITE(ah, AR_NEXT_DTIM,
+- TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
+- REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
++ REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
++ REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
+
+ REG_WRITE(ah, AR_SLEEP1,
+ SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
+@@ -2350,8 +2305,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
+ REG_WRITE(ah, AR_SLEEP2,
+ SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
+
+- REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
+- REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
++ REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
++ REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
+
+ REGWRITE_BUFFER_FLUSH(ah);
+
+@@ -2987,20 +2942,6 @@ static const struct ath_gen_timer_config
+
+ /* HW generic timer primitives */
+
+-/* compute and clear index of rightmost 1 */
+-static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
+-{
+- u32 b;
+-
+- b = *mask;
+- b &= (0-b);
+- *mask &= ~b;
+- b *= debruijn32;
+- b >>= 27;
+-
+- return timer_table->gen_timer_index[b];
+-}
+-
+ u32 ath9k_hw_gettsf32(struct ath_hw *ah)
+ {
+ return REG_READ(ah, AR_TSF_L32);
+@@ -3016,6 +2957,10 @@ struct ath_gen_timer *ath_gen_timer_allo
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+ struct ath_gen_timer *timer;
+
++ if ((timer_index < AR_FIRST_NDP_TIMER) ||
++ (timer_index >= ATH_MAX_GEN_TIMER))
++ return NULL;
++
+ timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
+ if (timer == NULL)
+ return NULL;
+@@ -3033,23 +2978,13 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
+
+ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
+ struct ath_gen_timer *timer,
+- u32 trig_timeout,
++ u32 timer_next,
+ u32 timer_period)
+ {
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+- u32 tsf, timer_next;
+-
+- BUG_ON(!timer_period);
+-
+- set_bit(timer->index, &timer_table->timer_mask.timer_bits);
+-
+- tsf = ath9k_hw_gettsf32(ah);
++ u32 mask = 0;
+
+- timer_next = tsf + trig_timeout;
+-
+- ath_dbg(ath9k_hw_common(ah), BTCOEX,
+- "current tsf %x period %x timer_next %x\n",
+- tsf, timer_period, timer_next);
++ timer_table->timer_mask |= BIT(timer->index);
+
+ /*
+ * Program generic timer registers
+@@ -3075,10 +3010,19 @@ void ath9k_hw_gen_timer_start(struct ath
+ (1 << timer->index));
+ }
+
+- /* Enable both trigger and thresh interrupt masks */
+- REG_SET_BIT(ah, AR_IMR_S5,
+- (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
+- SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
++ if (timer->trigger)
++ mask |= SM(AR_GENTMR_BIT(timer->index),
++ AR_IMR_S5_GENTIMER_TRIG);
++ if (timer->overflow)
++ mask |= SM(AR_GENTMR_BIT(timer->index),
++ AR_IMR_S5_GENTIMER_THRESH);
++
++ REG_SET_BIT(ah, AR_IMR_S5, mask);
++
++ if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
++ ah->imask |= ATH9K_INT_GENTIMER;
++ ath9k_hw_set_interrupts(ah);
++ }
+ }
+ EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
+
+@@ -3086,11 +3030,6 @@ void ath9k_hw_gen_timer_stop(struct ath_
+ {
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+
+- if ((timer->index < AR_FIRST_NDP_TIMER) ||
+- (timer->index >= ATH_MAX_GEN_TIMER)) {
+- return;
+- }
+-
+ /* Clear generic timer enable bits. */
+ REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
+ gen_tmr_configuration[timer->index].mode_mask);
+@@ -3110,7 +3049,12 @@ void ath9k_hw_gen_timer_stop(struct ath_
+ (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
+ SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
+
+- clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
++ timer_table->timer_mask &= ~BIT(timer->index);
++
++ if (timer_table->timer_mask == 0) {
++ ah->imask &= ~ATH9K_INT_GENTIMER;
++ ath9k_hw_set_interrupts(ah);
++ }
+ }
+ EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
+
+@@ -3131,32 +3075,32 @@ void ath_gen_timer_isr(struct ath_hw *ah
+ {
+ struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+ struct ath_gen_timer *timer;
+- struct ath_common *common = ath9k_hw_common(ah);
+- u32 trigger_mask, thresh_mask, index;
++ unsigned long trigger_mask, thresh_mask;
++ unsigned int index;
+
+ /* get hardware generic timer interrupt status */
+ trigger_mask = ah->intr_gen_timer_trigger;
+ thresh_mask = ah->intr_gen_timer_thresh;
+- trigger_mask &= timer_table->timer_mask.val;
+- thresh_mask &= timer_table->timer_mask.val;
++ trigger_mask &= timer_table->timer_mask;
++ thresh_mask &= timer_table->timer_mask;
+
+- trigger_mask &= ~thresh_mask;
+-
+- while (thresh_mask) {
+- index = rightmost_index(timer_table, &thresh_mask);
++ for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
+ timer = timer_table->timers[index];
+- BUG_ON(!timer);
+- ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
+- index);
++ if (!timer)
++ continue;
++ if (!timer->overflow)
++ continue;
++
++ trigger_mask &= ~BIT(index);
+ timer->overflow(timer->arg);
+ }
+
+- while (trigger_mask) {
+- index = rightmost_index(timer_table, &trigger_mask);
++ for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
+ timer = timer_table->timers[index];
+- BUG_ON(!timer);
+- ath_dbg(common, BTCOEX,
+- "Gen timer[%d] trigger\n", index);
++ if (!timer)
++ continue;
++ if (!timer->trigger)
++ continue;
+ timer->trigger(timer->arg);
+ }
+ }
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
-@@ -283,7 +283,6 @@ struct ath9k_ops_config {
- int additional_swba_backoff;
+@@ -168,7 +168,7 @@
+ #define CAB_TIMEOUT_VAL 10
+ #define BEACON_TIMEOUT_VAL 10
+ #define MIN_BEACON_TIMEOUT_VAL 1
+-#define SLEEP_SLOP 3
++#define SLEEP_SLOP TU_TO_USEC(3)
+
+ #define INIT_CONFIG_STATUS 0x00000000
+ #define INIT_RSSI_THR 0x00000700
+@@ -280,11 +280,8 @@ struct ath9k_hw_capabilities {
+ struct ath9k_ops_config {
+ int dma_beacon_response_time;
+ int sw_beacon_response_time;
+- int additional_swba_backoff;
int ack_6mb;
u32 cwm_ignore_extcca;
- bool pcieSerDesWrite;
- u8 pcie_clock_req;
+- u8 pcie_clock_req;
u32 pcie_waen;
u8 analog_shiftreg;
-@@ -920,7 +919,7 @@ struct ath_hw {
+ u32 ofdm_trig_low;
+@@ -295,18 +292,11 @@ struct ath9k_ops_config {
+ int serialize_regmode;
+ bool rx_intr_mitigation;
+ bool tx_intr_mitigation;
+-#define SPUR_DISABLE 0
+-#define SPUR_ENABLE_IOCTL 1
+-#define SPUR_ENABLE_EEPROM 2
+-#define AR_SPUR_5413_1 1640
+-#define AR_SPUR_5413_2 1200
+ #define AR_NO_SPUR 0x8000
+ #define AR_BASE_FREQ_2GHZ 2300
+ #define AR_BASE_FREQ_5GHZ 4900
+ #define AR_SPUR_FEEQ_BOUND_HT40 19
+ #define AR_SPUR_FEEQ_BOUND_HT20 10
+- int spurmode;
+- u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
+ u8 max_txtrig_level;
+ u16 ani_poll_interval; /* ANI poll interval in ms */
+
+@@ -316,6 +306,8 @@ struct ath9k_ops_config {
+ u32 ant_ctrl_comm2g_switch_enable;
+ bool xatten_margin_cfg;
+ bool alt_mingainidx;
++ bool no_pll_pwrsave;
++ bool tx_gain_buffalo;
+ };
+
+ enum ath9k_int {
+@@ -459,10 +451,6 @@ struct ath9k_beacon_state {
+ u32 bs_intval;
+ #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
+ u32 bs_dtimperiod;
+- u16 bs_cfpperiod;
+- u16 bs_cfpmaxduration;
+- u32 bs_cfpnext;
+- u16 bs_timoffset;
+ u16 bs_bmissthreshold;
+ u32 bs_sleepduration;
+ u32 bs_tsfoor_threshold;
+@@ -498,12 +486,6 @@ struct ath9k_hw_version {
+
+ #define AR_GENTMR_BIT(_index) (1 << (_index))
+
+-/*
+- * Using de Bruijin sequence to look up 1's index in a 32 bit number
+- * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
+- */
+-#define debruijn32 0x077CB531U
+-
+ struct ath_gen_timer_configuration {
+ u32 next_addr;
+ u32 period_addr;
+@@ -519,12 +501,8 @@ struct ath_gen_timer {
+ };
+
+ struct ath_gen_timer_table {
+- u32 gen_timer_index[32];
+ struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
+- union {
+- unsigned long timer_bits;
+- u16 val;
+- } timer_mask;
++ u16 timer_mask;
+ };
+
+ struct ath_hw_antcomb_conf {
+@@ -689,7 +667,8 @@ struct ath_hw_ops {
+ struct ath9k_channel *chan,
+ u8 rxchainmask,
+ bool longcal);
+- bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
++ bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
++ u32 *sync_cause_p);
+ void (*set_txdesc)(struct ath_hw *ah, void *ds,
+ struct ath_tx_info *i);
+ int (*proc_txdesc)(struct ath_hw *ah, void *ds,
+@@ -785,7 +764,6 @@ struct ath_hw {
+ u32 txurn_interrupt_mask;
+ atomic_t intr_ref_cnt;
+ bool chip_fullsleep;
+- u32 atim_window;
+ u32 modes_index;
+
+ /* Calibration */
+@@ -864,6 +842,7 @@ struct ath_hw {
+ u32 gpio_mask;
+ u32 gpio_val;
+
++ struct ar5416IniArray ini_dfs;
+ struct ar5416IniArray iniModes;
+ struct ar5416IniArray iniCommon;
+ struct ar5416IniArray iniBB_RfGain;
+@@ -920,7 +899,7 @@ struct ath_hw {
/* Enterprise mode cap */
u32 ent_mode;
u32 wow_event_mask;
#endif
bool is_clk_25mhz;
-@@ -1126,7 +1125,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
+@@ -1016,13 +995,6 @@ bool ath9k_hw_check_alive(struct ath_hw
+
+ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
+
+-#ifdef CPTCFG_ATH9K_DEBUGFS
+-void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
+-#else
+-static inline void ath9k_debug_sync_cause(struct ath_common *common,
+- u32 sync_cause) {}
+-#endif
+-
+ /* Generic hw timer primitives */
+ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
+ void (*trigger)(void *),
+@@ -1126,7 +1098,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
#endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
u8 *user_mask, int pattern_count,
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -683,6 +683,7 @@ static int ath9k_init_softc(u16 devid, s
+@@ -470,7 +470,6 @@ static int ath9k_init_queues(struct ath_
+
+ sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
+ sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
+-
+ ath_cabq_update(sc);
+
+ sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
+@@ -554,7 +553,7 @@ static void ath9k_init_misc(struct ath_s
+ sc->spec_config.fft_period = 0xF;
+ }
+
+-static void ath9k_init_platform(struct ath_softc *sc)
++static void ath9k_init_pcoem_platform(struct ath_softc *sc)
+ {
+ struct ath_hw *ah = sc->sc_ah;
+ struct ath9k_hw_capabilities *pCap = &ah->caps;
+@@ -609,6 +608,11 @@ static void ath9k_init_platform(struct a
+ ah->config.pcie_waen = 0x0040473b;
+ ath_info(common, "Enable WAR for ASPM D3/L1\n");
+ }
++
++ if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
++ ah->config.no_pll_pwrsave = true;
++ ath_info(common, "Disable PLL PowerSave\n");
++ }
+ }
+
+ static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
+@@ -656,6 +660,27 @@ static void ath9k_eeprom_release(struct
+ release_firmware(sc->sc_ah->eeprom_blob);
+ }
+
++static int ath9k_init_soc_platform(struct ath_softc *sc)
++{
++ struct ath9k_platform_data *pdata = sc->dev->platform_data;
++ struct ath_hw *ah = sc->sc_ah;
++ int ret = 0;
++
++ if (!pdata)
++ return 0;
++
++ if (pdata->eeprom_name) {
++ ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
++ if (ret)
++ return ret;
++ }
++
++ if (pdata->tx_gain_buffalo)
++ ah->config.tx_gain_buffalo = true;
++
++ return ret;
++}
++
+ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
+ const struct ath_bus_ops *bus_ops)
+ {
+@@ -676,13 +701,13 @@ static int ath9k_init_softc(u16 devid, s
+ ah->reg_ops.read = ath9k_ioread32;
+ ah->reg_ops.write = ath9k_iowrite32;
+ ah->reg_ops.rmw = ath9k_reg_rmw;
+- atomic_set(&ah->intr_ref_cnt, -1);
+ sc->sc_ah = ah;
+ pCap = &ah->caps;
+
common = ath9k_hw_common(ah);
sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
sc->tx99_power = MAX_RATE_POWER + 1;
if (!pdata) {
ah->ah_flags |= AH_USE_EEPROM;
-@@ -730,6 +731,7 @@ static int ath9k_init_softc(u16 devid, s
+@@ -708,7 +733,11 @@ static int ath9k_init_softc(u16 devid, s
+ /*
+ * Platform quirks.
+ */
+- ath9k_init_platform(sc);
++ ath9k_init_pcoem_platform(sc);
++
++ ret = ath9k_init_soc_platform(sc);
++ if (ret)
++ return ret;
+
+ /*
+ * Enable WLAN/BT RX Antenna diversity only when:
+@@ -722,7 +751,6 @@ static int ath9k_init_softc(u16 devid, s
+ common->bt_ant_diversity = 1;
+
+ spin_lock_init(&common->cc_lock);
+-
+ spin_lock_init(&sc->sc_serial_rw);
+ spin_lock_init(&sc->sc_pm_lock);
+ mutex_init(&sc->mutex);
+@@ -730,6 +758,7 @@ static int ath9k_init_softc(u16 devid, s
tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
(unsigned long)sc);
INIT_WORK(&sc->hw_reset_work, ath_reset_work);
INIT_WORK(&sc->hw_check_work, ath_hw_check);
INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
-@@ -845,7 +847,8 @@ static const struct ieee80211_iface_limi
+@@ -743,12 +772,6 @@ static int ath9k_init_softc(u16 devid, s
+ ath_read_cachesize(common, &csz);
+ common->cachelsz = csz << 2; /* convert to bytes */
+
+- if (pdata && pdata->eeprom_name) {
+- ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
+- if (ret)
+- return ret;
+- }
+-
+ /* Initializes the hardware for all supported chipsets */
+ ret = ath9k_hw_init(ah);
+ if (ret)
+@@ -845,7 +868,8 @@ static const struct ieee80211_iface_limi
};
static const struct ieee80211_iface_limit if_dfs_limits[] = {
};
static const struct ieee80211_iface_combination if_comb[] = {
-@@ -862,20 +865,11 @@ static const struct ieee80211_iface_comb
+@@ -862,21 +886,12 @@ static const struct ieee80211_iface_comb
.max_interfaces = 1,
.num_different_channels = 1,
.beacon_int_infra_match = true,
-};
-#endif
-
- void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
+-void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
++static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
{
struct ath_hw *ah = sc->sc_ah;
-@@ -925,16 +919,6 @@ void ath9k_set_hw_capab(struct ath_softc
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -925,16 +940,6 @@ void ath9k_set_hw_capab(struct ath_softc
hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
hw->queues = 4;
hw->max_rates = 4;
hw->channel_change_time = 5000;
-@@ -960,6 +944,7 @@ void ath9k_set_hw_capab(struct ath_softc
+@@ -960,6 +965,7 @@ void ath9k_set_hw_capab(struct ath_softc
hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
&sc->sbands[IEEE80211_BAND_5GHZ];
ath9k_reload_chainmask_settings(sc);
SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
-@@ -1058,6 +1043,7 @@ static void ath9k_deinit_softc(struct at
+@@ -1058,6 +1064,7 @@ static void ath9k_deinit_softc(struct at
if (ATH_TXQ_SETUP(sc, i))
ath_tx_cleanupq(sc, &sc->tx.txq[i]);
{
ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
-@@ -487,6 +504,8 @@ void ath9k_tasklet(unsigned long data)
+@@ -487,8 +504,13 @@ void ath9k_tasklet(unsigned long data)
ath_tx_edma_tasklet(sc);
else
ath_tx_tasklet(sc);
+ wake_up(&sc->tx_wait);
}
++ if (status & ATH9K_INT_GENTIMER)
++ ath_gen_timer_isr(sc->sc_ah);
++
ath9k_btcoex_handle_interrupt(sc, status);
-@@ -579,7 +598,8 @@ irqreturn_t ath_isr(int irq, void *dev)
+
+ /* re-enable hardware interrupt */
+@@ -519,6 +541,7 @@ irqreturn_t ath_isr(int irq, void *dev)
+ struct ath_hw *ah = sc->sc_ah;
+ struct ath_common *common = ath9k_hw_common(ah);
+ enum ath9k_int status;
++ u32 sync_cause;
+ bool sched = false;
+
+ /*
+@@ -545,7 +568,8 @@ irqreturn_t ath_isr(int irq, void *dev)
+ * bits we haven't explicitly enabled so we mask the
+ * value to insure we only process bits we requested.
+ */
+- ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
++ ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
++ ath9k_debug_sync_cause(sc, sync_cause);
+ status &= ah->imask; /* discard unasked-for bits */
+
+ /*
+@@ -579,7 +603,8 @@ irqreturn_t ath_isr(int irq, void *dev)
goto chip_reset;
}
if (status & ATH9K_INT_BMISS) {
if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
ath_dbg(common, ANY, "during WoW we got a BMISS\n");
-@@ -588,6 +608,8 @@ irqreturn_t ath_isr(int irq, void *dev)
+@@ -588,6 +613,8 @@ irqreturn_t ath_isr(int irq, void *dev)
}
}
#endif
if (status & ATH9K_INT_SWBA)
tasklet_schedule(&sc->bcon_tasklet);
-@@ -627,7 +649,7 @@ chip_reset:
+@@ -627,7 +654,7 @@ chip_reset:
#undef SCHED_INTR
}
{
int r;
-@@ -1817,13 +1839,31 @@ static void ath9k_set_coverage_class(str
+@@ -735,6 +762,8 @@ static int ath9k_start(struct ieee80211_
+ */
+ ath9k_cmn_init_crypto(sc->sc_ah);
+
++ ath9k_hw_reset_tsf(ah);
++
+ spin_unlock_bh(&sc->sc_pcu_lock);
+
+ mutex_unlock(&sc->mutex);
+@@ -1635,13 +1664,8 @@ static void ath9k_bss_info_changed(struc
+ }
+
+ if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
+- (changed & BSS_CHANGED_BEACON_INT)) {
+- if (ah->opmode == NL80211_IFTYPE_AP &&
+- bss_conf->enable_beacon)
+- ath9k_set_tsfadjust(sc, vif);
+- if (ath9k_allow_beacon_config(sc, vif))
+- ath9k_beacon_config(sc, vif, changed);
+- }
++ (changed & BSS_CHANGED_BEACON_INT))
++ ath9k_beacon_config(sc, vif, changed);
+
+ if (changed & BSS_CHANGED_ERP_SLOT) {
+ if (bss_conf->use_short_slot)
+@@ -1817,13 +1841,31 @@ static void ath9k_set_coverage_class(str
mutex_unlock(&sc->mutex);
}
bool drain_txq;
mutex_lock(&sc->mutex);
-@@ -1841,25 +1881,9 @@ static void ath9k_flush(struct ieee80211
+@@ -1841,25 +1883,9 @@ static void ath9k_flush(struct ieee80211
return;
}
if (drop) {
ath9k_ps_wakeup(sc);
-@@ -2021,333 +2045,6 @@ static int ath9k_get_antenna(struct ieee
+@@ -2021,333 +2047,6 @@ static int ath9k_get_antenna(struct ieee
return 0;
}
static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
{
struct ath_softc *sc = hw->priv;
-@@ -2373,134 +2070,6 @@ static void ath9k_channel_switch_beacon(
+@@ -2373,134 +2072,6 @@ static void ath9k_channel_switch_beacon(
sc->csa_vif = vif;
}
struct ieee80211_ops ath9k_ops = {
.tx = ath9k_tx,
.start = ath9k_start,
-@@ -2531,7 +2100,7 @@ struct ieee80211_ops ath9k_ops = {
+@@ -2531,7 +2102,7 @@ struct ieee80211_ops ath9k_ops = {
.set_antenna = ath9k_set_antenna,
.get_antenna = ath9k_get_antenna,
-EXPORT_SYMBOL(ath9k_hw_wow_enable);
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
-@@ -1786,6 +1786,9 @@ bool ath_drain_all_txq(struct ath_softc
+@@ -174,14 +174,7 @@ static void ath_txq_skb_done(struct ath_
+ static struct ath_atx_tid *
+ ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
+ {
+- struct ieee80211_hdr *hdr;
+- u8 tidno = 0;
+-
+- hdr = (struct ieee80211_hdr *) skb->data;
+- if (ieee80211_is_data_qos(hdr->frame_control))
+- tidno = ieee80211_get_qos_ctl(hdr)[0];
+-
+- tidno &= IEEE80211_QOS_CTL_TID_MASK;
++ u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
+ return ATH_AN_2_TID(an, tidno);
+ }
+
+@@ -1276,6 +1269,10 @@ static void ath_tx_fill_desc(struct ath_
+ if (!rts_thresh || (len > rts_thresh))
+ rts = true;
+ }
++
++ if (!aggr)
++ len = fi->framelen;
++
+ ath_buf_set_rate(sc, bf, &info, len, rts);
+ }
+
+@@ -1786,6 +1783,9 @@ bool ath_drain_all_txq(struct ath_softc
if (!ATH_TXQ_SETUP(sc, i))
continue;
if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
npend |= BIT(i);
}
-@@ -2749,6 +2752,8 @@ void ath_tx_node_cleanup(struct ath_soft
+@@ -2749,6 +2749,8 @@ void ath_tx_node_cleanup(struct ath_soft
}
}
int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
struct ath_tx_control *txctl)
{
-@@ -2791,3 +2796,5 @@ int ath9k_tx99_send(struct ath_softc *sc
+@@ -2791,3 +2793,5 @@ int ath9k_tx99_send(struct ath_softc *sc
return 0;
}
--- a/net/mac80211/tx.c
+++ b/net/mac80211/tx.c
-@@ -1728,8 +1728,7 @@ netdev_tx_t ieee80211_monitor_start_xmit
+@@ -463,7 +463,6 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
+ {
+ struct sta_info *sta = tx->sta;
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb);
+- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data;
+ struct ieee80211_local *local = tx->local;
+
+ if (unlikely(!sta))
+@@ -474,15 +473,6 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
+ !(info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER))) {
+ int ac = skb_get_queue_mapping(tx->skb);
+
+- /* only deauth, disassoc and action are bufferable MMPDUs */
+- if (ieee80211_is_mgmt(hdr->frame_control) &&
+- !ieee80211_is_deauth(hdr->frame_control) &&
+- !ieee80211_is_disassoc(hdr->frame_control) &&
+- !ieee80211_is_action(hdr->frame_control)) {
+- info->flags |= IEEE80211_TX_CTL_NO_PS_BUFFER;
+- return TX_CONTINUE;
+- }
+-
+ ps_dbg(sta->sdata, "STA %pM aid %d: PS buffer for AC %d\n",
+ sta->sta.addr, sta->sta.aid, ac);
+ if (tx->local->total_ps_buffered >= TOTAL_MAX_TX_BUFFER)
+@@ -525,9 +515,21 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
+ static ieee80211_tx_result debug_noinline
+ ieee80211_tx_h_ps_buf(struct ieee80211_tx_data *tx)
+ {
++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb);
++ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data;
++
+ if (unlikely(tx->flags & IEEE80211_TX_PS_BUFFERED))
+ return TX_CONTINUE;
+
++ /* only deauth, disassoc and action are bufferable MMPDUs */
++ if (ieee80211_is_mgmt(hdr->frame_control) &&
++ !ieee80211_is_deauth(hdr->frame_control) &&
++ !ieee80211_is_disassoc(hdr->frame_control) &&
++ !ieee80211_is_action(hdr->frame_control)) {
++ info->flags |= IEEE80211_TX_CTL_NO_PS_BUFFER;
++ return TX_CONTINUE;
++ }
++
+ if (tx->flags & IEEE80211_TX_UNICAST)
+ return ieee80211_tx_h_unicast_ps_buf(tx);
+ else
+@@ -1728,8 +1730,7 @@ netdev_tx_t ieee80211_monitor_start_xmit
* radar detection by itself. We can do that later by adding a
* monitor flag interfaces used for AP support.
*/
goto fail_rcu;
ieee80211_xmit(sdata, skb, chan->band);
+@@ -2530,7 +2531,8 @@ struct sk_buff *ieee80211_beacon_get_tim
+ */
+ skb = dev_alloc_skb(local->tx_headroom +
+ beacon->head_len +
+- beacon->tail_len + 256);
++ beacon->tail_len + 256 +
++ local->hw.extra_beacon_tailroom);
+ if (!skb)
+ goto out;
+
+@@ -2562,7 +2564,8 @@ struct sk_buff *ieee80211_beacon_get_tim
+ ieee80211_update_csa(sdata, presp);
+
+
+- skb = dev_alloc_skb(local->tx_headroom + presp->head_len);
++ skb = dev_alloc_skb(local->tx_headroom + presp->head_len +
++ local->hw.extra_beacon_tailroom);
+ if (!skb)
+ goto out;
+ skb_reserve(skb, local->tx_headroom);
+@@ -2589,7 +2592,8 @@ struct sk_buff *ieee80211_beacon_get_tim
+ skb = dev_alloc_skb(local->tx_headroom +
+ bcn->head_len +
+ 256 + /* TIM IE */
+- bcn->tail_len);
++ bcn->tail_len +
++ local->hw.extra_beacon_tailroom);
+ if (!skb)
+ goto out;
+ skb_reserve(skb, local->tx_headroom);
--- a/net/mac80211/util.c
+++ b/net/mac80211/util.c
@@ -2259,14 +2259,17 @@ u64 ieee80211_calculate_rx_timestamp(str
NL80211_RADAR_CAC_ABORTED,
GFP_KERNEL);
}
-@@ -2459,14 +2462,9 @@ int ieee80211_send_action_csa(struct iee
+@@ -2459,16 +2462,146 @@ int ieee80211_send_action_csa(struct iee
WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT : 0x00;
put_unaligned_le16(WLAN_REASON_MESH_CHAN, pos); /* Reason Cd */
pos += 2;
}
ieee80211_tx_skb(sdata, skb);
---- a/net/wireless/chan.c
-+++ b/net/wireless/chan.c
-@@ -277,6 +277,32 @@ void cfg80211_set_dfs_state(struct wiphy
- width, dfs_state);
+ return 0;
}
-
-+static u32 cfg80211_get_start_freq(u32 center_freq,
-+ u32 bandwidth)
++
++static bool
++ieee80211_extend_noa_desc(struct ieee80211_noa_data *data, u32 tsf, int i)
+{
-+ u32 start_freq;
++ s32 end = data->desc[i].start + data->desc[i].duration - (tsf + 1);
++ int skip;
+
-+ if (bandwidth <= 20)
-+ start_freq = center_freq;
-+ else
-+ start_freq = center_freq - bandwidth/2 + 10;
++ if (end > 0)
++ return false;
+
-+ return start_freq;
++ /* End time is in the past, check for repetitions */
++ skip = DIV_ROUND_UP(-end, data->desc[i].interval);
++ if (data->count[i] < 255) {
++ if (data->count[i] <= skip) {
++ data->count[i] = 0;
++ return false;
++ }
++
++ data->count[i] -= skip;
++ }
++
++ data->desc[i].start += skip * data->desc[i].interval;
++
++ return true;
+}
+
-+static u32 cfg80211_get_end_freq(u32 center_freq,
-+ u32 bandwidth)
++static bool
++ieee80211_extend_absent_time(struct ieee80211_noa_data *data, u32 tsf,
++ s32 *offset)
+{
-+ u32 end_freq;
++ bool ret = false;
++ int i;
+
-+ if (bandwidth <= 20)
-+ end_freq = center_freq;
-+ else
-+ end_freq = center_freq + bandwidth/2 - 10;
++ for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
++ s32 cur;
+
-+ return end_freq;
++ if (!data->count[i])
++ continue;
++
++ if (ieee80211_extend_noa_desc(data, tsf + *offset, i))
++ ret = true;
++
++ cur = data->desc[i].start - tsf;
++ if (cur > *offset)
++ continue;
++
++ cur = data->desc[i].start + data->desc[i].duration - tsf;
++ if (cur > *offset)
++ *offset = cur;
++ }
++
++ return ret;
+}
+
- static int cfg80211_get_chans_dfs_required(struct wiphy *wiphy,
- u32 center_freq,
++static u32
++ieee80211_get_noa_absent_time(struct ieee80211_noa_data *data, u32 tsf)
++{
++ s32 offset = 0;
++ int tries = 0;
++
++ ieee80211_extend_absent_time(data, tsf, &offset);
++ do {
++ if (!ieee80211_extend_absent_time(data, tsf, &offset))
++ break;
++
++ tries++;
++ } while (tries < 5);
++
++ return offset;
++}
++
++void ieee80211_update_p2p_noa(struct ieee80211_noa_data *data, u32 tsf)
++{
++ u32 next_offset = BIT(31) - 1;
++ int i;
++
++ data->absent = 0;
++ data->has_next_tsf = false;
++ for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
++ s32 start;
++
++ if (!data->count[i])
++ continue;
++
++ ieee80211_extend_noa_desc(data, tsf, i);
++ start = data->desc[i].start - tsf;
++ if (start <= 0)
++ data->absent |= BIT(i);
++
++ if (next_offset > start)
++ next_offset = start;
++
++ data->has_next_tsf = true;
++ }
++
++ if (data->absent)
++ next_offset = ieee80211_get_noa_absent_time(data, tsf);
++
++ data->next_tsf = tsf + next_offset;
++}
++EXPORT_SYMBOL(ieee80211_update_p2p_noa);
++
++int ieee80211_parse_p2p_noa(const struct ieee80211_p2p_noa_attr *attr,
++ struct ieee80211_noa_data *data, u32 tsf)
++{
++ int ret = 0;
++ int i;
++
++ memset(data, 0, sizeof(*data));
++
++ for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
++ const struct ieee80211_p2p_noa_desc *desc = &attr->desc[i];
++
++ if (!desc->count || !desc->duration)
++ continue;
++
++ data->count[i] = desc->count;
++ data->desc[i].start = le32_to_cpu(desc->start_time);
++ data->desc[i].duration = le32_to_cpu(desc->duration);
++ data->desc[i].interval = le32_to_cpu(desc->interval);
++
++ if (data->count[i] > 1 &&
++ data->desc[i].interval < data->desc[i].duration)
++ continue;
++
++ ieee80211_extend_noa_desc(data, tsf, i);
++ ret++;
++ }
++
++ if (ret)
++ ieee80211_update_p2p_noa(data, tsf);
++
++ return ret;
++}
++EXPORT_SYMBOL(ieee80211_parse_p2p_noa);
+--- a/net/wireless/chan.c
++++ b/net/wireless/chan.c
+@@ -277,6 +277,32 @@ void cfg80211_set_dfs_state(struct wiphy
+ width, dfs_state);
+ }
+
++static u32 cfg80211_get_start_freq(u32 center_freq,
++ u32 bandwidth)
++{
++ u32 start_freq;
++
++ if (bandwidth <= 20)
++ start_freq = center_freq;
++ else
++ start_freq = center_freq - bandwidth/2 + 10;
++
++ return start_freq;
++}
++
++static u32 cfg80211_get_end_freq(u32 center_freq,
++ u32 bandwidth)
++{
++ u32 end_freq;
++
++ if (bandwidth <= 20)
++ end_freq = center_freq;
++ else
++ end_freq = center_freq + bandwidth/2 - 10;
++
++ return end_freq;
++}
++
+ static int cfg80211_get_chans_dfs_required(struct wiphy *wiphy,
+ u32 center_freq,
u32 bandwidth)
@@ -284,13 +310,8 @@ static int cfg80211_get_chans_dfs_requir
struct ieee80211_channel *c;
/*
* RXGAIN initvals.
*/
+@@ -1281,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs
+ static void ar9003_hw_set_radar_params(struct ath_hw *ah,
+ struct ath_hw_radar_conf *conf)
+ {
++ unsigned int regWrites = 0;
+ u32 radar_0 = 0, radar_1 = 0;
+
+ if (!conf) {
+@@ -1307,6 +1359,11 @@ static void ar9003_hw_set_radar_params(s
+ REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+ else
+ REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
++
++ if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
++ REG_WRITE_ARRAY(&ah->ini_dfs,
++ IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
++ }
+ }
+
+ static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
-@@ -656,13 +656,24 @@
+@@ -270,7 +270,7 @@
+ #define AR_PHY_AGC (AR_AGC_BASE + 0x14)
+ #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18)
+ #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
+-#define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20)
++#define AR_PHY_CCA_CTRL_0 (AR_AGC_BASE + 0x20)
+ #define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
+
+ /*
+@@ -341,14 +341,15 @@
+ #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
+ #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
+
++#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
++#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
++
+ #define AR_PHY_CCA_NOM_VAL_9462_2GHZ -127
+ #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ -127
+ #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ -60
+-#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95
+ #define AR_PHY_CCA_NOM_VAL_9462_5GHZ -127
+ #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ -127
+ #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ -60
+-#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100
+
+ #define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118
+
+@@ -397,6 +398,8 @@
+ #define AR9280_PHY_CCA_THRESH62_S 12
+ #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
+ #define AR_PHY_EXT_CCA0_THRESH62_S 0
++#define AR_PHY_EXT_CCA0_THRESH62_1 0x000001FF
++#define AR_PHY_EXT_CCA0_THRESH62_1_S 0
+ #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
+ #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
+ #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
+@@ -656,13 +659,24 @@
#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
#define AR_PHY_65NM_CH0_SYNTH7 0x16098
}
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-@@ -1040,8 +1040,8 @@ static void ar9003_hw_cl_cal_post_proc(s
+@@ -898,7 +898,7 @@ static void ar9003_hw_tx_iq_cal_reload(s
+
+ static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
+ {
+- int offset[8], total = 0, test;
++ int offset[8] = {0}, total = 0, test;
+ int agc_out, i;
+
+ REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
+@@ -923,12 +923,18 @@ static void ar9003_hw_manual_peak_cal(st
+ AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
+ REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
+ AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
+- if (is_2g)
+- REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
+- AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
+- else
++
++ if (AR_SREV_9330_11(ah)) {
+ REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
+- AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
++ AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
++ } else {
++ if (is_2g)
++ REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
++ AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
++ else
++ REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
++ AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
++ }
+
+ for (i = 6; i > 0; i--) {
+ offset[i] = BIT(i - 1);
+@@ -964,9 +970,9 @@ static void ar9003_hw_manual_peak_cal(st
+ AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
+ }
+
+-static void ar9003_hw_do_manual_peak_cal(struct ath_hw *ah,
+- struct ath9k_channel *chan,
+- bool run_rtt_cal)
++static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
++ struct ath9k_channel *chan,
++ bool run_rtt_cal)
+ {
+ struct ath9k_hw_cal_data *caldata = ah->caldata;
+ int i;
+@@ -1040,14 +1046,14 @@ static void ar9003_hw_cl_cal_post_proc(s
}
}
{
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_hw_cal_data *caldata = ah->caldata;
-@@ -1228,13 +1228,109 @@ skip_tx_iqcal:
+ bool txiqcal_done = false;
+ bool is_reusable = true, status = true;
+- bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
++ bool run_rtt_cal = false, run_agc_cal;
+ bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
+ u32 rx_delay = 0;
+ u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
+@@ -1119,22 +1125,12 @@ static bool ar9003_hw_init_cal(struct at
+ REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
+ AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
+ txiqcal_done = run_agc_cal = true;
+- } else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
+- run_agc_cal = true;
+- sep_iq_cal = true;
+ }
+
+ skip_tx_iqcal:
+ if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
+ ar9003_mci_init_cal_req(ah, &is_reusable);
+
+- if (sep_iq_cal) {
+- txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
+- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+- udelay(5);
+- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+- }
+-
+ if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
+ rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
+ /* Disable BB_active */
+@@ -1155,7 +1151,7 @@ skip_tx_iqcal:
+ AR_PHY_AGC_CONTROL_CAL,
+ 0, AH_WAIT_TIMEOUT);
+
+- ar9003_hw_do_manual_peak_cal(ah, chan, run_rtt_cal);
++ ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
+ }
+
+ if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
+@@ -1228,13 +1224,112 @@ skip_tx_iqcal:
return true;
}
+
+skip_tx_iqcal:
+ if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
++ if (AR_SREV_9330_11(ah))
++ ar9003_hw_manual_peak_cal(ah, 0, IS_CHAN_2GHZ(chan));
++
+ /* Calibrate the AGC */
+ REG_WRITE(ah, AR_PHY_AGC_CONTROL,
+ REG_READ(ah, AR_PHY_AGC_CONTROL) |
}
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-@@ -3984,18 +3984,20 @@ static void ar9003_hw_quick_drop_apply(s
+@@ -131,6 +131,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -138,7 +139,7 @@ static const struct ar9300_eeprom ar9300
+ },
+ .base_ext1 = {
+ .ant_div_control = 0,
+- .future = {0, 0, 0},
++ .future = {0, 0},
+ .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ .calFreqPier2G = {
+@@ -333,6 +334,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -707,6 +709,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -714,7 +717,7 @@ static const struct ar9300_eeprom ar9300
+ },
+ .base_ext1 = {
+ .ant_div_control = 0,
+- .future = {0, 0, 0},
++ .future = {0, 0},
+ .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ .calFreqPier2G = {
+@@ -909,6 +912,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -1284,6 +1288,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -1291,7 +1296,7 @@ static const struct ar9300_eeprom ar9300
+ },
+ .base_ext1 = {
+ .ant_div_control = 0,
+- .future = {0, 0, 0},
++ .future = {0, 0},
+ .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ .calFreqPier2G = {
+@@ -1486,6 +1491,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -1861,6 +1867,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -1868,7 +1875,7 @@ static const struct ar9300_eeprom ar9300
+ },
+ .base_ext1 = {
+ .ant_div_control = 0,
+- .future = {0, 0, 0},
++ .future = {0, 0},
+ .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ .calFreqPier2G = {
+@@ -2063,6 +2070,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -2437,6 +2445,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80C080),
+ .papdRateMaskHt40 = LE32(0x0080C080),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -2444,7 +2453,7 @@ static const struct ar9300_eeprom ar9300
+ },
+ .base_ext1 = {
+ .ant_div_control = 0,
+- .future = {0, 0, 0},
++ .future = {0, 0},
+ .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ .calFreqPier2G = {
+@@ -2639,6 +2648,7 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .switchcomspdt = 0,
+ .xlna_bias_strength = 0,
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0,
+@@ -3965,7 +3975,7 @@ static void ar9003_hw_apply_tuning_caps(
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+ u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
+
+- if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
++ if (AR_SREV_9340(ah))
+ return;
+
+ if (eep->baseEepHeader.featureEnable & 0x40) {
+@@ -3984,18 +3994,20 @@ static void ar9003_hw_quick_drop_apply(s
int quick_drop;
s32 t[3], f[3] = {5180, 5500, 5785};
}
static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
-@@ -4035,7 +4037,7 @@ static void ar9003_hw_xlna_bias_strength
+@@ -4035,7 +4047,7 @@ static void ar9003_hw_xlna_bias_strength
struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
u8 bias;
return;
if (!AR_SREV_9300(ah))
+@@ -4109,6 +4121,37 @@ static void ar9003_hw_thermo_cal_apply(s
+ }
+ }
+
++static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah,
++ bool is2ghz)
++{
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = {
++ AR_PHY_CCA_CTRL_0,
++ AR_PHY_CCA_CTRL_1,
++ AR_PHY_CCA_CTRL_2,
++ };
++ int chain;
++ u32 val;
++
++ if (is2ghz) {
++ if (!(eep->base_ext1.misc_enable & BIT(2)))
++ return;
++ } else {
++ if (!(eep->base_ext1.misc_enable & BIT(3)))
++ return;
++ }
++
++ for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
++ if (!(ah->caps.tx_chainmask & BIT(chain)))
++ continue;
++
++ val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain];
++ REG_RMW_FIELD(ah, cca_ctrl[chain],
++ AR_PHY_EXT_CCA0_THRESH62_1, val);
++ }
++
++}
++
+ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+ {
+@@ -4120,9 +4163,10 @@ static void ath9k_hw_ar9300_set_board_va
+ ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
+ ar9003_hw_atten_apply(ah, chan);
+ ar9003_hw_quick_drop_apply(ah, chan->channel);
+- if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
++ if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
+ ar9003_hw_internal_regulator_apply(ah);
+ ar9003_hw_apply_tuning_caps(ah);
++ ar9003_hw_apply_minccapwr_thresh(ah, chan);
+ ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
+ ar9003_hw_thermometer_apply(ah);
+ ar9003_hw_thermo_cal_apply(ah);
--- a/net/mac80211/ieee80211_i.h
+++ b/net/mac80211/ieee80211_i.h
@@ -735,6 +735,7 @@ struct ieee80211_sub_if_data {
--- a/net/mac80211/ibss.c
+++ b/net/mac80211/ibss.c
-@@ -550,12 +550,12 @@ int ieee80211_ibss_finish_csa(struct iee
+@@ -534,7 +534,7 @@ int ieee80211_ibss_finish_csa(struct iee
+ int err;
+ u16 capability;
+
+- sdata_lock(sdata);
++ sdata_assert_lock(sdata);
+ /* update cfg80211 bss information with the new channel */
+ if (!is_zero_ether_addr(ifibss->bssid)) {
+ capability = WLAN_CAPABILITY_IBSS;
+@@ -550,16 +550,15 @@ int ieee80211_ibss_finish_csa(struct iee
capability);
/* XXX: should not really modify cfg80211 data */
if (cbss) {
/* generate the beacon */
err = ieee80211_ibss_csa_beacon(sdata, NULL);
-@@ -922,7 +922,7 @@ ieee80211_ibss_process_chanswitch(struct
+- sdata_unlock(sdata);
+ if (err < 0)
+ return err;
+
+@@ -922,7 +921,7 @@ ieee80211_ibss_process_chanswitch(struct
IEEE80211_MAX_QUEUE_MAP,
IEEE80211_QUEUE_STOP_REASON_CSA);
}
static int ath6kl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
+--- a/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
+@@ -20,6 +20,44 @@
+
+ /* AR9462 2.1 */
+
++#define ar9462_2p1_mac_postamble ar9462_2p0_mac_postamble
++
++#define ar9462_2p1_baseband_core ar9462_2p0_baseband_core
++
++#define ar9462_2p1_radio_core ar9462_2p0_radio_core
++
++#define ar9462_2p1_radio_postamble ar9462_2p0_radio_postamble
++
++#define ar9462_2p1_soc_postamble ar9462_2p0_soc_postamble
++
++#define ar9462_2p1_radio_postamble_sys2ant ar9462_2p0_radio_postamble_sys2ant
++
++#define ar9462_2p1_common_rx_gain ar9462_2p0_common_rx_gain
++
++#define ar9462_2p1_common_mixed_rx_gain ar9462_2p0_common_mixed_rx_gain
++
++#define ar9462_2p1_common_5g_xlna_only_rxgain ar9462_2p0_common_5g_xlna_only_rxgain
++
++#define ar9462_2p1_baseband_core_mix_rxgain ar9462_2p0_baseband_core_mix_rxgain
++
++#define ar9462_2p1_baseband_postamble_mix_rxgain ar9462_2p0_baseband_postamble_mix_rxgain
++
++#define ar9462_2p1_baseband_postamble_5g_xlna ar9462_2p0_baseband_postamble_5g_xlna
++
++#define ar9462_2p1_common_wo_xlna_rx_gain ar9462_2p0_common_wo_xlna_rx_gain
++
++#define ar9462_2p1_modes_low_ob_db_tx_gain ar9462_2p0_modes_low_ob_db_tx_gain
++
++#define ar9462_2p1_modes_high_ob_db_tx_gain ar9462_2p0_modes_high_ob_db_tx_gain
++
++#define ar9462_2p1_modes_mix_ob_db_tx_gain ar9462_2p0_modes_mix_ob_db_tx_gain
++
++#define ar9462_2p1_modes_fast_clock ar9462_2p0_modes_fast_clock
++
++#define ar9462_2p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
++
++#define ar9462_2p1_pciephy_clkreq_disable_L1 ar9462_2p0_pciephy_clkreq_disable_L1
++
+ static const u32 ar9462_2p1_mac_core[][2] = {
+ /* Addr allmodes */
+ {0x00000008, 0x00000000},
+@@ -183,168 +221,6 @@ static const u32 ar9462_2p1_mac_core[][2
+ {0x000083d0, 0x000301ff},
+ };
+
+-static const u32 ar9462_2p1_mac_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+- {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+- {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+- {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+- {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+- {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+- {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+-};
+-
+-static const u32 ar9462_2p1_baseband_core[][2] = {
+- /* Addr allmodes */
+- {0x00009800, 0xafe68e30},
+- {0x00009804, 0xfd14e000},
+- {0x00009808, 0x9c0a9f6b},
+- {0x0000980c, 0x04900000},
+- {0x00009814, 0x9280c00a},
+- {0x00009818, 0x00000000},
+- {0x0000981c, 0x00020028},
+- {0x00009834, 0x6400a290},
+- {0x00009838, 0x0108ecff},
+- {0x0000983c, 0x0d000600},
+- {0x00009880, 0x201fff00},
+- {0x00009884, 0x00001042},
+- {0x000098a4, 0x00200400},
+- {0x000098b0, 0x32440bbe},
+- {0x000098d0, 0x004b6a8e},
+- {0x000098d4, 0x00000820},
+- {0x000098dc, 0x00000000},
+- {0x000098e4, 0x01ffffff},
+- {0x000098e8, 0x01ffffff},
+- {0x000098ec, 0x01ffffff},
+- {0x000098f0, 0x00000000},
+- {0x000098f4, 0x00000000},
+- {0x00009bf0, 0x80000000},
+- {0x00009c04, 0xff55ff55},
+- {0x00009c08, 0x0320ff55},
+- {0x00009c0c, 0x00000000},
+- {0x00009c10, 0x00000000},
+- {0x00009c14, 0x00046384},
+- {0x00009c18, 0x05b6b440},
+- {0x00009c1c, 0x00b6b440},
+- {0x00009d00, 0xc080a333},
+- {0x00009d04, 0x40206c10},
+- {0x00009d08, 0x009c4060},
+- {0x00009d0c, 0x9883800a},
+- {0x00009d10, 0x01834061},
+- {0x00009d14, 0x00c0040b},
+- {0x00009d18, 0x00000000},
+- {0x00009e08, 0x0038230c},
+- {0x00009e24, 0x990bb515},
+- {0x00009e28, 0x0c6f0000},
+- {0x00009e30, 0x06336f77},
+- {0x00009e34, 0x6af6532f},
+- {0x00009e38, 0x0cc80c00},
+- {0x00009e40, 0x15262820},
+- {0x00009e4c, 0x00001004},
+- {0x00009e50, 0x00ff03f1},
+- {0x00009e54, 0xe4c555c2},
+- {0x00009e58, 0xfd857722},
+- {0x00009e5c, 0xe9198724},
+- {0x00009fc0, 0x803e4788},
+- {0x00009fc4, 0x0001efb5},
+- {0x00009fcc, 0x40000014},
+- {0x00009fd0, 0x0a193b93},
+- {0x0000a20c, 0x00000000},
+- {0x0000a220, 0x00000000},
+- {0x0000a224, 0x00000000},
+- {0x0000a228, 0x10002310},
+- {0x0000a23c, 0x00000000},
+- {0x0000a244, 0x0c000000},
+- {0x0000a2a0, 0x00000001},
+- {0x0000a2c0, 0x00000001},
+- {0x0000a2c8, 0x00000000},
+- {0x0000a2cc, 0x18c43433},
+- {0x0000a2d4, 0x00000000},
+- {0x0000a2ec, 0x00000000},
+- {0x0000a2f0, 0x00000000},
+- {0x0000a2f4, 0x00000000},
+- {0x0000a2f8, 0x00000000},
+- {0x0000a344, 0x00000000},
+- {0x0000a34c, 0x00000000},
+- {0x0000a350, 0x0000a000},
+- {0x0000a364, 0x00000000},
+- {0x0000a370, 0x00000000},
+- {0x0000a390, 0x00000001},
+- {0x0000a394, 0x00000444},
+- {0x0000a398, 0x001f0e0f},
+- {0x0000a39c, 0x0075393f},
+- {0x0000a3a0, 0xb79f6427},
+- {0x0000a3c0, 0x20202020},
+- {0x0000a3c4, 0x22222220},
+- {0x0000a3c8, 0x20200020},
+- {0x0000a3cc, 0x20202020},
+- {0x0000a3d0, 0x20202020},
+- {0x0000a3d4, 0x20202020},
+- {0x0000a3d8, 0x20202020},
+- {0x0000a3dc, 0x20202020},
+- {0x0000a3e0, 0x20202020},
+- {0x0000a3e4, 0x20202020},
+- {0x0000a3e8, 0x20202020},
+- {0x0000a3ec, 0x20202020},
+- {0x0000a3f0, 0x00000000},
+- {0x0000a3f4, 0x00000006},
+- {0x0000a3f8, 0x0c9bd380},
+- {0x0000a3fc, 0x000f0f01},
+- {0x0000a400, 0x8fa91f01},
+- {0x0000a404, 0x00000000},
+- {0x0000a408, 0x0e79e5c6},
+- {0x0000a40c, 0x00820820},
+- {0x0000a414, 0x1ce739ce},
+- {0x0000a418, 0x2d001dce},
+- {0x0000a434, 0x00000000},
+- {0x0000a438, 0x00001801},
+- {0x0000a43c, 0x00100000},
+- {0x0000a444, 0x00000000},
+- {0x0000a448, 0x05000080},
+- {0x0000a44c, 0x00000001},
+- {0x0000a450, 0x00010000},
+- {0x0000a454, 0x07000000},
+- {0x0000a644, 0xbfad9d74},
+- {0x0000a648, 0x0048060a},
+- {0x0000a64c, 0x00002037},
+- {0x0000a670, 0x03020100},
+- {0x0000a674, 0x09080504},
+- {0x0000a678, 0x0d0c0b0a},
+- {0x0000a67c, 0x13121110},
+- {0x0000a680, 0x31301514},
+- {0x0000a684, 0x35343332},
+- {0x0000a688, 0x00000036},
+- {0x0000a690, 0x00000838},
+- {0x0000a6b0, 0x0000000a},
+- {0x0000a6b4, 0x00512c01},
+- {0x0000a7c0, 0x00000000},
+- {0x0000a7c4, 0xfffffffc},
+- {0x0000a7c8, 0x00000000},
+- {0x0000a7cc, 0x00000000},
+- {0x0000a7d0, 0x00000000},
+- {0x0000a7d4, 0x00000004},
+- {0x0000a7dc, 0x00000000},
+- {0x0000a7f0, 0x80000000},
+- {0x0000a8d0, 0x004b6a8e},
+- {0x0000a8d4, 0x00000820},
+- {0x0000a8dc, 0x00000000},
+- {0x0000a8f0, 0x00000000},
+- {0x0000a8f4, 0x00000000},
+- {0x0000abf0, 0x80000000},
+- {0x0000b2d0, 0x00000080},
+- {0x0000b2d4, 0x00000000},
+- {0x0000b2ec, 0x00000000},
+- {0x0000b2f0, 0x00000000},
+- {0x0000b2f4, 0x00000000},
+- {0x0000b2f8, 0x00000000},
+- {0x0000b408, 0x0e79e5c0},
+- {0x0000b40c, 0x00820820},
+- {0x0000b420, 0x00000000},
+- {0x0000b6b0, 0x0000000a},
+- {0x0000b6b4, 0x00000001},
+-};
+-
+ static const u32 ar9462_2p1_baseband_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
+@@ -361,7 +237,7 @@ static const u32 ar9462_2p1_baseband_pos
+ {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e},
+ {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
+- {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
++ {0x00009e20, 0x000003a5, 0x000003a5, 0x000003a5, 0x000003a5},
+ {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
+ {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
+ {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
+@@ -400,1375 +276,16 @@ static const u32 ar9462_2p1_baseband_pos
+ {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000},
+ {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
+- {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
++ {0x0000ae20, 0x000001a6, 0x000001a6, 0x000001aa, 0x000001aa},
+ {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
+ };
+
+-static const u32 ar9462_2p1_radio_core[][2] = {
+- /* Addr allmodes */
+- {0x00016000, 0x36db6db6},
+- {0x00016004, 0x6db6db40},
+- {0x00016008, 0x73f00000},
+- {0x0001600c, 0x00000000},
+- {0x00016010, 0x6d820001},
+- {0x00016040, 0x7f80fff8},
+- {0x0001604c, 0x2699e04f},
+- {0x00016050, 0x6db6db6c},
+- {0x00016058, 0x6c200000},
+- {0x00016080, 0x000c0000},
+- {0x00016084, 0x9a68048c},
+- {0x00016088, 0x54214514},
+- {0x0001608c, 0x1203040b},
+- {0x00016090, 0x24926490},
+- {0x00016098, 0xd2888888},
+- {0x000160a0, 0x0a108ffe},
+- {0x000160a4, 0x812fc491},
+- {0x000160a8, 0x423c8000},
+- {0x000160b4, 0x92000000},
+- {0x000160b8, 0x0285dddc},
+- {0x000160bc, 0x02908888},
+- {0x000160c0, 0x00adb6d0},
+- {0x000160c4, 0x6db6db60},
+- {0x000160c8, 0x6db6db6c},
+- {0x000160cc, 0x0de6c1b0},
+- {0x00016100, 0x3fffbe04},
+- {0x00016104, 0xfff80000},
+- {0x00016108, 0x00200400},
+- {0x00016110, 0x00000000},
+- {0x00016144, 0x02084080},
+- {0x00016148, 0x000080c0},
+- {0x00016280, 0x050a0001},
+- {0x00016284, 0x3d841418},
+- {0x00016288, 0x00000000},
+- {0x0001628c, 0xe3000000},
+- {0x00016290, 0xa1005080},
+- {0x00016294, 0x00000020},
+- {0x00016298, 0x54a82900},
+- {0x00016340, 0x121e4276},
+- {0x00016344, 0x00300000},
+- {0x00016400, 0x36db6db6},
+- {0x00016404, 0x6db6db40},
+- {0x00016408, 0x73f00000},
+- {0x0001640c, 0x00000000},
+- {0x00016410, 0x6c800001},
+- {0x00016440, 0x7f80fff8},
+- {0x0001644c, 0x4699e04f},
+- {0x00016450, 0x6db6db6c},
+- {0x00016500, 0x3fffbe04},
+- {0x00016504, 0xfff80000},
+- {0x00016508, 0x00200400},
+- {0x00016510, 0x00000000},
+- {0x00016544, 0x02084080},
+- {0x00016548, 0x000080c0},
+-};
+-
+-static const u32 ar9462_2p1_radio_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
+- {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
+- {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
+- {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
+-};
+-
+ static const u32 ar9462_2p1_soc_preamble[][2] = {
+ /* Addr allmodes */
+- {0x000040a4, 0x00a0c1c9},
++ {0x000040a4, 0x00a0c9c9},
+ {0x00007020, 0x00000000},
+ {0x00007034, 0x00000002},
+ {0x00007038, 0x000004c2},
+ };
+
+-static const u32 ar9462_2p1_soc_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
+-};
+-
+-static const u32 ar9462_2p1_radio_postamble_sys2ant[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
+- {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
+- {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
+-};
+-
+-static const u32 ar9462_2p1_common_rx_gain[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x01910190},
+- {0x0000a030, 0x01930192},
+- {0x0000a034, 0x01950194},
+- {0x0000a038, 0x038a0196},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x22222229},
+- {0x0000a084, 0x1d1d1d1d},
+- {0x0000a088, 0x1d1d1d1d},
+- {0x0000a08c, 0x1d1d1d1d},
+- {0x0000a090, 0x171d1d1d},
+- {0x0000a094, 0x11111717},
+- {0x0000a098, 0x00030311},
+- {0x0000a09c, 0x00000000},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x2a2d2f32},
+- {0x0000b084, 0x21232328},
+- {0x0000b088, 0x19191c1e},
+- {0x0000b08c, 0x12141417},
+- {0x0000b090, 0x07070e0e},
+- {0x0000b094, 0x03030305},
+- {0x0000b098, 0x00000003},
+- {0x0000b09c, 0x00000000},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+-static const u32 ar9462_2p1_common_mixed_rx_gain[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x03820190},
+- {0x0000a030, 0x03840383},
+- {0x0000a034, 0x03880385},
+- {0x0000a038, 0x038a0389},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x29292929},
+- {0x0000a084, 0x29292929},
+- {0x0000a088, 0x29292929},
+- {0x0000a08c, 0x29292929},
+- {0x0000a090, 0x22292929},
+- {0x0000a094, 0x1d1d2222},
+- {0x0000a098, 0x0c111117},
+- {0x0000a09c, 0x00030303},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x2a2d2f32},
+- {0x0000b084, 0x21232328},
+- {0x0000b088, 0x19191c1e},
+- {0x0000b08c, 0x12141417},
+- {0x0000b090, 0x07070e0e},
+- {0x0000b094, 0x03030305},
+- {0x0000b098, 0x00000003},
+- {0x0000b09c, 0x00000000},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+-static const u32 ar9462_2p1_baseband_core_mix_rxgain[][2] = {
+- /* Addr allmodes */
+- {0x00009fd0, 0x0a2d6b93},
+-};
+-
+-static const u32 ar9462_2p1_baseband_postamble_mix_rxgain[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae},
+- {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da},
+- {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81},
+- {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8},
+- {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e},
+- {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e},
+-};
+-
+-static const u32 ar9462_2p1_baseband_postamble_5g_xlna[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
+-};
+-
+-static const u32 ar9462_2p1_common_wo_xlna_rx_gain[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x03820190},
+- {0x0000a030, 0x03840383},
+- {0x0000a034, 0x03880385},
+- {0x0000a038, 0x038a0389},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x29292929},
+- {0x0000a084, 0x29292929},
+- {0x0000a088, 0x29292929},
+- {0x0000a08c, 0x29292929},
+- {0x0000a090, 0x22292929},
+- {0x0000a094, 0x1d1d2222},
+- {0x0000a098, 0x0c111117},
+- {0x0000a09c, 0x00030303},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x32323232},
+- {0x0000b084, 0x2f2f3232},
+- {0x0000b088, 0x23282a2d},
+- {0x0000b08c, 0x1c1e2123},
+- {0x0000b090, 0x14171919},
+- {0x0000b094, 0x0e0e1214},
+- {0x0000b098, 0x03050707},
+- {0x0000b09c, 0x00030303},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+-static const u32 ar9462_2p1_common_5g_xlna_only_rx_gain[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x03820190},
+- {0x0000a030, 0x03840383},
+- {0x0000a034, 0x03880385},
+- {0x0000a038, 0x038a0389},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x29292929},
+- {0x0000a084, 0x29292929},
+- {0x0000a088, 0x29292929},
+- {0x0000a08c, 0x29292929},
+- {0x0000a090, 0x22292929},
+- {0x0000a094, 0x1d1d2222},
+- {0x0000a098, 0x0c111117},
+- {0x0000a09c, 0x00030303},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x2a2d2f32},
+- {0x0000b084, 0x21232328},
+- {0x0000b088, 0x19191c1e},
+- {0x0000b08c, 0x12141417},
+- {0x0000b090, 0x07070e0e},
+- {0x0000b094, 0x03030305},
+- {0x0000b098, 0x00000003},
+- {0x0000b09c, 0x00000000},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+-static const u32 ar9462_2p1_modes_low_ob_db_tx_gain[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+- {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+- {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+- {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
+- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
+- {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
+- {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
+- {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
+- {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
+- {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
+- {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
+- {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
+- {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
+- {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
+- {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
+- {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
+- {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
+- {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
+- {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
+- {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
+- {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
+- {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
+- {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
+- {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
+- {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+- {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
+- {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
+- {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
+- {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
+- {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
+- {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
+- {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
+- {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
+- {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
+- {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
+- {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+- {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+- {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
+- {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
+- {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
+- {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
+- {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
+- {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
+-};
+-
+-static const u32 ar9462_2p1_modes_high_ob_db_tx_gain[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+- {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+- {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+- {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de},
+- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
+- {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
+- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
+- {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
+- {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
+- {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
+- {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
+- {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
+- {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
+- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
+- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
+- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
+- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
+- {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81},
+- {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83},
+- {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84},
+- {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
+- {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
+- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
+- {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
+- {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec},
+- {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0},
+- {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4},
+- {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
+- {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
+- {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
+- {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
+- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
+- {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
+- {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
+- {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
+- {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
+- {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
+- {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
+- {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+- {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+- {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
+- {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060},
+- {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
+- {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
+- {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
+- {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
+-};
+-
+-static const u32 ar9462_2p1_modes_mix_ob_db_tx_gain[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+- {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+- {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+- {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de},
+- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400},
+- {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402},
+- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
+- {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603},
+- {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02},
+- {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04},
+- {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20},
+- {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20},
+- {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22},
+- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24},
+- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640},
+- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660},
+- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861},
+- {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81},
+- {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83},
+- {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84},
+- {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3},
+- {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5},
+- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9},
+- {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb},
+- {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec},
+- {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0},
+- {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4},
+- {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
+- {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
+- {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
+- {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
+- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
+- {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
+- {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
+- {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
+- {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
+- {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
+- {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
+- {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+- {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+- {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+-};
+-
+-static const u32 ar9462_2p1_modes_fast_clock[][3] = {
+- /* Addr 5G_HT20 5G_HT40 */
+- {0x00001030, 0x00000268, 0x000004d0},
+- {0x00001070, 0x0000018c, 0x00000318},
+- {0x000010b0, 0x00000fd0, 0x00001fa0},
+- {0x00008014, 0x044c044c, 0x08980898},
+- {0x0000801c, 0x148ec02b, 0x148ec057},
+- {0x00008318, 0x000044c0, 0x00008980},
+- {0x00009e00, 0x0372131c, 0x0372131c},
+- {0x0000a230, 0x0000400b, 0x00004016},
+- {0x0000a254, 0x00000898, 0x00001130},
+-};
+-
+-static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = {
+- /* Addr allmodes */
+- {0x0000a398, 0x00000000},
+- {0x0000a39c, 0x6f7f0301},
+- {0x0000a3a0, 0xca9228ee},
+-};
+-
+ #endif /* INITVALS_9462_2P1_H */
+--- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
+@@ -20,24 +20,11 @@
+
+ /* AR9485 1.1 */
+
+-static const u32 ar9485_1_1_mac_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+- {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+- {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+- {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+- {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+- {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+- {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+-};
++#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1
+
+-static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x18012e5e},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0000080c},
+-};
++#define ar9485_1_1_mac_postamble ar9331_1p1_mac_postamble
++
++#define ar9485_1_1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
+
+ static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
+ /* Addr allmodes */
+@@ -553,100 +540,6 @@ static const u32 ar9485Modes_low_ob_db_t
+ {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+ };
+
+-static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+- {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0x7999a83a, 0x7999a83a},
+- {0x0000a2dc, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
+- {0x0000a2e0, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
+- {0x0000a2e4, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
+- {0x0000a2e8, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+- {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+- {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+- {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+- {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+- {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+- {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+- {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+- {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+- {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+- {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
+- {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
+- {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
+- {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
+- {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
+- {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
+- {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
+- {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
+- {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
+- {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
+- {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
+- {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
+- {0x0000a580, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a584, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a588, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a58c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a590, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a594, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a598, 0x00000000, 0x00000000, 0x01404501, 0x01404501},
+- {0x0000a59c, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
+- {0x0000a5a0, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
+- {0x0000a5a4, 0x00000000, 0x00000000, 0x02808803, 0x02808803},
+- {0x0000a5a8, 0x00000000, 0x00000000, 0x04c14b04, 0x04c14b04},
+- {0x0000a5ac, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
+- {0x0000a5b0, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
+- {0x0000a5b4, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
+- {0x0000a5b8, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
+- {0x0000a5bc, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
+- {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
+- {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
+-};
+-
+ static const u32 ar9485Modes_green_spur_ob_db_tx_gain_1_1[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
+@@ -1101,20 +994,6 @@ static const u32 ar9485_common_rx_gain_1
+ {0x0000a1fc, 0x00000296},
+ };
+
+-static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x18052e5e},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0000080c},
+-};
+-
+-static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x18053e5e},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0000080c},
+-};
+-
+ static const u32 ar9485_1_1_soc_preamble[][2] = {
+ /* Addr allmodes */
+ {0x00004014, 0xba280400},
+@@ -1173,13 +1052,6 @@ static const u32 ar9485_1_1_baseband_pos
+ {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ };
+
+-static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x18013e5e},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0000080c},
+-};
+-
+ static const u32 ar9485_1_1_radio_postamble[][2] = {
+ /* Addr allmodes */
+ {0x0001609c, 0x0b283f31},
+@@ -1351,11 +1223,18 @@ static const u32 ar9485_1_1_mac_core[][2
+ {0x000083d0, 0x000301ff},
+ };
+
+-static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
++static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
+ /* Addr allmodes */
+- {0x0000a398, 0x00000000},
+- {0x0000a39c, 0x6f7f0301},
+- {0x0000a3a0, 0xca9228ee},
++ {0x00018c00, 0x18013e5e},
++ {0x00018c04, 0x000801d8},
++ {0x00018c08, 0x0000080c},
++};
++
++static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
++ /* Addr allmodes */
++ {0x00018c00, 0x1801265e},
++ {0x00018c04, 0x000801d8},
++ {0x00018c08, 0x0000080c},
+ };
+
+ #endif /* INITVALS_9485_H */
+--- a/drivers/net/wireless/ath/ath9k/pci.c
++++ b/drivers/net/wireless/ath/ath9k/pci.c
+@@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
+ 0x3219),
+ .driver_data = ATH9K_PCI_BT_ANT_DIV },
+
++ /* AR9485 cards with PLL power-save disabled by default. */
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_AZWAVE,
++ 0x2C97),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_AZWAVE,
++ 0x2100),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ 0x1C56, /* ASKEY */
++ 0x4001),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ 0x11AD, /* LITEON */
++ 0x6627),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ 0x11AD, /* LITEON */
++ 0x6628),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_FOXCONN,
++ 0xE04E),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_FOXCONN,
++ 0xE04F),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ 0x144F, /* ASKEY */
++ 0x7197),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ 0x1B9A, /* XAVI */
++ 0x2000),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ 0x1B9A, /* XAVI */
++ 0x2001),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_AZWAVE,
++ 0x1186),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_AZWAVE,
++ 0x1F86),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_AZWAVE,
++ 0x1195),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_AZWAVE,
++ 0x1F95),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ 0x1B9A, /* XAVI */
++ 0x1C00),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ 0x1B9A, /* XAVI */
++ 0x1C01),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
++ 0x0032,
++ PCI_VENDOR_ID_ASUSTEK,
++ 0x850D),
++ .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
++
+ { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
+ { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
+
+--- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
+@@ -20,7 +20,15 @@
+
+ /* AR9462 2.0 */
+
+-static const u32 ar9462_modes_fast_clock_2p0[][3] = {
++#define ar9462_2p0_mac_postamble ar9331_1p1_mac_postamble
++
++#define ar9462_2p0_common_wo_xlna_rx_gain ar9300Common_wo_xlna_rx_gain_table_2p2
++
++#define ar9462_2p0_common_5g_xlna_only_rxgain ar9462_2p0_common_mixed_rx_gain
++
++#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
++
++static const u32 ar9462_2p0_modes_fast_clock[][3] = {
+ /* Addr 5G_HT20 5G_HT40 */
+ {0x00001030, 0x00000268, 0x000004d0},
+ {0x00001070, 0x0000018c, 0x00000318},
+@@ -33,13 +41,6 @@ static const u32 ar9462_modes_fast_clock
+ {0x0000a254, 0x00000898, 0x00001130},
+ };
+
+-static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x18253ede},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0003780c},
+-};
+-
+ static const u32 ar9462_2p0_baseband_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
+@@ -99,7 +100,7 @@ static const u32 ar9462_2p0_baseband_pos
+ {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
+ };
+
+-static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
++static const u32 ar9462_2p0_common_rx_gain[][2] = {
+ /* Addr allmodes */
+ {0x0000a000, 0x00010000},
+ {0x0000a004, 0x00030002},
+@@ -359,20 +360,13 @@ static const u32 ar9462_common_rx_gain_t
+ {0x0000b1fc, 0x00000196},
+ };
+
+-static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
++static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = {
+ /* Addr allmodes */
+ {0x00018c00, 0x18213ede},
+ {0x00018c04, 0x000801d8},
+ {0x00018c08, 0x0003780c},
+ };
+
+-static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x18212ede},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0003780c},
+-};
+-
+ static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
+@@ -380,348 +374,81 @@ static const u32 ar9462_2p0_radio_postam
+ {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
+ };
+
+-static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x03820190},
+- {0x0000a030, 0x03840383},
+- {0x0000a034, 0x03880385},
+- {0x0000a038, 0x038a0389},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x29292929},
+- {0x0000a084, 0x29292929},
+- {0x0000a088, 0x29292929},
+- {0x0000a08c, 0x29292929},
+- {0x0000a090, 0x22292929},
+- {0x0000a094, 0x1d1d2222},
+- {0x0000a098, 0x0c111117},
+- {0x0000a09c, 0x00030303},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x32323232},
+- {0x0000b084, 0x2f2f3232},
+- {0x0000b088, 0x23282a2d},
+- {0x0000b08c, 0x1c1e2123},
+- {0x0000b090, 0x14171919},
+- {0x0000b094, 0x0e0e1214},
+- {0x0000b098, 0x03050707},
+- {0x0000b09c, 0x00030303},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+-static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
+- /* Addr allmodes */
+- {0x0000a398, 0x00000000},
+- {0x0000a39c, 0x6f7f0301},
+- {0x0000a3a0, 0xca9228ee},
+-};
+-
+-static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+- {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+- {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+- {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+- {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
+- {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
+- {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
+- {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
+- {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
+- {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
+- {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
+- {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
+- {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
+- {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
+- {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
+- {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
+- {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
+- {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
+- {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
+- {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
+- {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
+- {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
+- {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
+- {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
+- {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
+- {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+- {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
+- {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
+- {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
+- {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
+- {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
+- {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
+- {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
+- {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
+- {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
+- {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
+- {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+- {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+- {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
+- {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
+- {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
+- {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
+- {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
+- {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
+- {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
+-};
+-
+-static const u32 ar9462_2p0_soc_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
+-};
+-
+-static const u32 ar9462_2p0_baseband_core[][2] = {
++static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
++ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
++ {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
++ {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
++ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
++ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
++ {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
++ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
++ {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
++ {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
++ {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
++ {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
++ {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
++ {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
++ {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
++ {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
++ {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
++ {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
++ {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
++ {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
++ {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
++ {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
++ {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
++ {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
++ {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
++ {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
++ {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
++ {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
++ {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
++ {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
++ {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
++ {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
++ {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
++ {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
++ {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
++ {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
++ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
++ {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
++ {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
++ {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
++ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
++ {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
++ {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
++ {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
++ {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
++ {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
++ {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
++ {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
++ {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
++ {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
++ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
++ {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
++ {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
++ {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
++ {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
++ {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
++ {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
++};
++
++static const u32 ar9462_2p0_soc_postamble[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
++};
++
++static const u32 ar9462_2p0_baseband_core[][2] = {
+ /* Addr allmodes */
+ {0x00009800, 0xafe68e30},
+ {0x00009804, 0xfd14e000},
+@@ -879,7 +606,7 @@ static const u32 ar9462_2p0_radio_postam
+ {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
+ };
+
+-static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = {
++static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+ {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+@@ -942,7 +669,7 @@ static const u32 ar9462_modes_mix_ob_db_
+ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+ };
+
+-static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
++static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
+ {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
+@@ -1240,19 +967,7 @@ static const u32 ar9462_2p0_mac_core[][2
+ {0x000083d0, 0x000301ff},
+ };
+
+-static const u32 ar9462_2p0_mac_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+- {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+- {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+- {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+- {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+- {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+- {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+-};
+-
+-static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
++static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = {
+ /* Addr allmodes */
+ {0x0000a000, 0x00010000},
+ {0x0000a004, 0x00030002},
+@@ -1517,266 +1232,6 @@ static const u32 ar9462_2p0_baseband_pos
+ {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
+ };
+
+-static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x03820190},
+- {0x0000a030, 0x03840383},
+- {0x0000a034, 0x03880385},
+- {0x0000a038, 0x038a0389},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x29292929},
+- {0x0000a084, 0x29292929},
+- {0x0000a088, 0x29292929},
+- {0x0000a08c, 0x29292929},
+- {0x0000a090, 0x22292929},
+- {0x0000a094, 0x1d1d2222},
+- {0x0000a098, 0x0c111117},
+- {0x0000a09c, 0x00030303},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x2a2d2f32},
+- {0x0000b084, 0x21232328},
+- {0x0000b088, 0x19191c1e},
+- {0x0000b08c, 0x12141417},
+- {0x0000b090, 0x07070e0e},
+- {0x0000b094, 0x03030305},
+- {0x0000b098, 0x00000003},
+- {0x0000b09c, 0x00000000},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+ static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] = {
+ /* Addr allmodes */
+ {0x00009fd0, 0x0a2d6b93},
+--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+@@ -303,7 +303,7 @@ static const u32 ar9300_2p2_mac_postambl
+ {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+ {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+ {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
++ {0x00008120, 0x18f04800, 0x18f04800, 0x18f04810, 0x18f04810},
+ {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+ {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+ };
+@@ -352,7 +352,7 @@ static const u32 ar9300_2p2_baseband_pos
+ {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
+ {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
+ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+- {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
++ {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
+ {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
+ {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
+@@ -378,9 +378,9 @@ static const u32 ar9300_2p2_baseband_cor
+ {0x00009814, 0x9280c00a},
+ {0x00009818, 0x00000000},
+ {0x0000981c, 0x00020028},
+- {0x00009834, 0x6400a290},
++ {0x00009834, 0x6400a190},
+ {0x00009838, 0x0108ecff},
+- {0x0000983c, 0x0d000600},
++ {0x0000983c, 0x14000600},
+ {0x00009880, 0x201fff00},
+ {0x00009884, 0x00001042},
+ {0x000098a4, 0x00200400},
+@@ -401,7 +401,7 @@ static const u32 ar9300_2p2_baseband_cor
+ {0x00009d04, 0x40206c10},
+ {0x00009d08, 0x009c4060},
+ {0x00009d0c, 0x9883800a},
+- {0x00009d10, 0x01834061},
++ {0x00009d10, 0x01884061},
+ {0x00009d14, 0x00c0040b},
+ {0x00009d18, 0x00000000},
+ {0x00009e08, 0x0038230c},
+@@ -459,7 +459,7 @@ static const u32 ar9300_2p2_baseband_cor
+ {0x0000a3e8, 0x20202020},
+ {0x0000a3ec, 0x20202020},
+ {0x0000a3f0, 0x00000000},
+- {0x0000a3f4, 0x00000246},
++ {0x0000a3f4, 0x00000000},
+ {0x0000a3f8, 0x0c9bd380},
+ {0x0000a3fc, 0x000f0f01},
+ {0x0000a400, 0x8fa91f01},
+@@ -534,107 +534,107 @@ static const u32 ar9300_2p2_baseband_cor
+
+ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+- {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+- {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
++ {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
++ {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
++ {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
+ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
+- {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+- {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
+- {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
+- {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
+- {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
+- {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
+- {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
+- {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
+- {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
+- {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
+- {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
+- {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
+- {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
+- {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
+- {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
+- {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
+- {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
+- {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
+- {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
+- {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
+- {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
+- {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
+- {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+- {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+- {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+- {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+- {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+- {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+- {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+- {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
+- {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
+- {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
+- {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
+- {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
+- {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
+- {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
+- {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
+- {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
+- {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
+- {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
+- {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
+- {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
+- {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
+- {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
+- {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
+- {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
+- {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
+- {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
+- {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
+- {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
+- {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
+- {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
+- {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
+- {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
+- {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+- {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+- {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+- {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+- {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+- {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+- {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
++ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
++ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
++ {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
++ {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
++ {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
++ {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
++ {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
++ {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
++ {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
++ {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
++ {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
++ {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
++ {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
++ {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
++ {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
++ {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
++ {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
++ {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
++ {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
++ {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
++ {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
++ {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
++ {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
++ {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
++ {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
++ {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
++ {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
++ {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
++ {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
++ {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
++ {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
++ {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
++ {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
++ {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
++ {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
++ {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
++ {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
++ {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
++ {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
++ {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
++ {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
++ {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
++ {0x0000a5cc, 0x5e88442e, 0x5e88442e, 0x47801a83, 0x47801a83},
++ {0x0000a5d0, 0x628a4431, 0x628a4431, 0x4a801c84, 0x4a801c84},
++ {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
++ {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
++ {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
++ {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
++ {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
+ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
+- {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
+- {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
+- {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
+- {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
+- {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
+- {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
+- {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
+- {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+- {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+- {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
++ {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
++ {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
++ {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
++ {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
++ {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
++ {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
++ {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
++ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
++ {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
++ {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
++ {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
++ {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
+ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+- {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
+- {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
++ {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
++ {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
++ {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
+ {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+ {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
+- {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
++ {0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
+ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+ {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
+- {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
++ {0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
+ {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+ {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
+- {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
++ {0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
+ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+ };
+
+@@ -644,7 +644,7 @@ static const u32 ar9300Modes_high_ob_db_
+ {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
+ {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
+ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
+- {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
++ {0x0000a410, 0x000050d4, 0x000050d4, 0x000050d9, 0x000050d9},
+ {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+ {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
+ {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
+@@ -1086,8 +1086,8 @@ static const u32 ar9300Common_rx_gain_ta
+ {0x0000b074, 0x00000000},
+ {0x0000b078, 0x00000000},
+ {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x2a2d2f32},
+- {0x0000b084, 0x21232328},
++ {0x0000b080, 0x23232323},
++ {0x0000b084, 0x21232323},
+ {0x0000b088, 0x19191c1e},
+ {0x0000b08c, 0x12141417},
+ {0x0000b090, 0x07070e0e},
+@@ -1385,9 +1385,9 @@ static const u32 ar9300_2p2_mac_core[][2
+ {0x000081f8, 0x00000000},
+ {0x000081fc, 0x00000000},
+ {0x00008240, 0x00100000},
+- {0x00008244, 0x0010f424},
++ {0x00008244, 0x0010f400},
+ {0x00008248, 0x00000800},
+- {0x0000824c, 0x0001e848},
++ {0x0000824c, 0x0001e800},
+ {0x00008250, 0x00000000},
+ {0x00008254, 0x00000000},
+ {0x00008258, 0x00000000},
+@@ -1726,16 +1726,30 @@ static const u32 ar9300PciePhy_pll_on_cl
+
+ static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
+ /* Addr allmodes */
+- {0x00004040, 0x08253e5e},
++ {0x00004040, 0x0825365e},
+ {0x00004040, 0x0008003b},
+ {0x00004044, 0x00000000},
+ };
+
+ static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
+ /* Addr allmodes */
+- {0x00004040, 0x08213e5e},
++ {0x00004040, 0x0821365e},
+ {0x00004040, 0x0008003b},
+ {0x00004044, 0x00000000},
+ };
+
++static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
++ /* Addr allmodes */
++ {0x0000a398, 0x00000000},
++ {0x0000a39c, 0x6f7f0301},
++ {0x0000a3a0, 0xca9228ee},
++};
++
++static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = {
++ /* Addr 5G 2G */
++ {0x00009824, 0x5ac668d0, 0x5ac668d0},
++ {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
++ {0x00009e14, 0x37b9625e, 0x37b9625e},
++};
++
+ #endif /* INITVALS_9003_2P2_H */
+--- /dev/null
++++ b/drivers/net/wireless/ath/ath9k/ar9565_1p1_initvals.h
+@@ -0,0 +1,64 @@
++/*
++ * Copyright (c) 2010-2011 Atheros Communications Inc.
++ * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef INITVALS_9565_1P1_H
++#define INITVALS_9565_1P1_H
++
++/* AR9565 1.1 */
++
++#define ar9565_1p1_mac_core ar9565_1p0_mac_core
++
++#define ar9565_1p1_mac_postamble ar9565_1p0_mac_postamble
++
++#define ar9565_1p1_baseband_core ar9565_1p0_baseband_core
++
++#define ar9565_1p1_baseband_postamble ar9565_1p0_baseband_postamble
++
++#define ar9565_1p1_radio_core ar9565_1p0_radio_core
++
++#define ar9565_1p1_soc_preamble ar9565_1p0_soc_preamble
++
++#define ar9565_1p1_soc_postamble ar9565_1p0_soc_postamble
++
++#define ar9565_1p1_Common_rx_gain_table ar9565_1p0_Common_rx_gain_table
++
++#define ar9565_1p1_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_Modes_lowest_ob_db_tx_gain_table
++
++#define ar9565_1p1_pciephy_clkreq_disable_L1 ar9565_1p0_pciephy_clkreq_disable_L1
++
++#define ar9565_1p1_modes_fast_clock ar9565_1p0_modes_fast_clock
++
++#define ar9565_1p1_common_wo_xlna_rx_gain_table ar9565_1p0_common_wo_xlna_rx_gain_table
++
++#define ar9565_1p1_modes_low_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
++
++#define ar9565_1p1_modes_high_ob_db_tx_gain_table ar9565_1p0_modes_high_ob_db_tx_gain_table
++
++#define ar9565_1p1_modes_high_power_tx_gain_table ar9565_1p0_modes_high_power_tx_gain_table
++
++#define ar9565_1p1_baseband_core_txfir_coeff_japan_2484 ar9565_1p0_baseband_core_txfir_coeff_japan_2484
++
++static const u32 ar9565_1p1_radio_postamble[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
++ {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
++ {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
++ {0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000},
++ {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
++};
++
++#endif /* INITVALS_9565_1P1_H */
+--- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
+@@ -20,18 +20,34 @@
+
+ /* AR9580 1.0 */
+
++#define ar9580_1p0_soc_preamble ar9300_2p2_soc_preamble
++
++#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
++
++#define ar9580_1p0_radio_core ar9300_2p2_radio_core
++
++#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
++
++#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
++
++#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
++
++#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
++
+ #define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
+
++#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
++
+ static const u32 ar9580_1p0_radio_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
+ {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
+ {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
+- {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
+ {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
+- {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
+ {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
+- {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
+ {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
+ };
+
+@@ -41,12 +57,10 @@ static const u32 ar9580_1p0_baseband_cor
+ {0x00009804, 0xfd14e000},
+ {0x00009808, 0x9c0a9f6b},
+ {0x0000980c, 0x04900000},
+- {0x00009814, 0x3280c00a},
+- {0x00009818, 0x00000000},
+ {0x0000981c, 0x00020028},
+- {0x00009834, 0x6400a290},
++ {0x00009834, 0x6400a190},
+ {0x00009838, 0x0108ecff},
+- {0x0000983c, 0x0d000600},
++ {0x0000983c, 0x14000600},
+ {0x00009880, 0x201fff00},
+ {0x00009884, 0x00001042},
+ {0x000098a4, 0x00200400},
+@@ -67,7 +81,7 @@ static const u32 ar9580_1p0_baseband_cor
+ {0x00009d04, 0x40206c10},
+ {0x00009d08, 0x009c4060},
+ {0x00009d0c, 0x9883800a},
+- {0x00009d10, 0x01834061},
++ {0x00009d10, 0x01884061},
+ {0x00009d14, 0x00c0040b},
+ {0x00009d18, 0x00000000},
+ {0x00009e08, 0x0038230c},
+@@ -198,8 +212,6 @@ static const u32 ar9580_1p0_baseband_cor
+ {0x0000c420, 0x00000000},
+ };
+
+-#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
+-
+ static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
+@@ -306,7 +318,112 @@ static const u32 ar9580_1p0_low_ob_db_tx
+ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+ };
+
+-#define ar9580_1p0_high_power_tx_gain_table ar9580_1p0_low_ob_db_tx_gain_table
++static const u32 ar9580_1p0_high_power_tx_gain_table[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
++ {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
++ {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
++ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
++ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
++ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
++ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
++ {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
++ {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
++ {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
++ {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
++ {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
++ {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
++ {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
++ {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
++ {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
++ {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
++ {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
++ {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
++ {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
++ {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
++ {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
++ {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
++ {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
++ {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
++ {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
++ {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
++ {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
++ {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
++ {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
++ {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
++ {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
++ {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
++ {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
++ {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
++ {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
++ {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
++ {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
++ {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
++ {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
++ {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
++ {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
++ {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
++ {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
++ {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
++ {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
++ {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
++ {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
++ {0x0000a5cc, 0x5a88442e, 0x5a88442e, 0x47801a83, 0x47801a83},
++ {0x0000a5d0, 0x5e8a4431, 0x5e8a4431, 0x4a801c84, 0x4a801c84},
++ {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
++ {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
++ {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
++ {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
++ {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
++ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
++ {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
++ {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
++ {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
++ {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
++ {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
++ {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
++ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
++ {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
++ {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
++ {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
++ {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
++ {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
++ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
++ {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
++ {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
++ {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
++ {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
++ {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
++ {0x00016048, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
++ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
++ {0x00016288, 0x05a2040a, 0x05a2040a, 0x05a20408, 0x05a20408},
++ {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
++ {0x00016448, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
++ {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
++ {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
++ {0x00016848, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
++ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
++};
+
+ static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+@@ -414,8 +531,6 @@ static const u32 ar9580_1p0_lowest_ob_db
+ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+ };
+
+-#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
+-
+ static const u32 ar9580_1p0_mac_core[][2] = {
+ /* Addr allmodes */
+ {0x00000008, 0x00000000},
+@@ -679,14 +794,6 @@ static const u32 ar9580_1p0_mixed_ob_db_
+ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+ };
+
+-#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
+-
+-#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
+-
+-#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
+-
+-#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
+-
+ static const u32 ar9580_1p0_type6_tx_gain_table[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
+@@ -761,165 +868,271 @@ static const u32 ar9580_1p0_type6_tx_gai
+ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+ };
+
+-static const u32 ar9580_1p0_soc_preamble[][2] = {
++static const u32 ar9580_1p0_rx_gain_table[][2] = {
+ /* Addr allmodes */
+- {0x000040a4, 0x00a0c1c9},
+- {0x00007008, 0x00000000},
+- {0x00007020, 0x00000000},
+- {0x00007034, 0x00000002},
+- {0x00007038, 0x000004c2},
+- {0x00007048, 0x00000008},
+-};
+-
+-#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0
+-
+-static const u32 ar9580_1p0_radio_core[][2] = {
+- /* Addr allmodes */
+- {0x00016000, 0x36db6db6},
+- {0x00016004, 0x6db6db40},
+- {0x00016008, 0x73f00000},
+- {0x0001600c, 0x00000000},
+- {0x00016040, 0x7f80fff8},
+- {0x0001604c, 0x76d005b5},
+- {0x00016050, 0x556cf031},
+- {0x00016054, 0x13449440},
+- {0x00016058, 0x0c51c92c},
+- {0x0001605c, 0x3db7fffc},
+- {0x00016060, 0xfffffffc},
+- {0x00016064, 0x000f0278},
+- {0x0001606c, 0x6db60000},
+- {0x00016080, 0x00000000},
+- {0x00016084, 0x0e48048c},
+- {0x00016088, 0x54214514},
+- {0x0001608c, 0x119f481e},
+- {0x00016090, 0x24926490},
+- {0x00016098, 0xd2888888},
+- {0x000160a0, 0x0a108ffe},
+- {0x000160a4, 0x812fc370},
+- {0x000160a8, 0x423c8000},
+- {0x000160b4, 0x92480080},
+- {0x000160c0, 0x00adb6d0},
+- {0x000160c4, 0x6db6db60},
+- {0x000160c8, 0x6db6db6c},
+- {0x000160cc, 0x01e6c000},
+- {0x00016100, 0x3fffbe01},
+- {0x00016104, 0xfff80000},
+- {0x00016108, 0x00080010},
+- {0x00016144, 0x02084080},
+- {0x00016148, 0x00000000},
+- {0x00016280, 0x058a0001},
+- {0x00016284, 0x3d840208},
+- {0x00016288, 0x05a20408},
+- {0x0001628c, 0x00038c07},
+- {0x00016290, 0x00000004},
+- {0x00016294, 0x458aa14f},
+- {0x00016380, 0x00000000},
+- {0x00016384, 0x00000000},
+- {0x00016388, 0x00800700},
+- {0x0001638c, 0x00800700},
+- {0x00016390, 0x00800700},
+- {0x00016394, 0x00000000},
+- {0x00016398, 0x00000000},
+- {0x0001639c, 0x00000000},
+- {0x000163a0, 0x00000001},
+- {0x000163a4, 0x00000001},
+- {0x000163a8, 0x00000000},
+- {0x000163ac, 0x00000000},
+- {0x000163b0, 0x00000000},
+- {0x000163b4, 0x00000000},
+- {0x000163b8, 0x00000000},
+- {0x000163bc, 0x00000000},
+- {0x000163c0, 0x000000a0},
+- {0x000163c4, 0x000c0000},
+- {0x000163c8, 0x14021402},
+- {0x000163cc, 0x00001402},
+- {0x000163d0, 0x00000000},
+- {0x000163d4, 0x00000000},
+- {0x00016400, 0x36db6db6},
+- {0x00016404, 0x6db6db40},
+- {0x00016408, 0x73f00000},
+- {0x0001640c, 0x00000000},
+- {0x00016440, 0x7f80fff8},
+- {0x0001644c, 0x76d005b5},
+- {0x00016450, 0x556cf031},
+- {0x00016454, 0x13449440},
+- {0x00016458, 0x0c51c92c},
+- {0x0001645c, 0x3db7fffc},
+- {0x00016460, 0xfffffffc},
+- {0x00016464, 0x000f0278},
+- {0x0001646c, 0x6db60000},
+- {0x00016500, 0x3fffbe01},
+- {0x00016504, 0xfff80000},
+- {0x00016508, 0x00080010},
+- {0x00016544, 0x02084080},
+- {0x00016548, 0x00000000},
+- {0x00016780, 0x00000000},
+- {0x00016784, 0x00000000},
+- {0x00016788, 0x00800700},
+- {0x0001678c, 0x00800700},
+- {0x00016790, 0x00800700},
+- {0x00016794, 0x00000000},
+- {0x00016798, 0x00000000},
+- {0x0001679c, 0x00000000},
+- {0x000167a0, 0x00000001},
+- {0x000167a4, 0x00000001},
+- {0x000167a8, 0x00000000},
+- {0x000167ac, 0x00000000},
+- {0x000167b0, 0x00000000},
+- {0x000167b4, 0x00000000},
+- {0x000167b8, 0x00000000},
+- {0x000167bc, 0x00000000},
+- {0x000167c0, 0x000000a0},
+- {0x000167c4, 0x000c0000},
+- {0x000167c8, 0x14021402},
+- {0x000167cc, 0x00001402},
+- {0x000167d0, 0x00000000},
+- {0x000167d4, 0x00000000},
+- {0x00016800, 0x36db6db6},
+- {0x00016804, 0x6db6db40},
+- {0x00016808, 0x73f00000},
+- {0x0001680c, 0x00000000},
+- {0x00016840, 0x7f80fff8},
+- {0x0001684c, 0x76d005b5},
+- {0x00016850, 0x556cf031},
+- {0x00016854, 0x13449440},
+- {0x00016858, 0x0c51c92c},
+- {0x0001685c, 0x3db7fffc},
+- {0x00016860, 0xfffffffc},
+- {0x00016864, 0x000f0278},
+- {0x0001686c, 0x6db60000},
+- {0x00016900, 0x3fffbe01},
+- {0x00016904, 0xfff80000},
+- {0x00016908, 0x00080010},
+- {0x00016944, 0x02084080},
+- {0x00016948, 0x00000000},
+- {0x00016b80, 0x00000000},
+- {0x00016b84, 0x00000000},
+- {0x00016b88, 0x00800700},
+- {0x00016b8c, 0x00800700},
+- {0x00016b90, 0x00800700},
+- {0x00016b94, 0x00000000},
+- {0x00016b98, 0x00000000},
+- {0x00016b9c, 0x00000000},
+- {0x00016ba0, 0x00000001},
+- {0x00016ba4, 0x00000001},
+- {0x00016ba8, 0x00000000},
+- {0x00016bac, 0x00000000},
+- {0x00016bb0, 0x00000000},
+- {0x00016bb4, 0x00000000},
+- {0x00016bb8, 0x00000000},
+- {0x00016bbc, 0x00000000},
+- {0x00016bc0, 0x000000a0},
+- {0x00016bc4, 0x000c0000},
+- {0x00016bc8, 0x14021402},
+- {0x00016bcc, 0x00001402},
+- {0x00016bd0, 0x00000000},
+- {0x00016bd4, 0x00000000},
++ {0x0000a000, 0x00010000},
++ {0x0000a004, 0x00030002},
++ {0x0000a008, 0x00050004},
++ {0x0000a00c, 0x00810080},
++ {0x0000a010, 0x00830082},
++ {0x0000a014, 0x01810180},
++ {0x0000a018, 0x01830182},
++ {0x0000a01c, 0x01850184},
++ {0x0000a020, 0x01890188},
++ {0x0000a024, 0x018b018a},
++ {0x0000a028, 0x018d018c},
++ {0x0000a02c, 0x01910190},
++ {0x0000a030, 0x01930192},
++ {0x0000a034, 0x01950194},
++ {0x0000a038, 0x038a0196},
++ {0x0000a03c, 0x038c038b},
++ {0x0000a040, 0x0390038d},
++ {0x0000a044, 0x03920391},
++ {0x0000a048, 0x03940393},
++ {0x0000a04c, 0x03960395},
++ {0x0000a050, 0x00000000},
++ {0x0000a054, 0x00000000},
++ {0x0000a058, 0x00000000},
++ {0x0000a05c, 0x00000000},
++ {0x0000a060, 0x00000000},
++ {0x0000a064, 0x00000000},
++ {0x0000a068, 0x00000000},
++ {0x0000a06c, 0x00000000},
++ {0x0000a070, 0x00000000},
++ {0x0000a074, 0x00000000},
++ {0x0000a078, 0x00000000},
++ {0x0000a07c, 0x00000000},
++ {0x0000a080, 0x22222229},
++ {0x0000a084, 0x1d1d1d1d},
++ {0x0000a088, 0x1d1d1d1d},
++ {0x0000a08c, 0x1d1d1d1d},
++ {0x0000a090, 0x171d1d1d},
++ {0x0000a094, 0x11111717},
++ {0x0000a098, 0x00030311},
++ {0x0000a09c, 0x00000000},
++ {0x0000a0a0, 0x00000000},
++ {0x0000a0a4, 0x00000000},
++ {0x0000a0a8, 0x00000000},
++ {0x0000a0ac, 0x00000000},
++ {0x0000a0b0, 0x00000000},
++ {0x0000a0b4, 0x00000000},
++ {0x0000a0b8, 0x00000000},
++ {0x0000a0bc, 0x00000000},
++ {0x0000a0c0, 0x001f0000},
++ {0x0000a0c4, 0x01000101},
++ {0x0000a0c8, 0x011e011f},
++ {0x0000a0cc, 0x011c011d},
++ {0x0000a0d0, 0x02030204},
++ {0x0000a0d4, 0x02010202},
++ {0x0000a0d8, 0x021f0200},
++ {0x0000a0dc, 0x0302021e},
++ {0x0000a0e0, 0x03000301},
++ {0x0000a0e4, 0x031e031f},
++ {0x0000a0e8, 0x0402031d},
++ {0x0000a0ec, 0x04000401},
++ {0x0000a0f0, 0x041e041f},
++ {0x0000a0f4, 0x0502041d},
++ {0x0000a0f8, 0x05000501},
++ {0x0000a0fc, 0x051e051f},
++ {0x0000a100, 0x06010602},
++ {0x0000a104, 0x061f0600},
++ {0x0000a108, 0x061d061e},
++ {0x0000a10c, 0x07020703},
++ {0x0000a110, 0x07000701},
++ {0x0000a114, 0x00000000},
++ {0x0000a118, 0x00000000},
++ {0x0000a11c, 0x00000000},
++ {0x0000a120, 0x00000000},
++ {0x0000a124, 0x00000000},
++ {0x0000a128, 0x00000000},
++ {0x0000a12c, 0x00000000},
++ {0x0000a130, 0x00000000},
++ {0x0000a134, 0x00000000},
++ {0x0000a138, 0x00000000},
++ {0x0000a13c, 0x00000000},
++ {0x0000a140, 0x001f0000},
++ {0x0000a144, 0x01000101},
++ {0x0000a148, 0x011e011f},
++ {0x0000a14c, 0x011c011d},
++ {0x0000a150, 0x02030204},
++ {0x0000a154, 0x02010202},
++ {0x0000a158, 0x021f0200},
++ {0x0000a15c, 0x0302021e},
++ {0x0000a160, 0x03000301},
++ {0x0000a164, 0x031e031f},
++ {0x0000a168, 0x0402031d},
++ {0x0000a16c, 0x04000401},
++ {0x0000a170, 0x041e041f},
++ {0x0000a174, 0x0502041d},
++ {0x0000a178, 0x05000501},
++ {0x0000a17c, 0x051e051f},
++ {0x0000a180, 0x06010602},
++ {0x0000a184, 0x061f0600},
++ {0x0000a188, 0x061d061e},
++ {0x0000a18c, 0x07020703},
++ {0x0000a190, 0x07000701},
++ {0x0000a194, 0x00000000},
++ {0x0000a198, 0x00000000},
++ {0x0000a19c, 0x00000000},
++ {0x0000a1a0, 0x00000000},
++ {0x0000a1a4, 0x00000000},
++ {0x0000a1a8, 0x00000000},
++ {0x0000a1ac, 0x00000000},
++ {0x0000a1b0, 0x00000000},
++ {0x0000a1b4, 0x00000000},
++ {0x0000a1b8, 0x00000000},
++ {0x0000a1bc, 0x00000000},
++ {0x0000a1c0, 0x00000000},
++ {0x0000a1c4, 0x00000000},
++ {0x0000a1c8, 0x00000000},
++ {0x0000a1cc, 0x00000000},
++ {0x0000a1d0, 0x00000000},
++ {0x0000a1d4, 0x00000000},
++ {0x0000a1d8, 0x00000000},
++ {0x0000a1dc, 0x00000000},
++ {0x0000a1e0, 0x00000000},
++ {0x0000a1e4, 0x00000000},
++ {0x0000a1e8, 0x00000000},
++ {0x0000a1ec, 0x00000000},
++ {0x0000a1f0, 0x00000396},
++ {0x0000a1f4, 0x00000396},
++ {0x0000a1f8, 0x00000396},
++ {0x0000a1fc, 0x00000196},
++ {0x0000b000, 0x00010000},
++ {0x0000b004, 0x00030002},
++ {0x0000b008, 0x00050004},
++ {0x0000b00c, 0x00810080},
++ {0x0000b010, 0x00830082},
++ {0x0000b014, 0x01810180},
++ {0x0000b018, 0x01830182},
++ {0x0000b01c, 0x01850184},
++ {0x0000b020, 0x02810280},
++ {0x0000b024, 0x02830282},
++ {0x0000b028, 0x02850284},
++ {0x0000b02c, 0x02890288},
++ {0x0000b030, 0x028b028a},
++ {0x0000b034, 0x0388028c},
++ {0x0000b038, 0x038a0389},
++ {0x0000b03c, 0x038c038b},
++ {0x0000b040, 0x0390038d},
++ {0x0000b044, 0x03920391},
++ {0x0000b048, 0x03940393},
++ {0x0000b04c, 0x03960395},
++ {0x0000b050, 0x00000000},
++ {0x0000b054, 0x00000000},
++ {0x0000b058, 0x00000000},
++ {0x0000b05c, 0x00000000},
++ {0x0000b060, 0x00000000},
++ {0x0000b064, 0x00000000},
++ {0x0000b068, 0x00000000},
++ {0x0000b06c, 0x00000000},
++ {0x0000b070, 0x00000000},
++ {0x0000b074, 0x00000000},
++ {0x0000b078, 0x00000000},
++ {0x0000b07c, 0x00000000},
++ {0x0000b080, 0x23232323},
++ {0x0000b084, 0x21232323},
++ {0x0000b088, 0x19191c1e},
++ {0x0000b08c, 0x12141417},
++ {0x0000b090, 0x07070e0e},
++ {0x0000b094, 0x03030305},
++ {0x0000b098, 0x00000003},
++ {0x0000b09c, 0x00000000},
++ {0x0000b0a0, 0x00000000},
++ {0x0000b0a4, 0x00000000},
++ {0x0000b0a8, 0x00000000},
++ {0x0000b0ac, 0x00000000},
++ {0x0000b0b0, 0x00000000},
++ {0x0000b0b4, 0x00000000},
++ {0x0000b0b8, 0x00000000},
++ {0x0000b0bc, 0x00000000},
++ {0x0000b0c0, 0x003f0020},
++ {0x0000b0c4, 0x00400041},
++ {0x0000b0c8, 0x0140005f},
++ {0x0000b0cc, 0x0160015f},
++ {0x0000b0d0, 0x017e017f},
++ {0x0000b0d4, 0x02410242},
++ {0x0000b0d8, 0x025f0240},
++ {0x0000b0dc, 0x027f0260},
++ {0x0000b0e0, 0x0341027e},
++ {0x0000b0e4, 0x035f0340},
++ {0x0000b0e8, 0x037f0360},
++ {0x0000b0ec, 0x04400441},
++ {0x0000b0f0, 0x0460045f},
++ {0x0000b0f4, 0x0541047f},
++ {0x0000b0f8, 0x055f0540},
++ {0x0000b0fc, 0x057f0560},
++ {0x0000b100, 0x06400641},
++ {0x0000b104, 0x0660065f},
++ {0x0000b108, 0x067e067f},
++ {0x0000b10c, 0x07410742},
++ {0x0000b110, 0x075f0740},
++ {0x0000b114, 0x077f0760},
++ {0x0000b118, 0x07800781},
++ {0x0000b11c, 0x07a0079f},
++ {0x0000b120, 0x07c107bf},
++ {0x0000b124, 0x000007c0},
++ {0x0000b128, 0x00000000},
++ {0x0000b12c, 0x00000000},
++ {0x0000b130, 0x00000000},
++ {0x0000b134, 0x00000000},
++ {0x0000b138, 0x00000000},
++ {0x0000b13c, 0x00000000},
++ {0x0000b140, 0x003f0020},
++ {0x0000b144, 0x00400041},
++ {0x0000b148, 0x0140005f},
++ {0x0000b14c, 0x0160015f},
++ {0x0000b150, 0x017e017f},
++ {0x0000b154, 0x02410242},
++ {0x0000b158, 0x025f0240},
++ {0x0000b15c, 0x027f0260},
++ {0x0000b160, 0x0341027e},
++ {0x0000b164, 0x035f0340},
++ {0x0000b168, 0x037f0360},
++ {0x0000b16c, 0x04400441},
++ {0x0000b170, 0x0460045f},
++ {0x0000b174, 0x0541047f},
++ {0x0000b178, 0x055f0540},
++ {0x0000b17c, 0x057f0560},
++ {0x0000b180, 0x06400641},
++ {0x0000b184, 0x0660065f},
++ {0x0000b188, 0x067e067f},
++ {0x0000b18c, 0x07410742},
++ {0x0000b190, 0x075f0740},
++ {0x0000b194, 0x077f0760},
++ {0x0000b198, 0x07800781},
++ {0x0000b19c, 0x07a0079f},
++ {0x0000b1a0, 0x07c107bf},
++ {0x0000b1a4, 0x000007c0},
++ {0x0000b1a8, 0x00000000},
++ {0x0000b1ac, 0x00000000},
++ {0x0000b1b0, 0x00000000},
++ {0x0000b1b4, 0x00000000},
++ {0x0000b1b8, 0x00000000},
++ {0x0000b1bc, 0x00000000},
++ {0x0000b1c0, 0x00000000},
++ {0x0000b1c4, 0x00000000},
++ {0x0000b1c8, 0x00000000},
++ {0x0000b1cc, 0x00000000},
++ {0x0000b1d0, 0x00000000},
++ {0x0000b1d4, 0x00000000},
++ {0x0000b1d8, 0x00000000},
++ {0x0000b1dc, 0x00000000},
++ {0x0000b1e0, 0x00000000},
++ {0x0000b1e4, 0x00000000},
++ {0x0000b1e8, 0x00000000},
++ {0x0000b1ec, 0x00000000},
++ {0x0000b1f0, 0x00000396},
++ {0x0000b1f4, 0x00000396},
++ {0x0000b1f8, 0x00000396},
++ {0x0000b1fc, 0x00000196},
+ };
+
+ static const u32 ar9580_1p0_baseband_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
++ {0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a},
++ {0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
+ {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+ {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
+@@ -956,7 +1169,7 @@ static const u32 ar9580_1p0_baseband_pos
+ {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
+ {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
+ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+- {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
++ {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
+ {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
+ {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
+@@ -994,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll
+ {0x00004044, 0x00000000},
+ };
+
++static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = {
++ /* Addr 5G 2G */
++ {0x00009814, 0x3400c00f, 0x3400c00f},
++ {0x00009824, 0x5ac668d0, 0x5ac668d0},
++ {0x00009828, 0x06903080, 0x06903080},
++ {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
++ {0x00009e14, 0x37b9625e, 0x37b9625e},
++};
++
+ #endif /* INITVALS_9580_1P0_H */
+--- a/drivers/net/wireless/ath/ath9k/reg.h
++++ b/drivers/net/wireless/ath/ath9k/reg.h
+@@ -809,6 +809,8 @@
+ #define AR_SREV_REVISION_9462_21 3
+ #define AR_SREV_VERSION_9565 0x2C0
+ #define AR_SREV_REVISION_9565_10 0
++#define AR_SREV_REVISION_9565_101 1
++#define AR_SREV_REVISION_9565_11 2
+ #define AR_SREV_VERSION_9550 0x400
+
+ #define AR_SREV_5416(_ah) \
+@@ -881,9 +883,6 @@
+
+ #define AR_SREV_9330(_ah) \
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))
+-#define AR_SREV_9330_10(_ah) \
+- (AR_SREV_9330((_ah)) && \
+- ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_10))
+ #define AR_SREV_9330_11(_ah) \
+ (AR_SREV_9330((_ah)) && \
+ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11))
+@@ -927,10 +926,18 @@
+
+ #define AR_SREV_9565(_ah) \
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))
+-
+ #define AR_SREV_9565_10(_ah) \
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
+ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))
++#define AR_SREV_9565_101(_ah) \
++ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
++ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101))
++#define AR_SREV_9565_11(_ah) \
++ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
++ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11))
++#define AR_SREV_9565_11_OR_LATER(_ah) \
++ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
++ ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11))
+
+ #define AR_SREV_9550(_ah) \
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
+--- a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
+@@ -18,6 +18,10 @@
+ #ifndef INITVALS_9330_1P1_H
+ #define INITVALS_9330_1P1_H
+
++#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
++
++#define ar9331_modes_high_power_tx_gain_1p1 ar9331_modes_lowest_ob_db_tx_gain_1p1
++
+ static const u32 ar9331_1p1_baseband_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
+@@ -55,7 +59,7 @@ static const u32 ar9331_1p1_baseband_pos
+ {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
++ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18},
+ {0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982},
+ {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+ {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+@@ -252,7 +256,7 @@ static const u32 ar9331_modes_low_ob_db_
+ {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
+ {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
+ {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
+- {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
++ {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d4, 0x000050d4},
+ {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+ {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+ {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+@@ -337,8 +341,6 @@ static const u32 ar9331_modes_low_ob_db_
+ {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
+ };
+
+-#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
+-
+ static const u32 ar9331_1p1_xtal_25M[][2] = {
+ /* Addr allmodes */
+ {0x00007038, 0x000002f8},
+@@ -373,17 +375,17 @@ static const u32 ar9331_1p1_radio_core[]
+ {0x000160b4, 0x92480040},
+ {0x000160c0, 0x006db6db},
+ {0x000160c4, 0x0186db60},
+- {0x000160c8, 0x6db4db6c},
++ {0x000160c8, 0x6db6db6c},
+ {0x000160cc, 0x6de6c300},
+ {0x000160d0, 0x14500820},
+ {0x00016100, 0x04cb0001},
+ {0x00016104, 0xfff80015},
+ {0x00016108, 0x00080010},
+ {0x0001610c, 0x00170000},
+- {0x00016140, 0x10800000},
++ {0x00016140, 0x50804000},
+ {0x00016144, 0x01884080},
+ {0x00016148, 0x000080c0},
+- {0x00016280, 0x01000015},
++ {0x00016280, 0x01001015},
+ {0x00016284, 0x14d20000},
+ {0x00016288, 0x00318000},
+ {0x0001628c, 0x50000000},
+@@ -622,12 +624,12 @@ static const u32 ar9331_1p1_baseband_cor
+ {0x0000a370, 0x00000000},
+ {0x0000a390, 0x00000001},
+ {0x0000a394, 0x00000444},
+- {0x0000a398, 0x001f0e0f},
+- {0x0000a39c, 0x0075393f},
+- {0x0000a3a0, 0xb79f6427},
+- {0x0000a3a4, 0x00000000},
+- {0x0000a3a8, 0xaaaaaaaa},
+- {0x0000a3ac, 0x3c466478},
++ {0x0000a398, 0x00000000},
++ {0x0000a39c, 0x210d0401},
++ {0x0000a3a0, 0xab9a7144},
++ {0x0000a3a4, 0x00000011},
++ {0x0000a3a8, 0x3c3c003d},
++ {0x0000a3ac, 0x30310030},
+ {0x0000a3c0, 0x20202020},
+ {0x0000a3c4, 0x22222220},
+ {0x0000a3c8, 0x20200020},
+@@ -686,100 +688,18 @@ static const u32 ar9331_1p1_baseband_cor
+ {0x0000a7dc, 0x00000001},
+ };
+
+-static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
++static const u32 ar9331_1p1_mac_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
+- {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
+- {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
+- {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
+- {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
+- {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
+- {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+- {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+- {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+- {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+- {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+- {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+- {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
+- {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
+- {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
+- {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
+- {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
+- {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
+- {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
+- {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
+- {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
+- {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
+- {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
+- {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+- {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+- {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+- {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+- {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
+- {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
+- {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
+- {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
+- {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
+- {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
+- {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
+- {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
+- {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
+- {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
+- {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
+- {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
+- {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
+- {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
+- {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
+- {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
+- {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
+- {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
+- {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
+- {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
+- {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
+- {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
+- {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
+- {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+- {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+- {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+- {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+- {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+- {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+- {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
+- {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
+- {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
+- {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
+- {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+- {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+- {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+- {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+- {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+- {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+- {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
+- {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
++ {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
++ {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
++ {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
++ {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
++ {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
++ {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
++ {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
++ {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+ };
+
+-#define ar9331_1p1_mac_postamble ar9300_2p2_mac_postamble
+-
+ static const u32 ar9331_1p1_soc_preamble[][2] = {
+ /* Addr allmodes */
+ {0x00007020, 0x00000000},
+--- a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
+@@ -18,6 +18,28 @@
+ #ifndef INITVALS_9330_1P2_H
+ #define INITVALS_9330_1P2_H
+
++#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
++
++#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
++
++#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
++
++#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
++
++#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
++
++#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
++
++#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
++
++#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
++
++#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
++
++#define ar9331_1p2_mac_core ar9331_1p1_mac_core
++
++#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
++
+ static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
+@@ -103,57 +125,6 @@ static const u32 ar9331_modes_high_ob_db
+ {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+ };
+
+-#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
+-
+-#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_power_tx_gain_1p2
+-
+-#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_low_ob_db_tx_gain_1p2
+-
+-static const u32 ar9331_1p2_baseband_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
+- {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
+- {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+- {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
+- {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
+- {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
+- {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
+- {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
+- {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
+- {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
+- {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
+- {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+- {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
+- {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
+- {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
+- {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
+- {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
+- {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
+- {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
+- {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
+- {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+- {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
+- {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
+- {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
+- {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
+- {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
+- {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
+- {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
+- {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
+- {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
+- {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
+- {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+- {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
+- {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+- {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+- {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+-};
+-
+ static const u32 ar9331_1p2_radio_core[][2] = {
+ /* Addr allmodes */
+ {0x00016000, 0x36db6db6},
+@@ -219,24 +190,318 @@ static const u32 ar9331_1p2_radio_core[]
+ {0x000163d4, 0x00000000},
+ };
+
+-#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
+-
+-#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
+-
+-#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
+-
+-#define ar9331_1p2_baseband_core ar9331_1p1_baseband_core
+-
+-#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
+-
+-#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
+-
+-#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
+-
+-#define ar9331_1p2_mac_core ar9331_1p1_mac_core
++static const u32 ar9331_1p2_baseband_core[][2] = {
++ /* Addr allmodes */
++ {0x00009800, 0xafe68e30},
++ {0x00009804, 0xfd14e000},
++ {0x00009808, 0x9c0a8f6b},
++ {0x0000980c, 0x04800000},
++ {0x00009814, 0x9280c00a},
++ {0x00009818, 0x00000000},
++ {0x0000981c, 0x00020028},
++ {0x00009834, 0x5f3ca3de},
++ {0x00009838, 0x0108ecff},
++ {0x0000983c, 0x14750600},
++ {0x00009880, 0x201fff00},
++ {0x00009884, 0x00001042},
++ {0x000098a4, 0x00200400},
++ {0x000098b0, 0x32840bbe},
++ {0x000098d0, 0x004b6a8e},
++ {0x000098d4, 0x00000820},
++ {0x000098dc, 0x00000000},
++ {0x000098f0, 0x00000000},
++ {0x000098f4, 0x00000000},
++ {0x00009c04, 0x00000000},
++ {0x00009c08, 0x03200000},
++ {0x00009c0c, 0x00000000},
++ {0x00009c10, 0x00000000},
++ {0x00009c14, 0x00046384},
++ {0x00009c18, 0x05b6b440},
++ {0x00009c1c, 0x00b6b440},
++ {0x00009d00, 0xc080a333},
++ {0x00009d04, 0x40206c10},
++ {0x00009d08, 0x009c4060},
++ {0x00009d0c, 0x1883800a},
++ {0x00009d10, 0x01834061},
++ {0x00009d14, 0x00c00400},
++ {0x00009d18, 0x00000000},
++ {0x00009e08, 0x0038233c},
++ {0x00009e24, 0x9927b515},
++ {0x00009e28, 0x12ef0200},
++ {0x00009e30, 0x06336f77},
++ {0x00009e34, 0x6af6532f},
++ {0x00009e38, 0x0cc80c00},
++ {0x00009e40, 0x0d261820},
++ {0x00009e4c, 0x00001004},
++ {0x00009e50, 0x00ff03f1},
++ {0x00009fc0, 0x803e4788},
++ {0x00009fc4, 0x0001efb5},
++ {0x00009fcc, 0x40000014},
++ {0x0000a20c, 0x00000000},
++ {0x0000a220, 0x00000000},
++ {0x0000a224, 0x00000000},
++ {0x0000a228, 0x10002310},
++ {0x0000a23c, 0x00000000},
++ {0x0000a244, 0x0c000000},
++ {0x0000a2a0, 0x00000001},
++ {0x0000a2c0, 0x00000001},
++ {0x0000a2c8, 0x00000000},
++ {0x0000a2cc, 0x18c43433},
++ {0x0000a2d4, 0x00000000},
++ {0x0000a2dc, 0x00000000},
++ {0x0000a2e0, 0x00000000},
++ {0x0000a2e4, 0x00000000},
++ {0x0000a2e8, 0x00000000},
++ {0x0000a2ec, 0x00000000},
++ {0x0000a2f0, 0x00000000},
++ {0x0000a2f4, 0x00000000},
++ {0x0000a2f8, 0x00000000},
++ {0x0000a344, 0x00000000},
++ {0x0000a34c, 0x00000000},
++ {0x0000a350, 0x0000a000},
++ {0x0000a364, 0x00000000},
++ {0x0000a370, 0x00000000},
++ {0x0000a390, 0x00000001},
++ {0x0000a394, 0x00000444},
++ {0x0000a398, 0x001f0e0f},
++ {0x0000a39c, 0x0075393f},
++ {0x0000a3a0, 0xb79f6427},
++ {0x0000a3a4, 0x00000000},
++ {0x0000a3a8, 0xaaaaaaaa},
++ {0x0000a3ac, 0x3c466478},
++ {0x0000a3c0, 0x20202020},
++ {0x0000a3c4, 0x22222220},
++ {0x0000a3c8, 0x20200020},
++ {0x0000a3cc, 0x20202020},
++ {0x0000a3d0, 0x20202020},
++ {0x0000a3d4, 0x20202020},
++ {0x0000a3d8, 0x20202020},
++ {0x0000a3dc, 0x20202020},
++ {0x0000a3e0, 0x20202020},
++ {0x0000a3e4, 0x20202020},
++ {0x0000a3e8, 0x20202020},
++ {0x0000a3ec, 0x20202020},
++ {0x0000a3f0, 0x00000000},
++ {0x0000a3f4, 0x00000006},
++ {0x0000a3f8, 0x0cdbd380},
++ {0x0000a3fc, 0x000f0f01},
++ {0x0000a400, 0x8fa91f01},
++ {0x0000a404, 0x00000000},
++ {0x0000a408, 0x0e79e5c6},
++ {0x0000a40c, 0x00820820},
++ {0x0000a414, 0x1ce739ce},
++ {0x0000a418, 0x2d001dce},
++ {0x0000a41c, 0x1ce739ce},
++ {0x0000a420, 0x000001ce},
++ {0x0000a424, 0x1ce739ce},
++ {0x0000a428, 0x000001ce},
++ {0x0000a42c, 0x1ce739ce},
++ {0x0000a430, 0x1ce739ce},
++ {0x0000a434, 0x00000000},
++ {0x0000a438, 0x00001801},
++ {0x0000a43c, 0x00000000},
++ {0x0000a440, 0x00000000},
++ {0x0000a444, 0x00000000},
++ {0x0000a448, 0x04000000},
++ {0x0000a44c, 0x00000001},
++ {0x0000a450, 0x00010000},
++ {0x0000a458, 0x00000000},
++ {0x0000a640, 0x00000000},
++ {0x0000a644, 0x3fad9d74},
++ {0x0000a648, 0x0048060a},
++ {0x0000a64c, 0x00003c37},
++ {0x0000a670, 0x03020100},
++ {0x0000a674, 0x09080504},
++ {0x0000a678, 0x0d0c0b0a},
++ {0x0000a67c, 0x13121110},
++ {0x0000a680, 0x31301514},
++ {0x0000a684, 0x35343332},
++ {0x0000a688, 0x00000036},
++ {0x0000a690, 0x00000838},
++ {0x0000a7c0, 0x00000000},
++ {0x0000a7c4, 0xfffffffc},
++ {0x0000a7c8, 0x00000000},
++ {0x0000a7cc, 0x00000000},
++ {0x0000a7d0, 0x00000000},
++ {0x0000a7d4, 0x00000004},
++ {0x0000a7dc, 0x00000001},
++};
+
+-#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
++static const u32 ar9331_1p2_baseband_postamble[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
++ {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
++ {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
++ {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
++ {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
++ {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
++ {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
++ {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
++ {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
++ {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
++ {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
++ {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
++ {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
++ {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
++ {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
++ {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
++ {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
++ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
++ {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
++ {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
++ {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
++ {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
++ {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
++ {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
++ {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
++ {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
++ {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
++ {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
++ {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
++ {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
++ {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
++ {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
++ {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
++ {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
++ {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
++ {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++};
+
+-#define ar9331_common_rx_gain_1p2 ar9485_common_rx_gain_1_1
++static const u32 ar9331_common_rx_gain_1p2[][2] = {
++ /* Addr allmodes */
++ {0x0000a000, 0x00010000},
++ {0x0000a004, 0x00030002},
++ {0x0000a008, 0x00050004},
++ {0x0000a00c, 0x00810080},
++ {0x0000a010, 0x01800082},
++ {0x0000a014, 0x01820181},
++ {0x0000a018, 0x01840183},
++ {0x0000a01c, 0x01880185},
++ {0x0000a020, 0x018a0189},
++ {0x0000a024, 0x02850284},
++ {0x0000a028, 0x02890288},
++ {0x0000a02c, 0x03850384},
++ {0x0000a030, 0x03890388},
++ {0x0000a034, 0x038b038a},
++ {0x0000a038, 0x038d038c},
++ {0x0000a03c, 0x03910390},
++ {0x0000a040, 0x03930392},
++ {0x0000a044, 0x03950394},
++ {0x0000a048, 0x00000396},
++ {0x0000a04c, 0x00000000},
++ {0x0000a050, 0x00000000},
++ {0x0000a054, 0x00000000},
++ {0x0000a058, 0x00000000},
++ {0x0000a05c, 0x00000000},
++ {0x0000a060, 0x00000000},
++ {0x0000a064, 0x00000000},
++ {0x0000a068, 0x00000000},
++ {0x0000a06c, 0x00000000},
++ {0x0000a070, 0x00000000},
++ {0x0000a074, 0x00000000},
++ {0x0000a078, 0x00000000},
++ {0x0000a07c, 0x00000000},
++ {0x0000a080, 0x28282828},
++ {0x0000a084, 0x28282828},
++ {0x0000a088, 0x28282828},
++ {0x0000a08c, 0x28282828},
++ {0x0000a090, 0x28282828},
++ {0x0000a094, 0x21212128},
++ {0x0000a098, 0x171c1c1c},
++ {0x0000a09c, 0x02020212},
++ {0x0000a0a0, 0x00000202},
++ {0x0000a0a4, 0x00000000},
++ {0x0000a0a8, 0x00000000},
++ {0x0000a0ac, 0x00000000},
++ {0x0000a0b0, 0x00000000},
++ {0x0000a0b4, 0x00000000},
++ {0x0000a0b8, 0x00000000},
++ {0x0000a0bc, 0x00000000},
++ {0x0000a0c0, 0x001f0000},
++ {0x0000a0c4, 0x111f1100},
++ {0x0000a0c8, 0x111d111e},
++ {0x0000a0cc, 0x111b111c},
++ {0x0000a0d0, 0x22032204},
++ {0x0000a0d4, 0x22012202},
++ {0x0000a0d8, 0x221f2200},
++ {0x0000a0dc, 0x221d221e},
++ {0x0000a0e0, 0x33013302},
++ {0x0000a0e4, 0x331f3300},
++ {0x0000a0e8, 0x4402331e},
++ {0x0000a0ec, 0x44004401},
++ {0x0000a0f0, 0x441e441f},
++ {0x0000a0f4, 0x55015502},
++ {0x0000a0f8, 0x551f5500},
++ {0x0000a0fc, 0x6602551e},
++ {0x0000a100, 0x66006601},
++ {0x0000a104, 0x661e661f},
++ {0x0000a108, 0x7703661d},
++ {0x0000a10c, 0x77017702},
++ {0x0000a110, 0x00007700},
++ {0x0000a114, 0x00000000},
++ {0x0000a118, 0x00000000},
++ {0x0000a11c, 0x00000000},
++ {0x0000a120, 0x00000000},
++ {0x0000a124, 0x00000000},
++ {0x0000a128, 0x00000000},
++ {0x0000a12c, 0x00000000},
++ {0x0000a130, 0x00000000},
++ {0x0000a134, 0x00000000},
++ {0x0000a138, 0x00000000},
++ {0x0000a13c, 0x00000000},
++ {0x0000a140, 0x001f0000},
++ {0x0000a144, 0x111f1100},
++ {0x0000a148, 0x111d111e},
++ {0x0000a14c, 0x111b111c},
++ {0x0000a150, 0x22032204},
++ {0x0000a154, 0x22012202},
++ {0x0000a158, 0x221f2200},
++ {0x0000a15c, 0x221d221e},
++ {0x0000a160, 0x33013302},
++ {0x0000a164, 0x331f3300},
++ {0x0000a168, 0x4402331e},
++ {0x0000a16c, 0x44004401},
++ {0x0000a170, 0x441e441f},
++ {0x0000a174, 0x55015502},
++ {0x0000a178, 0x551f5500},
++ {0x0000a17c, 0x6602551e},
++ {0x0000a180, 0x66006601},
++ {0x0000a184, 0x661e661f},
++ {0x0000a188, 0x7703661d},
++ {0x0000a18c, 0x77017702},
++ {0x0000a190, 0x00007700},
++ {0x0000a194, 0x00000000},
++ {0x0000a198, 0x00000000},
++ {0x0000a19c, 0x00000000},
++ {0x0000a1a0, 0x00000000},
++ {0x0000a1a4, 0x00000000},
++ {0x0000a1a8, 0x00000000},
++ {0x0000a1ac, 0x00000000},
++ {0x0000a1b0, 0x00000000},
++ {0x0000a1b4, 0x00000000},
++ {0x0000a1b8, 0x00000000},
++ {0x0000a1bc, 0x00000000},
++ {0x0000a1c0, 0x00000000},
++ {0x0000a1c4, 0x00000000},
++ {0x0000a1c8, 0x00000000},
++ {0x0000a1cc, 0x00000000},
++ {0x0000a1d0, 0x00000000},
++ {0x0000a1d4, 0x00000000},
++ {0x0000a1d8, 0x00000000},
++ {0x0000a1dc, 0x00000000},
++ {0x0000a1e0, 0x00000000},
++ {0x0000a1e4, 0x00000000},
++ {0x0000a1e8, 0x00000000},
++ {0x0000a1ec, 0x00000000},
++ {0x0000a1f0, 0x00000396},
++ {0x0000a1f4, 0x00000396},
++ {0x0000a1f8, 0x00000396},
++ {0x0000a1fc, 0x00000296},
++};
+
+ #endif /* INITVALS_9330_1P2_H */
+--- a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
+@@ -20,6 +20,14 @@
+
+ /* AR955X 1.0 */
+
++#define ar955x_1p0_soc_postamble ar9300_2p2_soc_postamble
++
++#define ar955x_1p0_common_rx_gain_table ar9300Common_rx_gain_table_2p2
++
++#define ar955x_1p0_common_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
++
++#define ar955x_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
++
+ static const u32 ar955x_1p0_radio_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
+@@ -37,13 +45,6 @@ static const u32 ar955x_1p0_radio_postam
+ {0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
+ };
+
+-static const u32 ar955x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
+- /* Addr allmodes */
+- {0x0000a398, 0x00000000},
+- {0x0000a39c, 0x6f7f0301},
+- {0x0000a3a0, 0xca9228ee},
+-};
+-
+ static const u32 ar955x_1p0_baseband_postamble[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
+@@ -473,266 +474,6 @@ static const u32 ar955x_1p0_mac_core[][2
+ {0x000083d0, 0x8c7901ff},
+ };
+
+-static const u32 ar955x_1p0_common_rx_gain_table[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x01910190},
+- {0x0000a030, 0x01930192},
+- {0x0000a034, 0x01950194},
+- {0x0000a038, 0x038a0196},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x22222229},
+- {0x0000a084, 0x1d1d1d1d},
+- {0x0000a088, 0x1d1d1d1d},
+- {0x0000a08c, 0x1d1d1d1d},
+- {0x0000a090, 0x171d1d1d},
+- {0x0000a094, 0x11111717},
+- {0x0000a098, 0x00030311},
+- {0x0000a09c, 0x00000000},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x23232323},
+- {0x0000b084, 0x21232323},
+- {0x0000b088, 0x19191c1e},
+- {0x0000b08c, 0x12141417},
+- {0x0000b090, 0x07070e0e},
+- {0x0000b094, 0x03030305},
+- {0x0000b098, 0x00000003},
+- {0x0000b09c, 0x00000000},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+ static const u32 ar955x_1p0_baseband_core[][2] = {
+ /* Addr allmodes */
+ {0x00009800, 0xafe68e30},
+@@ -891,266 +632,6 @@ static const u32 ar955x_1p0_baseband_cor
+ {0x0000c420, 0x00000000},
+ };
+
+-static const u32 ar955x_1p0_common_wo_xlna_rx_gain_table[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x00830082},
+- {0x0000a014, 0x01810180},
+- {0x0000a018, 0x01830182},
+- {0x0000a01c, 0x01850184},
+- {0x0000a020, 0x01890188},
+- {0x0000a024, 0x018b018a},
+- {0x0000a028, 0x018d018c},
+- {0x0000a02c, 0x03820190},
+- {0x0000a030, 0x03840383},
+- {0x0000a034, 0x03880385},
+- {0x0000a038, 0x038a0389},
+- {0x0000a03c, 0x038c038b},
+- {0x0000a040, 0x0390038d},
+- {0x0000a044, 0x03920391},
+- {0x0000a048, 0x03940393},
+- {0x0000a04c, 0x03960395},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x29292929},
+- {0x0000a084, 0x29292929},
+- {0x0000a088, 0x29292929},
+- {0x0000a08c, 0x29292929},
+- {0x0000a090, 0x22292929},
+- {0x0000a094, 0x1d1d2222},
+- {0x0000a098, 0x0c111117},
+- {0x0000a09c, 0x00030303},
+- {0x0000a0a0, 0x00000000},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x01000101},
+- {0x0000a0c8, 0x011e011f},
+- {0x0000a0cc, 0x011c011d},
+- {0x0000a0d0, 0x02030204},
+- {0x0000a0d4, 0x02010202},
+- {0x0000a0d8, 0x021f0200},
+- {0x0000a0dc, 0x0302021e},
+- {0x0000a0e0, 0x03000301},
+- {0x0000a0e4, 0x031e031f},
+- {0x0000a0e8, 0x0402031d},
+- {0x0000a0ec, 0x04000401},
+- {0x0000a0f0, 0x041e041f},
+- {0x0000a0f4, 0x0502041d},
+- {0x0000a0f8, 0x05000501},
+- {0x0000a0fc, 0x051e051f},
+- {0x0000a100, 0x06010602},
+- {0x0000a104, 0x061f0600},
+- {0x0000a108, 0x061d061e},
+- {0x0000a10c, 0x07020703},
+- {0x0000a110, 0x07000701},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x01000101},
+- {0x0000a148, 0x011e011f},
+- {0x0000a14c, 0x011c011d},
+- {0x0000a150, 0x02030204},
+- {0x0000a154, 0x02010202},
+- {0x0000a158, 0x021f0200},
+- {0x0000a15c, 0x0302021e},
+- {0x0000a160, 0x03000301},
+- {0x0000a164, 0x031e031f},
+- {0x0000a168, 0x0402031d},
+- {0x0000a16c, 0x04000401},
+- {0x0000a170, 0x041e041f},
+- {0x0000a174, 0x0502041d},
+- {0x0000a178, 0x05000501},
+- {0x0000a17c, 0x051e051f},
+- {0x0000a180, 0x06010602},
+- {0x0000a184, 0x061f0600},
+- {0x0000a188, 0x061d061e},
+- {0x0000a18c, 0x07020703},
+- {0x0000a190, 0x07000701},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000196},
+- {0x0000b000, 0x00010000},
+- {0x0000b004, 0x00030002},
+- {0x0000b008, 0x00050004},
+- {0x0000b00c, 0x00810080},
+- {0x0000b010, 0x00830082},
+- {0x0000b014, 0x01810180},
+- {0x0000b018, 0x01830182},
+- {0x0000b01c, 0x01850184},
+- {0x0000b020, 0x02810280},
+- {0x0000b024, 0x02830282},
+- {0x0000b028, 0x02850284},
+- {0x0000b02c, 0x02890288},
+- {0x0000b030, 0x028b028a},
+- {0x0000b034, 0x0388028c},
+- {0x0000b038, 0x038a0389},
+- {0x0000b03c, 0x038c038b},
+- {0x0000b040, 0x0390038d},
+- {0x0000b044, 0x03920391},
+- {0x0000b048, 0x03940393},
+- {0x0000b04c, 0x03960395},
+- {0x0000b050, 0x00000000},
+- {0x0000b054, 0x00000000},
+- {0x0000b058, 0x00000000},
+- {0x0000b05c, 0x00000000},
+- {0x0000b060, 0x00000000},
+- {0x0000b064, 0x00000000},
+- {0x0000b068, 0x00000000},
+- {0x0000b06c, 0x00000000},
+- {0x0000b070, 0x00000000},
+- {0x0000b074, 0x00000000},
+- {0x0000b078, 0x00000000},
+- {0x0000b07c, 0x00000000},
+- {0x0000b080, 0x32323232},
+- {0x0000b084, 0x2f2f3232},
+- {0x0000b088, 0x23282a2d},
+- {0x0000b08c, 0x1c1e2123},
+- {0x0000b090, 0x14171919},
+- {0x0000b094, 0x0e0e1214},
+- {0x0000b098, 0x03050707},
+- {0x0000b09c, 0x00030303},
+- {0x0000b0a0, 0x00000000},
+- {0x0000b0a4, 0x00000000},
+- {0x0000b0a8, 0x00000000},
+- {0x0000b0ac, 0x00000000},
+- {0x0000b0b0, 0x00000000},
+- {0x0000b0b4, 0x00000000},
+- {0x0000b0b8, 0x00000000},
+- {0x0000b0bc, 0x00000000},
+- {0x0000b0c0, 0x003f0020},
+- {0x0000b0c4, 0x00400041},
+- {0x0000b0c8, 0x0140005f},
+- {0x0000b0cc, 0x0160015f},
+- {0x0000b0d0, 0x017e017f},
+- {0x0000b0d4, 0x02410242},
+- {0x0000b0d8, 0x025f0240},
+- {0x0000b0dc, 0x027f0260},
+- {0x0000b0e0, 0x0341027e},
+- {0x0000b0e4, 0x035f0340},
+- {0x0000b0e8, 0x037f0360},
+- {0x0000b0ec, 0x04400441},
+- {0x0000b0f0, 0x0460045f},
+- {0x0000b0f4, 0x0541047f},
+- {0x0000b0f8, 0x055f0540},
+- {0x0000b0fc, 0x057f0560},
+- {0x0000b100, 0x06400641},
+- {0x0000b104, 0x0660065f},
+- {0x0000b108, 0x067e067f},
+- {0x0000b10c, 0x07410742},
+- {0x0000b110, 0x075f0740},
+- {0x0000b114, 0x077f0760},
+- {0x0000b118, 0x07800781},
+- {0x0000b11c, 0x07a0079f},
+- {0x0000b120, 0x07c107bf},
+- {0x0000b124, 0x000007c0},
+- {0x0000b128, 0x00000000},
+- {0x0000b12c, 0x00000000},
+- {0x0000b130, 0x00000000},
+- {0x0000b134, 0x00000000},
+- {0x0000b138, 0x00000000},
+- {0x0000b13c, 0x00000000},
+- {0x0000b140, 0x003f0020},
+- {0x0000b144, 0x00400041},
+- {0x0000b148, 0x0140005f},
+- {0x0000b14c, 0x0160015f},
+- {0x0000b150, 0x017e017f},
+- {0x0000b154, 0x02410242},
+- {0x0000b158, 0x025f0240},
+- {0x0000b15c, 0x027f0260},
+- {0x0000b160, 0x0341027e},
+- {0x0000b164, 0x035f0340},
+- {0x0000b168, 0x037f0360},
+- {0x0000b16c, 0x04400441},
+- {0x0000b170, 0x0460045f},
+- {0x0000b174, 0x0541047f},
+- {0x0000b178, 0x055f0540},
+- {0x0000b17c, 0x057f0560},
+- {0x0000b180, 0x06400641},
+- {0x0000b184, 0x0660065f},
+- {0x0000b188, 0x067e067f},
+- {0x0000b18c, 0x07410742},
+- {0x0000b190, 0x075f0740},
+- {0x0000b194, 0x077f0760},
+- {0x0000b198, 0x07800781},
+- {0x0000b19c, 0x07a0079f},
+- {0x0000b1a0, 0x07c107bf},
+- {0x0000b1a4, 0x000007c0},
+- {0x0000b1a8, 0x00000000},
+- {0x0000b1ac, 0x00000000},
+- {0x0000b1b0, 0x00000000},
+- {0x0000b1b4, 0x00000000},
+- {0x0000b1b8, 0x00000000},
+- {0x0000b1bc, 0x00000000},
+- {0x0000b1c0, 0x00000000},
+- {0x0000b1c4, 0x00000000},
+- {0x0000b1c8, 0x00000000},
+- {0x0000b1cc, 0x00000000},
+- {0x0000b1d0, 0x00000000},
+- {0x0000b1d4, 0x00000000},
+- {0x0000b1d8, 0x00000000},
+- {0x0000b1dc, 0x00000000},
+- {0x0000b1e0, 0x00000000},
+- {0x0000b1e4, 0x00000000},
+- {0x0000b1e8, 0x00000000},
+- {0x0000b1ec, 0x00000000},
+- {0x0000b1f0, 0x00000396},
+- {0x0000b1f4, 0x00000396},
+- {0x0000b1f8, 0x00000396},
+- {0x0000b1fc, 0x00000196},
+-};
+-
+ static const u32 ar955x_1p0_soc_preamble[][2] = {
+ /* Addr allmodes */
+ {0x00007000, 0x00000000},
+@@ -1263,11 +744,6 @@ static const u32 ar955x_1p0_modes_no_xpa
+ {0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
+ };
+
+-static const u32 ar955x_1p0_soc_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
+-};
+-
+ static const u32 ar955x_1p0_modes_fast_clock[][3] = {
+ /* Addr 5G_HT20 5G_HT40 */
+ {0x00001030, 0x00000268, 0x000004d0},
+--- a/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
+@@ -20,6 +20,12 @@
+
+ /* AR9565 1.0 */
+
++#define ar9565_1p0_mac_postamble ar9331_1p1_mac_postamble
++
++#define ar9565_1p0_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
++
++#define ar9565_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
++
+ static const u32 ar9565_1p0_mac_core[][2] = {
+ /* Addr allmodes */
+ {0x00000008, 0x00000000},
+@@ -182,18 +188,6 @@ static const u32 ar9565_1p0_mac_core[][2
+ {0x000083d0, 0x800301ff},
+ };
+
+-static const u32 ar9565_1p0_mac_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+- {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+- {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+- {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+- {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+- {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+- {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+-};
+-
+ static const u32 ar9565_1p0_baseband_core[][2] = {
+ /* Addr allmodes */
+ {0x00009800, 0xafe68e30},
+@@ -711,66 +705,6 @@ static const u32 ar9565_1p0_Common_rx_ga
+ {0x0000b1fc, 0x00000196},
+ };
+
+-static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
+- {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
+- {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
+- {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
+- {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
+- {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
+- {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
+- {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
+- {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
+- {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
+- {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
+- {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
+- {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
+- {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
+- {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
+- {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
+- {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
+- {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
+- {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
+- {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
+- {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
+- {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
+- {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
+- {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
+- {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
+- {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
+- {0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+-};
+-
+ static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = {
+ /* Addr allmodes */
+ {0x00018c00, 0x18212ede},
+@@ -1231,11 +1165,4 @@ static const u32 ar9565_1p0_modes_high_p
+ {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ };
+
+-static const u32 ar9565_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
+- /* Addr allmodes */
+- {0x0000a398, 0x00000000},
+- {0x0000a39c, 0x6f7f0301},
+- {0x0000a3a0, 0xca9228ee},
+-};
+-
+ #endif /* INITVALS_9565_1P0_H */
+--- a/include/linux/ath9k_platform.h
++++ b/include/linux/ath9k_platform.h
+@@ -32,6 +32,8 @@ struct ath9k_platform_data {
+ u32 gpio_val;
+
+ bool is_clk_25mhz;
++ bool tx_gain_buffalo;
++
+ int (*get_mac_revision)(void);
+ int (*external_reset)(void);
+ };
+--- /dev/null
++++ b/drivers/net/wireless/ath/ath9k/ar9003_buffalo_initvals.h
+@@ -0,0 +1,126 @@
++/*
++ * Copyright (c) 2013 Qualcomm Atheros Inc.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef INITVALS_9003_BUFFALO_H
++#define INITVALS_9003_BUFFALO_H
++
++static const u32 ar9300Modes_high_power_tx_gain_table_buffalo[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
++ {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
++ {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
++ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
++ {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
++ {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
++ {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
++ {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
++ {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
++ {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
++ {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
++ {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
++ {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
++ {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
++ {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
++ {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
++ {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
++ {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
++ {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
++ {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
++ {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
++ {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
++ {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
++ {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
++ {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
++ {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
++ {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
++ {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
++ {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
++ {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
++ {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
++ {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
++ {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
++ {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
++ {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
++ {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
++ {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
++ {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
++ {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
++ {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
++ {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
++ {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
++ {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
++ {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
++ {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
++ {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
++ {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
++ {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
++ {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
++ {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
++ {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
++ {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
++ {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
++ {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
++ {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
++ {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
++ {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
++ {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
++ {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
++ {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
++ {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
++ {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
++ {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
++ {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
++ {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
++ {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
++ {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
++ {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
++ {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
++ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
++ {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
++ {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
++ {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
++ {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
++ {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
++ {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
++ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
++ {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
++ {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
++ {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
++ {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
++ {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
++ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
++};
++
++#endif /* INITVALS_9003_BUFFALO_H */
+--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+@@ -29,7 +29,8 @@ static void ar9002_hw_set_desc_link(void
+ ((struct ath_desc*) ds)->ds_link = ds_link;
+ }
+
+-static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
++static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked,
++ u32 *sync_cause_p)
+ {
+ u32 isr = 0;
+ u32 mask2 = 0;
+@@ -76,9 +77,16 @@ static bool ar9002_hw_get_isr(struct ath
+ mask2 |= ATH9K_INT_CST;
+ if (isr2 & AR_ISR_S2_TSFOOR)
+ mask2 |= ATH9K_INT_TSFOOR;
++
++ if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
++ REG_WRITE(ah, AR_ISR_S2, isr2);
++ isr &= ~AR_ISR_BCNMISC;
++ }
+ }
+
+- isr = REG_READ(ah, AR_ISR_RAC);
++ if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
++ isr = REG_READ(ah, AR_ISR_RAC);
++
+ if (isr == 0xffffffff) {
+ *masked = 0;
+ return false;
+@@ -97,11 +105,23 @@ static bool ar9002_hw_get_isr(struct ath
+
+ *masked |= ATH9K_INT_TX;
+
+- s0_s = REG_READ(ah, AR_ISR_S0_S);
++ if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
++ s0_s = REG_READ(ah, AR_ISR_S0_S);
++ s1_s = REG_READ(ah, AR_ISR_S1_S);
++ } else {
++ s0_s = REG_READ(ah, AR_ISR_S0);
++ REG_WRITE(ah, AR_ISR_S0, s0_s);
++ s1_s = REG_READ(ah, AR_ISR_S1);
++ REG_WRITE(ah, AR_ISR_S1, s1_s);
++
++ isr &= ~(AR_ISR_TXOK |
++ AR_ISR_TXDESC |
++ AR_ISR_TXERR |
++ AR_ISR_TXEOL);
++ }
++
+ ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
+ ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
+-
+- s1_s = REG_READ(ah, AR_ISR_S1_S);
+ ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
+ ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
+ }
+@@ -114,13 +134,23 @@ static bool ar9002_hw_get_isr(struct ath
+ *masked |= mask2;
+ }
+
++ if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
++ REG_WRITE(ah, AR_ISR, isr);
++ REG_READ(ah, AR_ISR);
++ }
++
+ if (AR_SREV_9100(ah))
+ return true;
+
+ if (isr & AR_ISR_GENTMR) {
+ u32 s5_s;
+
+- s5_s = REG_READ(ah, AR_ISR_S5_S);
++ if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
++ s5_s = REG_READ(ah, AR_ISR_S5_S);
++ } else {
++ s5_s = REG_READ(ah, AR_ISR_S5);
++ }
++
+ ah->intr_gen_timer_trigger =
+ MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
+
+@@ -133,10 +163,16 @@ static bool ar9002_hw_get_isr(struct ath
+ if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
+ !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
+ *masked |= ATH9K_INT_TIM_TIMER;
++
++ if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
++ REG_WRITE(ah, AR_ISR_S5, s5_s);
++ isr &= ~AR_ISR_GENTMR;
++ }
+ }
+
+ if (sync_cause) {
+- ath9k_debug_sync_cause(common, sync_cause);
++ if (sync_cause_p)
++ *sync_cause_p = sync_cause;
+ fatal_int =
+ (sync_cause &
+ (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
+--- a/drivers/net/wireless/ath/ath9k/antenna.c
++++ b/drivers/net/wireless/ath/ath9k/antenna.c
+@@ -724,14 +724,14 @@ void ath_ant_comb_scan(struct ath_softc
+ struct ath_ant_comb *antcomb = &sc->ant_comb;
+ int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
+ int curr_main_set;
+- int main_rssi = rs->rs_rssi_ctl0;
+- int alt_rssi = rs->rs_rssi_ctl1;
++ int main_rssi = rs->rs_rssi_ctl[0];
++ int alt_rssi = rs->rs_rssi_ctl[1];
+ int rx_ant_conf, main_ant_conf;
+ bool short_scan = false, ret;
+
+- rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
++ rx_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_CURRENT_SHIFT) &
+ ATH_ANT_RX_MASK;
+- main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
++ main_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_MAIN_SHIFT) &
+ ATH_ANT_RX_MASK;
+
+ if (alt_rssi >= antcomb->low_rssi_thresh) {
+--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+@@ -32,12 +32,8 @@ static int ar9002_hw_init_mode_regs(stru
+ return 0;
+ }
+
+- if (ah->config.pcie_clock_req)
+- INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9280PciePhy_clkreq_off_L1_9280);
+- else
+- INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9280PciePhy_clkreq_always_on_L1_9280);
++ INIT_INI_ARRAY(&ah->iniPcieSerdes,
++ ar9280PciePhy_clkreq_always_on_L1_9280);
+
+ if (AR_SREV_9287_11_OR_LATER(ah)) {
+ INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
+--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+@@ -201,7 +201,6 @@ static void ar9002_hw_spur_mitigate(stru
+ ath9k_hw_get_channel_centers(ah, chan, ¢ers);
+ freq = centers.synth_center;
+
+- ah->config.spurmode = SPUR_ENABLE_EEPROM;
+ for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+ cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+@@ -175,7 +175,8 @@ static void ar9003_hw_set_desc_link(void
+ ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
+ }
+
+-static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
++static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked,
++ u32 *sync_cause_p)
+ {
+ u32 isr = 0;
+ u32 mask2 = 0;
+@@ -310,7 +311,8 @@ static bool ar9003_hw_get_isr(struct ath
+ ar9003_mci_get_isr(ah, masked);
+
+ if (sync_cause) {
+- ath9k_debug_sync_cause(common, sync_cause);
++ if (sync_cause_p)
++ *sync_cause_p = sync_cause;
+ fatal_int =
+ (sync_cause &
+ (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
+@@ -476,12 +478,12 @@ int ath9k_hw_process_rxdesc_edma(struct
+
+ /* XXX: Keycache */
+ rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
+- rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
+- rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
+- rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
+- rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
+- rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
+- rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
++ rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_RxRSSIAnt00);
++ rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_RxRSSIAnt01);
++ rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_RxRSSIAnt02);
++ rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_RxRSSIAnt10);
++ rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_RxRSSIAnt11);
++ rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_RxRSSIAnt12);
+
+ if (rxsp->status11 & AR_RxKeyIdxValid)
+ rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
+--- a/drivers/net/wireless/ath/ath9k/beacon.c
++++ b/drivers/net/wireless/ath/ath9k/beacon.c
+@@ -274,18 +274,19 @@ static int ath9k_beacon_choose_slot(stru
+ return slot;
+ }
+
+-void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
++static void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
+ {
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+ struct ath_vif *avp = (void *)vif->drv_priv;
+- u64 tsfadjust;
++ u32 tsfadjust;
+
+ if (avp->av_bslot == 0)
+ return;
+
+- tsfadjust = cur_conf->beacon_interval * avp->av_bslot / ATH_BCBUF;
+- avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
++ tsfadjust = cur_conf->beacon_interval * avp->av_bslot;
++ tsfadjust = TU_TO_USEC(tsfadjust) / ATH_BCBUF;
++ avp->tsf_adjust = cpu_to_le64(tsfadjust);
+
+ ath_dbg(common, CONFIG, "tsfadjust is: %llu for bslot: %d\n",
+ (unsigned long long)tsfadjust, avp->av_bslot);
+@@ -431,6 +432,33 @@ static void ath9k_beacon_init(struct ath
+ ath9k_hw_enable_interrupts(ah);
+ }
+
++/* Calculate the modulo of a 64 bit TSF snapshot with a TU divisor */
++static u32 ath9k_mod_tsf64_tu(u64 tsf, u32 div_tu)
++{
++ u32 tsf_mod, tsf_hi, tsf_lo, mod_hi, mod_lo;
++
++ tsf_mod = tsf & (BIT(10) - 1);
++ tsf_hi = tsf >> 32;
++ tsf_lo = ((u32) tsf) >> 10;
++
++ mod_hi = tsf_hi % div_tu;
++ mod_lo = ((mod_hi << 22) + tsf_lo) % div_tu;
++
++ return (mod_lo << 10) | tsf_mod;
++}
++
++static u32 ath9k_get_next_tbtt(struct ath_softc *sc, u64 tsf,
++ unsigned int interval)
++{
++ struct ath_hw *ah = sc->sc_ah;
++ unsigned int offset;
++
++ tsf += TU_TO_USEC(FUDGE + ah->config.sw_beacon_response_time);
++ offset = ath9k_mod_tsf64_tu(tsf, interval);
++
++ return (u32) tsf + TU_TO_USEC(interval) - offset;
++}
++
+ /*
+ * For multi-bss ap support beacons are either staggered evenly over N slots or
+ * burst together. For the former arrange for the SWBA to be delivered for each
+@@ -446,7 +474,8 @@ static void ath9k_beacon_config_ap(struc
+ /* NB: the beacon interval is kept internally in TU's */
+ intval = TU_TO_USEC(conf->beacon_interval);
+ intval /= ATH_BCBUF;
+- nexttbtt = intval;
++ nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah),
++ conf->beacon_interval);
+
+ if (conf->enable_beacon)
+ ah->imask |= ATH9K_INT_SWBA;
+@@ -458,7 +487,7 @@ static void ath9k_beacon_config_ap(struc
+ (conf->enable_beacon) ? "Enable" : "Disable",
+ nexttbtt, intval, conf->beacon_interval);
+
+- ath9k_beacon_init(sc, nexttbtt, intval, true);
++ ath9k_beacon_init(sc, nexttbtt, intval, false);
+ }
+
+ /*
+@@ -475,11 +504,9 @@ static void ath9k_beacon_config_sta(stru
+ struct ath_hw *ah = sc->sc_ah;
+ struct ath_common *common = ath9k_hw_common(ah);
+ struct ath9k_beacon_state bs;
+- int dtimperiod, dtimcount, sleepduration;
+- int cfpperiod, cfpcount;
+- u32 nexttbtt = 0, intval, tsftu;
++ int dtim_intval, sleepduration;
++ u32 nexttbtt = 0, intval;
+ u64 tsf;
+- int num_beacons, offset, dtim_dec_count, cfp_dec_count;
+
+ /* No need to configure beacon if we are not associated */
+ if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
+@@ -492,53 +519,25 @@ static void ath9k_beacon_config_sta(stru
+ intval = conf->beacon_interval;
+
+ /*
+- * Setup dtim and cfp parameters according to
++ * Setup dtim parameters according to
+ * last beacon we received (which may be none).
+ */
+- dtimperiod = conf->dtim_period;
+- dtimcount = conf->dtim_count;
+- if (dtimcount >= dtimperiod) /* NB: sanity check */
+- dtimcount = 0;
+- cfpperiod = 1; /* NB: no PCF support yet */
+- cfpcount = 0;
+-
++ dtim_intval = intval * conf->dtim_period;
+ sleepduration = conf->listen_interval * intval;
+
+ /*
+ * Pull nexttbtt forward to reflect the current
+- * TSF and calculate dtim+cfp state for the result.
++ * TSF and calculate dtim state for the result.
+ */
+ tsf = ath9k_hw_gettsf64(ah);
+- tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
++ nexttbtt = ath9k_get_next_tbtt(sc, tsf, intval);
+
+- num_beacons = tsftu / intval + 1;
+- offset = tsftu % intval;
+- nexttbtt = tsftu - offset;
+- if (offset)
+- nexttbtt += intval;
+-
+- /* DTIM Beacon every dtimperiod Beacon */
+- dtim_dec_count = num_beacons % dtimperiod;
+- /* CFP every cfpperiod DTIM Beacon */
+- cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod;
+- if (dtim_dec_count)
+- cfp_dec_count++;
+-
+- dtimcount -= dtim_dec_count;
+- if (dtimcount < 0)
+- dtimcount += dtimperiod;
+-
+- cfpcount -= cfp_dec_count;
+- if (cfpcount < 0)
+- cfpcount += cfpperiod;
+-
+- bs.bs_intval = intval;
++ bs.bs_intval = TU_TO_USEC(intval);
++ bs.bs_dtimperiod = conf->dtim_period * bs.bs_intval;
+ bs.bs_nexttbtt = nexttbtt;
+- bs.bs_dtimperiod = dtimperiod*intval;
+- bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
+- bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
+- bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
+- bs.bs_cfpmaxduration = 0;
++ bs.bs_nextdtim = nexttbtt;
++ if (conf->dtim_period > 1)
++ bs.bs_nextdtim = ath9k_get_next_tbtt(sc, tsf, dtim_intval);
+
+ /*
+ * Calculate the number of consecutive beacons to miss* before taking
+@@ -566,18 +565,16 @@ static void ath9k_beacon_config_sta(stru
+ * XXX fixed at 100ms
+ */
+
+- bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration);
++ bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100),
++ sleepduration));
+ if (bs.bs_sleepduration > bs.bs_dtimperiod)
+ bs.bs_sleepduration = bs.bs_dtimperiod;
+
+ /* TSF out of range threshold fixed at 1 second */
+ bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
+
+- ath_dbg(common, BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
+- ath_dbg(common, BEACON,
+- "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
+- bs.bs_bmissthreshold, bs.bs_sleepduration,
+- bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
++ ath_dbg(common, BEACON, "bmiss: %u sleep: %u\n",
++ bs.bs_bmissthreshold, bs.bs_sleepduration);
+
+ /* Set the computed STA beacon timers */
+
+@@ -600,25 +597,11 @@ static void ath9k_beacon_config_adhoc(st
+
+ intval = TU_TO_USEC(conf->beacon_interval);
+
+- if (conf->ibss_creator) {
++ if (conf->ibss_creator)
+ nexttbtt = intval;
+- } else {
+- u32 tbtt, offset, tsftu;
+- u64 tsf;
+-
+- /*
+- * Pull nexttbtt forward to reflect the current
+- * sync'd TSF.
+- */
+- tsf = ath9k_hw_gettsf64(ah);
+- tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE;
+- offset = tsftu % conf->beacon_interval;
+- tbtt = tsftu - offset;
+- if (offset)
+- tbtt += conf->beacon_interval;
+-
+- nexttbtt = TU_TO_USEC(tbtt);
+- }
++ else
++ nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah),
++ conf->beacon_interval);
+
+ if (conf->enable_beacon)
+ ah->imask |= ATH9K_INT_SWBA;
+@@ -640,7 +623,8 @@ static void ath9k_beacon_config_adhoc(st
+ set_bit(SC_OP_BEACONS, &sc->sc_flags);
+ }
+
+-bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
++static bool ath9k_allow_beacon_config(struct ath_softc *sc,
++ struct ieee80211_vif *vif)
+ {
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ath_vif *avp = (void *)vif->drv_priv;
+@@ -711,12 +695,17 @@ void ath9k_beacon_config(struct ath_soft
+ unsigned long flags;
+ bool skip_beacon = false;
+
++ if (vif->type == NL80211_IFTYPE_AP)
++ ath9k_set_tsfadjust(sc, vif);
++
++ if (!ath9k_allow_beacon_config(sc, vif))
++ return;
++
+ if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
+ ath9k_cache_beacon_config(sc, bss_conf);
+ ath9k_set_beacon(sc);
+ set_bit(SC_OP_BEACONS, &sc->sc_flags);
+ return;
+-
+ }
+
+ /*
+--- a/drivers/net/wireless/ath/ath9k/btcoex.c
++++ b/drivers/net/wireless/ath/ath9k/btcoex.c
+@@ -66,7 +66,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_
+ .bt_first_slot_time = 5,
+ .bt_hold_rx_clear = true,
+ };
+- u32 i, idx;
+ bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
+
+ if (AR_SREV_9300_20_OR_LATER(ah))
+@@ -88,11 +87,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_
+ SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
+ SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
+ AR_BT_DISABLE_BT_ANT;
+-
+- for (i = 0; i < 32; i++) {
+- idx = (debruijn32 << i) >> 27;
+- ah->hw_gen_timers.gen_timer_index[idx] = i;
+- }
+ }
+ EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
+
+--- a/drivers/net/wireless/ath/ath9k/dfs.c
++++ b/drivers/net/wireless/ath/ath9k/dfs.c
+@@ -158,8 +158,8 @@ void ath9k_dfs_process_phyerr(struct ath
+ return;
+ }
+
+- ard.rssi = rs->rs_rssi_ctl0;
+- ard.ext_rssi = rs->rs_rssi_ext0;
++ ard.rssi = rs->rs_rssi_ctl[0];
++ ard.ext_rssi = rs->rs_rssi_ext[0];
+
+ /*
+ * hardware stores this as 8 bit signed value.
+--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
++++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+@@ -1085,31 +1085,7 @@ static void ath9k_hw_4k_set_board_values
+
+ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
+ {
+-#define EEP_MAP4K_SPURCHAN \
+- (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
+- struct ath_common *common = ath9k_hw_common(ah);
+-
+- u16 spur_val = AR_NO_SPUR;
+-
+- ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
+- i, is2GHz, ah->config.spurchans[i][is2GHz]);
+-
+- switch (ah->config.spurmode) {
+- case SPUR_DISABLE:
+- break;
+- case SPUR_ENABLE_IOCTL:
+- spur_val = ah->config.spurchans[i][is2GHz];
+- ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
+- spur_val);
+- break;
+- case SPUR_ENABLE_EEPROM:
+- spur_val = EEP_MAP4K_SPURCHAN;
+- break;
+- }
+-
+- return spur_val;
+-
+-#undef EEP_MAP4K_SPURCHAN
++ return ah->eeprom.map4k.modalHeader.spurChans[i].spurChan;
+ }
+
+ const struct eeprom_ops eep_4k_ops = {
+--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
++++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+@@ -1004,31 +1004,7 @@ static void ath9k_hw_ar9287_set_board_va
+ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
+ u16 i, bool is2GHz)
+ {
+-#define EEP_MAP9287_SPURCHAN \
+- (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
+-
+- struct ath_common *common = ath9k_hw_common(ah);
+- u16 spur_val = AR_NO_SPUR;
+-
+- ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
+- i, is2GHz, ah->config.spurchans[i][is2GHz]);
+-
+- switch (ah->config.spurmode) {
+- case SPUR_DISABLE:
+- break;
+- case SPUR_ENABLE_IOCTL:
+- spur_val = ah->config.spurchans[i][is2GHz];
+- ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
+- spur_val);
+- break;
+- case SPUR_ENABLE_EEPROM:
+- spur_val = EEP_MAP9287_SPURCHAN;
+- break;
+- }
+-
+- return spur_val;
+-
+-#undef EEP_MAP9287_SPURCHAN
++ return ah->eeprom.map9287.modalHeader.spurChans[i].spurChan;
+ }
+
+ const struct eeprom_ops eep_ar9287_ops = {
+--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
++++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
+@@ -1348,31 +1348,7 @@ static void ath9k_hw_def_set_txpower(str
+
+ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
+ {
+-#define EEP_DEF_SPURCHAN \
+- (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
+- struct ath_common *common = ath9k_hw_common(ah);
+-
+- u16 spur_val = AR_NO_SPUR;
+-
+- ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
+- i, is2GHz, ah->config.spurchans[i][is2GHz]);
+-
+- switch (ah->config.spurmode) {
+- case SPUR_DISABLE:
+- break;
+- case SPUR_ENABLE_IOCTL:
+- spur_val = ah->config.spurchans[i][is2GHz];
+- ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
+- spur_val);
+- break;
+- case SPUR_ENABLE_EEPROM:
+- spur_val = EEP_DEF_SPURCHAN;
+- break;
+- }
+-
+- return spur_val;
+-
+-#undef EEP_DEF_SPURCHAN
++ return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
+ }
+
+ const struct eeprom_ops eep_def_ops = {
+--- a/drivers/net/wireless/ath/ath9k/gpio.c
++++ b/drivers/net/wireless/ath/ath9k/gpio.c
+@@ -157,36 +157,6 @@ static void ath_detect_bt_priority(struc
+ }
+ }
+
+-static void ath9k_gen_timer_start(struct ath_hw *ah,
+- struct ath_gen_timer *timer,
+- u32 trig_timeout,
+- u32 timer_period)
+-{
+- ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period);
+-
+- if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
+- ath9k_hw_disable_interrupts(ah);
+- ah->imask |= ATH9K_INT_GENTIMER;
+- ath9k_hw_set_interrupts(ah);
+- ath9k_hw_enable_interrupts(ah);
+- }
+-}
+-
+-static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
+-{
+- struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+-
+- ath9k_hw_gen_timer_stop(ah, timer);
+-
+- /* if no timer is enabled, turn off interrupt mask */
+- if (timer_table->timer_mask.val == 0) {
+- ath9k_hw_disable_interrupts(ah);
+- ah->imask &= ~ATH9K_INT_GENTIMER;
+- ath9k_hw_set_interrupts(ah);
+- ath9k_hw_enable_interrupts(ah);
+- }
+-}
+-
+ static void ath_mci_ftp_adjust(struct ath_softc *sc)
+ {
+ struct ath_btcoex *btcoex = &sc->btcoex;
+@@ -257,19 +227,9 @@ static void ath_btcoex_period_timer(unsi
+
+ spin_unlock_bh(&btcoex->btcoex_lock);
+
+- /*
+- * btcoex_period is in msec while (btocex/btscan_)no_stomp are in usec,
+- * ensure that we properly convert btcoex_period to usec
+- * for any comparision with (btcoex/btscan_)no_stomp.
+- */
+- if (btcoex->btcoex_period * 1000 != btcoex->btcoex_no_stomp) {
+- if (btcoex->hw_timer_enabled)
+- ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
+-
+- ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period,
+- timer_period * 10);
+- btcoex->hw_timer_enabled = true;
+- }
++ if (btcoex->btcoex_period != btcoex->btcoex_no_stomp)
++ mod_timer(&btcoex->no_stomp_timer,
++ jiffies + msecs_to_jiffies(timer_period));
+
+ ath9k_ps_restore(sc);
+
+@@ -282,7 +242,7 @@ skip_hw_wakeup:
+ * Generic tsf based hw timer which configures weight
+ * registers to time slice between wlan and bt traffic
+ */
+-static void ath_btcoex_no_stomp_timer(void *arg)
++static void ath_btcoex_no_stomp_timer(unsigned long arg)
+ {
+ struct ath_softc *sc = (struct ath_softc *)arg;
+ struct ath_hw *ah = sc->sc_ah;
+@@ -311,24 +271,18 @@ static int ath_init_btcoex_timer(struct
+ struct ath_btcoex *btcoex = &sc->btcoex;
+
+ btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD;
+- btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 1000 *
++ btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
+ btcoex->btcoex_period / 100;
+- btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 1000 *
++ btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) *
+ btcoex->btcoex_period / 100;
+
+ setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
+ (unsigned long) sc);
++ setup_timer(&btcoex->no_stomp_timer, ath_btcoex_no_stomp_timer,
++ (unsigned long) sc);
+
+ spin_lock_init(&btcoex->btcoex_lock);
+
+- btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
+- ath_btcoex_no_stomp_timer,
+- ath_btcoex_no_stomp_timer,
+- (void *) sc, AR_FIRST_NDP_TIMER);
+-
+- if (!btcoex->no_stomp_timer)
+- return -ENOMEM;
+-
+ return 0;
+ }
+
+@@ -343,10 +297,7 @@ void ath9k_btcoex_timer_resume(struct at
+ ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n");
+
+ /* make sure duty cycle timer is also stopped when resuming */
+- if (btcoex->hw_timer_enabled) {
+- ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
+- btcoex->hw_timer_enabled = false;
+- }
++ del_timer_sync(&btcoex->no_stomp_timer);
+
+ btcoex->bt_priority_cnt = 0;
+ btcoex->bt_priority_time = jiffies;
+@@ -363,24 +314,16 @@ void ath9k_btcoex_timer_resume(struct at
+ void ath9k_btcoex_timer_pause(struct ath_softc *sc)
+ {
+ struct ath_btcoex *btcoex = &sc->btcoex;
+- struct ath_hw *ah = sc->sc_ah;
+
+ del_timer_sync(&btcoex->period_timer);
+-
+- if (btcoex->hw_timer_enabled) {
+- ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
+- btcoex->hw_timer_enabled = false;
+- }
++ del_timer_sync(&btcoex->no_stomp_timer);
+ }
+
+ void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
+ {
+ struct ath_btcoex *btcoex = &sc->btcoex;
+
+- if (btcoex->hw_timer_enabled) {
+- ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
+- btcoex->hw_timer_enabled = false;
+- }
++ del_timer_sync(&btcoex->no_stomp_timer);
+ }
+
+ u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen)
+@@ -400,12 +343,6 @@ u16 ath9k_btcoex_aggr_limit(struct ath_s
+
+ void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status)
+ {
+- struct ath_hw *ah = sc->sc_ah;
+-
+- if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
+- if (status & ATH9K_INT_GENTIMER)
+- ath_gen_timer_isr(sc->sc_ah);
+-
+ if (status & ATH9K_INT_MCI)
+ ath_mci_intr(sc);
+ }
+@@ -447,10 +384,6 @@ void ath9k_deinit_btcoex(struct ath_soft
+ {
+ struct ath_hw *ah = sc->sc_ah;
+
+- if ((sc->btcoex.no_stomp_timer) &&
+- ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE)
+- ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
+-
+ if (ath9k_hw_mci_is_enabled(ah))
+ ath_mci_cleanup(sc);
+ }
+--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
++++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+@@ -70,11 +70,11 @@ static void ath9k_htc_beacon_config_sta(
+ struct ath9k_beacon_state bs;
+ enum ath9k_int imask = 0;
+ int dtimperiod, dtimcount, sleepduration;
+- int cfpperiod, cfpcount, bmiss_timeout;
++ int bmiss_timeout;
+ u32 nexttbtt = 0, intval, tsftu;
+ __be32 htc_imask = 0;
+ u64 tsf;
+- int num_beacons, offset, dtim_dec_count, cfp_dec_count;
++ int num_beacons, offset, dtim_dec_count;
+ int ret __attribute__ ((unused));
+ u8 cmd_rsp;
+
+@@ -84,7 +84,7 @@ static void ath9k_htc_beacon_config_sta(
+ bmiss_timeout = (ATH_DEFAULT_BMISS_LIMIT * bss_conf->beacon_interval);
+
+ /*
+- * Setup dtim and cfp parameters according to
++ * Setup dtim parameters according to
+ * last beacon we received (which may be none).
+ */
+ dtimperiod = bss_conf->dtim_period;
+@@ -93,8 +93,6 @@ static void ath9k_htc_beacon_config_sta(
+ dtimcount = 1;
+ if (dtimcount >= dtimperiod) /* NB: sanity check */
+ dtimcount = 0;
+- cfpperiod = 1; /* NB: no PCF support yet */
+- cfpcount = 0;
+
+ sleepduration = intval;
+ if (sleepduration <= 0)
+@@ -102,7 +100,7 @@ static void ath9k_htc_beacon_config_sta(
+
+ /*
+ * Pull nexttbtt forward to reflect the current
+- * TSF and calculate dtim+cfp state for the result.
++ * TSF and calculate dtim state for the result.
+ */
+ tsf = ath9k_hw_gettsf64(priv->ah);
+ tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
+@@ -115,26 +113,14 @@ static void ath9k_htc_beacon_config_sta(
+
+ /* DTIM Beacon every dtimperiod Beacon */
+ dtim_dec_count = num_beacons % dtimperiod;
+- /* CFP every cfpperiod DTIM Beacon */
+- cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod;
+- if (dtim_dec_count)
+- cfp_dec_count++;
+-
+ dtimcount -= dtim_dec_count;
+ if (dtimcount < 0)
+ dtimcount += dtimperiod;
+
+- cfpcount -= cfp_dec_count;
+- if (cfpcount < 0)
+- cfpcount += cfpperiod;
+-
+- bs.bs_intval = intval;
+- bs.bs_nexttbtt = nexttbtt;
+- bs.bs_dtimperiod = dtimperiod*intval;
+- bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
+- bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
+- bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
+- bs.bs_cfpmaxduration = 0;
++ bs.bs_intval = TU_TO_USEC(intval);
++ bs.bs_nexttbtt = TU_TO_USEC(nexttbtt);
++ bs.bs_dtimperiod = dtimperiod * bs.bs_intval;
++ bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount * bs.bs_intval;
+
+ /*
+ * Calculate the number of consecutive beacons to miss* before taking
+@@ -161,7 +147,8 @@ static void ath9k_htc_beacon_config_sta(
+ * XXX fixed at 100ms
+ */
+
+- bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration);
++ bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100),
++ sleepduration));
+ if (bs.bs_sleepduration > bs.bs_dtimperiod)
+ bs.bs_sleepduration = bs.bs_dtimperiod;
+
+@@ -170,10 +157,8 @@ static void ath9k_htc_beacon_config_sta(
+
+ ath_dbg(common, CONFIG, "intval: %u tsf: %llu tsftu: %u\n",
+ intval, tsf, tsftu);
+- ath_dbg(common, CONFIG,
+- "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
+- bs.bs_bmissthreshold, bs.bs_sleepduration,
+- bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
++ ath_dbg(common, CONFIG, "bmiss: %u sleep: %u\n",
++ bs.bs_bmissthreshold, bs.bs_sleepduration);
+
+ /* Set the computed STA beacon timers */
+
+--- a/drivers/net/wireless/ath/ath9k/mac.c
++++ b/drivers/net/wireless/ath/ath9k/mac.c
+@@ -481,8 +481,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw
+ | AR_Q_MISC_CBR_INCR_DIS0);
+ value = (qi->tqi_readyTime -
+ (ah->config.sw_beacon_response_time -
+- ah->config.dma_beacon_response_time) -
+- ah->config.additional_swba_backoff) * 1024;
++ ah->config.dma_beacon_response_time)) * 1024;
+ REG_WRITE(ah, AR_QRDYTIMECFG(q),
+ value | AR_Q_RDYTIMECFG_EN);
+ REG_SET_BIT(ah, AR_DMISC(q),
+@@ -550,25 +549,25 @@ int ath9k_hw_rxprocdesc(struct ath_hw *a
+
+ if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
+ rs->rs_rssi = ATH9K_RSSI_BAD;
+- rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
+- rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
+- rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
+- rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
+- rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
+- rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
++ rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD;
++ rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD;
++ rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD;
++ rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD;
++ rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD;
++ rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD;
+ } else {
+ rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
+- rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
++ rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0,
+ AR_RxRSSIAnt00);
+- rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
++ rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0,
+ AR_RxRSSIAnt01);
+- rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
++ rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0,
+ AR_RxRSSIAnt02);
+- rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
++ rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4,
+ AR_RxRSSIAnt10);
+- rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
++ rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4,
+ AR_RxRSSIAnt11);
+- rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
++ rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4,
+ AR_RxRSSIAnt12);
+ }
+ if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
+--- a/drivers/net/wireless/ath/ath9k/mac.h
++++ b/drivers/net/wireless/ath/ath9k/mac.h
+@@ -133,12 +133,8 @@ struct ath_rx_status {
+ u8 rs_rate;
+ u8 rs_antenna;
+ u8 rs_more;
+- int8_t rs_rssi_ctl0;
+- int8_t rs_rssi_ctl1;
+- int8_t rs_rssi_ctl2;
+- int8_t rs_rssi_ext0;
+- int8_t rs_rssi_ext1;
+- int8_t rs_rssi_ext2;
++ int8_t rs_rssi_ctl[3];
++ int8_t rs_rssi_ext[3];
+ u8 rs_isaggr;
+ u8 rs_firstaggr;
+ u8 rs_moreaggr;
+--- a/drivers/net/wireless/ath/ath9k/mci.c
++++ b/drivers/net/wireless/ath/ath9k/mci.c
+@@ -200,7 +200,7 @@ skip_tuning:
+ if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
+ btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
+
+- btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
++ btcoex->btcoex_no_stomp = btcoex->btcoex_period *
+ (100 - btcoex->duty_cycle) / 100;
+
+ ath9k_hw_btcoex_enable(sc->sc_ah);
+--- a/drivers/net/wireless/ath/ath9k/recv.c
++++ b/drivers/net/wireless/ath/ath9k/recv.c
+@@ -15,7 +15,6 @@
+ */
+
+ #include <linux/dma-mapping.h>
+-#include <linux/relay.h>
+ #include "ath9k.h"
+ #include "ar9003_mac.h"
+
+@@ -906,6 +905,7 @@ static void ath9k_process_rssi(struct at
+ struct ath_hw *ah = common->ah;
+ int last_rssi;
+ int rssi = rx_stats->rs_rssi;
++ int i, j;
+
+ /*
+ * RSSI is not available for subframes in an A-MPDU.
+@@ -924,6 +924,20 @@ static void ath9k_process_rssi(struct at
+ return;
+ }
+
++ for (i = 0, j = 0; i < ARRAY_SIZE(rx_stats->rs_rssi_ctl); i++) {
++ s8 rssi;
++
++ if (!(ah->rxchainmask & BIT(i)))
++ continue;
++
++ rssi = rx_stats->rs_rssi_ctl[i];
++ if (rssi != ATH9K_RSSI_BAD) {
++ rxs->chains |= BIT(j);
++ rxs->chain_signal[j] = ah->noise + rssi;
++ }
++ j++;
++ }
++
+ /*
+ * Update Beacon RSSI, this is used by ANI.
+ */
+@@ -960,186 +974,6 @@ static void ath9k_process_tsf(struct ath
+ rxs->mactime += 0x100000000ULL;
+ }
+
+-#ifdef CPTCFG_ATH9K_DEBUGFS
+-static s8 fix_rssi_inv_only(u8 rssi_val)
+-{
+- if (rssi_val == 128)
+- rssi_val = 0;
+- return (s8) rssi_val;
+-}
+-#endif
+-
+-/* returns 1 if this was a spectral frame, even if not handled. */
+-static int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
+- struct ath_rx_status *rs, u64 tsf)
+-{
+-#ifdef CPTCFG_ATH9K_DEBUGFS
+- struct ath_hw *ah = sc->sc_ah;
+- u8 num_bins, *bins, *vdata = (u8 *)hdr;
+- struct fft_sample_ht20 fft_sample_20;
+- struct fft_sample_ht20_40 fft_sample_40;
+- struct fft_sample_tlv *tlv;
+- struct ath_radar_info *radar_info;
+- int len = rs->rs_datalen;
+- int dc_pos;
+- u16 fft_len, length, freq = ah->curchan->chan->center_freq;
+- enum nl80211_channel_type chan_type;
+-
+- /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer
+- * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT
+- * yet, but this is supposed to be possible as well.
+- */
+- if (rs->rs_phyerr != ATH9K_PHYERR_RADAR &&
+- rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT &&
+- rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL)
+- return 0;
+-
+- /* check if spectral scan bit is set. This does not have to be checked
+- * if received through a SPECTRAL phy error, but shouldn't hurt.
+- */
+- radar_info = ((struct ath_radar_info *)&vdata[len]) - 1;
+- if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK))
+- return 0;
+-
+- chan_type = cfg80211_get_chandef_type(&sc->hw->conf.chandef);
+- if ((chan_type == NL80211_CHAN_HT40MINUS) ||
+- (chan_type == NL80211_CHAN_HT40PLUS)) {
+- fft_len = SPECTRAL_HT20_40_TOTAL_DATA_LEN;
+- num_bins = SPECTRAL_HT20_40_NUM_BINS;
+- bins = (u8 *)fft_sample_40.data;
+- } else {
+- fft_len = SPECTRAL_HT20_TOTAL_DATA_LEN;
+- num_bins = SPECTRAL_HT20_NUM_BINS;
+- bins = (u8 *)fft_sample_20.data;
+- }
+-
+- /* Variation in the data length is possible and will be fixed later */
+- if ((len > fft_len + 2) || (len < fft_len - 1))
+- return 1;
+-
+- switch (len - fft_len) {
+- case 0:
+- /* length correct, nothing to do. */
+- memcpy(bins, vdata, num_bins);
+- break;
+- case -1:
+- /* first byte missing, duplicate it. */
+- memcpy(&bins[1], vdata, num_bins - 1);
+- bins[0] = vdata[0];
+- break;
+- case 2:
+- /* MAC added 2 extra bytes at bin 30 and 32, remove them. */
+- memcpy(bins, vdata, 30);
+- bins[30] = vdata[31];
+- memcpy(&bins[31], &vdata[33], num_bins - 31);
+- break;
+- case 1:
+- /* MAC added 2 extra bytes AND first byte is missing. */
+- bins[0] = vdata[0];
+- memcpy(&bins[1], vdata, 30);
+- bins[31] = vdata[31];
+- memcpy(&bins[32], &vdata[33], num_bins - 32);
+- break;
+- default:
+- return 1;
+- }
+-
+- /* DC value (value in the middle) is the blind spot of the spectral
+- * sample and invalid, interpolate it.
+- */
+- dc_pos = num_bins / 2;
+- bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2;
+-
+- if ((chan_type == NL80211_CHAN_HT40MINUS) ||
+- (chan_type == NL80211_CHAN_HT40PLUS)) {
+- s8 lower_rssi, upper_rssi;
+- s16 ext_nf;
+- u8 lower_max_index, upper_max_index;
+- u8 lower_bitmap_w, upper_bitmap_w;
+- u16 lower_mag, upper_mag;
+- struct ath9k_hw_cal_data *caldata = ah->caldata;
+- struct ath_ht20_40_mag_info *mag_info;
+-
+- if (caldata)
+- ext_nf = ath9k_hw_getchan_noise(ah, ah->curchan,
+- caldata->nfCalHist[3].privNF);
+- else
+- ext_nf = ATH_DEFAULT_NOISE_FLOOR;
+-
+- length = sizeof(fft_sample_40) - sizeof(struct fft_sample_tlv);
+- fft_sample_40.tlv.type = ATH_FFT_SAMPLE_HT20_40;
+- fft_sample_40.tlv.length = __cpu_to_be16(length);
+- fft_sample_40.freq = __cpu_to_be16(freq);
+- fft_sample_40.channel_type = chan_type;
+-
+- if (chan_type == NL80211_CHAN_HT40PLUS) {
+- lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
+- upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
+-
+- fft_sample_40.lower_noise = ah->noise;
+- fft_sample_40.upper_noise = ext_nf;
+- } else {
+- lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
+- upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
+-
+- fft_sample_40.lower_noise = ext_nf;
+- fft_sample_40.upper_noise = ah->noise;
+- }
+- fft_sample_40.lower_rssi = lower_rssi;
+- fft_sample_40.upper_rssi = upper_rssi;
+-
+- mag_info = ((struct ath_ht20_40_mag_info *)radar_info) - 1;
+- lower_mag = spectral_max_magnitude(mag_info->lower_bins);
+- upper_mag = spectral_max_magnitude(mag_info->upper_bins);
+- fft_sample_40.lower_max_magnitude = __cpu_to_be16(lower_mag);
+- fft_sample_40.upper_max_magnitude = __cpu_to_be16(upper_mag);
+- lower_max_index = spectral_max_index(mag_info->lower_bins);
+- upper_max_index = spectral_max_index(mag_info->upper_bins);
+- fft_sample_40.lower_max_index = lower_max_index;
+- fft_sample_40.upper_max_index = upper_max_index;
+- lower_bitmap_w = spectral_bitmap_weight(mag_info->lower_bins);
+- upper_bitmap_w = spectral_bitmap_weight(mag_info->upper_bins);
+- fft_sample_40.lower_bitmap_weight = lower_bitmap_w;
+- fft_sample_40.upper_bitmap_weight = upper_bitmap_w;
+- fft_sample_40.max_exp = mag_info->max_exp & 0xf;
+-
+- fft_sample_40.tsf = __cpu_to_be64(tsf);
+-
+- tlv = (struct fft_sample_tlv *)&fft_sample_40;
+- } else {
+- u8 max_index, bitmap_w;
+- u16 magnitude;
+- struct ath_ht20_mag_info *mag_info;
+-
+- length = sizeof(fft_sample_20) - sizeof(struct fft_sample_tlv);
+- fft_sample_20.tlv.type = ATH_FFT_SAMPLE_HT20;
+- fft_sample_20.tlv.length = __cpu_to_be16(length);
+- fft_sample_20.freq = __cpu_to_be16(freq);
+-
+- fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
+- fft_sample_20.noise = ah->noise;
+-
+- mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;
+- magnitude = spectral_max_magnitude(mag_info->all_bins);
+- fft_sample_20.max_magnitude = __cpu_to_be16(magnitude);
+- max_index = spectral_max_index(mag_info->all_bins);
+- fft_sample_20.max_index = max_index;
+- bitmap_w = spectral_bitmap_weight(mag_info->all_bins);
+- fft_sample_20.bitmap_weight = bitmap_w;
+- fft_sample_20.max_exp = mag_info->max_exp & 0xf;
+-
+- fft_sample_20.tsf = __cpu_to_be64(tsf);
+-
+- tlv = (struct fft_sample_tlv *)&fft_sample_20;
+- }
+-
+- ath_debug_send_fft_sample(sc, tlv);
+- return 1;
+-#else
+- return 0;
+-#endif
+-}
+-
+ static bool ath9k_is_mybeacon(struct ath_softc *sc, struct ieee80211_hdr *hdr)
+ {
+ struct ath_hw *ah = sc->sc_ah;
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+@@ -270,10 +270,20 @@ struct cal_ctl_data_5g {
+ u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
+ } __packed;
+
++#define MAX_BASE_EXTENSION_FUTURE 2
++
+ struct ar9300_BaseExtension_1 {
+ u8 ant_div_control;
+- u8 future[3];
+- u8 tempslopextension[8];
++ u8 future[MAX_BASE_EXTENSION_FUTURE];
++ /*
++ * misc_enable:
++ *
++ * BIT 0 - TX Gain Cap enable.
++ * BIT 1 - Uncompressed Checksum enable.
++ * BIT 2/3 - MinCCApwr enable 2g/5g.
++ */
++ u8 misc_enable;
++ int8_t tempslopextension[8];
+ int8_t quick_drop_low;
+ int8_t quick_drop_high;
+ } __packed;
+--- a/drivers/net/wireless/ath/ath9k/debug.h
++++ b/drivers/net/wireless/ath/ath9k/debug.h
+@@ -292,11 +292,11 @@ void ath9k_sta_add_debugfs(struct ieee80
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct dentry *dir);
+-void ath_debug_send_fft_sample(struct ath_softc *sc,
+- struct fft_sample_tlv *fft_sample);
+ void ath9k_debug_stat_ant(struct ath_softc *sc,
+ struct ath_hw_antcomb_conf *div_ant_conf,
+ int main_rssi_avg, int alt_rssi_avg);
++void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
++
+ #else
+
+ #define RX_STAT_INC(c) /* NOP */
+@@ -331,6 +331,11 @@ static inline void ath9k_debug_stat_ant(
+
+ }
+
++static inline void
++ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
++{
++}
++
+ #endif /* CPTCFG_ATH9K_DEBUGFS */
+
+ #endif /* DEBUG_H */
+--- /dev/null
++++ b/drivers/net/wireless/ath/ath9k/spectral.c
+@@ -0,0 +1,543 @@
++/*
++ * Copyright (c) 2013 Qualcomm Atheros, Inc.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/relay.h>
++#include "ath9k.h"
++
++static s8 fix_rssi_inv_only(u8 rssi_val)
++{
++ if (rssi_val == 128)
++ rssi_val = 0;
++ return (s8) rssi_val;
++}
++
++static void ath_debug_send_fft_sample(struct ath_softc *sc,
++ struct fft_sample_tlv *fft_sample_tlv)
++{
++ int length;
++ if (!sc->rfs_chan_spec_scan)
++ return;
++
++ length = __be16_to_cpu(fft_sample_tlv->length) +
++ sizeof(*fft_sample_tlv);
++ relay_write(sc->rfs_chan_spec_scan, fft_sample_tlv, length);
++}
++
++/* returns 1 if this was a spectral frame, even if not handled. */
++int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
++ struct ath_rx_status *rs, u64 tsf)
++{
++ struct ath_hw *ah = sc->sc_ah;
++ u8 num_bins, *bins, *vdata = (u8 *)hdr;
++ struct fft_sample_ht20 fft_sample_20;
++ struct fft_sample_ht20_40 fft_sample_40;
++ struct fft_sample_tlv *tlv;
++ struct ath_radar_info *radar_info;
++ int len = rs->rs_datalen;
++ int dc_pos;
++ u16 fft_len, length, freq = ah->curchan->chan->center_freq;
++ enum nl80211_channel_type chan_type;
++
++ /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer
++ * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT
++ * yet, but this is supposed to be possible as well.
++ */
++ if (rs->rs_phyerr != ATH9K_PHYERR_RADAR &&
++ rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT &&
++ rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL)
++ return 0;
++
++ /* check if spectral scan bit is set. This does not have to be checked
++ * if received through a SPECTRAL phy error, but shouldn't hurt.
++ */
++ radar_info = ((struct ath_radar_info *)&vdata[len]) - 1;
++ if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK))
++ return 0;
++
++ chan_type = cfg80211_get_chandef_type(&sc->hw->conf.chandef);
++ if ((chan_type == NL80211_CHAN_HT40MINUS) ||
++ (chan_type == NL80211_CHAN_HT40PLUS)) {
++ fft_len = SPECTRAL_HT20_40_TOTAL_DATA_LEN;
++ num_bins = SPECTRAL_HT20_40_NUM_BINS;
++ bins = (u8 *)fft_sample_40.data;
++ } else {
++ fft_len = SPECTRAL_HT20_TOTAL_DATA_LEN;
++ num_bins = SPECTRAL_HT20_NUM_BINS;
++ bins = (u8 *)fft_sample_20.data;
++ }
++
++ /* Variation in the data length is possible and will be fixed later */
++ if ((len > fft_len + 2) || (len < fft_len - 1))
++ return 1;
++
++ switch (len - fft_len) {
++ case 0:
++ /* length correct, nothing to do. */
++ memcpy(bins, vdata, num_bins);
++ break;
++ case -1:
++ /* first byte missing, duplicate it. */
++ memcpy(&bins[1], vdata, num_bins - 1);
++ bins[0] = vdata[0];
++ break;
++ case 2:
++ /* MAC added 2 extra bytes at bin 30 and 32, remove them. */
++ memcpy(bins, vdata, 30);
++ bins[30] = vdata[31];
++ memcpy(&bins[31], &vdata[33], num_bins - 31);
++ break;
++ case 1:
++ /* MAC added 2 extra bytes AND first byte is missing. */
++ bins[0] = vdata[0];
++ memcpy(&bins[1], vdata, 30);
++ bins[31] = vdata[31];
++ memcpy(&bins[32], &vdata[33], num_bins - 32);
++ break;
++ default:
++ return 1;
++ }
++
++ /* DC value (value in the middle) is the blind spot of the spectral
++ * sample and invalid, interpolate it.
++ */
++ dc_pos = num_bins / 2;
++ bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2;
++
++ if ((chan_type == NL80211_CHAN_HT40MINUS) ||
++ (chan_type == NL80211_CHAN_HT40PLUS)) {
++ s8 lower_rssi, upper_rssi;
++ s16 ext_nf;
++ u8 lower_max_index, upper_max_index;
++ u8 lower_bitmap_w, upper_bitmap_w;
++ u16 lower_mag, upper_mag;
++ struct ath9k_hw_cal_data *caldata = ah->caldata;
++ struct ath_ht20_40_mag_info *mag_info;
++
++ if (caldata)
++ ext_nf = ath9k_hw_getchan_noise(ah, ah->curchan,
++ caldata->nfCalHist[3].privNF);
++ else
++ ext_nf = ATH_DEFAULT_NOISE_FLOOR;
++
++ length = sizeof(fft_sample_40) - sizeof(struct fft_sample_tlv);
++ fft_sample_40.tlv.type = ATH_FFT_SAMPLE_HT20_40;
++ fft_sample_40.tlv.length = __cpu_to_be16(length);
++ fft_sample_40.freq = __cpu_to_be16(freq);
++ fft_sample_40.channel_type = chan_type;
++
++ if (chan_type == NL80211_CHAN_HT40PLUS) {
++ lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
++ upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]);
++
++ fft_sample_40.lower_noise = ah->noise;
++ fft_sample_40.upper_noise = ext_nf;
++ } else {
++ lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]);
++ upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
++
++ fft_sample_40.lower_noise = ext_nf;
++ fft_sample_40.upper_noise = ah->noise;
++ }
++ fft_sample_40.lower_rssi = lower_rssi;
++ fft_sample_40.upper_rssi = upper_rssi;
++
++ mag_info = ((struct ath_ht20_40_mag_info *)radar_info) - 1;
++ lower_mag = spectral_max_magnitude(mag_info->lower_bins);
++ upper_mag = spectral_max_magnitude(mag_info->upper_bins);
++ fft_sample_40.lower_max_magnitude = __cpu_to_be16(lower_mag);
++ fft_sample_40.upper_max_magnitude = __cpu_to_be16(upper_mag);
++ lower_max_index = spectral_max_index(mag_info->lower_bins);
++ upper_max_index = spectral_max_index(mag_info->upper_bins);
++ fft_sample_40.lower_max_index = lower_max_index;
++ fft_sample_40.upper_max_index = upper_max_index;
++ lower_bitmap_w = spectral_bitmap_weight(mag_info->lower_bins);
++ upper_bitmap_w = spectral_bitmap_weight(mag_info->upper_bins);
++ fft_sample_40.lower_bitmap_weight = lower_bitmap_w;
++ fft_sample_40.upper_bitmap_weight = upper_bitmap_w;
++ fft_sample_40.max_exp = mag_info->max_exp & 0xf;
++
++ fft_sample_40.tsf = __cpu_to_be64(tsf);
++
++ tlv = (struct fft_sample_tlv *)&fft_sample_40;
++ } else {
++ u8 max_index, bitmap_w;
++ u16 magnitude;
++ struct ath_ht20_mag_info *mag_info;
++
++ length = sizeof(fft_sample_20) - sizeof(struct fft_sample_tlv);
++ fft_sample_20.tlv.type = ATH_FFT_SAMPLE_HT20;
++ fft_sample_20.tlv.length = __cpu_to_be16(length);
++ fft_sample_20.freq = __cpu_to_be16(freq);
++
++ fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
++ fft_sample_20.noise = ah->noise;
++
++ mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;
++ magnitude = spectral_max_magnitude(mag_info->all_bins);
++ fft_sample_20.max_magnitude = __cpu_to_be16(magnitude);
++ max_index = spectral_max_index(mag_info->all_bins);
++ fft_sample_20.max_index = max_index;
++ bitmap_w = spectral_bitmap_weight(mag_info->all_bins);
++ fft_sample_20.bitmap_weight = bitmap_w;
++ fft_sample_20.max_exp = mag_info->max_exp & 0xf;
++
++ fft_sample_20.tsf = __cpu_to_be64(tsf);
++
++ tlv = (struct fft_sample_tlv *)&fft_sample_20;
++ }
++
++ ath_debug_send_fft_sample(sc, tlv);
++
++ return 1;
++}
++
++/*********************/
++/* spectral_scan_ctl */
++/*********************/
++
++static ssize_t read_file_spec_scan_ctl(struct file *file, char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ char *mode = "";
++ unsigned int len;
++
++ switch (sc->spectral_mode) {
++ case SPECTRAL_DISABLED:
++ mode = "disable";
++ break;
++ case SPECTRAL_BACKGROUND:
++ mode = "background";
++ break;
++ case SPECTRAL_CHANSCAN:
++ mode = "chanscan";
++ break;
++ case SPECTRAL_MANUAL:
++ mode = "manual";
++ break;
++ }
++ len = strlen(mode);
++ return simple_read_from_buffer(user_buf, count, ppos, mode, len);
++}
++
++static ssize_t write_file_spec_scan_ctl(struct file *file,
++ const char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
++ char buf[32];
++ ssize_t len;
++
++ if (config_enabled(CPTCFG_ATH9K_TX99))
++ return -EOPNOTSUPP;
++
++ len = min(count, sizeof(buf) - 1);
++ if (copy_from_user(buf, user_buf, len))
++ return -EFAULT;
++
++ buf[len] = '\0';
++
++ if (strncmp("trigger", buf, 7) == 0) {
++ ath9k_spectral_scan_trigger(sc->hw);
++ } else if (strncmp("background", buf, 9) == 0) {
++ ath9k_spectral_scan_config(sc->hw, SPECTRAL_BACKGROUND);
++ ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
++ } else if (strncmp("chanscan", buf, 8) == 0) {
++ ath9k_spectral_scan_config(sc->hw, SPECTRAL_CHANSCAN);
++ ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
++ } else if (strncmp("manual", buf, 6) == 0) {
++ ath9k_spectral_scan_config(sc->hw, SPECTRAL_MANUAL);
++ ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
++ } else if (strncmp("disable", buf, 7) == 0) {
++ ath9k_spectral_scan_config(sc->hw, SPECTRAL_DISABLED);
++ ath_dbg(common, CONFIG, "spectral scan: disabled\n");
++ } else {
++ return -EINVAL;
++ }
++
++ return count;
++}
++
++static const struct file_operations fops_spec_scan_ctl = {
++ .read = read_file_spec_scan_ctl,
++ .write = write_file_spec_scan_ctl,
++ .open = simple_open,
++ .owner = THIS_MODULE,
++ .llseek = default_llseek,
++};
++
++/*************************/
++/* spectral_short_repeat */
++/*************************/
++
++static ssize_t read_file_spectral_short_repeat(struct file *file,
++ char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ char buf[32];
++ unsigned int len;
++
++ len = sprintf(buf, "%d\n", sc->spec_config.short_repeat);
++ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
++}
++
++static ssize_t write_file_spectral_short_repeat(struct file *file,
++ const char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ unsigned long val;
++ char buf[32];
++ ssize_t len;
++
++ len = min(count, sizeof(buf) - 1);
++ if (copy_from_user(buf, user_buf, len))
++ return -EFAULT;
++
++ buf[len] = '\0';
++ if (kstrtoul(buf, 0, &val))
++ return -EINVAL;
++
++ if (val < 0 || val > 1)
++ return -EINVAL;
++
++ sc->spec_config.short_repeat = val;
++ return count;
++}
++
++static const struct file_operations fops_spectral_short_repeat = {
++ .read = read_file_spectral_short_repeat,
++ .write = write_file_spectral_short_repeat,
++ .open = simple_open,
++ .owner = THIS_MODULE,
++ .llseek = default_llseek,
++};
++
++/******************/
++/* spectral_count */
++/******************/
++
++static ssize_t read_file_spectral_count(struct file *file,
++ char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ char buf[32];
++ unsigned int len;
++
++ len = sprintf(buf, "%d\n", sc->spec_config.count);
++ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
++}
++
++static ssize_t write_file_spectral_count(struct file *file,
++ const char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ unsigned long val;
++ char buf[32];
++ ssize_t len;
++
++ len = min(count, sizeof(buf) - 1);
++ if (copy_from_user(buf, user_buf, len))
++ return -EFAULT;
++
++ buf[len] = '\0';
++ if (kstrtoul(buf, 0, &val))
++ return -EINVAL;
++
++ if (val < 0 || val > 255)
++ return -EINVAL;
++
++ sc->spec_config.count = val;
++ return count;
++}
++
++static const struct file_operations fops_spectral_count = {
++ .read = read_file_spectral_count,
++ .write = write_file_spectral_count,
++ .open = simple_open,
++ .owner = THIS_MODULE,
++ .llseek = default_llseek,
++};
++
++/*******************/
++/* spectral_period */
++/*******************/
++
++static ssize_t read_file_spectral_period(struct file *file,
++ char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ char buf[32];
++ unsigned int len;
++
++ len = sprintf(buf, "%d\n", sc->spec_config.period);
++ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
++}
++
++static ssize_t write_file_spectral_period(struct file *file,
++ const char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ unsigned long val;
++ char buf[32];
++ ssize_t len;
++
++ len = min(count, sizeof(buf) - 1);
++ if (copy_from_user(buf, user_buf, len))
++ return -EFAULT;
++
++ buf[len] = '\0';
++ if (kstrtoul(buf, 0, &val))
++ return -EINVAL;
++
++ if (val < 0 || val > 255)
++ return -EINVAL;
++
++ sc->spec_config.period = val;
++ return count;
++}
++
++static const struct file_operations fops_spectral_period = {
++ .read = read_file_spectral_period,
++ .write = write_file_spectral_period,
++ .open = simple_open,
++ .owner = THIS_MODULE,
++ .llseek = default_llseek,
++};
++
++/***********************/
++/* spectral_fft_period */
++/***********************/
++
++static ssize_t read_file_spectral_fft_period(struct file *file,
++ char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ char buf[32];
++ unsigned int len;
++
++ len = sprintf(buf, "%d\n", sc->spec_config.fft_period);
++ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
++}
++
++static ssize_t write_file_spectral_fft_period(struct file *file,
++ const char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ath_softc *sc = file->private_data;
++ unsigned long val;
++ char buf[32];
++ ssize_t len;
++
++ len = min(count, sizeof(buf) - 1);
++ if (copy_from_user(buf, user_buf, len))
++ return -EFAULT;
++
++ buf[len] = '\0';
++ if (kstrtoul(buf, 0, &val))
++ return -EINVAL;
++
++ if (val < 0 || val > 15)
++ return -EINVAL;
++
++ sc->spec_config.fft_period = val;
++ return count;
++}
++
++static const struct file_operations fops_spectral_fft_period = {
++ .read = read_file_spectral_fft_period,
++ .write = write_file_spectral_fft_period,
++ .open = simple_open,
++ .owner = THIS_MODULE,
++ .llseek = default_llseek,
++};
++
++/*******************/
++/* Relay interface */
++/*******************/
++
++static struct dentry *create_buf_file_handler(const char *filename,
++ struct dentry *parent,
++ umode_t mode,
++ struct rchan_buf *buf,
++ int *is_global)
++{
++ struct dentry *buf_file;
++
++ buf_file = debugfs_create_file(filename, mode, parent, buf,
++ &relay_file_operations);
++ *is_global = 1;
++ return buf_file;
++}
++
++static int remove_buf_file_handler(struct dentry *dentry)
++{
++ debugfs_remove(dentry);
++
++ return 0;
++}
++
++struct rchan_callbacks rfs_spec_scan_cb = {
++ .create_buf_file = create_buf_file_handler,
++ .remove_buf_file = remove_buf_file_handler,
++};
++
++/*********************/
++/* Debug Init/Deinit */
++/*********************/
++
++void ath9k_spectral_deinit_debug(struct ath_softc *sc)
++{
++ if (config_enabled(CPTCFG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) {
++ relay_close(sc->rfs_chan_spec_scan);
++ sc->rfs_chan_spec_scan = NULL;
++ }
++}
++
++void ath9k_spectral_init_debug(struct ath_softc *sc)
++{
++ sc->rfs_chan_spec_scan = relay_open("spectral_scan",
++ sc->debug.debugfs_phy,
++ 1024, 256, &rfs_spec_scan_cb,
++ NULL);
++ debugfs_create_file("spectral_scan_ctl",
++ S_IRUSR | S_IWUSR,
++ sc->debug.debugfs_phy, sc,
++ &fops_spec_scan_ctl);
++ debugfs_create_file("spectral_short_repeat",
++ S_IRUSR | S_IWUSR,
++ sc->debug.debugfs_phy, sc,
++ &fops_spectral_short_repeat);
++ debugfs_create_file("spectral_count",
++ S_IRUSR | S_IWUSR,
++ sc->debug.debugfs_phy, sc,
++ &fops_spectral_count);
++ debugfs_create_file("spectral_period",
++ S_IRUSR | S_IWUSR,
++ sc->debug.debugfs_phy, sc,
++ &fops_spectral_period);
++ debugfs_create_file("spectral_fft_period",
++ S_IRUSR | S_IWUSR,
++ sc->debug.debugfs_phy, sc,
++ &fops_spectral_fft_period);
++}
+--- /dev/null
++++ b/drivers/net/wireless/ath/ath9k/spectral.h
+@@ -0,0 +1,212 @@
++/*
++ * Copyright (c) 2013 Qualcomm Atheros, Inc.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef SPECTRAL_H
++#define SPECTRAL_H
++
++/* enum spectral_mode:
++ *
++ * @SPECTRAL_DISABLED: spectral mode is disabled
++ * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
++ * something else.
++ * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
++ * is performed manually.
++ * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
++ * during a channel scan.
++ */
++enum spectral_mode {
++ SPECTRAL_DISABLED = 0,
++ SPECTRAL_BACKGROUND,
++ SPECTRAL_MANUAL,
++ SPECTRAL_CHANSCAN,
++};
++
++#define SPECTRAL_SCAN_BITMASK 0x10
++/* Radar info packet format, used for DFS and spectral formats. */
++struct ath_radar_info {
++ u8 pulse_length_pri;
++ u8 pulse_length_ext;
++ u8 pulse_bw_info;
++} __packed;
++
++/* The HT20 spectral data has 4 bytes of additional information at it's end.
++ *
++ * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
++ * [7:0]: all bins max_magnitude[9:2]
++ * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
++ * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
++ */
++struct ath_ht20_mag_info {
++ u8 all_bins[3];
++ u8 max_exp;
++} __packed;
++
++#define SPECTRAL_HT20_NUM_BINS 56
++
++/* WARNING: don't actually use this struct! MAC may vary the amount of
++ * data by -1/+2. This struct is for reference only.
++ */
++struct ath_ht20_fft_packet {
++ u8 data[SPECTRAL_HT20_NUM_BINS];
++ struct ath_ht20_mag_info mag_info;
++ struct ath_radar_info radar_info;
++} __packed;
++
++#define SPECTRAL_HT20_TOTAL_DATA_LEN (sizeof(struct ath_ht20_fft_packet))
++
++/* Dynamic 20/40 mode:
++ *
++ * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
++ * [7:0]: lower bins max_magnitude[9:2]
++ * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
++ * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
++ * [7:0]: upper bins max_magnitude[9:2]
++ * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
++ * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
++ */
++struct ath_ht20_40_mag_info {
++ u8 lower_bins[3];
++ u8 upper_bins[3];
++ u8 max_exp;
++} __packed;
++
++#define SPECTRAL_HT20_40_NUM_BINS 128
++
++/* WARNING: don't actually use this struct! MAC may vary the amount of
++ * data. This struct is for reference only.
++ */
++struct ath_ht20_40_fft_packet {
++ u8 data[SPECTRAL_HT20_40_NUM_BINS];
++ struct ath_ht20_40_mag_info mag_info;
++ struct ath_radar_info radar_info;
++} __packed;
++
++
++#define SPECTRAL_HT20_40_TOTAL_DATA_LEN (sizeof(struct ath_ht20_40_fft_packet))
++
++/* grabs the max magnitude from the all/upper/lower bins */
++static inline u16 spectral_max_magnitude(u8 *bins)
++{
++ return (bins[0] & 0xc0) >> 6 |
++ (bins[1] & 0xff) << 2 |
++ (bins[2] & 0x03) << 10;
++}
++
++/* return the max magnitude from the all/upper/lower bins */
++static inline u8 spectral_max_index(u8 *bins)
++{
++ s8 m = (bins[2] & 0xfc) >> 2;
++
++ /* TODO: this still doesn't always report the right values ... */
++ if (m > 32)
++ m |= 0xe0;
++ else
++ m &= ~0xe0;
++
++ return m + 29;
++}
++
++/* return the bitmap weight from the all/upper/lower bins */
++static inline u8 spectral_bitmap_weight(u8 *bins)
++{
++ return bins[0] & 0x3f;
++}
++
++/* FFT sample format given to userspace via debugfs.
++ *
++ * Please keep the type/length at the front position and change
++ * other fields after adding another sample type
++ *
++ * TODO: this might need rework when switching to nl80211-based
++ * interface.
++ */
++enum ath_fft_sample_type {
++ ATH_FFT_SAMPLE_HT20 = 1,
++ ATH_FFT_SAMPLE_HT20_40,
++};
++
++struct fft_sample_tlv {
++ u8 type; /* see ath_fft_sample */
++ __be16 length;
++ /* type dependent data follows */
++} __packed;
++
++struct fft_sample_ht20 {
++ struct fft_sample_tlv tlv;
++
++ u8 max_exp;
++
++ __be16 freq;
++ s8 rssi;
++ s8 noise;
++
++ __be16 max_magnitude;
++ u8 max_index;
++ u8 bitmap_weight;
++
++ __be64 tsf;
++
++ u8 data[SPECTRAL_HT20_NUM_BINS];
++} __packed;
++
++struct fft_sample_ht20_40 {
++ struct fft_sample_tlv tlv;
++
++ u8 channel_type;
++ __be16 freq;
++
++ s8 lower_rssi;
++ s8 upper_rssi;
++
++ __be64 tsf;
++
++ s8 lower_noise;
++ s8 upper_noise;
++
++ __be16 lower_max_magnitude;
++ __be16 upper_max_magnitude;
++
++ u8 lower_max_index;
++ u8 upper_max_index;
++
++ u8 lower_bitmap_weight;
++ u8 upper_bitmap_weight;
++
++ u8 max_exp;
++
++ u8 data[SPECTRAL_HT20_40_NUM_BINS];
++} __packed;
++
++void ath9k_spectral_init_debug(struct ath_softc *sc);
++void ath9k_spectral_deinit_debug(struct ath_softc *sc);
++
++void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
++int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
++ enum spectral_mode spectral_mode);
++
++#ifdef CPTCFG_ATH9K_DEBUGFS
++int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
++ struct ath_rx_status *rs, u64 tsf);
++#else
++static inline int ath_process_fft(struct ath_softc *sc,
++ struct ieee80211_hdr *hdr,
++ struct ath_rx_status *rs, u64 tsf)
++{
++ return 0;
++}
++#endif /* CPTCFG_ATH9K_DEBUGFS */
++
++#endif /* SPECTRAL_H */
+--- a/include/net/mac80211.h
++++ b/include/net/mac80211.h
+@@ -1566,6 +1566,9 @@ enum ieee80211_hw_flags {
+ * @extra_tx_headroom: headroom to reserve in each transmit skb
+ * for use by the driver (e.g. for transmit headers.)
+ *
++ * @extra_beacon_tailroom: tailroom to reserve in each beacon tx skb.
++ * Can be used by drivers to add extra IEs.
++ *
+ * @channel_change_time: time (in microseconds) it takes to change channels.
+ *
+ * @max_signal: Maximum value for signal (rssi) in RX information, used
+@@ -1644,6 +1647,7 @@ struct ieee80211_hw {
+ void *priv;
+ u32 flags;
+ unsigned int extra_tx_headroom;
++ unsigned int extra_beacon_tailroom;
+ int channel_change_time;
+ int vif_data_size;
+ int sta_data_size;
+@@ -4595,4 +4599,49 @@ bool ieee80211_tx_prepare_skb(struct iee
+ struct ieee80211_vif *vif, struct sk_buff *skb,
+ int band, struct ieee80211_sta **sta);
+
++/**
++ * struct ieee80211_noa_data - holds temporary data for tracking P2P NoA state
++ *
++ * @next_tsf: TSF timestamp of the next absent state change
++ * @has_next_tsf: next absent state change event pending
++ *
++ * @absent: descriptor bitmask, set if GO is currently absent
++ *
++ * private:
++ *
++ * @count: count fields from the NoA descriptors
++ * @desc: adjusted data from the NoA
++ */
++struct ieee80211_noa_data {
++ u32 next_tsf;
++ bool has_next_tsf;
++
++ u8 absent;
++
++ u8 count[IEEE80211_P2P_NOA_DESC_MAX];
++ struct {
++ u32 start;
++ u32 duration;
++ u32 interval;
++ } desc[IEEE80211_P2P_NOA_DESC_MAX];
++};
++
++/**
++ * ieee80211_parse_p2p_noa - initialize NoA tracking data from P2P IE
++ *
++ * @attr: P2P NoA IE
++ * @data: NoA tracking data
++ * @tsf: current TSF timestamp
++ */
++int ieee80211_parse_p2p_noa(const struct ieee80211_p2p_noa_attr *attr,
++ struct ieee80211_noa_data *data, u32 tsf);
++
++/**
++ * ieee80211_update_p2p_noa - get next pending P2P GO absent state change
++ *
++ * @data: NoA tracking data
++ * @tsf: current TSF timestamp
++ */
++void ieee80211_update_p2p_noa(struct ieee80211_noa_data *data, u32 tsf);
++
+ #endif /* MAC80211_H */
+--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
++++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
+@@ -49,9 +49,10 @@ static inline bool ath9k_hw_calibrate(st
+ return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
+ }
+
+-static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
++static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked,
++ u32 *sync_cause_p)
+ {
+- return ath9k_hw_ops(ah)->get_isr(ah, masked);
++ return ath9k_hw_ops(ah)->get_isr(ah, masked, sync_cause_p);
+ }
+
+ static inline void ath9k_hw_set_txdesc(struct ath_hw *ah, void *ds,
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