target/linux/sunxi/patches-3.14/110-dt-sun6i-add-pll-and-spi-modclocks.patch

   1 From 7f94ebf35b017f1664e957857a7f36752e2577cd Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Wed, 5 Feb 2014 14:05:04 +0100
   4 Subject: [PATCH] ARM: sun6i: dt: Add PLL6 and SPI module clocks
   5
   6 The module clocks in the A31 are still compatible with the A10 one. Add the SPI
   7 module clocks and the PLL6 in the device tree to allow their use by the SPI
   8 controllers.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++--------
  13  1 file changed, 37 insertions(+), 9 deletions(-)
  14
  15 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
  16 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
  17 @@ -83,16 +83,12 @@
  18                         clocks = <&osc24M>;
  19                 };
  20
  21 -               /*
  22 -                * This is a dummy clock, to be used as placeholder on
  23 -                * other mux clocks when a specific parent clock is not
  24 -                * yet implemented. It should be dropped when the driver
  25 -                * is complete.
  26 -                */
  27 -               pll6: pll6 {
  28 +               pll6: clk@01c20028 {
  29                         #clock-cells = <0>;
  30 -                       compatible = "fixed-clock";
  31 -                       clock-frequency = <0>;
  32 +                       compatible = "allwinner,sun6i-a31-pll6-clk";
  33 +                       reg = <0x01c20028 0x4>;
  34 +                       clocks = <&osc24M>;
  35 +                       clock-output-names = "pll6";
  36                 };
  37
  38                 cpu: cpu@01c20050 {
  39 @@ -192,6 +188,38 @@
  40                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
  41                                         "apb2_uart4", "apb2_uart5";
  42                 };
  43 +
  44 +               spi0_clk: clk@01c200a0 {
  45 +                       #clock-cells = <0>;
  46 +                       compatible = "allwinner,sun4i-mod0-clk";
  47 +                       reg = <0x01c200a0 0x4>;
  48 +                       clocks = <&osc24M>, <&pll6>;
  49 +                       clock-output-names = "spi0";
  50 +               };
  51 +
  52 +               spi1_clk: clk@01c200a4 {
  53 +                       #clock-cells = <0>;
  54 +                       compatible = "allwinner,sun4i-mod0-clk";
  55 +                       reg = <0x01c200a4 0x4>;
  56 +                       clocks = <&osc24M>, <&pll6>;
  57 +                       clock-output-names = "spi1";
  58 +               };
  59 +
  60 +               spi2_clk: clk@01c200a8 {
  61 +                       #clock-cells = <0>;
  62 +                       compatible = "allwinner,sun4i-mod0-clk";
  63 +                       reg = <0x01c200a8 0x4>;
  64 +                       clocks = <&osc24M>, <&pll6>;
  65 +                       clock-output-names = "spi2";
  66 +               };
  67 +
  68 +               spi3_clk: clk@01c200ac {
  69 +                       #clock-cells = <0>;
  70 +                       compatible = "allwinner,sun4i-mod0-clk";
  71 +                       reg = <0x01c200ac 0x4>;
  72 +                       clocks = <&osc24M>, <&pll6>;
  73 +                       clock-output-names = "spi3";
  74 +               };
  75         };
  76
  77         soc@01c00000 {