e31358b742fe582f2d8f7d5066aa803fc5f8e0f5
[openwrt.git] / target / linux / sunxi / patches-3.13 / 150-1-clk-sunxi-implement-mmc-phasectrl.patch
1 From 4f43ab43125a12dbc23e352ac0eb4fd80a876fb5 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Fri, 20 Sep 2013 20:29:17 -0300
4 Subject: [PATCH] clk: sunxi: Implement MMC phase control
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Signed-off-by: Emilio López <emilio@elopez.com.ar>
10 ---
11  drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
12  1 file changed, 35 insertions(+)
13
14 --- a/drivers/clk/sunxi/clk-sunxi.c
15 +++ b/drivers/clk/sunxi/clk-sunxi.c
16 @@ -361,6 +361,41 @@ static void sun4i_get_mod0_factors(u32 *
17  
18  
19  /**
20 + * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
21 + */
22 +
23 +void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
24 +{
25 +       #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
26 +       #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
27 +
28 +       struct clk_composite *composite = to_clk_composite(hw);
29 +       struct clk_hw *rate_hw = composite->rate_hw;
30 +       struct clk_factors *factors = to_clk_factors(rate_hw);
31 +       unsigned long flags = 0;
32 +       u32 reg;
33 +
34 +       if (factors->lock)
35 +               spin_lock_irqsave(factors->lock, flags);
36 +
37 +       reg = readl(factors->reg);
38 +
39 +       /* set sample clock phase control */
40 +       reg &= ~(0x7 << 20);
41 +       reg |= ((sample & 0x7) << 20);
42 +
43 +       /* set output clock phase control */
44 +       reg &= ~(0x7 << 8);
45 +       reg |= ((output & 0x7) << 8);
46 +
47 +       writel(reg, factors->reg);
48 +
49 +       if (factors->lock)
50 +               spin_unlock_irqrestore(factors->lock, flags);
51 +}
52 +
53 +
54 +/**
55   * sunxi_factors_clk_setup() - Setup function for factor clocks
56   */
57