target/linux/sunxi/patches-3.13/127-3-dt-sun6i-rename-clock-node-names.patch

   1 From 5cd0fa24e51d342f175d31ecb72c2e957a6bd0af Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Mon, 3 Feb 2014 09:51:43 +0800
   4 Subject: [PATCH] ARM: dts: sun6i: rename clock node names to clk@N
   5
   6 Device tree naming conventions state that node names should match
   7 node function. Change fully functioning clock nodes to match and
   8 add clock-output-names to all sunxi clock nodes.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun6i-a31.dtsi | 19 ++++++++++++++-----
  14  1 file changed, 14 insertions(+), 5 deletions(-)
  15
  16 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
  17 index fc07f70..d3f1995 100644
  18 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
  19 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
  20 @@ -70,17 +70,19 @@
  21                         clock-frequency = <24000000>;
  22                 };
  23
  24 -               osc32k: osc32k {
  25 +               osc32k: clk@0 {
  26                         #clock-cells = <0>;
  27                         compatible = "fixed-clock";
  28                         clock-frequency = <32768>;
  29 +                       clock-output-names = "osc32k";
  30                 };
  31
  32 -               pll1: pll1@01c20000 {
  33 +               pll1: clk@01c20000 {
  34                         #clock-cells = <0>;
  35                         compatible = "allwinner,sun6i-a31-pll1-clk";
  36                         reg = <0x01c20000 0x4>;
  37                         clocks = <&osc24M>;
  38 +                       clock-output-names = "pll1";
  39                 };
  40
  41                 pll6: clk@01c20028 {
  42 @@ -103,6 +105,7 @@
  43                          * Allwinner.
  44                          */
  45                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
  46 +                       clock-output-names = "cpu";
  47                 };
  48
  49                 axi: axi@01c20050 {
  50 @@ -110,6 +113,7 @@
  51                         compatible = "allwinner,sun4i-axi-clk";
  52                         reg = <0x01c20050 0x4>;
  53                         clocks = <&cpu>;
  54 +                       clock-output-names = "axi";
  55                 };
  56
  57                 ahb1_mux: ahb1_mux@01c20054 {
  58 @@ -117,6 +121,7 @@
  59                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
  60                         reg = <0x01c20054 0x4>;
  61                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
  62 +                       clock-output-names = "ahb1_mux";
  63                 };
  64
  65                 ahb1: ahb1@01c20054 {
  66 @@ -124,9 +129,10 @@
  67                         compatible = "allwinner,sun4i-ahb-clk";
  68                         reg = <0x01c20054 0x4>;
  69                         clocks = <&ahb1_mux>;
  70 +                       clock-output-names = "ahb1";
  71                 };
  72
  73 -               ahb1_gates: ahb1_gates@01c20060 {
  74 +               ahb1_gates: clk@01c20060 {
  75                         #clock-cells = <1>;
  76                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
  77                         reg = <0x01c20060 0x8>;
  78 @@ -152,9 +158,10 @@
  79                         compatible = "allwinner,sun4i-apb0-clk";
  80                         reg = <0x01c20054 0x4>;
  81                         clocks = <&ahb1>;
  82 +                       clock-output-names = "apb1";
  83                 };
  84
  85 -               apb1_gates: apb1_gates@01c20060 {
  86 +               apb1_gates: clk@01c20068 {
  87                         #clock-cells = <1>;
  88                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
  89                         reg = <0x01c20068 0x4>;
  90 @@ -169,6 +176,7 @@
  91                         compatible = "allwinner,sun4i-apb1-mux-clk";
  92                         reg = <0x01c20058 0x4>;
  93                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
  94 +                       clock-output-names = "apb2_mux";
  95                 };
  96
  97                 apb2: apb2@01c20058 {
  98 @@ -176,9 +184,10 @@
  99                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 100                         reg = <0x01c20058 0x4>;
 101                         clocks = <&apb2_mux>;
 102 +                       clock-output-names = "apb2";
 103                 };
 104
 105 -               apb2_gates: apb2_gates@01c2006c {
 106 +               apb2_gates: clk@01c2006c {
 107                         #clock-cells = <1>;
 108                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 109                         reg = <0x01c2006c 0x4>;
 110 --
 111 1.8.5.5
 112