target/linux/sunxi/patches-3.12/185-clk-sunxi-mmc-phasectrl.patch

   1 From e074907f73e0bc70740901fb4a05fdf5fc81b3ff Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Fri, 20 Sep 2013 20:29:17 -0300
   4 Subject: [PATCH] clk: sunxi: Implement MMC phase control
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  10 ---
  11  drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
  12  1 file changed, 35 insertions(+)
  13
  14 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
  15 index 360d705..d2b8d3c 100644
  16 --- a/drivers/clk/sunxi/clk-sunxi.c
  17 +++ b/drivers/clk/sunxi/clk-sunxi.c
  18 @@ -352,6 +352,41 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
  19
  20
  21  /**
  22 + * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
  23 + */
  24 +
  25 +void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
  26 +{
  27 +       #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
  28 +       #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
  29 +
  30 +       struct clk_composite *composite = to_clk_composite(hw);
  31 +       struct clk_hw *rate_hw = composite->rate_hw;
  32 +       struct clk_factors *factors = to_clk_factors(rate_hw);
  33 +       unsigned long flags = 0;
  34 +       u32 reg;
  35 +
  36 +       if (factors->lock)
  37 +               spin_lock_irqsave(factors->lock, flags);
  38 +
  39 +       reg = readl(factors->reg);
  40 +
  41 +       /* set sample clock phase control */
  42 +       reg &= ~(0x7 << 20);
  43 +       reg |= ((sample & 0x7) << 20);
  44 +
  45 +       /* set output clock phase control */
  46 +       reg &= ~(0x7 << 8);
  47 +       reg |= ((output & 0x7) << 8);
  48 +
  49 +       writel(reg, factors->reg);
  50 +
  51 +       if (factors->lock)
  52 +               spin_unlock_irqrestore(factors->lock, flags);
  53 +}
  54 +
  55 +
  56 +/**
  57   * sunxi_factors_clk_setup() - Setup function for factor clocks
  58   */
  59
  60 --
  61 1.8.5.1
  62