target/linux/sunxi/files/drivers/mmc/host/sunxi-mci.c

   1 /*
   2  * Driver for sunxi SD/MMC host controllers
   3  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
   4  * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
   5  * (C) Copyright 2013-2013 O2S GmbH <www.o2s.ch>
   6  * (C) Copyright 2013-2013 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
   7  * (C) Copyright 2013-2013 Hans de Goede <hdegoede@redhat.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22
  23 #include <linux/clk.h>
  24 #include <linux/clk-private.h>
  25 #include <linux/clk/sunxi.h>
  26
  27 #include <linux/gpio.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/scatterlist.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/slab.h>
  33 #include <linux/regulator/consumer.h>
  34
  35 #include <linux/of_address.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/of_platform.h>
  38
  39 #include <linux/mmc/host.h>
  40 #include <linux/mmc/sd.h>
  41 #include <linux/mmc/mmc.h>
  42 #include <linux/mmc/core.h>
  43 #include <linux/mmc/card.h>
  44
  45 #include "sunxi-mci.h"
  46
  47 static void sunxi_mmc_init_host(struct mmc_host *mmc)
  48 {
  49         u32 rval;
  50         struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
  51
  52         /* reset controller */
  53         rval = mci_readl(smc_host, REG_GCTRL) | SDXC_HWReset;
  54         mci_writel(smc_host, REG_GCTRL, rval);
  55
  56         mci_writel(smc_host, REG_FTRGL, 0x20070008);
  57         mci_writel(smc_host, REG_TMOUT, 0xffffffff);
  58         mci_writel(smc_host, REG_IMASK, smc_host->sdio_imask);
  59         mci_writel(smc_host, REG_RINTR, 0xffffffff);
  60         mci_writel(smc_host, REG_DBGC, 0xdeb);
  61         mci_writel(smc_host, REG_FUNS, 0xceaa0000);
  62         mci_writel(smc_host, REG_DLBA, smc_host->sg_dma);
  63         rval = mci_readl(smc_host, REG_GCTRL)|SDXC_INTEnb;
  64         rval &= ~SDXC_AccessDoneDirect;
  65         mci_writel(smc_host, REG_GCTRL, rval);
  66 }
  67
  68 static void sunxi_mmc_exit_host(struct sunxi_mmc_host *smc_host)
  69 {
  70         mci_writel(smc_host, REG_GCTRL, SDXC_HWReset);
  71 }
  72
  73 /* /\* UHS-I Operation Modes */
  74 /*  * DS                25MHz   12.5MB/s        3.3V */
  75 /*  * HS                50MHz   25MB/s          3.3V */
  76 /*  * SDR12     25MHz   12.5MB/s        1.8V */
  77 /*  * SDR25     50MHz   25MB/s          1.8V */
  78 /*  * SDR50     100MHz  50MB/s          1.8V */
  79 /*  * SDR104    208MHz  104MB/s         1.8V */
  80 /*  * DDR50     50MHz   50MB/s          1.8V */
  81 /*  * MMC Operation Modes */
  82 /*  * DS                26MHz   26MB/s          3/1.8/1.2V */
  83 /*  * HS                52MHz   52MB/s          3/1.8/1.2V */
  84 /*  * HSDDR     52MHz   104MB/s         3/1.8/1.2V */
  85 /*  * HS200     200MHz  200MB/s         1.8/1.2V */
  86 /*  * */
  87 /*  * Spec. Timing */
  88 /*  * SD3.0 */
  89 /*  * Fcclk    Tcclk   Fsclk   Tsclk   Tis     Tih     odly  RTis     RTih */
  90 /*  * 400K     2.5us   24M     41ns    5ns     5ns     1     2209ns   41ns */
  91 /*  * 25M      40ns    600M    1.67ns  5ns     5ns     3     14.99ns  5.01ns */
  92 /*  * 50M      20ns    600M    1.67ns  6ns     2ns     3     14.99ns  5.01ns */
  93 /*  * 50MDDR   20ns    600M    1.67ns  6ns     0.8ns   2     6.67ns   3.33ns */
  94 /*  * 104M     9.6ns   600M    1.67ns  3ns     0.8ns   1     7.93ns   1.67ns */
  95 /*  * 208M     4.8ns   600M    1.67ns  1.4ns   0.8ns   1     3.33ns   1.67ns */
  96
  97 /*  * 25M      40ns    300M    3.33ns  5ns     5ns     2     13.34ns   6.66ns */
  98 /*  * 50M      20ns    300M    3.33ns  6ns     2ns     2     13.34ns   6.66ns */
  99 /*  * 50MDDR   20ns    300M    3.33ns  6ns     0.8ns   1     6.67ns    3.33ns */
 100 /*  * 104M     9.6ns   300M    3.33ns  3ns     0.8ns   0     7.93ns    1.67ns */
 101 /*  * 208M     4.8ns   300M    3.33ns  1.4ns   0.8ns   0     3.13ns    1.67ns */
 102
 103 /*  * eMMC4.5 */
 104 /*  * 400K     2.5us   24M     41ns    3ns     3ns     1     2209ns    41ns */
 105 /*  * 25M      40ns    600M    1.67ns  3ns     3ns     3     14.99ns   5.01ns */
 106 /*  * 50M      20ns    600M    1.67ns  3ns     3ns     3     14.99ns   5.01ns */
 107 /*  * 50MDDR   20ns    600M    1.67ns  2.5ns   2.5ns   2     6.67ns    3.33ns */
 108 /*  * 200M     5ns     600M    1.67ns  1.4ns   0.8ns   1     3.33ns    1.67ns */
 109 /*  *\/ */
 110
 111 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 112                                     struct mmc_data *data)
 113 {
 114         struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
 115         struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma;
 116         int i, max_len = (1 << host->idma_des_size_bits);
 117
 118         for (i = 0; i < data->sg_len; i++) {
 119                 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
 120                                  SDXC_IDMAC_DES0_DIC;
 121
 122                 if (data->sg[i].length == max_len)
 123                         pdes[i].buf_size = 0; /* 0 == max_len */
 124                 else
 125                         pdes[i].buf_size = data->sg[i].length;
 126
 127                 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
 128                 pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
 129         }
 130         pdes[0].config |= SDXC_IDMAC_DES0_FD;
 131         pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
 132
 133         wmb(); /* Ensure idma_des hit main mem before we start the idmac */
 134 }
 135
 136 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
 137 {
 138         if (data->flags & MMC_DATA_WRITE)
 139                 return DMA_TO_DEVICE;
 140         else
 141                 return DMA_FROM_DEVICE;
 142 }
 143
 144 static int sunxi_mmc_prepare_dma(struct sunxi_mmc_host *smc_host,
 145                                  struct mmc_data *data)
 146 {
 147         u32 dma_len;
 148         u32 i;
 149         u32 temp;
 150         struct scatterlist *sg;
 151
 152         dma_len = dma_map_sg(mmc_dev(smc_host->mmc), data->sg, data->sg_len,
 153                              sunxi_mmc_get_dma_dir(data));
 154         if (dma_len == 0) {
 155                 dev_err(mmc_dev(smc_host->mmc), "dma_map_sg failed\n");
 156                 return -ENOMEM;
 157         }
 158
 159         for_each_sg(data->sg, sg, data->sg_len, i) {
 160                 if (sg->offset & 3 || sg->length & 3) {
 161                         dev_err(mmc_dev(smc_host->mmc),
 162                                 "unaligned scatterlist: os %x length %d\n",
 163                                 sg->offset, sg->length);
 164                         return -EINVAL;
 165                 }
 166         }
 167
 168         sunxi_mmc_init_idma_des(smc_host, data);
 169
 170         temp = mci_readl(smc_host, REG_GCTRL);
 171         temp |= SDXC_DMAEnb;
 172         mci_writel(smc_host, REG_GCTRL, temp);
 173         temp |= SDXC_DMAReset;
 174         mci_writel(smc_host, REG_GCTRL, temp);
 175
 176         mci_writel(smc_host, REG_DMAC, SDXC_IDMACSoftRST);
 177
 178         if (!(data->flags & MMC_DATA_WRITE))
 179                 mci_writel(smc_host, REG_IDIE, SDXC_IDMACReceiveInt);
 180
 181         mci_writel(smc_host, REG_DMAC, SDXC_IDMACFixBurst | SDXC_IDMACIDMAOn);
 182
 183         return 0;
 184 }
 185
 186 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
 187                                        struct mmc_request *req)
 188 {
 189         u32 cmd_val = SDXC_Start | SDXC_RspExp | SDXC_StopAbortCMD
 190                         | SDXC_CheckRspCRC | MMC_STOP_TRANSMISSION;
 191         u32 ri = 0;
 192         unsigned long expire = jiffies + msecs_to_jiffies(1000);
 193
 194         mci_writel(host, REG_CARG, 0);
 195         mci_writel(host, REG_CMDR, cmd_val);
 196         do {
 197                 ri = mci_readl(host, REG_RINTR);
 198         } while (!(ri & (SDXC_CmdDone | SDXC_IntErrBit)) &&
 199                  time_before(jiffies, expire));
 200
 201         if (ri & SDXC_IntErrBit) {
 202                 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
 203                 if (req->stop)
 204                         req->stop->resp[0] = -ETIMEDOUT;
 205         } else {
 206                 if (req->stop)
 207                         req->stop->resp[0] = mci_readl(host, REG_RESP0);
 208         }
 209
 210         mci_writel(host, REG_RINTR, 0xffff);
 211 }
 212
 213 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
 214 {
 215         struct mmc_command *cmd = smc_host->mrq->cmd;
 216         struct mmc_data *data = smc_host->mrq->data;
 217
 218         /* For some cmds timeout is normal with sd/mmc cards */
 219         if ((smc_host->int_sum & SDXC_IntErrBit) == SDXC_RespTimeout &&
 220                         (cmd->opcode == 5 || cmd->opcode == 52))
 221                 return;
 222
 223         dev_err(mmc_dev(smc_host->mmc),
 224                 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
 225                 smc_host->mmc->index, cmd->opcode,
 226                 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
 227                 smc_host->int_sum & SDXC_RespErr     ? " RE"     : "",
 228                 smc_host->int_sum & SDXC_RespCRCErr  ? " RCE"    : "",
 229                 smc_host->int_sum & SDXC_DataCRCErr  ? " DCE"    : "",
 230                 smc_host->int_sum & SDXC_RespTimeout ? " RTO"    : "",
 231                 smc_host->int_sum & SDXC_DataTimeout ? " DTO"    : "",
 232                 smc_host->int_sum & SDXC_FIFORunErr  ? " FE"     : "",
 233                 smc_host->int_sum & SDXC_HardWLocked ? " HL"     : "",
 234                 smc_host->int_sum & SDXC_StartBitErr ? " SBE"    : "",
 235                 smc_host->int_sum & SDXC_EndBitErr   ? " EBE"    : ""
 236                 );
 237 }
 238
 239 static void sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
 240 {
 241         struct mmc_request *mrq;
 242         unsigned long iflags;
 243
 244         spin_lock_irqsave(&host->lock, iflags);
 245
 246         mrq = host->mrq;
 247         if (!mrq) {
 248                 spin_unlock_irqrestore(&host->lock, iflags);
 249                 dev_err(mmc_dev(host->mmc), "no request to finalize\n");
 250                 return;
 251         }
 252
 253         if (host->int_sum & SDXC_IntErrBit) {
 254                 sunxi_mmc_dump_errinfo(host);
 255                 mrq->cmd->error = -ETIMEDOUT;
 256                 if (mrq->data)
 257                         mrq->data->error = -ETIMEDOUT;
 258                 if (mrq->stop)
 259                         mrq->stop->error = -ETIMEDOUT;
 260         } else {
 261                 if (mrq->cmd->flags & MMC_RSP_136) {
 262                         mrq->cmd->resp[0] = mci_readl(host, REG_RESP3);
 263                         mrq->cmd->resp[1] = mci_readl(host, REG_RESP2);
 264                         mrq->cmd->resp[2] = mci_readl(host, REG_RESP1);
 265                         mrq->cmd->resp[3] = mci_readl(host, REG_RESP0);
 266                 } else {
 267                         mrq->cmd->resp[0] = mci_readl(host, REG_RESP0);
 268                 }
 269                 if (mrq->data)
 270                         mrq->data->bytes_xfered =
 271                                 mrq->data->blocks * mrq->data->blksz;
 272         }
 273
 274         if (mrq->data) {
 275                 struct mmc_data *data = mrq->data;
 276                 u32 temp;
 277
 278                 mci_writel(host, REG_IDST, 0x337);
 279                 mci_writel(host, REG_DMAC, 0);
 280                 temp = mci_readl(host, REG_GCTRL);
 281                 mci_writel(host, REG_GCTRL, temp|SDXC_DMAReset);
 282                 temp &= ~SDXC_DMAEnb;
 283                 mci_writel(host, REG_GCTRL, temp);
 284                 temp |= SDXC_FIFOReset;
 285                 mci_writel(host, REG_GCTRL, temp);
 286                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 287                                      sunxi_mmc_get_dma_dir(data));
 288         }
 289
 290         mci_writel(host, REG_RINTR, 0xffff);
 291
 292         dev_dbg(mmc_dev(host->mmc), "req done, resp %08x %08x %08x %08x\n",
 293                 mrq->cmd->resp[0], mrq->cmd->resp[1],
 294                 mrq->cmd->resp[2], mrq->cmd->resp[3]);
 295
 296         host->mrq = NULL;
 297         host->int_sum = 0;
 298         host->wait_dma = 0;
 299
 300         spin_unlock_irqrestore(&host->lock, iflags);
 301
 302         if (mrq->data && mrq->data->error) {
 303                 dev_err(mmc_dev(host->mmc),
 304                         "data error, sending stop command\n");
 305                 sunxi_mmc_send_manual_stop(host, mrq);
 306         }
 307
 308         mmc_request_done(host->mmc, mrq);
 309 }
 310
 311 static s32 sunxi_mmc_get_ro(struct mmc_host *mmc)
 312 {
 313         struct sunxi_mmc_host *host = mmc_priv(mmc);
 314
 315         int read_only = 0;
 316
 317         if (gpio_is_valid(host->wp_pin)) {
 318                 pinctrl_request_gpio(host->wp_pin);
 319                 read_only = gpio_get_value(host->wp_pin);
 320         }
 321
 322         return read_only;
 323 }
 324
 325 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
 326 {
 327         struct sunxi_mmc_host *host = dev_id;
 328         u32 finalize = 0;
 329         u32 sdio_int = 0;
 330         u32 msk_int;
 331         u32 idma_int;
 332
 333         spin_lock(&host->lock);
 334
 335         idma_int  = mci_readl(host, REG_IDST);
 336         msk_int   = mci_readl(host, REG_MISTA);
 337
 338         dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
 339                 host->mrq, msk_int, idma_int);
 340
 341         if (host->mrq) {
 342                 if (idma_int & SDXC_IDMACReceiveInt)
 343                         host->wait_dma = 0;
 344
 345                 host->int_sum |= msk_int;
 346
 347                 /* Wait for CmdDone on RespTimeout before finishing the req */
 348                 if ((host->int_sum & SDXC_RespTimeout) &&
 349                                 !(host->int_sum & SDXC_CmdDone))
 350                         mci_writel(host, REG_IMASK,
 351                                    host->sdio_imask | SDXC_CmdDone);
 352                 else if (host->int_sum & SDXC_IntErrBit)
 353                         finalize = 1; /* Don't wait for dma on error */
 354                 else if (host->int_sum & SDXC_IntDoneBit && !host->wait_dma)
 355                         finalize = 1; /* Done */
 356
 357                 if (finalize) {
 358                         mci_writel(host, REG_IMASK, host->sdio_imask);
 359                         mci_writel(host, REG_IDIE, 0);
 360                 }
 361         }
 362
 363         if (msk_int & SDXC_SDIOInt)
 364                 sdio_int = 1;
 365
 366         mci_writel(host, REG_RINTR, msk_int);
 367         mci_writel(host, REG_IDST, idma_int);
 368
 369         spin_unlock(&host->lock);
 370
 371         if (finalize)
 372                 tasklet_schedule(&host->tasklet);
 373
 374         if (sdio_int)
 375                 mmc_signal_sdio_irq(host->mmc);
 376
 377         return IRQ_HANDLED;
 378 }
 379
 380 static void sunxi_mmc_tasklet(unsigned long data)
 381 {
 382         struct sunxi_mmc_host *smc_host = (struct sunxi_mmc_host *) data;
 383         sunxi_mmc_finalize_request(smc_host);
 384 }
 385
 386 static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
 387 {
 388         unsigned long expire = jiffies + msecs_to_jiffies(2000);
 389         u32 rval;
 390
 391         rval = mci_readl(host, REG_CLKCR);
 392         rval &= ~(SDXC_CardClkOn | SDXC_LowPowerOn);
 393         if (oclk_en)
 394                 rval |= SDXC_CardClkOn;
 395         if (!host->io_flag)
 396                 rval |= SDXC_LowPowerOn;
 397         mci_writel(host, REG_CLKCR, rval);
 398
 399         rval = SDXC_Start | SDXC_UPCLKOnly | SDXC_WaitPreOver;
 400         if (host->voltage_switching)
 401                 rval |= SDXC_VolSwitch;
 402         mci_writel(host, REG_CMDR, rval);
 403         do {
 404                 rval = mci_readl(host, REG_CMDR);
 405         } while (time_before(jiffies, expire) && (rval & SDXC_Start));
 406
 407         if (rval & SDXC_Start) {
 408                 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
 409                 host->ferror = 1;
 410         }
 411 }
 412
 413 static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
 414                                   u32 oclk_dly, u32 sclk_dly)
 415 {
 416         unsigned long iflags;
 417         struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
 418
 419         spin_lock_irqsave(&smc_host->lock, iflags);
 420         clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
 421         spin_unlock_irqrestore(&smc_host->lock, iflags);
 422 }
 423
 424 struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
 425         { MMC_CLK_400K, 0, 7 },
 426         { MMC_CLK_25M, 0, 5 },
 427         { MMC_CLK_50M, 3, 5 },
 428         { MMC_CLK_50MDDR, 2, 4 },
 429         { MMC_CLK_50MDDR_8BIT, 2, 4 },
 430         { MMC_CLK_100M, 1, 4 },
 431         { MMC_CLK_200M, 1, 4 },
 432 };
 433
 434 static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
 435                                    unsigned int rate)
 436 {
 437         u32 newrate;
 438         u32 src_clk;
 439         u32 oclk_dly;
 440         u32 sclk_dly;
 441         u32 temp;
 442         struct sunxi_mmc_clk_dly *dly = NULL;
 443
 444         newrate = clk_round_rate(smc_host->clk_mod, rate);
 445         if (smc_host->clk_mod_rate == newrate) {
 446                 dev_dbg(mmc_dev(smc_host->mmc), "clk already %d, rounded %d\n",
 447                         rate, newrate);
 448                 return;
 449         }
 450
 451         dev_dbg(mmc_dev(smc_host->mmc), "setting clk to %d, rounded %d\n",
 452                 rate, newrate);
 453
 454         /* setting clock rate */
 455         clk_disable(smc_host->clk_mod);
 456         clk_set_rate(smc_host->clk_mod, newrate);
 457         clk_enable(smc_host->clk_mod);
 458         smc_host->clk_mod_rate = newrate = clk_get_rate(smc_host->clk_mod);
 459         dev_dbg(mmc_dev(smc_host->mmc), "clk is now %d\n", newrate);
 460
 461         sunxi_mmc_oclk_onoff(smc_host, 0);
 462         /* clear internal divider */
 463         temp = mci_readl(smc_host, REG_CLKCR);
 464         temp &= ~0xff;
 465         mci_writel(smc_host, REG_CLKCR, temp);
 466
 467         /* determine delays */
 468         if (rate <= 400000) {
 469                 dly = &mmc_clk_dly[MMC_CLK_400K];
 470         } else if (rate <= 25000000) {
 471                 dly = &mmc_clk_dly[MMC_CLK_25M];
 472         } else if (rate <= 50000000) {
 473                 if (smc_host->ddr) {
 474                         if (smc_host->bus_width == 8)
 475                                 dly = &mmc_clk_dly[MMC_CLK_50MDDR_8BIT];
 476                         else
 477                                 dly = &mmc_clk_dly[MMC_CLK_50MDDR];
 478                 } else {
 479                         dly = &mmc_clk_dly[MMC_CLK_50M];
 480                 }
 481         } else if (rate <= 104000000) {
 482                 dly = &mmc_clk_dly[MMC_CLK_100M];
 483         } else if (rate <= 208000000) {
 484                 dly = &mmc_clk_dly[MMC_CLK_200M];
 485         } else
 486                 dly = &mmc_clk_dly[MMC_CLK_50M];
 487
 488         oclk_dly = dly->oclk_dly;
 489         sclk_dly = dly->sclk_dly;
 490
 491         src_clk = clk_get_rate(clk_get_parent(smc_host->clk_mod));
 492         if (src_clk >= 300000000 && src_clk <= 400000000) {
 493                 if (oclk_dly)
 494                         oclk_dly--;
 495                 if (sclk_dly)
 496                         sclk_dly--;
 497         }
 498
 499         sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
 500         sunxi_mmc_oclk_onoff(smc_host, 1);
 501
 502         /* oclk_onoff sets various irq status bits, clear these */
 503         mci_writel(smc_host, REG_RINTR,
 504                    mci_readl(smc_host, REG_RINTR) & ~SDXC_SDIOInt);
 505 }
 506
 507 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 508 {
 509         struct sunxi_mmc_host *host = mmc_priv(mmc);
 510         u32 temp;
 511         s32 err;
 512
 513         /* Set the power state */
 514         switch (ios->power_mode) {
 515         case MMC_POWER_ON:
 516                 break;
 517
 518         case MMC_POWER_UP:
 519                 if (!IS_ERR(host->vmmc)) {
 520                         mmc_regulator_set_ocr(host->mmc, host->vmmc, ios->vdd);
 521                         udelay(200);
 522                 }
 523
 524                 err =  clk_prepare_enable(host->clk_ahb);
 525                 if (err) {
 526                         dev_err(mmc_dev(host->mmc), "AHB clk err %d\n", err);
 527                         host->ferror = 1;
 528                         return;
 529                 }
 530                 err =  clk_prepare_enable(host->clk_mod);
 531                 if (err) {
 532                         dev_err(mmc_dev(host->mmc), "MOD clk err %d\n", err);
 533                         host->ferror = 1;
 534                         return;
 535                 }
 536
 537                 sunxi_mmc_init_host(mmc);
 538                 enable_irq(host->irq);
 539
 540                 dev_dbg(mmc_dev(host->mmc), "power on!\n");
 541                 host->ferror = 0;
 542                 break;
 543
 544         case MMC_POWER_OFF:
 545                 dev_dbg(mmc_dev(host->mmc), "power off!\n");
 546                 disable_irq(host->irq);
 547                 sunxi_mmc_exit_host(host);
 548                 clk_disable_unprepare(host->clk_ahb);
 549                 clk_disable_unprepare(host->clk_mod);
 550                 if (!IS_ERR(host->vmmc))
 551                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
 552                 host->ferror = 0;
 553                 break;
 554         }
 555
 556         /* set bus width */
 557         switch (ios->bus_width) {
 558         case MMC_BUS_WIDTH_1:
 559                 mci_writel(host, REG_WIDTH, SDXC_WIDTH1);
 560                 host->bus_width = 1;
 561                 break;
 562         case MMC_BUS_WIDTH_4:
 563                 mci_writel(host, REG_WIDTH, SDXC_WIDTH4);
 564                 host->bus_width = 4;
 565                 break;
 566         case MMC_BUS_WIDTH_8:
 567                 mci_writel(host, REG_WIDTH, SDXC_WIDTH8);
 568                 host->bus_width = 8;
 569                 break;
 570         }
 571
 572         /* set ddr mode */
 573         temp = mci_readl(host, REG_GCTRL);
 574         if (ios->timing == MMC_TIMING_UHS_DDR50) {
 575                 temp |= SDXC_DDR_MODE;
 576                 host->ddr = 1;
 577         } else {
 578                 temp &= ~SDXC_DDR_MODE;
 579                 host->ddr = 0;
 580         }
 581         mci_writel(host, REG_GCTRL, temp);
 582
 583         /* set up clock */
 584         if (ios->clock && ios->power_mode) {
 585                 dev_dbg(mmc_dev(host->mmc), "ios->clock: %d\n", ios->clock);
 586                 sunxi_mmc_clk_set_rate(host, ios->clock);
 587                 usleep_range(50000, 55000);
 588         }
 589 }
 590
 591 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 592 {
 593         struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
 594         unsigned long flags;
 595         u32 imask;
 596
 597         spin_lock_irqsave(&smc_host->lock, flags);
 598         imask = mci_readl(smc_host, REG_IMASK);
 599         if (enable) {
 600                 smc_host->sdio_imask = SDXC_SDIOInt;
 601                 imask |= SDXC_SDIOInt;
 602         } else {
 603                 smc_host->sdio_imask = 0;
 604                 imask &= ~SDXC_SDIOInt;
 605         }
 606         mci_writel(smc_host, REG_IMASK, imask);
 607         spin_unlock_irqrestore(&smc_host->lock, flags);
 608 }
 609
 610 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
 611 {
 612         struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
 613         mci_writel(smc_host, REG_HWRST, 0);
 614         udelay(10);
 615         mci_writel(smc_host, REG_HWRST, 1);
 616         udelay(300);
 617 }
 618
 619 static int sunxi_mmc_card_present(struct mmc_host *mmc)
 620 {
 621         struct sunxi_mmc_host *host = mmc_priv(mmc);
 622
 623         switch (host->cd_mode) {
 624         case CARD_DETECT_BY_GPIO_POLL:
 625                 return !gpio_get_value(host->cd_pin); /* Signal inverted */
 626         case CARD_ALWAYS_PRESENT:
 627                 return 1;
 628         }
 629         return 0; /* Never reached */
 630 }
 631
 632 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 633 {
 634         struct sunxi_mmc_host *host = mmc_priv(mmc);
 635         struct mmc_command *cmd = mrq->cmd;
 636         struct mmc_data *data = mrq->data;
 637         unsigned long iflags;
 638         u32 imask = SDXC_IntErrBit;
 639         u32 cmd_val = SDXC_Start | (cmd->opcode & 0x3f);
 640         u32 byte_cnt = 0;
 641         int ret;
 642
 643         if (!sunxi_mmc_card_present(mmc) || host->ferror) {
 644                 dev_dbg(mmc_dev(host->mmc), "no medium present\n");
 645                 mrq->cmd->error = -ENOMEDIUM;
 646                 mmc_request_done(mmc, mrq);
 647                 return;
 648         }
 649
 650         if (data) {
 651                 byte_cnt = data->blksz * data->blocks;
 652                 mci_writel(host, REG_BLKSZ, data->blksz);
 653                 mci_writel(host, REG_BCNTR, byte_cnt);
 654                 ret = sunxi_mmc_prepare_dma(host, data);
 655                 if (ret < 0) {
 656                         dev_err(mmc_dev(host->mmc), "prepare DMA failed\n");
 657                         cmd->error = ret;
 658                         cmd->data->error = ret;
 659                         mmc_request_done(host->mmc, mrq);
 660                         return;
 661                 }
 662         }
 663
 664         if (cmd->opcode == MMC_GO_IDLE_STATE) {
 665                 cmd_val |= SDXC_SendInitSeq;
 666                 imask |= SDXC_CmdDone;
 667         }
 668
 669         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 670                 cmd_val |= SDXC_VolSwitch;
 671                 imask |= SDXC_VolChgDone;
 672                 host->voltage_switching = 1;
 673                 sunxi_mmc_oclk_onoff(host, 1);
 674         }
 675
 676         if (cmd->flags & MMC_RSP_PRESENT) {
 677                 cmd_val |= SDXC_RspExp;
 678                 if (cmd->flags & MMC_RSP_136)
 679                         cmd_val |= SDXC_LongRsp;
 680                 if (cmd->flags & MMC_RSP_CRC)
 681                         cmd_val |= SDXC_CheckRspCRC;
 682
 683                 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
 684                         cmd_val |= SDXC_DataExp | SDXC_WaitPreOver;
 685                         if (cmd->data->flags & MMC_DATA_STREAM) {
 686                                 imask |= SDXC_AutoCMDDone;
 687                                 cmd_val |= SDXC_Seqmod | SDXC_SendAutoStop;
 688                         }
 689                         if (cmd->data->stop) {
 690                                 imask |= SDXC_AutoCMDDone;
 691                                 cmd_val |= SDXC_SendAutoStop;
 692                         } else
 693                                 imask |= SDXC_DataOver;
 694
 695                         if (cmd->data->flags & MMC_DATA_WRITE)
 696                                 cmd_val |= SDXC_Write;
 697                         else
 698                                 host->wait_dma = 1;
 699                 } else
 700                         imask |= SDXC_CmdDone;
 701         } else
 702                 imask |= SDXC_CmdDone;
 703
 704         dev_dbg(mmc_dev(host->mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
 705                 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
 706                 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
 707
 708         spin_lock_irqsave(&host->lock, iflags);
 709         host->mrq = mrq;
 710         mci_writel(host, REG_IMASK, host->sdio_imask | imask);
 711         spin_unlock_irqrestore(&host->lock, iflags);
 712
 713         mci_writel(host, REG_CARG, cmd->arg);
 714         mci_writel(host, REG_CMDR, cmd_val);
 715 }
 716
 717 static const struct of_device_id sunxi_mmc_of_match[] = {
 718         { .compatible = "allwinner,sun4i-mmc", },
 719         { .compatible = "allwinner,sun5i-mmc", },
 720         { /* sentinel */ }
 721 };
 722 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
 723
 724 static struct mmc_host_ops sunxi_mmc_ops = {
 725         .request         = sunxi_mmc_request,
 726         .set_ios         = sunxi_mmc_set_ios,
 727         .get_ro          = sunxi_mmc_get_ro,
 728         .get_cd          = sunxi_mmc_card_present,
 729         .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
 730         .hw_reset        = sunxi_mmc_hw_reset,
 731 };
 732
 733 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
 734                                       struct platform_device *pdev)
 735 {
 736         struct device_node *np = pdev->dev.of_node;
 737         int ret;
 738
 739         if (of_device_is_compatible(np, "allwinner,sun4i-mmc"))
 740                 host->idma_des_size_bits = 13;
 741         else
 742                 host->idma_des_size_bits = 16;
 743
 744         host->vmmc = devm_regulator_get_optional(&pdev->dev, "vmmc");
 745         if (IS_ERR(host->vmmc) && PTR_ERR(host->vmmc) == -EPROBE_DEFER)
 746                 return -EPROBE_DEFER;
 747
 748         host->reg_base = devm_ioremap_resource(&pdev->dev,
 749                               platform_get_resource(pdev, IORESOURCE_MEM, 0));
 750         if (IS_ERR(host->reg_base))
 751                 return PTR_ERR(host->reg_base);
 752
 753         host->irq = platform_get_irq(pdev, 0);
 754         ret = devm_request_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 0,
 755                                "sunxi-mci", host);
 756         if (ret)
 757                 return ret;
 758         disable_irq(host->irq);
 759
 760         host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
 761         if (IS_ERR(host->clk_ahb)) {
 762                 dev_err(&pdev->dev, "Could not get ahb clock\n");
 763                 return PTR_ERR(host->clk_ahb);
 764         }
 765
 766         host->clk_mod = devm_clk_get(&pdev->dev, "mod");
 767         if (IS_ERR(host->clk_mod)) {
 768                 dev_err(&pdev->dev, "Could not get mod clock\n");
 769                 return PTR_ERR(host->clk_mod);
 770         }
 771
 772         of_property_read_u32(np, "bus-width", &host->bus_width);
 773         if (host->bus_width != 1 && host->bus_width != 4) {
 774                 dev_err(&pdev->dev, "Invalid bus-width %d\n", host->bus_width);
 775                 return -EINVAL;
 776         }
 777
 778         of_property_read_u32(np, "cd-mode", &host->cd_mode);
 779         switch (host->cd_mode) {
 780         case CARD_DETECT_BY_GPIO_POLL:
 781                 host->cd_pin = of_get_named_gpio(np, "cd-gpios", 0);
 782                 if (!gpio_is_valid(host->cd_pin)) {
 783                         dev_err(&pdev->dev, "Invalid cd-gpios\n");
 784                         return -EINVAL;
 785                 }
 786                 ret = devm_gpio_request(&pdev->dev, host->cd_pin, "mmc_cd");
 787                 if (ret) {
 788                         dev_err(&pdev->dev, "Could not get cd-gpios\n");
 789                         return ret;
 790                 }
 791                 gpio_direction_input(host->cd_pin);
 792                 break;
 793         case CARD_ALWAYS_PRESENT:
 794                 break;
 795         default:
 796                 dev_err(&pdev->dev, "Invalid cd-mode %d\n", host->cd_mode);
 797                 return -EINVAL;
 798         }
 799
 800         host->wp_pin = of_get_named_gpio(np, "wp-gpios", 0);
 801         if (gpio_is_valid(host->wp_pin)) {
 802                 ret = devm_gpio_request(&pdev->dev, host->wp_pin, "mmc_wp");
 803                 if (ret) {
 804                         dev_err(&pdev->dev, "Could not get wp-gpios\n");
 805                         return ret;
 806                 }
 807                 gpio_direction_input(host->wp_pin);
 808         }
 809
 810         return 0;
 811 }
 812
 813 static int sunxi_mmc_probe(struct platform_device *pdev)
 814 {
 815         struct sunxi_mmc_host *host;
 816         struct mmc_host *mmc;
 817         int ret;
 818
 819         mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
 820         if (!mmc) {
 821                 dev_err(&pdev->dev, "mmc alloc host failed\n");
 822                 return -ENOMEM;
 823         }
 824
 825         host = mmc_priv(mmc);
 826         host->mmc = mmc;
 827         spin_lock_init(&host->lock);
 828         tasklet_init(&host->tasklet, sunxi_mmc_tasklet, (unsigned long)host);
 829
 830         ret = sunxi_mmc_resource_request(host, pdev);
 831         if (ret)
 832                 goto error_free_host;
 833
 834         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
 835                                           &host->sg_dma, GFP_KERNEL);
 836         if (!host->sg_cpu) {
 837                 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
 838                 ret = -ENOMEM;
 839                 goto error_free_host;
 840         }
 841
 842         mmc->ops                = &sunxi_mmc_ops;
 843         mmc->max_blk_count      = 8192;
 844         mmc->max_blk_size       = 4096;
 845         mmc->max_segs           = PAGE_SIZE / sizeof(struct sunxi_idma_des);
 846         mmc->max_seg_size       = (1 << host->idma_des_size_bits);
 847         mmc->max_req_size       = mmc->max_seg_size * mmc->max_segs;
 848         /* 400kHz ~ 50MHz */
 849         mmc->f_min              =   400000;
 850         mmc->f_max              = 50000000;
 851         /* available voltages */
 852         if (!IS_ERR(host->vmmc))
 853                 mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vmmc);
 854         else
 855                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 856
 857         mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
 858                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
 859                 MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL |
 860                 MMC_CAP_DRIVER_TYPE_A;
 861         if (host->bus_width == 4)
 862                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 863         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
 864
 865         ret = mmc_add_host(mmc);
 866         if (ret)
 867                 goto error_free_dma;
 868
 869         dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
 870         platform_set_drvdata(pdev, mmc);
 871         return 0;
 872
 873 error_free_dma:
 874         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 875 error_free_host:
 876         mmc_free_host(mmc);
 877         return ret;
 878 }
 879
 880 static int sunxi_mmc_remove(struct platform_device *pdev)
 881 {
 882         struct mmc_host *mmc = platform_get_drvdata(pdev);
 883         struct sunxi_mmc_host *host = mmc_priv(mmc);
 884
 885         mmc_remove_host(mmc);
 886         sunxi_mmc_exit_host(host);
 887         tasklet_disable(&host->tasklet);
 888         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 889         mmc_free_host(mmc);
 890
 891         return 0;
 892 }
 893
 894 static struct platform_driver sunxi_mmc_driver = {
 895         .driver = {
 896                 .name   = "sunxi-mci",
 897                 .owner  = THIS_MODULE,
 898                 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
 899         },
 900         .probe          = sunxi_mmc_probe,
 901         .remove         = sunxi_mmc_remove,
 902 };
 903 module_platform_driver(sunxi_mmc_driver);
 904
 905 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
 906 MODULE_LICENSE("GPL v2");
 907 MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
 908 MODULE_ALIAS("platform:sunxi-mmc");